JP4198378B2 - Semiconductor test apparatus and semiconductor device test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus for testing a semiconductor device (hereinafter referred to as an LSI tester) and a test method for a semiconductor device, and more particularly to a test flow based on a control condition (hereinafter referred to as flag information) set in a flag from the outside. The present invention relates to a test flow control method for performing branch control of the above.
[0002]
[Prior art]
First, the configuration of a conventional LSI tester will be described. FIG. 6 is a block diagram showing a schematic configuration of a conventional LSI tester 500. Referring to FIG. 6, a conventional LSI tester 500 includes a first station 530 and a second station which are test stations on which an input / output unit 510, a tester body 520, and each device under test (hereinafter referred to as DUT) are mounted. The first station 530 includes a control flag setting unit 532, and the second station 540 includes a control flag setting unit 542. The tester body 520 includes a central processing unit (hereinafter referred to as CPU) 521, a storage unit (hereinafter referred to as memory) 522, a test resource generation unit 524, and a distribution unit 526. The operation of the conventional LSI tester 500 configured as described above is roughly as follows.
[0003]
First, the CPU 521 loads a test program from the input / output unit 510 and stores it in the memory unit 522. Next, the CPU 521 receives a test start command input by the operator from the first station 530 or the second station 540 and generates a test resource in the test resource generation unit 524. Further, the test is performed while distributing and supplying test resources to the DUT 1 of the first station 530 or the DUT 2 of the second station 540 via the distribution unit 526. The control flag setting unit 532 and the control flag setting unit 542 each set flag information that is a branch condition for the flow control of the test program executed in the corresponding station, and is configured by a normal toggle switch.
[0004]
Next, a semiconductor device testing method using the LSI tester 500 will be described focusing on test flow branching processing based on flag information. FIG. 7 is a schematic flowchart of a method for testing a semiconductor device by the LSI tester 500, and FIG. 8 is a detailed flowchart mainly showing the main part (test flow branching part) of the third step P103 of FIG. Hereinafter, a description will be given with reference to FIGS.
[0005]
At the start of the test, the operator loads the test program P1 into the LSI tester 500, and sets flag information, which is an independent branching condition, for each station by the control flag setting units 532 and 542. The example of FIG. 8 is an example in which the toggle switch is set to “F1 = 1”, “F2 = 0”, and “F3 = 1” corresponding to “1” and “0”, respectively. Further, the operator inputs a test start command from the corresponding first station 530, for example. Receiving the test start command, the CPU 521 executes the test program P1. The CPU 521 checks the information of the flag Fn set by the control flag setting unit 532 of the first station 530 in the flag reference instruction FLGn of the test program P1 (step S101n), and performs a branching process according to the information of Fn (step S101n). S102n). In the example of the flag reference instruction FLG1 in FIG. 8, since F1 = 1 is set, the CPU 521 selects and executes the instruction “Do11 (Y)”, and in the example of the flag reference instruction FLG2, F2 = 0. Therefore, the CPU 521 selects and executes the instruction “Do12 (N)”. Similarly, in the example of the flag reference instruction FLG3, since F3 = 1 is set, the CPU 521 selects and executes the instruction “Do13 (Y)” and ends the test program. Such a test flow control method is very effective for setting the values of F1, F2, and F3 so that the operator can freely change the test conditions and evaluate each test level.
[0006]
[Problems to be solved by the invention]
However, the above-described conventional technique has a problem that an erroneous test flow may be executed in the execution of the test program. This will be specifically described below.
[0007]
First, the control flag setting unit of the conventional LSI tester employs a method of setting flag information of “1” and “0” by a toggle switch or the like, and does not identify the state of no setting. If the setting is neglected, a test may be performed with the previous setting information. For example, it is a case where another apparatus user starts a test using another test program after setting flag information for technical investigation or maintenance of the test apparatus. That is, if a flag reference instruction based on flag information is adopted in the test program and another device user neglects to set the flag information, a test is performed with the flag information set by the previous user, resulting in an error. The test flow was executed.
[0008]
In addition, since the control flag setting unit for each station is not protected from accidental changes, there is a possibility that a test may be performed with incorrect flag information setting. For example, there is a possibility that the setting of the flag information is changed without the device user noticing when the toggle switch of the control flag setting unit touches a person's hand, body, jig or the like, and the test flow is executed erroneously.
[0009]
It is an object of the present invention to set test flag information of a test execution station when a semiconductor device test is performed by an LSI tester, and to use a test program that performs branch control of a test flow based on the flag information. An object of the present invention is to provide an LSI tester and a semiconductor device test method capable of arbitrarily and correctly executing flow branching control.
[0010]
[Means for Solving the Problems]
Therefore, the LSI tester according to the present invention has an input / output unit, a tester main unit, and a plurality of test stations.
Flag setting means for setting a control condition for controlling branching of the test flow in correspondence with a desired test program;
Checking the presence or absence of the control condition, if there is no flag to stop execution of the test program, if there is, flag reference instruction execution means for controlling the branch of the test program based on the control condition; At least.
[0011]
At this time, the tester main body unit stores the test program when the test program is executed;
It is desirable to further include flag deletion means for deleting the corresponding control condition when deleting the test program from the first storage means.
[0012]
Further, it may further comprise flag display means for displaying the corresponding control condition when executing the branch control of the test program.
[0013]
In addition, the method for testing a semiconductor device according to the present invention includes:
A first step of loading a test program for testing a predetermined semiconductor device into an LSI tester;
When the test program includes a branch process of a test flow of the test program, a control condition for controlling the branch process is set in correspondence with the test station of the LSI tester that tests the semiconductor device and the test program. A second step to set,
At least a third step of performing a test of the semiconductor device;
The third step includes
A condition setting confirmation step for confirming whether or not the control condition is set when processing a flag reference instruction for referring to the control condition in the process of executing the test of the semiconductor device;
If the control condition is not set, an alarm generation step for generating an alarm and stopping execution of the test program;
When the control condition is set, a branch processing step for controlling the branch of the test program based on the control condition;
It is characterized by including at least.
[0014]
In addition, another semiconductor device testing method according to the present invention includes:
A first step of loading a test program for testing a predetermined semiconductor device into an LSI tester;
When the test program includes a branch process of a test flow of the test program, a control condition for controlling the branch process is set in correspondence with the test station of the LSI tester that tests the semiconductor device and the test program. A second step to set,
At least a third step of performing a test of the semiconductor device;
The third step includes
A reference instruction confirmation step for confirming whether or not a flag reference instruction for referring to the control condition is used in the test program at the start of a test;
A condition setting confirmation step for confirming whether or not the control condition is set when the flag reference instruction is used;
If the control condition is not set, an alarm generation step for generating an alarm and stopping execution of the test program;
When the control condition is set, at least a test execution step for starting execution of the test program is provided,
The test execution step includes a branch processing step for controlling branching of the test program based on the control condition.
[0015]
At this time, when the branch of the test program is controlled based on the control condition, it may further include a display processing sub-step for displaying the control condition on the flag display means in parallel.
[0016]
In addition, when the test program loaded in the LSI tester is deleted from the LSI tester, the process further includes a fourth step of simultaneously deleting the control conditions set corresponding to the test program from the LSI tester. Is preferred.
[0017]
Further, the first step inputs in advance information specifying a test station of the LSI tester for testing the semiconductor device, and controls branching of the test flow of the test program corresponding to the test station and the test program. It is also possible to include a flag clearing step for deleting a control condition for doing so.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings.
FIG. 1 is a schematic block diagram of an embodiment of an LSI tester of the present invention. Referring to FIG. 1, the LSI tester 1 of this embodiment includes an input / output unit 10, a tester body 20, and a first test station 30 and a second test station 40, which are test stations on which a DUT is mounted. Further, the tester body 20 includes a CPU 21, a memory 22 which is a first storage means for storing the test program when the test program is executed, a test resource generator 24, a distribution unit 26, and a desired test. Flag setting means 211 for setting flag information, which is a control condition for controlling the branch of the test flow in correspondence with the program, and the presence or absence of flag information are checked. Stop execution of the program, and if there is, refer to the flag that controls the branch of the test program based on the set flag information. The instruction execution means 213, flag display means 215 for displaying flag setting information corresponding to execution of branch control of the test program, and flag information corresponding to deletion of the test program from the memory unit 22 are also combined. Flag deletion means 217 for deletion.
[0019]
The operation of the LSI tester 1 of the present embodiment configured as described above is roughly as follows. First, the CPU 21 loads a test program from the input / output unit 10 and stores it in the memory unit 22. Next, the CPU 21 receives a test start command (not shown) from the first station 30 or the second station 40, and the test resource generation unit 24 supplies a voltage power source corresponding to each instruction of the test program, a predetermined timing, and a voltage level. Generate test resources such as input signals. Furthermore, the test is performed while distributing and supplying test resources to the DUT 1 of the first station 30 or the DUT 2 of the second station 40 via the distribution unit 26. The flag setting unit 211, the flag reference instruction execution unit 213, the flag display unit 215, and the flag deletion unit 217 can be realized as a control program included in the configuration of the CPU 21, the memory unit 22, and the input / output unit 10, for example. .
[0020]
Specifically, the flag setting unit 211 is intentionally set by the operator, and after loading the test program, the test execution flow of the test program is associated with the station that performs the test and the test program. This is means for setting flag information as a branching condition in. That is, the operator sets flag information that is a corresponding branch condition by program control by the CPU 21 via the input / output unit 10 and stores the flag information in the memory unit 22. If the operator does not set it intentionally, the corresponding flag is not generated and stored. In addition, the flag information generated when the test program is deleted is also deleted.
[0021]
When the operator starts the test and the CPU 21 executes the flag reference instruction, the flag reference instruction execution means 213 reads the corresponding flag information and performs branching according to the flag information. If the CPU 21 executes the flag reference instruction and cannot read out the corresponding flag information (if the flag information is not specified and generated and stored), an alarm is generated and the execution is stopped.
[0022]
Alternatively, when the operator inputs a test start command, the flag reference command execution means 213 first determines whether each test program uses the flag reference command and if the flag reference command is used, the flag information of the corresponding station Determine whether is set. If the flag reference instruction is used and the flag information is not set, an alarm is output to stop the execution of the test program. If the flag is set, the test program is executed, The corresponding flag information may be confirmed with a flag reference instruction, and branch control of the test program according to the flag information may be performed.
[0023]
The flag display means 215 displays corresponding flag information when the operator starts a test and the CPU 21 executes a flag reference command. Note that display may be prohibited if specified specially.
[0024]
For example, when the test program is deleted from the memory unit 22 after the test is completed, the flag deletion unit 217 also deletes the corresponding flag information.
[0025]
In the LSI tester 1 of the present embodiment, first, after loading a test program, flag information is set by associating a test execution station with the test program. Thereafter, when the test by the test program is started, the LSI tester 1 branches while acquiring the information set in the corresponding flag and displaying the flag information in the flag reference instruction for acquiring the flag information for controlling the branch processing. Control processing. If the flag information is “unspecified” in the flag reference instruction, an alarm is output and execution of the test program is interrupted. In this way, the test flow of the test program can be arbitrarily and correctly executed.
[0026]
Next, a first embodiment of the semiconductor device test method of the present invention will be described focusing on the test flow control method. The semiconductor device testing method of this embodiment is a method suitable for testing with the LSI tester 1. 2 is a flowchart showing a semiconductor device testing method of the present embodiment using the LSI tester 1, FIG. 3 is a flowchart showing details of the third step of FIG. 2, and FIG. 4 is a flag reference processing step S1k (FIG. 3). However, k is a flowchart schematically showing the processing content of k (an integer of 1 ≦ k ≦ 3).
[0027]
Referring to FIGS. 2 to 4, the semiconductor device testing method of the present embodiment includes a first process P1 for loading a test program for testing a desired semiconductor device into the LSI tester 1,
When the test program includes a branch process of the test flow of the test program, flag information which is a control condition for controlling the branch process in correspondence with the test station and the test program of the LSI tester 1 that tests the semiconductor device A second step P2 for setting
A third step P3 for performing a test of the semiconductor device;
At least a fourth step of simultaneously deleting flag information set in correspondence with the test program from the LSI tester when the test program loaded in the LSI tester 1 is deleted from the LSI tester 1;
The third step P3 is
Based on the flag reference processing step S1n for processing the flag reference instruction by the flag reference instruction execution means 213 and the flag information Fn when there is a flag reference instruction FLGn that refers to the flag information Fn in the execution process of the semiconductor device test. Branch processing step S2n for controlling branching of the test program, and flag reference processing step S1n
Condition setting confirmation substep S11n for confirming whether flag information Fn is set,
When flag information Fn is set, information acquisition substep S12n for acquiring flag information Fn;
If the flag information Fn is not set, an alarm generation sub-step S13n that generates an alarm and stops execution of the test program;
An information display sub-step S14n for displaying the acquired flag information Fn on the flag display means 215.
[0028]
Hereinafter, a case where the semiconductor device under test DUT1 is tested at the first station 30 of the LSI tester 1 by the test program P1 will be described in more detail with reference to FIGS.
[0029]
First, at the start of the test, the operator loads the test program P1 into the LSI tester 1 and stores it in the memory unit 22 (first step P1). The flag setting means 211 provides flag information corresponding to the first station 30 and the test program P1. It is set and stored in the memory unit 22 (second process P2). Here, it is assumed that the flag information is set to “F1 = 1”, “F2 = 0”, and “F3 = 1”. Next, the operator inputs a test start command from the first station 30. Receiving the test start command, the CPU 21 sequentially performs command processing based on the test program P1. For the flag reference instruction FLG1, the flag reference instruction execution means 213 performs flag reference processing step S11. Specifically, first, in the condition setting confirmation substep S111, it is confirmed whether or not the corresponding flag F1 corresponding to the first station 30 and the test program P1 is set, and then in the information acquisition substep S121, the flag F1 is set. Therefore, the flag information F1 = 1 is acquired, and the flag information F1 = 1 is displayed on the flag display means 215 in the information display sub-step S141.
[0030]
Next, the branch of the test program is processed based on the flag information F1 in the branch processing step S21. In the example of FIG. 3, since F1 = 1 is set, the CPU 21 selectively executes the instruction “Do11 (Y)”.
[0031]
Similarly, in the flag reference instruction FLG2, since F2 = 0 is set, the CPU 21 selectively executes the instruction “Do12 (N)”, and in the flag reference instruction FLG3, F3 = 1 is set. The CPU 21 selectively executes the instruction “Do13 (Y)” and ends the test program.
[0032]
In the flag reference instruction FLGk (where k is an integer of 1 ≦ k ≦ 3), if the CPU 21 detects that the corresponding flag information Fk is not set, the alarm generation sub-step S13k is performed at that time, and the alarm is generated. Occurs and stops running the test program. Generates an alarm and stops execution.
[0033]
When the third step P3 is completed, the test program P1 stored in the memory unit 22 of the LSI tester 1 is deleted from the memory unit 22 in the fourth step P4, and the first station 30 and the test program P1 are associated with each other. The flag information F1, F2, F3 set in the above is also deleted from the memory unit 22 at the same time.
[0034]
As described above, in the semiconductor device test method of this embodiment using the LSI tester 1, the operator intentionally sets the station information to be used and the flag information corresponding to the test program via the input / output unit 10. Otherwise, the corresponding flag information is not generated and stored, and when the test program is deleted, the flag information generated corresponding to the test program is also deleted, so the flag information for controlling the branch of the test flow is accidental. It is possible to avoid erroneous test flow execution due to the change to.
[0035]
Also, branch information is controlled by setting flag information corresponding to the station and test program to be used, and if the flag information cannot be read out by executing a flag reference instruction, that is, branch processing is controlled. If the flag information is not specified and generated and stored, an alarm is generated and the execution of the test program is stopped, so that it is possible to avoid erroneous test flow execution due to omission of flag information.
[0036]
Next, a second embodiment of the semiconductor device test method of the present invention will be described focusing on the test flow control method. The semiconductor device test method according to the present embodiment is also a method suitable for implementation using the LSI tester 1. FIG. 5 is a flowchart showing a semiconductor device testing method of the present embodiment using the LSI tester 1.
[0037]
Referring to FIG. 5, the semiconductor device test method of the present embodiment includes a first process P1 for loading a test program for testing a desired semiconductor device into the LSI tester 1,
When the test program includes a branch process of the test flow of the test program, flag information for controlling the branch process is set in correspondence with the test station and the test program of the LSI tester 1 that tests the semiconductor device. Two steps P2,
A third step P3A for performing a test of the semiconductor device;
At least a fourth step of simultaneously deleting flag information set in correspondence with the test program from the LSI tester when the test program loaded in the LSI tester 1 is deleted from the LSI tester 1;
The third step P3A is
A reference instruction confirmation step S1 for confirming whether or not a flag reference instruction for referring to flag information is used in the test program at the start of the test;
Condition setting confirmation step S2 for confirming whether flag information is set when a flag reference instruction is used;
When flag information is set, a test execution step S3 for starting execution of the test program;
If the flag information is not set, at least an alarm generation step S4 that generates an alarm and stops execution of the test program,
The test execution step S3 includes a branch processing step for controlling the branch of the test program based on the flag information.
[0038]
In the semiconductor device testing method of the present embodiment, the first step P1, the second step P2, and the fourth step P4 are the same as those in the first embodiment, but the configuration of the third step P3A is the first embodiment. This is different from the configuration of the third step P3. Hereinafter, as for the third step P3A, as in the case of the first embodiment, the case where the semiconductor device DUT1 is tested at the first station 30 of the LSI tester 1 by the test program P1 will be described as an example with reference to FIGS. A more specific description will be given with reference to FIG.
[0039]
When the operator inputs a test start command from the corresponding station, the CPU 21 receiving the test start command first checks whether the test program P1 uses the flag reference command in the reference command check step S1.
[0040]
Since the test program P1 uses the flag reference instruction and the DUT1 is tested in the first station 30, the test program P1 and the first station 30 are then executed by the flag reference instruction execution means 213 in the condition setting confirmation step S2. It is confirmed whether the first flag information corresponding to is set. As described above, since the first flag information has been set, the first flag information is acquired by the flag display means 215 and displayed. In the example of FIG. 3, “F1 = 1”, “F2 = 0”, and “F3 = 1” are displayed.
[0041]
Next, the test program P1 is executed in the test execution step S3. As described above, since it has been confirmed that the first flag information is set, the flag reference instruction as in the first embodiment is processed during the processing of the flag reference instruction FLGn in the process of executing the test program. The execution unit 213 does not need to perform the condition setting confirmation sub-step S11n, and can immediately acquire the information of the corresponding flag Fn of the first flag information and perform the branching process according to the information of Fn. That is, the test execution step S3 of this embodiment can be processed in exactly the same way as the conventional third step P103 shown in FIG.
[0042]
Specifically, when the CPU 21 detects the flag reference instruction FLGn in the execution process of the test program P1, the flag reference instruction execution means 213 acquires information on the corresponding flag Fn corresponding to the first station 30 and the test program P1. Then, branch processing according to the information of Fn is performed. In the example of the flag reference instruction FLG1 in FIG. 3, since F1 = 1, the CPU 21 selectively executes the process “Do11 (Y)”. In the example of the flag reference instruction FLG2, the CPU 21 determines that “F2 = 0”. The process of Do12 (N) "is selected and executed. Similarly, in the example of the flag reference instruction FLG3, since F3 = 1, the CPU 21 selectively executes the process “Do13 (Y)” and ends the test program P1.
[0043]
Even in the semiconductor device test method of the present embodiment using the LSI tester 1, as in the case of the first embodiment, an erroneous test flow caused by accidental change of flag information for controlling the branch of the test flow. Execution can be avoided, and erroneous test flow execution due to omission of flag information can be avoided.
[0044]
Needless to say, the present invention is not limited to the description of the above-described embodiment, and various modifications can be made within the scope of the gist thereof.
[0045]
For example, in the semiconductor device test method described above, when the test program loaded in the LSI tester 1 in the fourth step P4 is deleted from the LSI tester 1, the flag information set corresponding to the test program is simultaneously displayed in the LSI. As described in the example of deleting from the tester, when loading a test program for testing a desired semiconductor device into the LSI tester 1 in the first step P1, information on the station to be used is input and The flag information corresponding to the station may be reset.
[0046]
In addition, the example of two test stations has been described, but the number of test stations is not limited to this and may be any number.
[0047]
In addition, the method for supplying to the test program LSI tester is not particularly mentioned, but a known method such as a method for supplying from an external storage device (not shown) such as a hard disk device or a method for supplying via a communication line is used. Can be used.
[0048]
【The invention's effect】
As described above, according to the LSI tester and the semiconductor device test method of the present invention, it is possible to avoid execution of an erroneous test flow due to accidental change of flag information for controlling the branch of the test flow. Is obtained. In addition, it is possible to avoid the erroneous execution of the test flow due to flag information omission.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an embodiment of an LSI tester of the present invention.
FIG. 2 is a flowchart showing a first embodiment of a semiconductor device testing method of the present invention.
FIG. 3 is a flowchart showing details of a third step in FIG. 2;
4 is a flowchart schematically showing the processing content of a flag reference processing step in FIG. 3;
FIG. 5 is a flowchart showing a second embodiment of a semiconductor device testing method of the present invention.
FIG. 6 is a block diagram showing a schematic configuration of a conventional LSI tester.
FIG. 7 is a schematic flowchart of a semiconductor device testing method using a conventional LSI tester.
FIG. 8 is a detailed flowchart showing mainly the main part of the third step in FIG. 7;
[Explanation of symbols]
1 LSI tester
10 Input / output section
20 Tester body
21 CPU
22 Memory part
24 Test resource generator
26 Distributor
30 1st station
40 2nd station
211 Flag setting means
213 Flag reference instruction execution means
215 Flag display means
217 Flag deletion means

Claims (10)

An input / output unit;
A tester body,
Have multiple test stations,
The tester body is
Flag setting means for setting a control condition for controlling branching of the test flow in correspondence with a desired test program;
At the start of the test, it is confirmed whether or not a flag reference instruction that refers to the control condition is used in the test program, and if the flag reference instruction is used , the presence or absence of the control condition is confirmed. If not, an alarm is generated and execution of the test program is stopped; if there is, flag reference instruction execution means for controlling branching of the test program based on the control condition;
A semiconductor test apparatus comprising at least: The tester body is
First storage means for storing the test program when the test program is executed;
When deleting the test program from the first storage means, flag deletion means for deleting the corresponding control conditions together,
The semiconductor test apparatus according to claim 1, further comprising:   3. The semiconductor test apparatus according to claim 1, further comprising flag display means for displaying the corresponding control condition when executing control of branching of the test program. A first step of loading a semiconductor test apparatus with a test program for testing a predetermined semiconductor device;
When the test program includes a branch process of the test flow of the test program, a control condition for controlling the branch process corresponding to the test station of the semiconductor test apparatus for testing the semiconductor device and the test program A second step of setting
At least a third step of performing a test of the semiconductor device;
The third step includes
A condition setting confirmation step for confirming whether or not the control condition is set when processing a flag reference instruction for referring to the control condition in the process of executing the test of the semiconductor device;
If the control condition is not set, an alarm generation step for generating an alarm and stopping execution of the test program;
When the control condition is set, a branch processing step for controlling the branch of the test program based on the control condition;
At least look at including the,
The first step inputs in advance information specifying a test station of the semiconductor test apparatus for testing the semiconductor device, and controls branching of the test flow of the test program corresponding to the test station and the test program. A test method for a semiconductor device, comprising: a flag clear step for deleting a control condition for the semiconductor device. A first step of loading a semiconductor test apparatus with a test program for testing a predetermined semiconductor device;
When the test program includes a branch process of the test flow of the test program, a control condition for controlling the branch process corresponding to the test station of the semiconductor test apparatus for testing the semiconductor device and the test program A second step of setting
At least a third step of executing a test of the semiconductor device, and at the start of the test, the third step checks whether or not a flag reference instruction for referring to the control condition is used in the test program A reference instruction confirmation step to perform,
A condition setting confirmation step for confirming whether or not the control condition is set when the flag reference instruction is used;
When the control condition is not set, an alarm generation step for generating an alarm and stopping the execution of the test program; and when the control condition is set, a test execution for starting the execution of the test program Comprising at least steps,
A test method for a semiconductor device, wherein the test execution step includes a branch processing step for controlling a branch of the test program based on the control condition. 6. The semiconductor device testing method according to claim 5 , further comprising a display processing sub-step of displaying the control condition on a flag display unit in parallel when the branch of the test program is controlled based on the control condition. When the test program loaded in the semiconductor test apparatus is deleted from the semiconductor test apparatus, the process further includes a fourth step of simultaneously deleting the control conditions set corresponding to the test program from the semiconductor test apparatus. The method for testing a semiconductor device according to claim 5 . The first step inputs in advance information specifying a test station of the semiconductor test apparatus for testing the semiconductor device, and controls branching of the test flow of the test program corresponding to the test station and the test program. The semiconductor device testing method according to claim 5 , further comprising a flag clearing step for deleting a control condition for the semiconductor device. 5. The semiconductor device testing method according to claim 4, further comprising a display processing sub-step of displaying the control condition on a flag display means in parallel when the branch of the test program is controlled based on the control condition. When the test program loaded in the semiconductor test apparatus is deleted from the semiconductor test apparatus, the process further includes a fourth step of simultaneously deleting the control conditions set corresponding to the test program from the semiconductor test apparatus. The method for testing a semiconductor device according to claim 4 or 9.

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