JP4197354B2 - Method for manufacturing electro-optical device - Google Patents

Description

  The present invention relates to an electro-optical device constituted by a thin film transistor formed on an insulating substrate and an IC chip provided on the same substrate, particularly an active matrix liquid crystal display device.

  In recent years, a technique for forming a thin film transistor (hereinafter referred to as TFT) using a semiconductor thin film formed on a glass substrate has been developed. Then, development of an electro-optical device that controls the voltage applied to the optical modulation layer sandwiched between the pair of substrates by the TFT and performs the ON / OFF operation of light is progressing.

  In particular, a liquid crystal panel using liquid crystal as an optical modulation layer is rapidly in demand as a display such as a viewfinder of a video camera or a monitor screen of a notebook computer.

  At present, the development of liquid crystal panels composed of polysilicon TFTs using a crystalline silicon film (typically a polysilicon film) as a semiconductor thin film is the mainstream. Since the polysilicon TFT has a higher operating speed than the amorphous silicon TFT, it is possible to form a monolithic liquid crystal panel in which a pixel matrix circuit and a drive circuit (shift register, etc.) are formed on the same substrate.

  Furthermore, there is a demand for realization of a system-on-panel that forms not only a drive circuit such as a shift register but also logic circuits such as a clock control circuit, a memory circuit, and a signal conversion circuit on the same substrate.

  Since such a logic circuit requires an operation speed on the order of GHz, an extremely high operation speed is required for the polysilicon TFT. In order to realize this, the element must be miniaturized according to the scaling law.

  However, it is very difficult to form a fine pattern having a wiring width of 1 μm or less on a generally used large glass substrate. For example, in a glass substrate, problems such as waviness on the substrate surface and shrinkage occur. In addition, it is extremely difficult to realize an optical system capable of forming a fine pattern over a wide range, and there are aspects in which the progress of exposure technology is a rule.

  Therefore, at present, it is the limit to build a drive circuit such as a shift register on the same substrate (still, the operation speed is insufficient and divided drive is performed), and other logic circuits rely on an external IC.

  In the present age when lightness, thinness and smallness are required, electro-optical devices are also required to be smaller and lighter. However, even if the functionality of the liquid crystal panel is enhanced by incorporating a drive circuit, it is an obstacle to downsizing and weight reduction of the apparatus as long as an external IC is attached to the liquid crystal panel.

  The present invention has been made in view of such problems, and is intended to provide an electro-optical device that can be further systematized and that is more portable and functional, and can be obtained at a low manufacturing cost. Let it be an issue.

The configuration of the invention disclosed in this specification is as follows.
A first substrate and a second substrate;
An electro-optic modulation layer provided between the first substrate and the second substrate;
In an electro-optical device having
On the first substrate, a plurality of bottom gate TFTs constituting a pixel matrix circuit, a source driving circuit and a gate driving circuit, and one or a plurality of IC chips constituting a logic circuit are provided.
The first substrate and the second substrate are bonded together such that all end surfaces except an arbitrary end surface are aligned with each other.
The IC chip is mounted on the first substrate adjacent to the arbitrary end face.

The above configuration is
A first substrate and a second substrate;
An electro-optic modulation layer provided between the first substrate and the second substrate;
In an electro-optical device having
On the first substrate, a plurality of bottom gate TFTs constituting a pixel matrix circuit, a source driving circuit and a gate driving circuit, and one or a plurality of IC chips constituting a logic circuit are provided.
The first substrate and the second substrate are bonded together with all the end surfaces thereof aligned except for the portion where the FPC is attached,
It can also be said that the IC chip is attached to a portion to which the FPC is attached.

The above configuration is
A first substrate and a second substrate;
An electro-optic modulation layer provided between the first substrate and the second substrate;
In an electro-optical device having
On the first substrate, a plurality of bottom gate TFTs constituting a pixel matrix circuit, a source driving circuit and a gate driving circuit, and one or a plurality of IC chips constituting a logic circuit are provided.
The first substrate is exposed only at the portion where the FPC is attached,
It can also be said that the IC chip is attached to a portion to which the FPC is attached.

  In the present invention, an extremely compact electro-optical device (particularly a liquid crystal module) is constructed because the substrate on the TFT manufacturing side and the substrate on the opposite side are bonded together so that the end faces are aligned as much as possible, and the IC chip is attached to the FPC attachment part. can do.

  Therefore, an IC chip-mounted system panel can be realized with a minimum size, so that a liquid crystal module having a very compact and multi-functionality can be realized. This directly contributes to reducing the size and weight of electronic devices (improving portability).

  In addition, since bottom gate type TFTs (particularly inverted stagger type TFTs) constituting the pixel matrix circuit and the drive circuit can be manufactured at low manufacturing costs, the cost of liquid crystal modules and the cost of electronic devices can be reduced. I can hope.

  In the present invention, a liquid crystal panel is formed by providing a liquid crystal layer between the first substrate 101 and the second substrate 105. At this time, the second substrate 105 is bonded to the first substrate 101. The feature of the present invention is that the end surfaces (side surfaces) 107 to 109 of the respective substrates are aligned.

  This configuration can be obtained by cutting the first substrate 101 and the second substrate 105 together, or by cutting the same position from both the front and back sides.

  However, it is necessary to remove the second substrate 105 and expose the first substrate 101 only in a portion where an FPC (flexible printed circuit) is attached. Therefore, the first substrate 101 is always exposed only there, and this portion is effectively used as a mounting portion for the IC chips 110 and 111.

  The present invention effectively utilizes the exposed portion of the first substrate 101, which has been used only as an FPC attachment portion, as an IC chip attachment portion, thereby minimizing the size of the first substrate 101. It is an object.

  The configuration of the present invention will be described with reference to FIG. FIG. 1 shows a liquid crystal module of the present invention. The liquid crystal module refers to a liquid crystal panel in which necessary components (polarizing plate, external IC, etc.) are mounted. In the present embodiment, the description of components that are not directly related to the configuration of the present invention, such as a polarizing plate, is omitted.

  In FIG. 1, reference numeral 101 denotes a first substrate. On the first substrate 101, a pixel matrix circuit 102, a source driving circuit 103, and a gate driving circuit 104 are bottom gate type TFTs (typically inverted stagger type TFTs). It is formed with it. Reference numeral 105 denotes a second substrate, which is a counter substrate for sandwiching an electro-optic modulation layer (liquid crystal in this embodiment) with the first substrate 101.

  A substrate having an insulating surface is used as the first substrate and the second substrate. Examples of the substrate having an insulating surface include a glass substrate provided with a base film, a quartz substrate, a ceramic substrate, and a silicon substrate. Further, the quartz substrate can be used without providing a base film.

  The feature of the present invention is that the end face of the first substrate 101 and the end face of the second substrate 105 are aligned as much as possible. That is, all the end surfaces except an arbitrary end surface are aligned and bonded together.

  In this case, it is preferable that the arbitrary end face has only one side. Therefore, when a square glass substrate is used as the first substrate, the three end faces are aligned between the first substrate and the second substrate, and only one side is not aligned. For example, as shown in FIG. 1, it is desirable to align all the end faces 107 to 109 except for the part to which the FPC 106 is attached.

  In order to expose the wiring on the first substrate 101, the portion to which the FPC is attached (portion adjacent to the arbitrary end face) needs to remove only the second substrate 105. In the present invention, IC chips 110 and 111 are formed on the first substrate 101 exposed for such a reason by a COG (chip on glass) method.

  There are two known methods for attaching an IC chip by COG, a face-down method and a face-up method (also referred to as a wire bonding method). If the face-down method is used in the present invention, the element formation surfaces of the IC chips 110 and 111 face the first substrate 101 side. Further, when the face-up method is used, the element formation surfaces of the IC chips 110 and 111 are directed to the second substrate 105 side.

  That is, the first substrate 101 and the second substrate 105 are configured such that all end faces 107 to 109 are aligned except for the FPC mounting portion, and the first substrate 101 is exposed only by the FPC mounting portion. It has become. IC chips 110 and 111 are attached to the exposed portions.

  Since an IC chip can form a deep submicron fine pattern of 0.35 μm or less (preferably 0.2 μm or less), a complex logic circuit can be formed on a chip of several mm square.

  The number of IC chips that can be attached to the liquid crystal panel of the present invention is not limited to two, and one or more IC chips may be provided as necessary.

  With the configuration as described above, the area occupied by the first substrate 101 can be minimized. That is, the size of the liquid crystal panel can be reduced as much as possible by effectively utilizing the FPC mounting portion of the first substrate 101 as the IC chip mounting portion.

  In addition, since the pixel matrix circuit 102 and the drive circuits 103 and 104 are formed of inverted staggered TFTs that can be manufactured at low manufacturing costs, the manufacturing cost of the liquid crystal panel body can be kept low. In this way, by suppressing the liquid crystal panel body to the lowest possible cost, the product price of the liquid crystal module mounted with the IC chip can be reduced.

  Further, the configuration shown in FIG. 1 has a significant effect in the manufacturing process of the liquid crystal panel. Usually, a plurality of liquid crystal panels are taken out from a single substrate (referred to as “multiple drawing”) to improve throughput and lower the unit price per liquid crystal panel. Therefore, the effect that the size of the liquid crystal panel can be minimized as in the present invention is effective in increasing the number of panels that can be formed in one large substrate.

  Conventionally, an external logic circuit formed on a printed circuit board and a monolithic liquid crystal panel are connected by an FPC to exchange signals. However, in the present invention, the necessary logic circuit is integrated into one chip. To form. Therefore, it is possible to realize a liquid crystal module that is extremely excellent in portability and functionality.

  In addition, since the liquid crystal module itself formed on a thin glass substrate has a function as a display, it is possible to reduce the size and weight of electronic devices (video cameras, portable information terminals, etc.) on which the liquid crystal module is mounted. The

  In the first embodiment, the COG method is used as an IC chip attachment method. However, a TAB (tape automated bonding) method can also be used. A configuration example in the case of using the TAB method is shown in FIG.

  In FIG. 2, the first substrate 101 and the second substrate 105 are bonded together with the configuration as described in the first embodiment. Naturally, as shown in the first embodiment, the first substrate 101 and the second substrate 105 are all aligned except for the FPC attachment portion, and the first substrate 101 is exposed only by the FPC attachment portion. .

  In this embodiment, TCP (tape carrier package) 201 to 203 are attached to the exposed part of the first substrate 101. TCP refers to a logic tape mounted on a flexible tape by gang bonding. In practice, both FPC and TCP are the same.

  By using the TAB method, the degree of freedom on the mounting surface such as connection pitch, shape, open structure and bending structure is improved. For this reason, it is suitable for increasing the capacity, definition, and color of the liquid crystal panel, and making the liquid crystal module thinner, lighter, and more compact.

  As the IC chips 110 and 111 used in the first embodiment, MOSFETs (also referred to as IGFETs) using bulk single crystals may be used. FIG. 3 shows an example in which an IC chip using a bulk single crystal is mounted. The configuration of the liquid crystal module shown in FIG. 3 is the same as that of the first embodiment.

  At this time, the source driving circuit 103 and the gate driving circuit 104 are composed of inverted staggered TFTs (indicated by 301). Although FIG. 3 shows a CMOS circuit (inverter circuit) in which N-type and P-type TFTs are complementarily combined, a shift register circuit, a buffer circuit, an analog switch circuit, etc. are usually constructed based on this.

  Next, the IC chips 110 and 111 are constituted by MOSFETs (shown by 302) using a bulk single crystal. The MOSFET indicated by 302 is formed by a normal IC forming technique. Detailed description is omitted in this embodiment.

  When a bulk single crystal is used as an IC chip, conventional IC technology can be followed, so that a very high yield and reliability can be ensured. Further, an IC chip having high functionality can be attached with a small mounting area.

  In this embodiment, an example in which an IC chip to be mounted on a liquid crystal module is formed with an SOI structure will be described. FIG. 4 shows an example in which an SOI structure IC chip is mounted. The configuration of the liquid crystal panel shown in FIG. 4 is the same as that of the first embodiment.

  In FIG. 4, the source drive circuit 103 and the gate drive circuit 104 are each configured with a CMOS circuit (indicated by 401) composed of inverted staggered TFTs as a basic circuit. Then, the IC chips 402 and 403 are configured by SOI structure FETs (indicated by 404).

  The SOI structure indicated by 404 in FIG. 4 is an example in which a transistor is formed on a known SIMOX substrate, but any other SOI structure (bonded SOI, SOI using a smart cut method, etc.) can be used. Is possible. A detailed description of the SOI structure here is omitted.

  In the case of the SOI structure, it is possible to configure a circuit that is superior in operating speed and reliability compared to a MOSFET using a bulk single crystal. This is thought to be due to the reduction of parasitic capacitance and suppression of the short channel effect by reducing the thickness of the active layer.

  It is also possible to attach an IC chip having a three-dimensional structure using SOI technology. In this case, the function of the circuit can be dramatically improved without increasing the mounting area.

  In this embodiment, an example in which an NTFT (N-channel TFT) and PTFT (P-channel TFT) are complementarily combined to form a source driving circuit and a gate driving circuit is shown.

  First, a base film 502 made of a silicon oxide film is provided on a glass substrate 501, and gate electrodes 503 and 504 are formed thereon. In this embodiment, an aluminum alloy having a thickness of 200 to 400 nm (aluminum with 2 wt% scandium added) is used as the gate electrodes 503 and 504. It may be used.

  Next, the gate electrodes 503 and 504 are anodized in tartaric acid to form nonporous anodic oxide films 505 and 506. A detailed formation method may be referred to Japanese Patent Application Laid-Open No. 7-13318. The anodized films 505 and 506 protect the gate electrodes 503 and 504 so that they can withstand the subsequent process temperature.

  Then, a gate insulating film 507 is formed thereon with a thickness of 100 to 200 nm. As the gate insulating film 507, a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film is used. In this embodiment, the anodic oxide films 505 and 506 also function as part of the gate insulating film.

Next, an amorphous silicon film 508 is formed to a thickness of 10 to 150 nm (preferably 10 to 75 nm, more preferably 15 to 45 nm). In addition to the amorphous silicon film, a semiconductor thin film containing silicon as a main component (for example, a silicon-germanium compound represented by Si _x Ge _1-x (0 <X <1)) can be used.

  When the state of FIG. 5A is obtained in this way, laser light or strong light having the same intensity as the laser light is irradiated to crystallize the amorphous silicon film 508. As the laser light, excimer laser light is preferable. As the excimer laser, a pulse laser using KrF, ArF, or XeCl as a light source may be used.

  As strong light having the same intensity as laser light, strong light from a halogen lamp or a metal halide lamp, or strong light from an infrared light or an ultraviolet light lamp can be used.

In this embodiment, after the amorphous silicon film 508 is dehydrogenated, a laser beam processed into a linear shape is scanned from one end to the other end of the substrate to crystallize the entire surface of the amorphous silicon film 508. At this time, the sweep speed of the laser beam is 1.2 mm / s, the processing temperature is room temperature, the pulse frequency is 30 Hz, and the laser energy is 300 to 315 mJ / cm ² . (Fig. 5 (B))

  Thus, a crystalline silicon film 509 is obtained as shown in FIG. Here, in this embodiment, channel doping is performed on both the NTFT region and the PTFT region to control the threshold voltage.

  In this embodiment, an element selected from group 15 (phosphorus is taken as an example) is added to the region that becomes NTFT to move the threshold voltage to the negative side, and the threshold is set to the region that becomes PTFT. A structure in which an element selected from group 13 (boron is taken as an example) is added to shift the value voltage to the plus side.

  First, a buffer layer 510 made of a silicon oxide film is formed on the crystalline silicon film 508 to a thickness of 50 to 200 nm (preferably 100 to 150 nm).

  First, a region to be a PTFT is concealed with a resist mask 511, and phosphorus is added by an ion implantation method (with mass separation) or an ion doping method (without mass separation). The phosphorus-containing region 512 is formed by this channel doping process. Arsenic, antimony, or the like may be added instead of phosphorus. (Fig. 5 (C))

At this time, the acceleration voltage is selected from 5 to 80 keV (typically 10 to 30 keV), and the dose amount is 1 × 10 ¹² to 1 × 10 ¹⁷ atoms / cm ² (preferably 1 × 10 ¹³ to 1 × 10 ¹⁶ atoms) / cm ² ). In this embodiment, the acceleration voltage is 30 keV, and the dose is 5 × 10 ¹³ atoms / cm ² .

  It should be noted that the dose amount must be obtained experimentally in advance. That is, it is confirmed in advance how much the threshold voltage shifts when channel doping is not performed, and in advance it is determined how much phosphorus needs to be added in order to obtain a desired threshold voltage. . Therefore, the dose does not have to be within the above range.

  At this time, since the crystalline silicon film 509 is very thin, if direct ion implantation is performed, the crystallinity is destroyed due to a great damage. In addition, when ion implantation is performed on a very thin film, it is very difficult to control the concentration of impurities.

  However, in this embodiment, since the through doping is performed through the buffer layer 510 described above, damage to the crystalline silicon film 509 during ion implantation can be suppressed. In addition, since the thick buffer layer 510 exists on the crystalline silicon film 509, the impurity concentration added to the crystalline silicon film 509 can be easily controlled.

  Further, the phosphorus concentration profile in the crystalline silicon film formed by ion implantation is adjusted so that the phosphorus concentration is lowered at the portion where the channel is formed (near the interface where the channel formation region and the gate insulating film are in contact). It is desirable. This effect will be described later.

  When the group 15 element is added to the region to be NTFT as described above, the resist mask 111 is removed, and the resist mask 113 is newly formed while hiding the region to be NTFT. Then, an element selected from group 13 (boron in this embodiment) is added to the region that will later become PTFT. The addition process may be referred to the previous phosphorus addition process. Of course, other than boron, gallium, indium, or the like can be used. (Fig. 5 (D))

  A boron-containing region 514 is formed in a region to be a PTFT by the process shown in FIG. Also in this case, as in the case of the group 15 element addition step, the buffer layer 510 reduces damage during ion implantation and facilitates concentration control.

  When the above impurity addition step is completed, the buffer layer 510 and the resist mask 513 are removed, and then active layers 515 and 516 are formed by patterning. Thereafter, excimer laser light is irradiated to recover the damage received in the ion implantation process and activate the added boron. (Fig. 5 (E))

Next, resist masks 517 and 518 are formed by performing backside exposure using the gate electrodes 503 and 504 as masks. Then, an impurity element imparting N-type (typically phosphorus or arsenic) is added to form low-concentration impurity regions 519 to 522 of about 1 × 10 ¹⁷ to 5 × 10 ¹⁸ atoms / cm ³ . (Fig. 6 (A))

Next, after removing the resist masks 517 and 518, patterning is performed again to form resist masks 523 and 524. At this time, the PTFT is completely covered. Then, an impurity element imparting N-type is added again at a higher concentration (about 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ ) than in FIG. 526 is formed.

  At this time, in the regions indicated by 527 and 528, the above-described low-concentration impurity regions remain as they are, and later function as LDD regions (Light Doped Drain). Further, a region indicated by 529 is a channel formation region. (Fig. 6 (B))

  Next, after removing the resist masks 523 and 524, resist masks 530 and 531 are formed so as to completely cover the NTFT.

Then, an impurity element imparting P-type (typically boron, gallium, indium) is added so as to have a concentration of about 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ , and the source region 532 of the PTFT, A drain region 533 is formed. A region indicated by 534 serves as a channel formation region. (Fig. 6 (C))

  Next, after removing the resist masks 530 and 531, irradiation with excimer laser light is applied to recover damage caused during ion implantation and activate the added impurities. (Fig. 6 (D))

  When the laser annealing is completed, an interlayer insulating film 535 is formed to a thickness of 300 to 500 nm. The interlayer insulating film 535 is formed of a silicon oxide film, a silicon nitride film, an organic resin film, or a laminated film thereof.

  Then, source electrodes 536 and 537 made of a metal thin film and an N common drain electrode 538 are formed thereon. As the metal thin film, aluminum, tantalum, titanium, tungsten, molybdenum, or a laminated film thereof may be used. The film thickness may be 100 to 300 nm. (Fig. 6 (E))

  Finally, the whole is subjected to heat treatment at 350 ° C. for about 2 hours in a hydrogen atmosphere, and the dangling bonds in the film (particularly in the channel formation region) are terminated with hydrogen. Through the above steps, a CMOS circuit having a structure as shown in FIG. 6E is completed.

  Note that the pixel TFT constituting the pixel matrix circuit is completed by forming an interlayer insulating film after the above steps and forming a pixel electrode electrically connected to the drain electrode thereon.

  In the present invention, a pixel matrix circuit and a drive circuit are configured by the inverted stagger type TFT manufactured by the above-described process. Note that the manufacturing process of this embodiment is merely an example for constituting the present invention, and the manufacturing method of an inverted staggered TFT that can be used in the present invention is not limited to this embodiment.

  Further, in this embodiment, channel doping is performed on NTFT and PTFT, but if not necessary, channel doping is not necessary.

  Even if channel doping is performed, another configuration may be employed in which channel doping is performed only on NTFT or PTFT only. In addition, the same conductivity type element may be added to both NTFT and PTFT. Further, the practitioner may appropriately determine whether the element to be added (group 15 element or group 13 element) needs to move the threshold voltage to the plus side or the minus side.

  In this embodiment, an example in which a semiconductor circuit using TFTs described in Japanese Patent Application Nos. 8-301249 and 8-301250 is used instead of an IC chip is shown.

  Since the TFTs described in Japanese Patent Application Nos. 8-301249 and 8-301250 have a very high operation speed, it is possible to construct a logic circuit which is conventionally constituted by an IC chip. In particular, if a silicon substrate is used as the substrate substrate, it can be handled like an IC chip.

  At this time, the bottom gate type TFT formed on the first substrate may be formed by any process. In this embodiment, a crystalline silicon film obtained by crystallizing an amorphous silicon film with an excimer laser is used as an active layer. Such a bottom gate type TFT can be manufactured by a known technique.

  FIG. 7 shows a simplified arrangement on the first substrate. In FIG. 7A, reference numeral 701 denotes a glass substrate (first substrate), on which a pixel matrix circuit 702 made of a bottom gate TFT formed by the above-described method and a source or gate driving circuit 703 are arranged. Is done. Reference numeral 704 denotes a semiconductor chip constituted by a TFT described in Japanese Patent Application Nos. 8-301249 and 8-301250, and is attached by a face-down COG method.

  FIG. 7B shows a case where the semiconductor chip 704 is attached by a face-down COG method. Reference numeral 705 denotes a bonding wire.

  In this embodiment, an example in which a manufacturing method different from that in Embodiment 5 is used for manufacturing an inverted staggered TFT on a first substrate will be described. Specifically, an example will be described in which a crystalline silicon film is formed by the technique described in Japanese Patent Laid-Open No. 7-130652, and the catalyst element used at that time is removed using the gettering effect by P (phosphorus). .

  First, in FIG. 8A, 801 is a glass substrate, 802 is a base film, 803 and 804 are gate electrodes made of an N-type polysilicon film, 805 is a gate insulating film, and 806 is an amorphous silicon film. is there. Any gate electrode can be used as long as it is the material shown in the fifth embodiment.

  In this embodiment, a film containing nickel (hereinafter referred to as a nickel-containing layer) 807 is formed on the amorphous silicon film 806. As a method for forming the nickel-containing layer 807, a technique described in Japanese Patent Laid-Open No. 7-130652 by the present inventors may be used. In addition, although both means of Example 1 and Example 2 of the gazette can be used, in consideration of productivity, the technique described in Example 1 of the gazette is used in this example. (Fig. 8 (A))

  In addition to nickel, the catalytic element is cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb). Gallium (Ga) or the like can be used.

  In the above publication, an example in which the catalyst element addition step is performed by a spin coating method is shown, but an ion implantation method or a plasma doping method can also be used. In this case, since the occupied area of the added region can be reduced and the growth distance of the lateral growth region can be easily controlled, this is an effective technique for configuring a miniaturized circuit.

  Next, after the catalyst element addition step is completed, after hydrogen removal at 500 ° C. for about 1 hour, a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) in an inert atmosphere, hydrogen atmosphere or oxygen atmosphere Then, the amorphous silicon film 806 is crystallized by applying heat treatment (furnace annealing) for 4 to 24 hours. In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to obtain a crystalline silicon film 808. (Fig. 8 (B))

  Next, a resist mask 809 having a plurality of openings is formed. This opening is formed at a position where a region that will not be used (removed) later as an active layer is exposed.

Next, phosphorus is added using the resist mask 809 as a mask. This adding step uses an ion implantation method or an ion doping method. The addition conditions are set such that the RF power is 20 W, the acceleration voltage is 5 to 30 keV (typically 10 keV), and the phosphorus dose is 1 × 10 ¹³ atoms / cm ² or more (preferably 5 × 10 ¹³ to 5 × 10 ¹⁵ atoms / cm ² ).

As a standard of the phosphorus concentration to be added, it is preferable to add a concentration one digit or more higher than the nickel concentration contained in the crystalline silicon film 808. Since the crystalline silicon film 808 contains about 1 × 10 ¹⁹ atoms / cm ³ of nickel, it is preferable to add phosphorus of about 1 × 10 ²⁰ atoms / cm ³ in that case.

  Thus, regions to which phosphorus is added (gettering regions) 810 to 812 are formed in part of the crystalline silicon film 808. (Fig. 8 (C))

  Next, after the resist mask 809 is removed, heat treatment for gettering nickel is performed. By this heat treatment, nickel contained in the gettering regions 813 and 814 is captured in the gettering regions 810 to 812 as indicated by arrows. (Fig. 8 (D))

  This heat treatment may be furnace annealing in an inert atmosphere, a hydrogen atmosphere, an oxidizing atmosphere, or an oxidizing atmosphere containing a halogen element. The treatment temperature may be 400 to 700 ° C. (preferably 550 to 650 ° C.), and the treatment time may be 2 hours or more (preferably 4 to 12 hours). The higher the processing temperature is, the shorter the time is required and the higher the gettering effect is. However, considering the heat resistance of the glass substrate, it is desirable to set it to 650 ° C. or lower.

  When nickel is gettered in the gettering regions 810 to 812 in this manner, the crystalline silicon film is patterned to form active layers 815 and 816 including only gettering regions 813 and 814. At this time, since the gettering regions 810 to 812 and the vicinity thereof contain nickel at a high concentration, it is desirable to completely remove them without using them for the active layer.

It was confirmed by SIMS (mass secondary ion analysis) that the nickel concentration in the active layers 815 and 816 obtained by the gettering process was reduced to 5 × 10 ¹⁷ atoms / cm ³ or less. Yes. (The concentration in this specification is defined by the minimum value of the SIMS measurement value.)

At present, it has only been found to be 5 × 10 ¹⁷ atoms / cm ³ or less due to the problem of the lower limit of detection, but in reality it is considered to have reached at least about 1 × 10 ¹⁴ atoms / cm ³ . Experimentally, it has been found that if the nickel concentration is 5 × 10 ¹⁷ atoms / cm ³ or less, the TFT characteristics are not affected.

  The state shown in FIG. 8E is obtained as described above. Thereafter, according to the process shown in Embodiment 5, a CMOS circuit having a structure as shown in FIG. 6E can be manufactured. Of course, the technique of this embodiment can also be applied to the pixel TFT constituting the pixel matrix circuit.

  In this embodiment, an example in which an ion implantation method or an ion doping method is used as a means for adding phosphorus is shown. An annealing in an atmosphere containing phosphorus (vapor phase method), a getter into an insulating film containing phosphorus. A ring (solid phase method) may be used.

  In the present invention, an image sensor using an inverted staggered TFT as a switching element can be formed in a part of the liquid crystal module having the structure shown in the first embodiment. The image sensor includes a TFT portion and a photoelectric conversion portion.

  With the configuration as in this embodiment, it is possible to realize a system panel in which an image sensor is built in the liquid crystal panel itself, and the effects of the present invention are more remarkably exhibited. In this case, it is also effective to incorporate a control circuit for controlling the image sensor in the IC chip.

  The present invention can also be applied to an EL display device using an EL material (organic EL, inorganic EL) as an electro-optic modulation layer. Since the EL display device is a self-luminous element, it has advantages such as high brightness and high viewing angle, and is suitable for use as a direct-view display.

  The present invention is intended to improve the portability and functionality of the electro-optical device and the electronic apparatus using the electro-optical device. Therefore, when the present invention is applied to a direct-view display, a remarkable invention effect can be obtained.

  In this embodiment, a configuration example of an IC chip mounted on the electro-optical device according to the present invention will be described with reference to a block diagram shown in FIG. The area surrounded by the dotted line is the system configuration of the IC chip. Further, in this embodiment, an example of a circuit in which an analog signal is digitally processed and converted into an analog signal and transmitted to a liquid crystal panel is shown.

  Analog signals transmitted from the outside are an R signal 11, a G signal 12, a B signal 13, a horizontal synchronization signal 14, and a vertical synchronization signal 15. The RGB signals 11 to 13 are output as analog signals through an A / D converter 16, a VRAM 17 (time axis expansion), a γ correction + polarity inversion circuit 18, and a D / A converter 19.

  Meanwhile, the clock generator 20 generates clock pulses and start pulses corresponding to XGA, SXGA, etc. based on the horizontal synchronization signal 14 and the vertical synchronization signal 15, and the A / D converter 16, VRAM 17, γ correction + polarity inversion circuit 18, etc. Sent to. The clock generator 20 is controlled by the control microcomputer 21.

  Thus, the R signal 22, the G signal 23, and the B signal 24 are output as analog signals that have undergone the necessary processing. A source driving circuit 25, a gate driving circuit 26, and a pixel matrix circuit 27 are formed on the liquid crystal panel with TFTs, and the aforementioned R signal 22, G signal 23, and B signal 24 are sent to the source driving circuit 25.

  In this embodiment, a configuration example of an IC chip mounted on the electro-optical device according to the present invention will be described with reference to a block diagram shown in FIG. This embodiment shows an example of a circuit for transmitting an analog signal as it is to a liquid crystal panel.

  Since the basic configuration has already been described in the tenth embodiment, only differences from the tenth embodiment will be described.

  Analog signals (R signal 11, G signal 12, and B signal 13) transmitted from the outside are output through an amplifier circuit 30, a γ correction + polarity inversion circuit 18, a sample hold 31, and a buffer amplifier 32. In this way, the R signal 33, the G signal 34, and the B signal 35 are output as analog signals that have undergone necessary processing. These signals are sent to the source drive circuit 25.

  In this embodiment, a configuration example of an IC chip mounted on the electro-optical device according to the present invention will be described with reference to a block diagram shown in FIG. This embodiment shows an example of a circuit for transmitting a digital signal as it is to a liquid crystal panel.

  The R signal 40, the G signal 41, and the B signal 42 are digital signals corresponding to, for example, 6 to 8 bits. The RGB signals 40 to 42 are subjected to necessary processing by the VRAM 43 and the γ correction circuit 44, and are transmitted to the source driving circuit 48 as an R signal 45, a G signal 46, and a B signal 47. In the case of the present embodiment, the source drive circuit 48 needs to have a circuit configuration corresponding to a digital signal.

  In this embodiment, a configuration example of an IC chip mounted on the electro-optical device according to the present invention will be described with reference to a block diagram shown in FIG. This embodiment shows a circuit example in which a digital signal is once processed and then transmitted to a liquid crystal panel.

  Since the basic configuration has already been described in the twelfth embodiment, only the differences will be described in the present embodiment.

  The digitized RGB signals 40 to 42 are first subjected to correction calculation processing by a DSP (digital signal processor) 50. At this time, the correction data is stored in the flash memory 51 and is read out as needed.

  Then, the corrected video signal is processed by the VRAM 43 and the γ correction circuit 44 and is transmitted to the source drive circuit 48 as an R signal 52, a G signal 53, and a B signal 54.

  In this embodiment, a configuration example of a process of forming RGB signals to be input to the system configuration shown in Embodiments 10 to 13 will be described with reference to a block diagram shown in FIG. The circuit configuration of this embodiment can also be mounted on a liquid crystal panel substrate by making it into one chip.

  As shown in FIG. 13A, the NTSC signal 60 is separated into a Y (luminance) signal 62 and a C (color) signal 63 by a YC separation circuit 61. These signals are separated into an R signal 65, a G signal 66, and a B signal 67 by an RGB separation circuit 64. Here, a horizontal synchronizing signal 68 and a vertical synchronizing signal 69 are formed.

  Note that other TV standard signals such as PAL signals are processed by a circuit having a similar configuration and sent to the liquid crystal panel.

  Further, as shown in FIG. 13B, signals from a laser disk and BS (satellite broadcast) are sent as a Y (luminance) signal 70 and a C (color) signal 71. This is processed by the RGB separation circuit 64 and separated into an R signal 72, a G signal 73, and a B signal 74. In addition, a horizontal synchronizing signal 75 and a vertical synchronizing signal 76 are also formed.

  These RGB signals and horizontal / vertical synchronizing signals are transmitted to the respective system circuits shown in the tenth to thirteenth embodiments, sent to the driving circuit of the liquid crystal panel, and restored as an image by the pixel matrix circuit.

  In this embodiment, a configuration example of a process of forming RGB signals to be input to the system configuration shown in the embodiments 10 to 13 will be described with reference to a block diagram shown in FIG. In the present embodiment, unlike the fourteenth embodiment, an example of a circuit configuration for supporting digital broadcasting in the United States or the like (corresponding to ATV) is shown.

  The video signal 80 is a signal obtained by performing various frequency conversion processes on the video signal received from the antenna. This signal is modulated to the original frequency by a VSB (or QAM) demodulation circuit. Then, it is returned to the signal encoded by the transport decoder 82.

  The signal processed in this way is input to MPEG2 (decoder) 83 to expand the frequency band. Then, the format conversion circuit 84 generates a desired format signal, and further forms an R signal 85, a G signal 86, a B signal 87, a horizontal synchronizing signal 88, and a vertical synchronizing signal 89.

  Since digital signals are handled so far, a D / A converter (not shown) may be provided after the format conversion circuit 84 when it is finally desired to obtain an analog signal.

  The video signal obtained as described above is processed by the systems shown in the tenth to thirteenth embodiments. Up to that point is performed by an IC chip, and a video signal processed on the IC chip may be sent to a source / gate drive circuit formed on a substrate by TFT.

  In this embodiment, a manufacturing process (multi-chamfering process) in the case of taking out a plurality of liquid crystal panels from a large substrate will be described with reference to FIG. In this embodiment, a case where four liquid crystal panels are manufactured from a large-sized square substrate is taken as an example.

  FIG. 15A shows a process of dividing a large substrate of the same size bonded together in the cell assembling process. In FIG. 15A, reference numeral 1501 denotes a sealing material (sealing material), and a liquid crystal material is sealed inside this enclosure. In this embodiment, first, as shown in FIG. 15A, the surface on which the liquid crystal inlet 1502 is formed is divided by a scriber.

  A scriber is an apparatus that divides a substrate by forming a thin groove (scribe groove) on the substrate and then applying a small impact to the substrate to generate a crack along the groove.

  In addition, a dicer is known as an apparatus for dividing the substrate. A dicer is an apparatus that divides a substrate by rotating a hard cutter (dicing saw) at high speed. However, when using a dicer, it is necessary to spray a large amount of water in order to suppress heat and polishing powder, so in the state shown in FIG. 15A where the liquid crystal injection port is empty, water enters the liquid crystal injection port. Can not.

  By the way, in the step of FIG. 15A, since the scribe groove is formed in the vicinity of the substrate surface, the first substrate side (substrate on which TFT is manufactured) 1503 and the second substrate side (substrate on the opposite side) 1504 are formed. Divide with a scribe groove. This will be described with reference to FIGS. 15B and 15C.

  FIG. 15B is a view of FIG. 15A viewed from the direction indicated by the arrow. First, as indicated by arrows in FIG. 15B, scribe grooves 1505 to 1508 are formed from both surfaces of the first substrate 1503 side and the second substrate 1504 side.

  At this time, as shown in FIG. 15B, the scribe groove 1508 formed in the first substrate 1503 and the scribe groove 1506 formed in the second substrate 1504 are aligned. By doing so, the configuration of the present invention (configuration in which end faces are aligned) is realized.

  At this time, scribe grooves 1505 and 1507 are formed only on the second substrate 1504. In this way, only part of the second substrate 1504 can be partially removed. As a result, a part of the first substrate 1503 is exposed.

  When the formation of the scribe groove as described above is completed, cutting is performed by cutting to obtain the state shown in FIG. The portion 1509 where the first substrate 1503 is exposed is used as a portion for attaching the FPC and the IC chip.

  In addition, the fact that the end face on the side where the liquid crystal injection port 1502 is formed is aligned between the first substrate and the second substrate as in this embodiment leads to a reduction in manufacturing cost. This is because if the end faces are aligned, the liquid crystal injection port can be made to come into contact with the liquid crystal surface in the subsequent liquid crystal injection process, so that the liquid level of the liquid crystal to be prepared can be minimized. That is, since the liquid crystal can be used efficiently, it greatly contributes to cost reduction.

  In this way, the two liquid crystal panels are divided into two substrates. Next, a liquid crystal material injection / sealing process is performed on each of the two substrates. Since this process may follow a well-known process, description is abbreviate | omitted.

  At this time, it is possible to inject a liquid crystal material into two liquid crystal panels at a time. Of course, it is also possible to batch-process two substrates at the same time and inject the liquid crystal material into four liquid crystal panels at a time.

  When the liquid crystal material injecting step and the sealing material sealing step are completed as described above, next, cutting with a dicer is performed along the direction shown in FIG. In addition, since the liquid crystal material 1510 is sealed in the previous process, a dicer can be used in this dividing process. Reference numeral 1511 denotes a sealing material for sealing the liquid crystal material.

  Advantages of using the dicer include that the cutting error is lower than that of the scriber and that the yield is high, and that the first substrate and the second substrate can be divided at a time, so that the throughput can be improved.

  The four liquid crystal panels are individually divided by the dividing process as described above. Since this dividing step may be performed collectively with a dicer, there is no inconvenience of having to scribe from both sides of the substrate like a scriber.

  In the present invention, since the end face of the first substrate and the end face of the second substrate are aligned on all end faces other than the end face adjacent to the portion to which the IC chip is attached, the liquid crystal panel dividing step shown in FIG. Ends.

  By the way, in the present embodiment, the division by the scriber and the division by the dicer are separately used in the dividing step, but the following attention is required for the proper use.

  First, when using a scriber, an impact is applied to the scribe groove to generate a crack, and the substrate is divided along the crack, so that stress is easily applied to an element (TFT or the like) formed on the substrate at the time of division. Stress applied to the element is not preferable because it may cause deterioration of element characteristics.

  Therefore, when a circuit that requires a high operating speed is formed in the vicinity of the dividing plane, it is preferable to perform the cutting by the dicer while avoiding the cutting by the scriber because the stress has a very bad influence. In other words, use a dicer as much as possible to divide the vicinity of a circuit that is susceptible to stress, and use a scriber only to divide the vicinity of a circuit where the influence of stress does not appear so much. Is desirable.

  Further, for example, a drive circuit formed with TFTs on a substrate is not easily stressed when covered with a liquid crystal material. Therefore, when a drive circuit is formed in a region surrounded by a sealing material that encloses liquid crystal, stress is hardly transmitted even if a scriber is used. If a dicer is used, the liquid crystal layer is disposed only on the pixel matrix circuit and the liquid crystal layer does not exist on the drive circuit, so that it is difficult to receive stress at the time of division.

  As described above, it is very effective to selectively use the division by the scriber and the division by the dicer depending on what kind of circuit is arranged in the vicinity of the substrate surface to be divided. In the case of using the scriber and the dicer properly as in the present embodiment, such attention is very significant.

  The liquid crystal module of the present invention is used as a display for various electronic devices. Note that the electronic apparatus described in this embodiment is defined as a product on which an electro-optical device typified by a liquid crystal module is mounted.

  Examples of such an electronic device include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer, a personal digital assistant (mobile computer, mobile phone, etc.), and the like. An example of them is shown in FIG.

  FIG. 17A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the display device 2004 and the like.

  FIG. 17B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102.

  FIG. 17C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and the like.

  FIG. 17D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.

  FIG. 17E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

  FIG. 17F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In particular, it can be said that it is very effective for an electronic device that places importance on portability.

  For example, since various signal processing can be performed by the IC chip, practically most functions of the electronic device are performed only by the liquid crystal module. That is, an electronic device such as a card type mobile computer can be realized.

The figure which shows the structure of a liquid crystal module. The figure which shows the structure of a liquid crystal module. The figure which shows the enlarged view of the circuit which comprises a liquid crystal module. The figure which shows the enlarged view of the circuit which comprises a liquid crystal module. 10A and 10B show a manufacturing process of a bottom gate type TFT. 10A and 10B show a manufacturing process of a bottom gate type TFT. The figure for demonstrating the cross-section of a liquid crystal module. 10A and 10B show a manufacturing process of a bottom gate type TFT. The figure which shows the system configuration | structure of a liquid crystal module. The figure which shows the system configuration | structure of a liquid crystal module. The figure which shows the system configuration | structure of a liquid crystal module. The figure which shows the system configuration | structure of a liquid crystal module. The figure which shows the system configuration | structure of a liquid crystal module. The figure which shows the system configuration | structure of a liquid crystal module. The figure for demonstrating the parting process in the case of multi-chamfering. The figure for demonstrating the parting process in the case of multi-chamfering. FIG. 10 illustrates an example of an electronic device.

Explanation of symbols

101 First substrate 102 Pixel matrix circuit 103 Source drive circuit 104 Gate drive circuit 105 Second substrate 106 FPC
107-109 End face 110, 111 IC chip

Claims (5)

A plurality of first substrates, a second substrate provided opposite to the first substrate, and a first side surface to a fourth side surface formed by dividing the first substrate. A third substrate, a plurality of fourth substrates having first to fourth sides formed by dividing the second substrate, the third substrate, and the fourth substrate; A method of manufacturing an electro-optical device having a sealing material provided between
The first side surface of the third substrate and the first side surface of the fourth substrate are separated using a scriber to divide the first side surface of the third substrate and the first side surface of the fourth substrate. A liquid crystal injection port is formed between the first side surface of the four substrates,
Dividing the third side surface of the fourth substrate using a scriber so as to expose a part of the upper surface adjacent to the third side surface of the third substrate;
Injecting liquid crystal material from the liquid crystal injection port,
Sealing the liquid crystal inlet;
Dividing the second side surface of the third substrate and the second side surface of the fourth substrate using a dicer,
Dividing the fourth side surface of the third substrate and the fourth side surface of the fourth substrate using a dicer,
A method of manufacturing an electro-optical device, wherein an FPC and an IC chip are attached to an upper surface adjacent to the third side surface of the third substrate. A plurality of first substrates, a second substrate provided opposite to the first substrate, and a first side surface to a fourth side surface formed by dividing the first substrate. A third substrate, a plurality of fourth substrates having first to fourth sides formed by dividing the second substrate, the third substrate, and the fourth substrate; A method of manufacturing an electro-optical device having a sealing material provided between
The first side surface of the third substrate and the first side surface of the fourth substrate are separated using a scriber to divide the first side surface of the third substrate and the first side surface of the fourth substrate. A liquid crystal injection port is formed between the first side surface of the four substrates,
Dividing the third side surface of the fourth substrate using a scriber so as to expose a part of the upper surface adjacent to the third side surface of the third substrate;
Injecting liquid crystal material from the liquid crystal injection port,
Sealing the liquid crystal inlet;
Dividing the second side surface of the third substrate and the second side surface of the fourth substrate using a dicer,
Dividing the fourth side surface of the third substrate and the fourth side surface of the fourth substrate using a dicer,
An FPC is attached to an upper surface adjacent to the third side surface of the third substrate,
A method for manufacturing an electro-optical device, wherein an IC chip is attached to an upper surface adjacent to the third side surface of the third substrate by a COG method. A plurality of first substrates, a second substrate provided opposite to the first substrate, and a first side surface to a fourth side surface formed by dividing the first substrate. A third substrate, a plurality of fourth substrates having first to fourth sides formed by dividing the second substrate, the third substrate, and the fourth substrate; A method of manufacturing an electro-optical device having a sealing material provided between
The first side surface of the third substrate and the first side surface of the fourth substrate are separated using a scriber to divide the first side surface of the third substrate and the first side surface of the fourth substrate. A liquid crystal injection port is formed between the first side surface of the four substrates,
Dividing the third side surface of the fourth substrate using a scriber so as to expose a part of the upper surface adjacent to the third side surface of the third substrate;
Injecting liquid crystal material from the liquid crystal injection port,
Sealing the liquid crystal inlet;
Dividing the second side surface of the third substrate and the second side surface of the fourth substrate using a dicer,
Dividing the fourth side surface of the third substrate and the fourth side surface of the fourth substrate using a dicer,
An FPC is attached to an upper surface adjacent to the third side surface of the third substrate,
An electro-optical device manufacturing method, wherein an IC chip is attached to an upper surface adjacent to the third side surface of the third substrate by a TAB method. A plurality of first substrates, a second substrate provided opposite to the first substrate, and a first side surface to a fourth side surface formed by dividing the first substrate. A third substrate, a plurality of fourth substrates having first to fourth sides formed by dividing the second substrate, the third substrate, and the fourth substrate; A method of manufacturing an electro-optical device having a sealing material provided between
The first side surface of the third substrate and the first side surface of the fourth substrate are separated using a scriber to divide the first side surface of the third substrate and the first side surface of the fourth substrate. A liquid crystal injection port is formed between the first side surface of the four substrates,
Dividing the third side surface of the fourth substrate using a scriber so as to expose a part of the upper surface adjacent to the third side surface of the third substrate;
Injecting liquid crystal material from the liquid crystal injection port,
Sealing the liquid crystal inlet;
Dividing the second side surface of the third substrate and the second side surface of the fourth substrate using a dicer,
Dividing the fourth side surface of the third substrate and the fourth side surface of the fourth substrate using a dicer,
An FPC is attached to an upper surface adjacent to the third side surface of the third substrate,
A method of manufacturing an electro-optical device, comprising attaching a TCP having an IC chip mounted on an upper surface adjacent to the third side surface of the third substrate.   5. The first side surface, the second side surface, and the fourth side surface of the third substrate according to claim 1, wherein the first substrate has the first side surface. A method of manufacturing an electro-optical device, wherein a side surface, the second side surface, and the fourth side surface are aligned with each other.

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