JP4193901B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP4193901B2
JP4193901B2 JP2007000036A JP2007000036A JP4193901B2 JP 4193901 B2 JP4193901 B2 JP 4193901B2 JP 2007000036 A JP2007000036 A JP 2007000036A JP 2007000036 A JP2007000036 A JP 2007000036A JP 4193901 B2 JP4193901 B2 JP 4193901B2
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circuit device
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義信 外山
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Seiko Epson Corp
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    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2924/14—Integrated circuits

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Description

本発明は、ダミーパターンが含まれる多層配線を有する半導体集積回路装置に関し、特にパッド構造周辺の信頼性対策に適用される。   The present invention relates to a semiconductor integrated circuit device having a multilayer wiring including a dummy pattern, and is particularly applied to a reliability measure around a pad structure.

コンパクト化が要求される携帯機器等に組込まれる半導体集積回路装置は、実装場所の制約が厳しくよりいっそうの縮小化が要求されている。ＩＣチップは素子の高集積化に伴い、より多層配線構造となる。各層の平坦化にはＣＭＰ（化学的機械的研磨）技術が取り入れられるチップもあるが製造コストが高くなる懸念がある。   A semiconductor integrated circuit device incorporated in a portable device or the like that is required to be compact is severely restricted in a mounting place, and is required to be further reduced. IC chips have a multi-layer wiring structure as the elements are highly integrated. Although there is a chip in which CMP (Chemical Mechanical Polishing) technology is adopted for planarizing each layer, there is a concern that the manufacturing cost becomes high.

より低コスト化のためＣＭＰ以外の方策がとられる多層配線構造としては、各層の平坦化向上のため実配線パターンに加えてダミーパターンが導入されている構成も少なくない。この場合、パッド形成領域下にもダミーパターンが形成される。例えば、ｎ層で構成されるアルミニウム配線層によるパッドの形成では、パッド領域直下にｎ−１層でなるアルミニウム配線層によるダミーパターンの形成が存在する。ダミーパターンはアルミニウム配線層各層でパッド領域下に設けられ、最上層ｎ層におけるパッドとビアを介して接続される構造もある。   As a multilayer wiring structure in which measures other than CMP are taken for further cost reduction, there are not a few configurations in which dummy patterns are introduced in addition to actual wiring patterns in order to improve planarization of each layer. In this case, a dummy pattern is also formed under the pad formation region. For example, in the formation of a pad by an aluminum wiring layer constituted by n layers, there is a formation of a dummy pattern by an aluminum wiring layer constituted by n−1 layers immediately under the pad region. There is also a structure in which the dummy pattern is provided below the pad region in each layer of the aluminum wiring layer, and is connected to the pad in the uppermost n layer through a via.

上述のように、配線層と接続されるパッドの構造では、パッド領域直下の配線層、さらにその下の配線層においてもそれぞれダミーパターンを延在させ、層間絶縁膜の平坦性に優れた多層配線構造を実現していた。   As described above, in the structure of the pad connected to the wiring layer, the dummy pattern is extended in the wiring layer immediately below the pad region and also in the wiring layer below it, and the multilayer wiring excellent in the flatness of the interlayer insulating film The structure was realized.

しかしながら、上記構成ではパッドへのボンディング、例えばワイヤボンディングやスタッドバンプ形成時の衝撃、あるいは通常の金属バンプに対するリード圧着による衝撃に弱い欠点がある。これはＳｉＯ２層間絶縁膜に対しダミーパターン金属（アルミニウム）の硬度が低いため上記のような衝撃に変形し易いためである。結局、硬度が不均一となりパッド直下の層間絶縁膜でクラックが発生するという危険性があった。 However, the above configuration has a drawback that it is vulnerable to bonding to the pad, for example, impact during wire bonding or stud bump formation, or impact due to lead pressure bonding to a normal metal bump. This is because the dummy pattern metal (aluminum) has a low hardness with respect to the SiO 2 interlayer insulating film, and thus is easily deformed by the impact as described above. Eventually, there was a risk that the hardness would be uneven and cracks would occur in the interlayer insulating film directly under the pad.

本発明は上記のような事情を考慮してなされたもので、ボンディング等、パッドへの圧力によるクラック発生を回避する半導体集積回路装置を提供しようとするものである。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device that avoids the occurrence of cracks due to pressure on the pads, such as bonding.

本発明の［請求項１］に係る半導体集積回路装置は、
半導体素子回路を構成する配線パターン及びダミーパターンが含まれる複数の配線層を有する半導体集積回路装置であって、
前記配線層の最上層ｎ層に形成された金属パッドと、
前記金属パッドの直下の（ｎ−１）層に形成された、前記ダミーパターンが形成されないダミーパターン禁止領域と、を具備し、
前記ダミーパターンは、前記金属パッドの直下で、かつ、少なくとも前記（ｎ−１）層より下の領域に形成されていることを特徴とする。
A semiconductor integrated circuit device according to [Claim 1] of the present invention includes:
A semiconductor integrated circuit device having a plurality of wiring layers including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A metal pad formed on the uppermost n layer of the wiring layer ;
The metal pads directly below the (n-1) layer formed, anda dummy pattern prohibition region in which the dummy pattern is not formed,
The dummy patterns are just below the metal pad, and characterized in that it is formed in the region below at least the (n-1) layer.

上記本発明に係る半導体集積回路装置によれば、少なくとも金属パッド形成領域直下はダミーパターン禁止領域となっている。ボンディング時の衝撃はダミーパターン禁止領域上を埋める層間絶縁膜にかかり、硬度の均一化によるクラック防止に寄与する。   According to the semiconductor integrated circuit device of the present invention, at least a region immediately below the metal pad forming region is a dummy pattern prohibited region. The impact at the time of bonding is applied to the interlayer insulating film filling the dummy pattern prohibited area, and contributes to prevention of cracks due to uniform hardness.

本発明の［請求項２］に係る半導体集積回路装置は［請求項１］に従属され、
前記ダミーパターン禁止領域は、前記（ｎ−１）層を含む１層置きに形成されることを特徴とする半導体集積回路装置。
A semiconductor integrated circuit device according to [Claim 2] of the present invention is dependent on [Claim 1],
2. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern prohibited area is formed every other layer including the (n-1) layers.

本発明の［請求項３］に係る半導体集積回路装置は［請求項１］に従属され、
前記ダミーパターン禁止領域は、前記（ｎ−１）層を含む所定数置きに形成されることを特徴とする。
A semiconductor integrated circuit device according to [Claim 3] of the present invention is dependent on [Claim 1],
The dummy pattern forbidden regions are formed every predetermined number including the (n-1) layers.

本発明の［請求項４］に係る半導体集積回路装置は、
半導体素子回路を構成する配線パターン及びダミーパターンが含まれる複数の配線層を有する半導体集積回路装置であって、
前記配線層の最上層ｎ層に形成された金属パッドと、
前記金属パッドの直下の（ｎ−１）層を含む所定距離の範囲内に形成された、前記ダミーパターンが形成されないダミーパターン禁止領域と、
を具備し、
前記ダミーパターンは、前記金属パッドの直下の（ｎ−１）層を含む所定距離の範囲外に形成されていることを特徴とする。
A semiconductor integrated circuit device according to [Claim 4] of the present invention is
A semiconductor integrated circuit device having a plurality of wiring layers including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A metal pad formed on the uppermost n layer of the wiring layer ;
A dummy pattern prohibition region in which the metal pad directly below the (n-1) layer formed within a predetermined distance including the dummy pattern is not formed,
Comprising
The dummy pattern is characterized by being formed out of the range of the predetermined distance including the (n-1) layer immediately below the metal pad.

上記［請求項２］〜［請求項４］それぞれに係る半導体集積回路装置によれば、金属パッドの領域直下またはその周辺には、ダミーパターンという硬度の低い層を混在させることなく、層間絶縁膜のみ存在させ、ボンディング衝撃に変形を起こし難い構造を実現する。より多層の配線となる場合、層間絶縁膜の平坦性を向上させるために間引きした形でダミーパターンを挿入する。   According to the semiconductor integrated circuit device according to each of the above-mentioned [Claim 2] to [Claim 4], an interlayer insulating film is formed without mixing a layer having a low hardness called a dummy pattern directly under or around the metal pad region. The structure that hardly causes deformation in the bonding impact is realized. In the case of a multilayer wiring, a dummy pattern is inserted in a thinned form in order to improve the flatness of the interlayer insulating film.

本発明の［請求項５］に係る駆動装置は［請求項１］〜［請求項４］いずれか一つに従属され、
前記半導体集積回路装置を備えることを特徴とする。
The drive device according to [Claim 5] of the present invention is dependent on any one of [Claim 1] to [Claim 4],
The semiconductor integrated circuit device is provided.

図１、図２は、それぞれ本発明の基本的実施形態に係る半導体集積回路装置の要部を示す平面図及び図１のＦ２−Ｆ２線に断面図である。内部回路側では半導体素子回路を構成する金属配線パターンＷＰが層間絶縁膜ＩＬ及びビアＶＩＡを介して多層配線構造を実現している。これら多層配線構造中には必要箇所にダミーパターンＤＰが含まれる。   FIG. 1 and FIG. 2 are a plan view showing a main part of a semiconductor integrated circuit device according to a basic embodiment of the present invention and a sectional view taken along line F2-F2 in FIG. On the internal circuit side, the metal wiring pattern WP constituting the semiconductor element circuit realizes a multilayer wiring structure through the interlayer insulating film IL and the via VIA. In these multilayer wiring structures, dummy patterns DP are included at necessary places.

このような多層配線の延長上の金属パッドＰＡＤ形成領域直下にはダミーパターン禁止領域ＰＲＯＨが設けられている。すなわち、ダミーパターン禁止領域ＰＲＯＨ上に層間絶縁膜ＩＬを介して半導体素子回路に繋がり外部との電気的接続領域を有する金属パッドＰＡＤが設けられている。   A dummy pattern inhibition region PROH is provided immediately below the metal pad PAD formation region on the extension of the multilayer wiring. That is, a metal pad PAD having an electrical connection region connected to the semiconductor element circuit via the interlayer insulating film IL is provided on the dummy pattern prohibition region PROH.

ＰＡＤ下周辺の所定距離ｄ１の範囲内はすべて層間絶縁膜ＩＬで埋められた構成となっている。金属パッドＰＡＤを囲む最上層はパッシベーション膜ＰＦであり、単層の絶縁膜または積層の絶縁膜で構成される。金属パッドＰＡＤは複数配列されるものであり、隣接するＰＡＤが所定距離ｄ１の範囲内に設けられれば当然ダミーパターン禁止領域ＰＲＯＨは金属パッドＰＡＤ配列直下に連続して設けられることになる。   The entire area within the predetermined distance d1 around the bottom of the PAD is filled with the interlayer insulating film IL. The uppermost layer surrounding the metal pad PAD is a passivation film PF, which is composed of a single-layer insulating film or a stacked insulating film. A plurality of metal pads PAD are arranged, and if adjacent PADs are provided within the range of the predetermined distance d1, the dummy pattern prohibited region PROH is naturally provided continuously immediately below the metal pad PAD arrangement.

上記実施形態の構成によれば、少なくとも金属パッドＰＡＤ形成領域直下はダミーパターン禁止領域ＰＲＯＨとなっている。ＰＡＤ下周辺の所定距離ｄ１の範囲内がすべて層間絶縁膜ＩＬで埋められている。金属パッドＰＡＤへのボンディング時の衝撃はダミーパターン禁止領域ＰＲＯＨ上を埋める層間絶縁膜ＩＬにかかる。   According to the configuration of the above embodiment, at least a region immediately below the metal pad PAD formation region is the dummy pattern prohibited region PROH. The entire area within the predetermined distance d1 around the lower part of the PAD is filled with the interlayer insulating film IL. The impact at the time of bonding to the metal pad PAD is applied to the interlayer insulating film IL filling the dummy pattern prohibited region PROH.

上述の衝撃とは、図示しないＰＡＤへのワイヤボンディングまたはスタッドバンプの形成、さらにはバンプ電極形成後の外部端子接続に伴う衝撃が含まれる。このような衝撃に対し、かかる層間絶縁膜ＩＬは硬度が均一化されているためクラックがほとんど発生しなくなる。   The above-mentioned impact includes an impact associated with wire bonding or stud bump formation on a PAD (not shown), and connection with an external terminal after bump electrode formation. In response to such an impact, the interlayer insulating film IL has a uniform hardness so that almost no cracks are generated.

なお、図に示すように、最上ｎ層の配線層でパッドＰＡＤが形成されている場合、ＰＡＤ直下においてｎ−１層の配線層によるダミーパターンは禁止されている形態（ダミーパターン禁止領域ＰＲＯＨ）となっているが、ｎ−１層より下の所定配線層についてはダミーパターンＤＰを配した構成としてもよい。   As shown in the figure, when the pad PAD is formed in the uppermost n wiring layers, dummy patterns by the n-1 wiring layers are prohibited immediately below the PAD (dummy pattern prohibited region PROH). However, for the predetermined wiring layer below the n−1 layer, a configuration in which a dummy pattern DP is disposed may be employed.

例えば破線で示すように、金属パッドＰＡＤ下の領域においてｎ−１層より下の所定の各配線層で１層置きに間引きしてダミーパターンＤＰを設けることも考えられる。これは、より層数の多い配線層構造では平坦性向上のためにダミーパターンの形成が有用だからである。   For example, as indicated by a broken line, dummy patterns DP may be provided by thinning out every other layer in a predetermined wiring layer below the n−1 layer in the region below the metal pad PAD. This is because the formation of a dummy pattern is useful for improving the flatness in a wiring layer structure having a larger number of layers.

もちろんその他の構成でｎ−１層より下の各配線層についてＰＡＤ下の領域にダミーパターンを設けてもよい。また、配線層数が少なく、平坦性が良好に保てるならば、パッドの領域下方ｎ−１層の配線層はもとよりすべてにおける多層配線の形成層についてパッドの領域下方はダミーパターン禁止領域ＰＲＯＨとしてもよい。   Of course, a dummy pattern may be provided in a region below the PAD for each wiring layer below the n−1 layer in other configurations. Further, if the number of wiring layers is small and the flatness can be kept good, the n-1 layer wiring layer below the pad region as well as all the multilayer wiring forming layers below the pad region can be used as the dummy pattern prohibited region PROH. Good.

図３は、本発明の一実施形態に係る半導体集積回路装置としてＬＣＤドライバＩＣチップの要部構成を示す平面図である。ＬＣＤドライバ（液晶表示駆動装置）ＩＣチップは、微細ピッチの端子配列を持つ短冊状のチップである。実装技術には、ワイヤボンディングの他、ＴＣＰ（Tape Carrier Package）等に利用されるＴＡＢ（Tape Automated Bonding）実装や、ＡＣＦ（Anisotropic Conductive Film ）等を利用して達成されるようなＣＯＧ（Chip On Glass ）またはＣＯＦ（Chip On FilmまたはFlexible）といった実装が知られている。これら接続時にはいずれも相当の圧力がかかる。   FIG. 3 is a plan view showing the main configuration of an LCD driver IC chip as a semiconductor integrated circuit device according to an embodiment of the present invention. An LCD driver (liquid crystal display driving device) IC chip is a strip-shaped chip having a fine pitch terminal arrangement. As the mounting technology, in addition to wire bonding, TAB (Tape Automated Bonding) mounting used for TCP (Tape Carrier Package) or the like, COG (Chip On) achieved by using ACF (Anisotropic Conductive Film), etc. Implementations such as Glass) or COF (Chip On Film or Flexible) are known. A considerable pressure is applied at the time of these connections.

ＬＣＤドライバＩＣチップ１０は、データが入力される入力回路１１、ＲＡＭ（Random Access Memory）等で構成される記憶部１２、データ処理部としてゲートアレイ等で形成されるロジック回路１３、及びラッチ回路を含み信号出力をする出力回路１４等が相関するように構成された内部の半導体素子回路を有している。   The LCD driver IC chip 10 includes an input circuit 11 to which data is input, a storage unit 12 including a RAM (Random Access Memory), a logic circuit 13 formed of a gate array as a data processing unit, and a latch circuit. The output circuit 14 for outputting a signal including the signal includes an internal semiconductor element circuit configured to be correlated.

入力パッド１５、出力パッド１６は上記入力回路１１中、あるいは出力回路１４中の一部のトランジスタ素子（図示せず）と繋がるよう層間絶縁膜（図示せず）を介して構成されている。これらパッド１５，１６の配列領域直下の配線層についてはダミーパターンを設けないダミーパターン禁止領域ＰＲＯＨとなっている（図１参照）。   The input pad 15 and the output pad 16 are configured via an interlayer insulating film (not shown) so as to be connected to a part of the transistor elements (not shown) in the input circuit 11 or the output circuit 14. The wiring layer immediately below the arrangement region of the pads 15 and 16 is a dummy pattern prohibited region PROH in which no dummy pattern is provided (see FIG. 1).

これにより、ボンディング時の衝撃に耐え得るようパッド１５，１６の配列領域周辺の所定距離範囲（例えば図２のｄ１）内はすべて層間絶縁膜で埋められた構成となる。その他の内部回路側は原則的にダミーパターン禁止領域ＰＲＯＨは設けない。各配線層で必要な箇所にダミーパターンが設けられることになる。また、パッド１５，１６の配列領域下方における所定距離ｄ１範囲以外の配線層では１層置きにダミーパターンを形成するなどの平坦化対策を工夫してよい。なお、このダミーパターン禁止領域ＰＲＯＨはチップ領域周囲の防湿リング（ガードリング）の形成に支障ないように設けるべきである。   As a result, a predetermined distance range (for example, d1 in FIG. 2) around the arrangement region of the pads 15 and 16 is filled with the interlayer insulating film so as to withstand an impact during bonding. On the other internal circuit side, the dummy pattern prohibition region PROH is not provided in principle. A dummy pattern is provided at a necessary place in each wiring layer. Further, it is possible to devise a flattening measure such as forming a dummy pattern every other layer in the wiring layer outside the predetermined distance d1 range below the arrangement region of the pads 15 and 16. The dummy pattern prohibited region PROH should be provided so as not to interfere with the formation of a moisture-proof ring (guard ring) around the chip region.

ＬＣＤドライバＩＣチップは、パッド１５，１６の配列が狭ピッチであることから、ダミーパターン禁止領域ＰＲＯＨはパッド配列領域下全域に設けられる。これにより、その後のパッド１５，１６へのバンプ形成、あるいはボンディング接続時の衝撃においても絶縁層が破損することなく信頼性が得られる。   In the LCD driver IC chip, since the arrangement of the pads 15 and 16 is narrow, the dummy pattern prohibited area PROH is provided in the entire area below the pad arrangement area. As a result, reliability can be obtained without damage to the insulating layer even in the subsequent bump formation on the pads 15 and 16 or the impact during bonding connection.

上記本発明の実施形態によれば、外部端子、つまりパッドあるいはバンプ接続時における応力集中領域を硬度の均一化された絶縁膜単体で構成する。これにより、ボンディング等の圧力によるパッド周辺のクラックの発生を回避することができる。   According to the embodiment of the present invention, the stress concentration region at the time of connecting the external terminal, that is, the pad or the bump is constituted by the insulating film having a uniform hardness. Thereby, generation | occurrence | production of the crack around a pad by the pressure of bonding etc. can be avoided.

以上説明したように本発明の半導体集積回路装置によれば、少なくとも金属パッド形成領域直下はダミーパターン禁止領域とし、ボンディング時の衝撃はダミーパターン禁止領域上を埋める層間絶縁膜にかかる。この結果、ボンディング等、パッドへの圧力によるクラック発生を回避する半導体集積回路装置を提供することができる。   As described above, according to the semiconductor integrated circuit device of the present invention, at least a region immediately below the metal pad formation region is a dummy pattern prohibited region, and an impact during bonding is applied to the interlayer insulating film filling the dummy pattern prohibited region. As a result, it is possible to provide a semiconductor integrated circuit device that avoids the occurrence of cracks due to pressure on the pad, such as bonding.

本発明の基本的実施形態に係る半導体集積回路装置の要部を示す平面図ある。It is a top view which shows the principal part of the semiconductor integrated circuit device which concerns on fundamental embodiment of this invention. 本発明の基本的実施形態に係る半導体集積回路装置の要部を示す図１のＦ２−Ｆ２線に沿う断面図である。FIG. 2 is a cross-sectional view taken along line F2-F2 of FIG. 1 showing a main part of the semiconductor integrated circuit device according to the basic embodiment of the present invention. 本発明の一実施形態に係る半導体集積回路装置としてＬＣＤドライバＩＣチップの要部構成を示す平面図である。It is a top view which shows the principal part structure of a LCD driver IC chip as a semiconductor integrated circuit device concerning one Embodiment of this invention.

符号の説明Explanation of symbols

ＷＰ…金属配線パターン
ＩＬ…層間絶縁膜
ＶＩＡ…ビア
ＰＡＤ…金属パッド
ＰＦ…パッシベーション膜
ＤＰ…ダミーターン
ＰＲＯＨ…ダミーターン禁止領域
１０…ＬＣＤドライバ（液晶表示駆動装置）ＩＣチップ
１１…入力回路、
１２…記憶部（ＲＡＭ）
１３…ロジック回路
１４…出力回路、
１５…入力パッド
１６…出力パッド WP ... Metal wiring pattern IL ... Interlayer insulating film VIA ... Via pad ... Metal pad PF ... Passivation film DP ... Dummy turn PROH ... Dummy turn prohibition region 10 ... LCD driver (liquid crystal display drive device) IC chip 11 ... Input circuit,
12 ... Storage unit (RAM)
13: Logic circuit 14: Output circuit,
15 ... Input pad 16 ... Output pad

Claims (5)

半導体素子回路を構成する配線パターン及びダミーパターンが含まれる複数の配線層を有する半導体集積回路装置であって、
前記配線層の最上層ｎ層に形成された金属パッドと、
前記金属パッドの直下の（ｎ−１）層に形成された、前記ダミーパターンが形成されないダミーパターン禁止領域と、を具備し、
前記ダミーパターンは、前記金属パッドの直下で、かつ、少なくとも前記（ｎ−１）層より下の領域に形成されていることを特徴とする半導体集積回路装置。 A semiconductor integrated circuit device having a plurality of wiring layers including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A metal pad formed on the uppermost n layer of the wiring layer ;
The metal pads directly below the (n-1) layer formed, anda dummy pattern prohibition region in which the dummy pattern is not formed,
The dummy patterns are just below the metal pad, and a semiconductor integrated circuit device characterized by being formed in the region below at least the (n-1) layer. 請求項１記載の半導体集積回路装置において、
前記ダミーパターン禁止領域は、前記（ｎ−１）層を含む１層置きに形成されることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 1.
2. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern prohibited area is formed every other layer including the (n-1) layers. 請求項１記載の半導体集積回路装置において、
前記ダミーパターン禁止領域は、前記（ｎ−１）層を含む所定数置きに形成されることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 1.
2. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern prohibition regions are formed every predetermined number including the (n-1) layers. 半導体素子回路を構成する配線パターン及びダミーパターンが含まれる複数の配線層を有する半導体集積回路装置であって、
前記配線層の最上層ｎ層に形成された金属パッドと、
前記金属パッドの直下の（ｎ−１）層を含む所定距離の範囲内に形成された、前記ダミーパターンが形成されないダミーパターン禁止領域と、
を具備し、
前記ダミーパターンは、前記金属パッドの直下の（ｎ−１）層を含む所定距離の範囲外に形成されていることを特徴とする半導体集積回路装置。 A semiconductor integrated circuit device having a plurality of wiring layers including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A metal pad formed on the uppermost n layer of the wiring layer ;
A dummy pattern prohibition region in which the metal pad directly below the (n-1) layer formed within a predetermined distance including the dummy pattern is not formed,
Comprising
The dummy patterns are semiconductor integrated circuit device characterized by being formed out of the range of the predetermined distance including the (n-1) layer immediately below the metal pad. 請求項１ないし４のいずれか一項において、In any one of Claims 1 thru | or 4,
前記半導体集積回路装置を備えることを特徴とする駆動装置。A drive device comprising the semiconductor integrated circuit device.
JP2007000036A 2007-01-04 2007-01-04 Semiconductor integrated circuit device Expired - Fee Related JP4193901B2 (en)

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