JP3922046B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- JP3922046B2 JP3922046B2 JP2002045921A JP2002045921A JP3922046B2 JP 3922046 B2 JP3922046 B2 JP 3922046B2 JP 2002045921 A JP2002045921 A JP 2002045921A JP 2002045921 A JP2002045921 A JP 2002045921A JP 3922046 B2 JP3922046 B2 JP 3922046B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【0001】
【発明の属する技術分野】
本発明は、ダミーパターンが含まれる多層配線を有する半導体集積回路装置に関し、特にパッド構造周辺の信頼性対策に適用される。
【0002】
【従来の技術】
コンパクト化が要求される携帯機器等に組込まれる半導体集積回路装置は、実装場所の制約が厳しくよりいっそうの縮小化が要求されている。ICチップは素子の高集積化に伴い、より多層配線構造となる。各層の平坦化にはCMP(化学的機械的研磨)技術が取り入れられるチップもあるが製造コストが高くなる懸念がある。
【0003】
より低コスト化のためCMP以外の方策がとられる多層配線構造としては、各層の平坦化向上のため実配線パターンに加えてダミーパターンが導入されている構成も少なくない。この場合、パッド形成領域下にもダミーパターンが形成される。例えば、n層で構成されるアルミニウム配線層によるパッドの形成では、パッド領域直下にn−1層でなるアルミニウム配線層によるダミーパターンの形成が存在する。ダミーパターンはアルミニウム配線層各層でパッド領域下に設けられ、最上層n層におけるパッドとビアを介して接続される構造もある。
【0004】
【発明が解決しようとする課題】
上述のように、配線層と接続されるパッドの構造では、パッド領域直下の配線層、さらにその下の配線層においてもそれぞれダミーパターンを延在させ、層間絶縁膜の平坦性に優れた多層配線構造を実現していた。
【0005】
しかしながら、上記構成ではパッドへのボンディング、例えばワイヤボンディングやスタッドバンプ形成時の衝撃、あるいは通常の金属バンプに対するリード圧着による衝撃に弱い欠点がある。これはSiO2層間絶縁膜に対しダミーパターン金属(アルミニウム)の硬度が低いため上記のような衝撃に変形し易いためである。結局、硬度が不均一となりパッド直下の層間絶縁膜でクラックが発生するという危険性があった。
【0006】
本発明は上記のような事情を考慮してなされたもので、ボンディング等、パッドへの圧力によるクラック発生を回避する半導体集積回路装置を提供しようとするものである。
【0007】
【課題を解決するための手段】
本発明の[請求項1]に係る半導体集積回路装置は、
半導体素子回路を構成する配線パターン及びダミーパターンが含まれる多層配線を有する半導体集積回路装置であって、
前記多層配線の所定の形成層において設けられるダミーパターン禁止領域と、
前記ダミーパターン禁止領域上に層間絶縁膜を介して設けられ、前記半導体素子回路に繋がり外部との電気的接続領域を有する金属パッドと、
を具備したことを特徴とする。
【0008】
上記本発明に係る半導体集積回路装置によれば、少なくとも金属パッド形成領域直下はダミーパターン禁止領域となっている。ボンディング時の衝撃はダミーパターン禁止領域上を埋める層間絶縁膜にかかり、硬度の均一化によるクラック防止に寄与する。
【0009】
本発明の[請求項2]に係る半導体集積回路装置は[請求項1]に従属され、
前記金属パッドは所定間隔をもって配列され、前記ダミーパターン禁止領域はこの金属パッド配列の領域周辺の所定距離範囲内すべてに設けられていることを特徴とする。
【0010】
本発明の[請求項3]に係る半導体集積回路装置は[請求項1]に従属され、
前記金属パッドは所定間隔をもって配列され、前記ダミーパターン禁止領域はこの金属パッド配列の領域下方の所定数おきの多層配線の形成層について設けられていることを特徴とする。
【0011】
本発明の[請求項4]に係る半導体集積回路装置は[請求項1]に従属され、
前記金属パッドは所定間隔をもって配列され、前記ダミーパターン禁止領域はこの金属パッド配列の領域下方すべてにおける多層配線の形成層について設けられていることを特徴とする。
【0012】
上記[請求項2]〜[請求項4]それぞれに係る半導体集積回路装置によれば、金属パッドの領域直下またはその周辺には、ダミーパターンという硬度の低い層を混在させることなく、層間絶縁膜のみ存在させ、ボンディング衝撃に変形を起こし難い構造を実現する。より多層の配線となる場合、層間絶縁膜の平坦性を向上させるために間引きした形でダミーパターンを挿入する。
【0013】
本発明の[請求項5]に係る半導体集積回路装置は[請求項1]〜[請求項4]いずれか一つに従属され、
前記金属パッドの周辺部を含み前記電気的接続領域の周りに形成された1層以上の絶縁膜と、
前記電気的接続領域上に設けられたバンプ電極と、
を具備したことを特徴とする。
【0014】
上記構成によれば、バンプ電極の形成時に圧力がかかる場合やバンプ電極形成後、バンプ電極への外部接続時に圧力がかかる場合の両者またはいずれかにおける衝撃に変形を起こし難い構造が実現される。
【0015】
【発明の実施の形態】
図1、図2は、それぞれ本発明の基本的実施形態に係る半導体集積回路装置の要部を示す平面図及び図1のF2−F2線に断面図である。内部回路側では半導体素子回路を構成する金属配線パターンWPが層間絶縁膜IL及びビアVIAを介して多層配線構造を実現している。これら多層配線構造中には必要箇所にダミーパターンDPが含まれる。
【0016】
このような多層配線の延長上の金属パッドPAD形成領域直下にはダミーパターン禁止領域PROHが設けられている。すなわち、ダミーパターン禁止領域PROH上に層間絶縁膜ILを介して半導体素子回路に繋がり外部との電気的接続領域を有する金属パッドPADが設けられている。
【0017】
PAD下周辺の所定距離d1の範囲内はすべて層間絶縁膜ILで埋められた構成となっている。金属パッドPADを囲む最上層はパッシベーション膜PFであり、単層の絶縁膜または積層の絶縁膜で構成される。金属パッドPADは複数配列されるものであり、隣接するPADが所定距離d1の範囲内に設けられれば当然ダミーパターン禁止領域PROHは金属パッドPAD配列直下に連続して設けられることになる。
【0018】
上記実施形態の構成によれば、少なくとも金属パッドPAD形成領域直下はダミーパターン禁止領域PROHとなっている。PAD下周辺の所定距離d1の範囲内がすべて層間絶縁膜ILで埋められている。金属パッドPADへのボンディング時の衝撃はダミーパターン禁止領域PROH上を埋める層間絶縁膜ILにかかる。
【0019】
上述の衝撃とは、図示しないPADへのワイヤボンディングまたはスタッドバンプの形成、さらにはバンプ電極形成後の外部端子接続に伴う衝撃が含まれる。このような衝撃に対し、かかる層間絶縁膜ILは硬度が均一化されているためクラックがほとんど発生しなくなる。
【0020】
なお、図に示すように、最上n層の配線層でパッドPADが形成されている場合、PAD直下においてn−1層の配線層によるダミーパターンは禁止されている形態(ダミーパターン禁止領域PROH)となっているが、n−1層より下のの所定配線層についてはダミーパターンDPを配した構成としてもよい。
【0021】
例えば破線で示すように、金属パッドPAD下の領域においてn−1層より下の所定の各配線層で1層置きに間引きしてダミーパターンDPを設けることも考えられる。これは、より層数の多い配線層構造では平坦性向上のためにダミーパターンの形成が有用だからである。
【0022】
もちろんその他の構成でn−1層より下の各配線層についてPAD下の領域にダミーパターンを設けてもよい。また、配線層数が少なく、平坦性が良好に保てるならば、パッドの領域下方n−1層の配線層はもとよりすべてにおける多層配線の形成層についてパッドの領域下方はダミーパターン禁止領域PROHとしてもよい。
【0023】
図3は、本発明の一実施形態に係る半導体集積回路装置としてLCDドライバICチップの要部構成を示す平面図である。LCDドライバ(液晶表示駆動装置)ICチップは、微細ピッチの端子配列を持つ短冊状のチップである。実装技術には、ワイヤボンディングの他、TCP(Tape Carrier Package)等に利用されるTAB(Tape Automated Bonding)実装や、ACF(Anisotropic Conductive Film )等を利用して達成されるようなCOG(Chip On Glass )またはCOF(Chip On FilmまたはFlexible)といった実装が知られている。これら接続時にはいずれも相当の圧力がかかる。
【0024】
LCDドライバICチップ10は、データが入力される入力回路11、RAM(Random Access Memory)等で構成される記憶部12、データ処理部としてゲートアレイ等で形成されるロジック回路13、及びラッチ回路を含み信号出力をする出力回路14等が相関するように構成された内部の半導体素子回路を有している。
【0025】
入力パッド15、出力パッド16は上記入力回路11中、あるいは出力回路14中の一部のトランジスタ素子(図示せず)と繋がるよう層間絶縁膜(図示せず)を介して構成されている。これらパッド15,16の配列領域直下の配線層についてはダミーパターンを設けないダミーパターン禁止領域PROHとなっている(図1参照)。
【0026】
これにより、ボンディング時の衝撃に耐え得るようパッド15,16の配列領域周辺の所定距離範囲(例えば図2のd1)内はすべて層間絶縁膜で埋められた構成となる。その他の内部回路側は原則的にダミーパターン禁止領域PROHは設けない。各配線層で必要な箇所にダミーパターンが設けられることになる。また、パッド15,16の配列領域下方における所定距離d1範囲以外の配線層では1層置きにダミーパターンを形成するなどの平坦化対策を工夫してよい。なお、このダミーパターン禁止領域PROHはチップ領域周囲の防湿リング(ガードリング)の形成に支障ないように設けるべきである。
【0027】
LCDドライバICチップは、パッド15,16の配列が狭ピッチであることから、ダミーパターン禁止領域PROHはパッド配列領域下全域に設けられる。これにより、その後のパッド15,16へのバンプ形成、あるいはボンディング接続時の衝撃においても絶縁層が破損することなく信頼性が得られる。
【0028】
上記本発明の実施形態によれば、外部端子、つまりパッドあるいはバンプ接続時における応力集中領域を硬度の均一化された絶縁膜単体で構成する。これにより、ボンディング等の圧力によるパッド周辺のクラックの発生を回避することができる。
【0029】
【発明の効果】
以上説明したように本発明の半導体集積回路装置によれば、少なくとも金属パッド形成領域直下はダミーパターン禁止領域とし、ボンディング時の衝撃はダミーパターン禁止領域上を埋める層間絶縁膜にかかる。この結果、ボンディング等、パッドへの圧力によるクラック発生を回避する半導体集積回路装置を提供することができる。
【図面の簡単な説明】
【図1】本発明の基本的実施形態に係る半導体集積回路装置の要部を示す平面図ある。
【図2】本発明の基本的実施形態に係る半導体集積回路装置の要部を示す図1のF2−F2線に沿う断面図である。
【図3】本発明の一実施形態に係る半導体集積回路装置としてLCDドライバICチップの要部構成を示す平面図である。
【符号の説明】
WP…金属配線パターン
IL…層間絶縁膜
VIA…ビア
PAD…金属パッド
PF…パッシベーション膜
DP…ダミーターン
PROH…ダミーターン禁止領域
10…LCDドライバ(液晶表示駆動装置)ICチップ
11…入力回路、
12…記憶部(RAM)
13…ロジック回路
14…出力回路、
15…入力パッド
16…出力パッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a multilayer wiring including a dummy pattern, and is particularly applied to a reliability measure around a pad structure.
[0002]
[Prior art]
A semiconductor integrated circuit device incorporated in a portable device or the like that is required to be compact is severely restricted in a mounting place, and is required to be further reduced. IC chips have a multi-layer wiring structure as the elements are highly integrated. Although there is a chip in which CMP (Chemical Mechanical Polishing) technology is adopted for planarizing each layer, there is a concern that the manufacturing cost becomes high.
[0003]
As a multilayer wiring structure in which measures other than CMP are taken for further cost reduction, there are not a few configurations in which dummy patterns are introduced in addition to actual wiring patterns in order to improve planarization of each layer. In this case, a dummy pattern is also formed under the pad formation region. For example, in the formation of a pad by an aluminum wiring layer constituted by n layers, there is a formation of a dummy pattern by an aluminum wiring layer constituted by n−1 layers immediately under the pad region. There is also a structure in which the dummy pattern is provided below the pad region in each layer of the aluminum wiring layer, and is connected to the pad in the uppermost n layer through a via.
[0004]
[Problems to be solved by the invention]
As described above, in the structure of the pad connected to the wiring layer, the dummy pattern is extended in the wiring layer immediately below the pad region and also in the wiring layer below it, and the multilayer wiring excellent in the flatness of the interlayer insulating film The structure was realized.
[0005]
However, the above configuration has a drawback that it is vulnerable to bonding to the pad, for example, impact during wire bonding or stud bump formation, or impact due to lead pressure bonding to a normal metal bump. This is because the dummy pattern metal (aluminum) has a low hardness with respect to the SiO 2 interlayer insulating film, and thus is easily deformed by the impact as described above. Eventually, there was a risk that the hardness would be uneven and cracks would occur in the interlayer insulating film directly under the pad.
[0006]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device that avoids the occurrence of cracks due to pressure on the pads, such as bonding.
[0007]
[Means for Solving the Problems]
A semiconductor integrated circuit device according to [Claim 1] of the present invention includes:
A semiconductor integrated circuit device having a multilayer wiring including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A dummy pattern prohibited region provided in a predetermined formation layer of the multilayer wiring;
A metal pad provided on the dummy pattern prohibition region via an interlayer insulating film, connected to the semiconductor element circuit and having an electrical connection region with the outside;
It is characterized by comprising.
[0008]
According to the semiconductor integrated circuit device of the present invention, at least a region immediately below the metal pad forming region is a dummy pattern prohibited region. The impact at the time of bonding is applied to the interlayer insulating film filling the dummy pattern prohibited area, and contributes to prevention of cracks due to uniform hardness.
[0009]
A semiconductor integrated circuit device according to [Claim 2] of the present invention is dependent on [Claim 1],
The metal pads are arranged at a predetermined interval, and the dummy pattern prohibited area is provided within a predetermined distance range around the metal pad arrangement area.
[0010]
A semiconductor integrated circuit device according to [Claim 3] of the present invention is dependent on [Claim 1],
The metal pads are arranged at a predetermined interval, and the dummy pattern prohibition region is provided for a predetermined number of multilayer wiring formation layers below the metal pad arrangement region.
[0011]
A semiconductor integrated circuit device according to [Claim 4] of the present invention is dependent on [Claim 1],
The metal pads are arranged at a predetermined interval, and the dummy pattern prohibition region is provided for a multilayer wiring formation layer all below the metal pad arrangement region.
[0012]
According to the semiconductor integrated circuit device according to each of the above-mentioned [Claim 2] to [Claim 4], an interlayer insulating film is formed without mixing a layer having a low hardness called a dummy pattern directly under or around the metal pad region. The structure that hardly causes deformation in the bonding impact is realized. In the case of a multilayer wiring, a dummy pattern is inserted in a thinned form in order to improve the flatness of the interlayer insulating film.
[0013]
The semiconductor integrated circuit device according to [Claim 5] of the present invention is dependent on any one of [Claim 1] to [Claim 4],
One or more insulating films formed around the electrical connection region including the periphery of the metal pad;
A bump electrode provided on the electrical connection region;
It is characterized by comprising.
[0014]
According to the above configuration, it is possible to realize a structure in which deformation is not easily caused in the impact in both or either of the case where pressure is applied when the bump electrode is formed or the pressure is applied when externally connected to the bump electrode after the bump electrode is formed.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 and FIG. 2 are a plan view showing a main part of a semiconductor integrated circuit device according to a basic embodiment of the present invention and a sectional view taken along line F2-F2 in FIG. On the internal circuit side, the metal wiring pattern WP constituting the semiconductor element circuit realizes a multilayer wiring structure through the interlayer insulating film IL and the via VIA. In these multilayer wiring structures, dummy patterns DP are included at necessary places.
[0016]
A dummy pattern inhibition region PROH is provided immediately below the metal pad PAD formation region on the extension of the multilayer wiring. That is, a metal pad PAD having an electrical connection region connected to the semiconductor element circuit via the interlayer insulating film IL is provided on the dummy pattern prohibition region PROH.
[0017]
The entire area within the predetermined distance d1 around the bottom of the PAD is filled with the interlayer insulating film IL. The uppermost layer surrounding the metal pad PAD is a passivation film PF, which is composed of a single-layer insulating film or a stacked insulating film. A plurality of metal pads PAD are arranged, and if adjacent PADs are provided within the range of the predetermined distance d1, the dummy pattern prohibited region PROH is naturally provided continuously immediately below the metal pad PAD arrangement.
[0018]
According to the configuration of the above embodiment, at least a region immediately below the metal pad PAD formation region is the dummy pattern prohibited region PROH. The entire area within the predetermined distance d1 around the lower part of the PAD is filled with the interlayer insulating film IL. The impact at the time of bonding to the metal pad PAD is applied to the interlayer insulating film IL filling the dummy pattern prohibited region PROH.
[0019]
The above-mentioned impact includes an impact associated with wire bonding or stud bump formation on a PAD (not shown), and connection with an external terminal after bump electrode formation. In response to such an impact, the interlayer insulating film IL has a uniform hardness so that almost no cracks are generated.
[0020]
As shown in the figure, when the pad PAD is formed in the uppermost n wiring layers, the dummy pattern by the n-1 wiring layers is prohibited immediately below the PAD (dummy pattern prohibited region PROH). However, for the predetermined wiring layer below the n−1 layer, a configuration in which a dummy pattern DP is disposed may be employed.
[0021]
For example, as indicated by a broken line, dummy patterns DP may be provided by thinning out every other layer in a predetermined wiring layer below the n−1 layer in the region below the metal pad PAD. This is because the formation of a dummy pattern is useful for improving the flatness in a wiring layer structure having a larger number of layers.
[0022]
Of course, a dummy pattern may be provided in a region below the PAD for each wiring layer below the n−1 layer in other configurations. Further, if the number of wiring layers is small and the flatness can be kept good, the n-1 layer wiring layer below the pad region as well as all the multilayer wiring forming layers below the pad region can be used as the dummy pattern prohibited region PROH. Good.
[0023]
FIG. 3 is a plan view showing the main configuration of an LCD driver IC chip as a semiconductor integrated circuit device according to an embodiment of the present invention. An LCD driver (liquid crystal display driving device) IC chip is a strip-shaped chip having a fine pitch terminal arrangement. As the mounting technology, in addition to wire bonding, TAB (Tape Automated Bonding) mounting used for TCP (Tape Carrier Package) or the like, COG (Chip On) achieved by using ACF (Anisotropic Conductive Film), etc. Implementations such as Glass) or COF (Chip On Film or Flexible) are known. A considerable pressure is applied at the time of these connections.
[0024]
The LCD
[0025]
The
[0026]
As a result, a predetermined distance range (for example, d1 in FIG. 2) around the arrangement region of the
[0027]
In the LCD driver IC chip, since the arrangement of the
[0028]
According to the embodiment of the present invention, the stress concentration region at the time of connecting the external terminal, that is, the pad or the bump is constituted by the insulating film having a uniform hardness. Thereby, generation | occurrence | production of the crack around a pad by the pressure of bonding etc. can be avoided.
[0029]
【The invention's effect】
As described above, according to the semiconductor integrated circuit device of the present invention, at least a region immediately below the metal pad formation region is a dummy pattern prohibited region, and an impact during bonding is applied to the interlayer insulating film filling the dummy pattern prohibited region. As a result, it is possible to provide a semiconductor integrated circuit device that avoids the occurrence of cracks due to pressure on the pad, such as bonding.
[Brief description of the drawings]
FIG. 1 is a plan view showing a main part of a semiconductor integrated circuit device according to a basic embodiment of the present invention.
2 is a cross-sectional view taken along the line F2-F2 of FIG. 1, showing the main part of the semiconductor integrated circuit device according to the basic embodiment of the present invention.
FIG. 3 is a plan view showing a main configuration of an LCD driver IC chip as a semiconductor integrated circuit device according to an embodiment of the present invention.
[Explanation of symbols]
WP ... Metal wiring pattern IL ... Interlayer insulating film VIA ... Via pad ... Metal pad PF ... Passivation film DP ... Dummy turn PROH ... Dummy
12 ... Storage unit (RAM)
13: Logic circuit 14: Output circuit,
15 ...
Claims (1)
所定の前記配線層において設けられるダミーパターン禁止領域と、
前記ダミーパターン禁止領域上に層間絶縁膜を介して設けられ、前記半導体素子回路に繋がり外部との電気的接続領域を有する金属パッドと、
を具備し、
前記金属パッドは所定間隔をもって配列され、
前記ダミーパターン禁止領域は、前記金属パッドが配置される前記配線層の直下の前記配線層を含む所定数おきの前記配線層に設けられていることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a plurality of wiring layers including a wiring pattern and a dummy pattern constituting a semiconductor element circuit,
A dummy pattern prohibited area provided in the predetermined wiring layer;
A metal pad provided on the dummy pattern prohibition region via an interlayer insulating film, connected to the semiconductor element circuit and having an electrical connection region with the outside;
Comprising
The metal pads are arranged at a predetermined interval,
2. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern prohibition region is provided in every predetermined number of the wiring layers including the wiring layer immediately below the wiring layer in which the metal pads are arranged.
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JP2007000036A Division JP4193901B2 (en) | 2007-01-04 | 2007-01-04 | Semiconductor integrated circuit device |
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