JP4177572B2 - Analog / digital (A / D) conversion circuit and conversion control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an analog / digital (A / D) conversion circuit and a conversion control method thereof, and is applied to, for example, a portable device such as a digital camera, a mobile phone, a portable terminal device, and the like that are required to be reduced in size and weight. In particular, the present invention relates to a conversion control method in A / D conversion that is effective in realizing a reduction in size and weight.
[0002]
[Prior art]
Some digital still cameras can record audio data. When performing this recording, the digital still camera uses an A / D conversion circuit to quantize an analog audio signal supplied to the A / D conversion circuit, and sequentially converts the quantized digital audio signal to a recording medium such as a flash memory. And recorded on this recording medium. The A / D conversion circuit performs sampling at a constant cycle, for example, using a frequency such as 22 kHz or 8 kHz for sampling an analog audio signal. In order to perform this sampling, an A / D conversion circuit dedicated to audio is usually provided. The A / D converter circuit employs a method of periodically starting in response to supply of a clock or trigger signal having a fixed period.
[0003]
Examples of devices to which such an A / D conversion circuit is applied include those disclosed in Japanese Patent Application Laid-Open Nos. 2000-350062 and 2000-261752. In the digital camera in the former publication, the audio signal processing means for processing the audio data input using the external audio input means and the audio data reproduced by the recording / reproducing means is in response to an operation input from the operation input means. The audio sampling data stored in the sampling data storage means is taken out and output as operation confirmation via the audio output means. This eliminates the need for a sound source circuit dedicated to the operation confirmation sound as in the prior art, and achieves a reduction in the number of parts.
[0004]
Further, the image-recording / playback apparatus with sound in the latter publication stores one image file and one or more sound files in association with position information and time information on the image, so that one or more sound information can be accurately and Efficient recording and playback.
[0005]
In addition, the digital still camera conventionally obtains the depression information of switches provided in the camera by a key matrix method, and controls the operation and signal processing corresponding to the camera based on the obtained information. It was.
[0006]
By the way, the following A / D conversion methods have been generalized recently. This A / D conversion method is a method in which the output voltage of the resistance matrix generated by the key switch operation is detected by the A / D converter, and the push-down information is obtained from this voltage change and the corresponding control is performed by the camera or the like. . By adopting this A / D conversion method, the digital still camera can reduce the number of parts and the circuit scale as compared with the conventional key matrix method. This brings about an advantage that the sound source circuit, the level comparison circuit and the like required so far can be reduced.
[0007]
[Problems to be solved by the invention]
By the way, in the A / D conversion method, since the operating frequencies of the audio and control A / D conversion circuits are greatly different, they are provided separately for audio and control, respectively. Further, among the A / D conversion circuits, an A / D conversion circuit dedicated for voice is inevitably provided with an application specific integrated circuit (ASIC) including various peripheral circuits for the A / D conversion circuit. This ASIC actually tends to increase the number of terminals and the circuit scale. In addition, the entire camera using the ASIC leads to an increase in peripheral circuits. For this reason, a digital still camera equipped with an A / D conversion circuit increases power consumption. This is a major obstacle to achieving the small size and light weight required for mobile devices such as digital still cameras.
[0008]
As described above, it is clear that the digital still camera is a further obstacle to reduction in size and weight by mounting one A / D conversion circuit for each of audio and control.
[0009]
Further, when the audio data conversion in the A / D conversion is, for example, 8 kHz or 22.4 kHz, the sampling period is every 125 μsec or 44.6 μsec. Data supply in this cycle places a heavy burden on a CPU (Central Processing Unit) that processes the supplied data, a bus that passes the data, and the like.
[0010]
The present invention eliminates the disadvantages of the prior art, and is an A / D conversion circuit capable of satisfying at least one of reduction in the scale of peripheral circuits used in common for voice and control and efficient conversion output. It is an object of the present invention to provide a conversion control method thereof.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention is configured such that each of a plurality of input signals including audio information representing continuous sound or control information representing arbitrarily supplied control is input as an input signal of a channel, and is predetermined from the outside. In response to a trigger signal supplied at a period of time, a predetermined channel is sequentially scanned repeatedly to sample an input signal of a selected channel, and this input signal is converted into a digital signal. Conversion control means for instructing selection to the digital conversion means.
[0012]
The A / D conversion circuit of the present invention scans each channel in response to a trigger supplied from the conversion control means to the digital conversion means, samples each channel signal supplied by selection, and performs digital conversion By doing so, digital conversion can be shared by one A / D conversion circuit corresponding to different sampling.
[0013]
Further, in order to solve the above-mentioned problems, the present invention provides a digital conversion means for converting each of a plurality of input signals as a channel input signal and converting the input signal supplied for each channel into a digital signal. Storage means for temporarily storing data of channel signals converted into digital signals in a unit to be collected, and packing control means for controlling packing according to the unit of transmission of data of each channel in the storage means It is characterized by that.
[0014]
The A / D conversion circuit according to the present invention converts the channel signals supplied in response to the trigger signal by the digital conversion means into digital data, and puts them into the storage means for each unit according to the control from the packing control means. By temporarily storing the data and outputting the collected data from the storage means, it is possible to reduce the processing load on the CPU or the like in the transmission processing of the A / D converted data.
[0015]
In order to solve the above-described problems, the present invention is configured such that each of a plurality of input signals including audio information representing continuous sound or control information representing arbitrarily supplied control is input as an input signal of a channel, and is predetermined from the outside. In response to a trigger signal supplied in a cycle, a predetermined channel is sequentially scanned repeatedly to sample the input signal of the selected channel and convert the input signal into a digital signal, and the digital conversion means Storage means for temporarily storing the data of channel signals converted into signals in one unit, and a channel selection instruction are supplied to the digital conversion means, and data transmission of each channel is adjusted to the storage means in units. Conversion control means for controlling stuffing.
[0016]
The A / D conversion circuit according to the present invention scans each channel in response to a trigger supplied from the conversion control means to the digital conversion means, performs digital conversion, and supports different sampling with one A / D conversion circuit. The conversion control means performs packing control of data in accordance with the unit for the storage means, and outputs the packed data from the storage means collectively. As a result, the processing load of the CPU and the like in the transmission processing of A / D converted data is reduced.
[0017]
Furthermore, in order to solve the above-described problem, the present invention uses a plurality of input signals including audio information representing sound or control information representing control as channel signals, and a first step of setting a scanning range of the channel signals. And a second step of sequentially selecting a single channel signal or a plurality of channel signals supplied in accordance with this setting, and a first step of converting one channel signal supplied in response to this selection into a digital signal. 3, a fourth step of temporarily storing the converted channel signal data for each unit handled by the data, and a fifth step of reading and storing the stored data collectively. It is characterized by including.
[0018]
The conversion control method of the A / D conversion circuit of the present invention sets the scanning range of the channel signal, sequentially selects the channel signal according to this setting, and digitally converts one channel signal supplied in response to this selection. Convert to signal. Then, the channel signal data is collectively stored for each unit handled by the data, and the combined data is transmitted. In this way, audio information that is continuously sampled and control information that is arbitrarily sampled are shared with information that differs in form, digital conversion corresponding to each input signal is performed, and the obtained data is output collectively Thus, the conversion output data can be efficiently transmitted.
[0019]
In order to solve the above-mentioned problem, the present invention uses a plurality of input signals including audio information representing sound or control information representing control as channel signals, and a first step of setting a scanning range of the channel signals. A second step of sequentially selecting a single channel signal or a plurality of channel signals supplied in accordance with the setting, and a third step of converting the channel signal supplied in response to the selection into a digital signal It is characterized by including.
[0020]
The conversion control method of the A / D conversion circuit of the present invention uses a plurality of input signals as channel signals, sets a scanning range of the channel signals, and supplies a single channel signal or a plurality of channels supplied according to the setting. Channel signals are sequentially selected, and a channel signal supplied in response to the selection is converted into a digital signal, so that information having different sampling characteristics such as voice information and control information can be shared.
[0021]
Furthermore, in order to solve the above-mentioned problem, the present invention uses a plurality of input signals including audio information representing speech or control information representing control as channel signals, and converts the supplied channel signals into digital signals. And a second step of temporarily storing the data for each unit handled by the data, and a third step of reading and storing the stored data collectively.
[0022]
The conversion control method of the A / D conversion circuit according to the present invention converts a supplied channel signal into a digital signal, temporarily stores the data for each unit handled by the data, and reads and stores the stored data. By transmitting, the conversion output data can be transmitted efficiently.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the A / D conversion circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0024]
In this embodiment, the A / D conversion circuit of the present invention is applied to the A / D conversion module 10. The illustration and description of parts not directly related to the present invention are omitted. Here, the reference number of the signal is represented by the reference number of the connecting line that appears.
[0025]
The A / D conversion module 10 of this embodiment has a feature that is used both for an audio sample and for a control data sample, which has never existed before. Both the operation at a fixed period in the voice sample and the operation at an arbitrary timing in the control data sample are satisfied.
[0026]
The A / D conversion module 10 of this embodiment includes an A / D conversion circuit 12, a data storage 14, a CPU 16, and a conversion control sequencer 18. The A / D conversion circuit 12 includes a multiplexer 120, an A / D conversion unit 122, and a digital control circuit 124. The multiplexer 120 has a function of multiplexing one input signal from a plurality of input signals. The multiplexer 120 selects eight input signals 10a to 10h to be supplied every predetermined time. The eight input signals 10a to 10h are analog signals such as voice, key matrix, and environment detection. The multiplexer 120 is supplied with eight analog selection signals 12 a for selecting an input signal from the A / D converter 122. The method of selection is performed in advance by default. When changing the setting, this initial setting is changed. When the number of all channels is set to 8, all scanning channels are changed from channel # 0 to # 7. In the case of variable setting, the scanning channels may be set to channels # 0 to # 3, for example, and channels # 4 to # 7 may be set to scan when necessary. The multiplexer 120 outputs the selected input signal 12b to the A / D converter 122.
[0027]
The A / D conversion unit 122 of this embodiment uses a successive approximation A / D conversion method as shown in FIG. The A / D converter 122 is supplied with the output signal 12b from the multiplexer 120 and the reference voltage signal (reference) 10i. The A / D converter 122 includes a D / A converter 122a, a comparator 122b, and a level shifter 122c. The above-described reference voltage signal 10i is input to the D / A converter 122a. The reference voltage signal 10i is a voltage signal corresponding to the maximum voltage of the input signal to be compared. The D / A converter 122a receives the data 12c supplied from the level shifter 122c. The decoder 1220 built in the D / A converter 122a decodes the supplied data 12c (digital value) to an analog voltage level. The D / A converter 122a outputs the analog voltage signal 12d corresponding to decoding in order from the MSB (Most Significant Bit) side to the comparator 122b based on the reference voltage signal 10i.
[0028]
The comparator 122b is supplied with the input signal 12b and the analog voltage signal 12d for comparison. The comparator 122b is supplied with a sample hold signal (or latch signal) 12e for performing a stable comparison from the level shifter 122c. The comparator 122b performs level comparison during this hold period. The comparator 122b searches for whether the input signal 12b is equal to or higher than the analog voltage signal 12d. The comparator 122b outputs the search result as an output signal 12f to the level shifter 122c. The comparator 122b determines that the search result is true when the input signal 12b is equal to or greater than the analog voltage signal 12d, and outputs “1” at this time, and outputs “0” when it is false. Then, the level shifter 122c outputs data 12c shifted to the next bit determination after the determination.
[0029]
The level shifter 122c is supplied with a conversion request signal 12g and a channel selection signal 180 from the digital control circuit 124 and the conversion control sequencer 18 shown in FIG. The conversion request signal 12g is a signal indicating shift enable. Further, the channel selection signal 180 is a signal indicating which channel is selected, and is provided by 3 bits (three signal lines) in order to represent corresponding to 8 inputs. The level shifter 122c supplies the multiplexer 120 with an analog selection signal 12a indicating whether or not each channel is selected by decoding 3 bits. The level shifter 122c outputs “1” or “0”, which is the binary search result from the comparator 122b, to the digital control circuit 124 of FIG.
[0030]
Returning to FIG. 1, the digital control circuit 124 is supplied with one conversion trigger signal 182 and an A / D conversion clock 184 from the conversion control sequencer 18. The digital control circuit 124 generates the conversion request signal 12g based on the supplied one conversion trigger signal 182 and the A / D conversion clock 184. The digital control circuit 124 receives the digital data 12i that is the result of the sequential search performed by the A / D conversion unit 122, and rearranges the supplied digital data in accordance with a predetermined bit resolution. As a result, the A / D conversion circuit 12 outputs, for example, 8-bit / 10-bit / 12-bit data 12j to the data storage 14.
[0031]
The data storage 14 is used as a pseudo FIFO memory using a FIFO (First-In First-Out) memory or a memory capable of high-speed operation. The data storage 14 not only stores the supplied data, but also has a function of storing (packing) data for a plurality of times or a plurality of channels, for example, in units of 32 bits or 64 bits. Yes. Packing data multiple times is a process of writing into the same channel and packing it. The packing of a plurality of channels is a packing in which scanned channel data are stored together in order. This clogging is instructed by a control signal 16a from the CPU 16, and data is packed in response to this instruction.
[0032]
As an example of the former packing, when 10-bit data is supplied from the digital control unit 124 and the analog channel # 0 (AN0) is collected into two packs, 10 bits of data of the corresponding channel are stored in the AD data register ADDT0 in the data storage 14. The bit is stored, and the 10-bit data of AN0 obtained by the next A / D conversion is stored in ADDT0. As a result, 20 bits of data of channel # 0 are collectively stored in the AD data register ADDT0.
[0033]
Similarly, if four packs of 8-bit data are stored, the data of the total channel AN0 are collectively stored in 32 bits. Of the control signals 16a from the CPU 16 in the AD data register ADDT0, the data storage 14 is supplied with a pack completion interrupt request signal or a DMA (Direct Memory Access) transfer request signal. In this case, the data storage 14 collectively sends out the data 14a packed in the AD data register ADDT0 in accordance with these request signals (as word data). The data storage 14 sequentially packs data every time the data of the target channel is updated.
[0034]
The data storage 14 specifies and sets the channel for sampling audio, and when the set and packed data is DMA transferred, the CPU 16 does not receive the influence of the load, and the continuous stream information is transferred to the audio data storage. Can be recorded. The audio data storage may be provided inside the A / D conversion module 10 or outside the module.
[0035]
The data storage 14 also stores control data that is arbitrarily supplied according to the cyclic channel scan in the AD data register of a predetermined channel. By the cyclic scanning of the channels set in this way, even if any key matrix operation is performed, the operation can be detected as the control data 14b without omission. The control data 14b is supplied to the CPU 16.
[0036]
The CPU 16 uses, for example, a 32-bit RISC (Reduced Instruction Set Computer). The CPU 16 sends the control signal 16a and the A / D conversion command 16b to the data storage 14 and conversion control so as to perform operation control and operation instruction according to a control program written in a ROM (Read Only Memory) (not shown). Output to sequencer 18. The CPU 16 is not limited to the arrangement at this position. The CPU 16 may be disposed outside the A / D conversion module 10.
[0037]
In addition to the A / D conversion command 16b, the conversion control sequencer 18 is supplied with an A / D conversion clock 20 and a conversion trigger signal 22. The conversion sequencer 18 selects an analog signal input to the multiplexer 120 in response to the input of the conversion trigger signal 22, that is, generates a channel selection signal 180. The channel selection signal 180 is a control command generated by the conversion control sequencer 18. Further, the conversion control sequencer 18 generates one conversion trigger signal 182 which is one of the control commands based on the conversion trigger signal 22 and supplies it to the digital control circuit 124. One conversion trigger signal 182 is an activation trigger for performing A / D conversion, and scanning is started by this input. The conversion trigger signal 22 supplied to the conversion control sequencer 18 from the outside is, for example, a pulse with a constant period of 8 kHz. The CPU 16 not only outputs the A / D conversion command 16b, but also generates and outputs a control signal 16c to the target circuit in accordance with the supplied control data 14b.
[0038]
With this configuration, voice and control A / D can be shared, and only one is required, and multiple time-series data are stored in one word of data, transferred to the destination, and burdened by the CPU. Is reduced. Along with this, the data rate required for the system bus is also reduced.
[0039]
Next, the operation of the A / D conversion module 10 will be briefly described (see FIG. 3). A conversion trigger signal 22 is supplied to the conversion control sequencer 18 from the outside. The conversion control sequencer 18 generates one conversion trigger signal 182 based on the conversion trigger signal 22, and outputs it to the digital control circuit 124 as shown in FIG. 3 (a). For example, when the conversion trigger signal is 8 kHz, the cycle of one conversion trigger signal 182 is T = 125 μsec. A / D conversion is performed in this cycle. Since the control program can be operated without starting the A / D conversion process, the algorithm of these programs can be simplified.
[0040]
Further, the conversion control sequencer 18 receives the A / D conversion command 16 b from the CPU 16 and supplies a channel selection signal 180 to the A / D conversion unit 122. The channel selection signal 12a is supplied from the A / D converter 122 to the multiplexer 120. The multiplexer 120 operates so as to perform a cyclic scan on the set channel, and selects each channel. By this selection, the input signal 12b of the set channel is sent to the A / D converter 122. The A / D converter 122 samples the input signal 12b in response to the conversion request signal 12g supplied from the digital control circuit 124, and outputs the comparison result 12i to the digital control circuit 124.
[0041]
The digital control circuit 124 starts conversion at the rising edge of one conversion trigger signal 182 (see FIG. 3 (a)). The digital control circuit 124 outputs the data to the data storage 14 with a predetermined bit resolution, and further performs packing for the same channel a plurality of times and records the data in the data storage 14 in units of words. A word is determined by the number of bits converted at a time and the number of packings.
[0042]
As described above, a plurality of channels can be cyclically scanned, or a specific channel can be scanned multiple times, converted, and packed to perform periodic sampling on the audio input signal and supplied arbitrarily. The input signal related to the control is also sampled without omission by the cyclic scanning. The cyclic scan may cover all channels.
[0043]
After the conversion, the data storage 14 reads out the control data 14b in response to the control signal 16a from the CPU 16 and supplies it to the CPU 16, as shown in FIG. Further, as shown in FIG. 3 (d), the data storage 14 regularly reads out the voice data 14a collected in response to the control signal 16a from the CPU 16, transfers it to the CPU / DMA, and supplies it. A / D conversion at an 8 kHz period places a burden on the CPU. By handling data including voice together, the number of processes can be reduced, so that a margin can be provided. Since DMA transfer is performed, a further margin can be made. At this time, not only the burden on the CPU but also the occupancy rate of the bus through which data passes can be reduced.
[0044]
In the above-described embodiment, the A / D conversion of the successive approximation A / D conversion method has been described. However, the present invention is not limited to this embodiment, and other A / D conversions such as a ΔΣ A / D conversion method, Needless to say, the present invention can also be applied to a parallel comparison A / D conversion method.
[0045]
A configuration when the A / D conversion module 10 is applied to the digital camera 30 will be briefly described (see FIG. 4). The digital camera 30 includes an A / D conversion module 10, a lens unit 32, a preprocessing unit 34, an image processing circuit 36, an audio data storage 38, a microphone 40, and an operation unit 42. The A / D conversion module 10 has the same configuration as described above. The description is omitted to avoid complexity.
[0046]
Although not shown, the lens unit 32 includes an imaging unit 320 in addition to an optical lens system, an AE (Automatic Exposure) adjustment mechanism, an AF (Automatic Focus) adjustment mechanism, and the like. The imaging unit 320 converts incident light that has passed through the optical lens system into a signal charge, and converts the signal charge Q into a voltage signal V. The imaging unit 320 includes a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) type, and the like. The imaging unit 320 outputs the converted voltage signal V as the image signal 44 to the preprocessing unit 34.
[0047]
The preprocessing unit 34 sequentially performs noise removal and digitization on the supplied image signal 44. In order to perform these processes, the preprocessing unit 34 includes a correlated double sampling (CDS) circuit and an image signal A / D conversion unit (both not shown). The image signal A / D conversion unit is not limited to the method used in the A / D conversion module 10. The preprocessing unit 34 outputs the digitized image data 46 to the image processing circuit 36.
[0048]
The image processing circuit 36 performs image processing on the supplied image data 46, and also includes an audio trigger circuit 360 and an audio processing circuit 362. As the image processing, the image processing circuit 36 basically performs an interpolation process and a broad band on the image data subjected to the gamma correction and the white balance adjustment. Then, the image processing circuit 36 performs luminance data Y and color data C by color difference matrix conversion processing on the image data that has undergone these image processing. _r , C _b (Hereinafter referred to as Y / C data). When compression is performed on the generated Y / C data, Y / C data 48 compressed by compression / decompression processing (not shown) is output to a storage (not shown). This storage may be an audio data storage 38.
[0049]
The audio trigger circuit 360 is enabled when the control signal 16c supplied from the CPU 16 in the A / D conversion module 10 indicates the audio sampling mode, for example. Then, the audio trigger circuit 360 receives the data 100 indicating the start of sampling and sends the conversion trigger signal 22 to the A / D conversion module 10. The conversion trigger signal 22 is a trigger period of 8 kHz, for example, as an external signal.
[0050]
The audio processing circuit 362 performs processing for returning the audio data 14b read from the audio data storage 38 to data having a predetermined bit resolution as audio processing. The image processing circuit 36 outputs the audio data 50 from the audio processing circuit 362 to a storage (not shown). This storage may be an audio data storage 38.
[0051]
The audio data storage 38 stores the audio data 14b packed according to the control signal 16c from the CPU 16, and records the audio data obtained by decomposing the audio data 14b packed by the audio processing circuit 362 into a predetermined number of bits. It is a semiconductor memory. As an example of this semiconductor memory, for example, there is SmartMedia (registered trademark). A magneto-optical recording medium may be used.
[0052]
The microphone 40 is a sensor having a function of converting sound into an electrical signal. Although not shown, the operation unit 42 is formed with a key matrix assigned to a release shutter button, a cross key, and a mode selection button. The microphone 40 and the operation unit 42 input audio signals and control signals from the key matrix to the A / D conversion module 10.
[0053]
Thus, even if a plurality of input signals are supplied to the A / D conversion module 10 as each channel signal, the A / D conversion module 10 cyclically scans the set channel and samples the audio signal at a predetermined timing, The latest control data can be read and used in the sampling performed in parallel.
[0054]
The operation of the digital camera 30 will be briefly described. In the digital camera 30, for example, an operation indicating an audio sampling mode is performed on the operation unit. The A / D conversion module 10 inputs a signal as a channel signal representing this operation, and one channel is selected by the multiplexer. The selected channel is digitally converted and packetized control data is temporarily stored. The stored packet is supplied to the CPU. The CPU supplies the control data 16c to the image processing circuit 36.
[0055]
The image processing circuit 36 receives the supplied control data 16c and puts the voice trigger circuit 360 into an operating state. The voice trigger circuit 360 outputs, for example, the conversion trigger signal 22 of 8 kHz to the A / D conversion module 10 at a predetermined interval as a start trigger. Since it is not necessary to supply the activation trigger each time by software, it can contribute to simplification of the algorithm. The A / D conversion module 10 digitally converts the audio signal sequentially supplied as the channel signal with a predetermined bit resolution while circulating through the channels set in advance.
[0056]
The A / D conversion module 10 packs each digitized data into a data storage to a predetermined bit amount for each channel. The A / D conversion module 10 supplies the packed audio data 14b to the audio data storage 38. The A / D conversion module 10 can reduce the load on the CPU and the bus by outputting data collectively for each channel in this way. The audio processing circuit 362 decomposes the packet data stored in the audio data storage 38 with a predetermined number of bits, and stores the obtained audio data 50 in the audio data storage 38 again. The above-described disassembly process is performed when there is time allowance.
[0057]
Further, the image data is recorded in the image recording area of the audio data storage 38 as the image data 48 processed through the imaging unit 320, the preprocessing unit 34, and the image processing circuit 36. The image recording area and the sound recording area may be stored in association with each other.
[0058]
By performing cyclic operation and trigger supply at a predetermined cycle in this way, multi-channel control data can be continuously sampled at a fixed cycle, reducing the number of A / D conversion modules. Can do. Also, by packing sampling data, the data is transferred all at once. This transfer can reduce the occupation rate of the bus used for data transfer. Therefore, since the load on the CPU is reduced, the efficiency (performance) of the system can be improved.
[0059]
Next, a modification of the A / D conversion module 10 will be described with reference to FIG. The A / D conversion module 10 includes the components shown in FIGS. The description of each configuration is omitted for the sake of simplicity. The A / D conversion module 10 operates using an analog power supply and a digital power supply. Components that use the analog power supply are a multiplexer 120, a part of the D / A converter 122a, and a comparator 122b. These components are represented by a frame 200 indicating an analog power supply usage range.
[0060]
Although not shown, the A / D conversion module 10 is provided with a changeover switch for switching the supply of analog power. An analog power supply control signal 186 is supplied from the conversion control sequencer 18 to the changeover switch. The A / D conversion module 10 is supplied with 8 kHz as the conversion trigger signal 22. On the other hand, the CPU 16 clock and the A / D conversion clock 20 use a high frequency of several hundred kHz. The time during which the A / D converter actually operates during one scanning time with respect to the input of one conversion trigger signal 22 is short.
[0061]
A portion of the A / D conversion module 10 that is not surrounded by the frame 200 described above is a logic circuit. This circuit does not operate when the conversion control sequencer 18 is not operating. At this time, the logic circuit can substantially reduce power consumption. However, a constant current flows through the analog circuit in the frame 200. As a result, the A / D conversion module 10 consumes power even though it is not operating. Therefore, when A / D conversion is not performed, the A / D conversion module 10 can be considered to reduce power consumption by cutting off power supply to the analog circuit.
[0062]
By the way, control of an analog power supply is usually performed by software. However, the control by software is such that it is turned on / off at the start and end of the operation. It is difficult to turn off the analog power supply during the sampling interval by software control and turn on the analog power supply in response to the start of sampling. Therefore, the A / D conversion module 10 has no measure for reducing power.
[0063]
The conversion control sequencer 18 is provided so that analog power supply, which is difficult with software, is controlled by hardware. The conversion control sequencer 18 detects the fall (timing t) of one conversion trigger signal 182 shown in FIG. ₁ 6), the analog power supply control signal 186 in FIG. 6 (d) is set to the high level and applied to the analog power supply changeover switch in the A / D conversion module 10. By this application, analog power is supplied to each circuit in the frame 200. The A / D conversion module 10 has a timing t ₂ Wait until This standby is the time until the supplied analog power supply is stabilized. Therefore, timing t ₂ The A / D conversion state is off as shown in FIG. 6 (c).
[0064]
The A / D conversion module 10 starts A / D conversion in response to the rising edge of the one conversion trigger signal 182. A / D conversion is performed according to cyclic scanning of a single channel or a predetermined channel (see FIG. 6B). The A / D conversion state is on (see FIG. 6 (c)). A signal indicating the end of A / D conversion is detected by the CPU 16, for example. The CPU 16 supplies a command for turning off the analog power supply to the conversion control sequencer 18 as shown in FIG. The conversion control sequencer 18 uses the timing t _Three As a result, the analog power supply control signal 186 shown in FIG. The changeover switch is turned off when the analog power supply control signal 186 is supplied. Then, the supply of analog power is cut off. Since the current consumption of the analog power supply, particularly the reference power supply, can be reduced during the period when A / D conversion is not performed, the A / D conversion module 10 can greatly contribute to the reduction in power consumption of the entire system.
[0065]
With the above configuration, the number of A / D conversion modules can be reduced. Further, the system bus occupancy can be reduced by packing the sampled data. As a result, the usable ratio of the CPU can be increased, so that the performance of the apparatus to which the present invention is applied can be improved.
[0066]
Furthermore, by shutting off the analog power supply during non-operation, which is difficult with software control, with the conversion control sequencer, power can be applied only when A / D conversion is used, reducing power consumption in this A / D conversion. be able to.
[0067]
In addition, although the case where this invention was applied to the digital camera was demonstrated as a specific example, it is not limited to the Example mentioned above, It can be used especially suitably for the portable apparatus etc. with which small size and lightweight are requested | required. Needless to say.
[0068]
【The invention's effect】
As described above, according to the A / D conversion circuit of the present invention, each channel is scanned in response to the trigger supplied from the conversion control means to the digital conversion means, and each channel signal supplied by selection is sampled. By performing digital conversion with this single A / D conversion circuit, even if the audio information and control information are different from continuous conversion and arbitrary conversion, digital conversion corresponding to each is performed Since this is performed in common, the circuit configuration can be simplified.
[0069]
Further, the A / D conversion circuit of the present invention converts each channel signal supplied in response to the trigger signal by the digital conversion means into digital data, and stores each unit in the storage means in accordance with the control from the packing control means. By temporarily storing the collected data and outputting the collected data from the storage means, the number of data transfers can be reduced, reducing the processing burden on the CPU etc. in the transmission processing of A / D converted data Therefore, it is possible to stabilize the apparatus equipped with the A / D conversion circuit and improve the performance of the apparatus.
[0070]
Further, the A / D conversion circuit of the present invention scans each channel in response to a trigger supplied from the conversion control means to the digital conversion means, and samples each channel signal supplied by selection. Digital conversion, even if the voice information and control information is a continuous conversion and conversion different from any conversion in a single A / D conversion circuit, it is sequentially scanned and digital conversion corresponding to each is performed and shared, The circuit configuration can be reduced, and the conversion control means performs packing control of data according to the unit for the storage means, and outputs the packed data from the storage means as a whole, thereby transmitting A / D converted data Reduces the processing load of the CPU, etc. in processing, reduces the circuit of the installed device, improves stable operation and performance with a margin Rukoto can.
[0071]
According to the conversion control method of the A / D conversion circuit of the present invention, the channel signal scanning range is set, the channel signals are sequentially selected according to this setting, and one channel signal supplied in response to this selection Is converted to a digital signal. Then, the channel signal data is collectively stored for each unit handled by the data, and the combined data is transmitted. Sampling can be shared even in the case of sampling of information that differs in form from audio information that performs continuous sampling and control information that is arbitrarily sampled in this way, and digital conversion corresponding to each input signal is performed, By controlling the output of the obtained data collectively, the transmission efficiency of the converted output data can be improved and the operation can be performed stably.
[0072]
Further, the conversion control method of the A / D conversion circuit according to the present invention uses a plurality of input signals including sound information representing sound or control information representing control as channel signals, and sets and sets a scanning range of the channel signals. A single channel signal or a plurality of channel signals to be supplied in accordance with the selection is sequentially selected, and the channel signal supplied in response to the selection is converted into a digital signal, and sampling characteristics of audio information and control information are obtained. Since different information can be shared, a significant reduction in the circuit configuration including peripheral circuits and the like can be promoted.
[0073]
Further, the conversion control method of the A / D conversion circuit according to the present invention converts the supplied channel signal into a digital signal, temporarily stores the data for each unit handled by the data, and reads the stored data. By transmitting the data collectively, the number of data transfers can be reduced and the conversion output data can be transmitted efficiently, so that the performance of the applied apparatus can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an A / D conversion module to which an A / D conversion circuit of the present invention is applied.
2 is a block diagram illustrating a configuration of an A / D conversion unit in the A / D conversion module of FIG. 1;
FIG. 3 is a timing chart for explaining the operation in the A / D conversion module of FIG. 1;
FIG. 4 is a block diagram showing a schematic configuration of a digital camera to which the A / D conversion circuit of the present invention is applied.
FIG. 5 is a block diagram showing a main configuration of an A / D conversion module to which a modification of the A / D conversion circuit of the present invention is applied.
6 is a timing chart for explaining the operation of the A / D conversion module of FIG. 5;
[Explanation of symbols]
10 A / D conversion module
12 A / D converter circuit
14 Data storage
16 CPU
18 Conversion control sequencer
120 multiplexer
122 A / D converter
124 Digital control circuit

Claims (2)

Each of a plurality of input signals including voice information representing continuous voice or control information representing arbitrarily supplied control is input as a channel input signal, the input signal is converted into a digital signal, and the digital signal is converted into a channel. In an analog-digital ( A / D ) conversion circuit that stores every time ,
Digital conversion means for sampling an input signal of a selected channel by repeating sequential scanning for a predetermined channel in response to a trigger signal supplied from the outside in a predetermined cycle, and converting the input signal into a digital signal; ,
Conversion control means for instructing the digital conversion means to select the channel ;
Digital control means for rearranging the converted digital signals in accordance with a predetermined bit resolution;
Storage means for temporarily storing data of the channel signal converted into the digital signal;
A command for outputting a command to the conversion control means and the storage, and a control means for controlling the conversion control means and the storage ;
The circuit realizes sampling of continuous data at a predetermined period and sampling of control data obtained by scanning for each trigger signal in response to a command from the trigger signal and the control means in the conversion control means , The continuous data is stored in the storage means in word units defined by the number of bits converted at a time and the number of packings combined into a predetermined bit unit, and stored from the storage means in response to a control signal of the control means An analog / digital (A / D) conversion circuit which reads out the control data in parallel with reading out continuous data and transferring the data to DMA ( Direct Memory Access ) . Each of a plurality of input signals including voice information representing continuous voice or control information representing arbitrarily supplied control is input as a channel input signal, the input signal is converted into a digital signal, and the digital signal is converted into a channel. In the conversion control method of the analog-digital ( A / D ) conversion circuit stored every time, the method includes:
A first step of setting a plurality of input signals including voice information representing voice or control information representing control as channel signals and setting a scanning range of the channel signals;
A second step of sequentially selecting the single channel signal or the plurality of channel signals supplied according to the setting;
A third step of converting one channel signal supplied in response to the selection into a digital signal;
A fourth step of temporarily storing the converted channel signal data collectively for each unit handled by the data;
A fifth step of reading out the stored data and transmitting the data together;
The second step indicates the start of one conversion, and when the activation signal supplied as a trigger at a predetermined cycle is input, the circuit is rotated once for the channels in the set range among the plurality of supplied channel signals. Scanning, and outputting the channel signals sequentially selected by the cyclic scanning one by one as each channel signal,
The third step rearranges the converted digital signals in accordance with a predetermined bit resolution ,
In a fourth step, the data is stored as a unit for handling the data by storage control in which the number of bits transmitted by the data is packed together.
The method realizes sampling of continuous data at a predetermined period and sampling of control data obtained by scanning for each trigger signal according to the control of the trigger and command, and the number of bits converted at a time and a predetermined number of bits. The continuous data continuously supplied in word units defined by the number of packings organized in bit units is stored in the storage means for storing, and the continuous data saved from the storage means in response to the control signal supplied by the control means A conversion control method for an analog / digital (A / D) conversion circuit, wherein the control data is also read in parallel with reading data and performing DMA ( Direct Memory Access ) transfer .

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