JP4166292B2 - Memory device for digital image signal, writing method and reading method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device, a writing method and a reading method for a digital image signal including a signal processing circuit for performing real-time signal processing in an IC circuit.
[0002]
[Prior art]
Hierarchical coding for generating image signals of a plurality of layers having different resolutions is known. That is, a code that forms a high resolution image signal as a first layer, a second layer image signal having a lower resolution, a third image signal having a lower layer than the second layer image signal,... (Referred to as hierarchical coding) has been proposed. According to this encoding, a plurality of image signals are transmitted via a single transmission path (communication path, recording medium), and on the receiving side, image data is reproduced by an image monitor corresponding to each of the plurality of hierarchies. Can do.
[0003]
More specifically, standard resolution video signals, high resolution video signals, computer display image data, low resolution video signals for high-speed search of an image database, and the like are video signals of different resolutions. In addition to high and low resolution, hierarchical encoding can be applied to image enlargement and reduction (so-called electronic zoom). Image scaling is a function often used in video game applications, for example.
[0004]
[Problems to be solved by the invention]
In the conventional hierarchical coding, when forming a second layer image signal of 1/4 the first layer (input) image signal and the number of pixels of the first layer image signal, the first layer image signal is The image signal of the second layer is formed by decimation to 1/4, and the difference between the input signal and the first layer interpolation signal interpolated from the second layer image signal is calculated, and this difference signal is transmitted. ing. As described above, in the conventional hierarchical coding, the number of pixels of the difference signal is equal to the number of pixels of the input image signal, and further, since the signal of the second layer is transmitted, the transmission data amount is increased from the original data amount. It was normal. When writing hierarchically structured image data to the memory, there is a problem that the capacity of the memory increases.
[0005]
In addition, when writing hierarchically structured image data in a memory, a signal processing circuit for hierarchical encoding is added to the memory, and a separate IC circuit is required. For this reason, there arises a problem of an increase in cost and an increase in space necessary for circuit arrangement.
[0006]
Accordingly, an object of the present invention is to store image data having a hierarchical structure in a memory whose capacity is equal to that required for the original input image data, while reducing the cost and space of the IC circuit. It is an object to provide a memory device, a writing method, and a reading method for a digital image signal that can be reduced.
[0007]
[Means for Solving the Problems]
In the invention of claim 1, the signal processing means for processing the digital image signal in real time and the memory means for writing the output data of the signal processing means are configured on a common semiconductor substrate,
When the input image data is used as the first layer image data, the signal processing means uses the average value of every N pixel data spatially adjacent to the first layer to obtain one pixel in the second layer. An encoding means for generating data and performing hierarchical encoding,
Dividing clock generating means for generating a predetermined divided clock obtained by dividing a clock synchronized with input image data,
N pixel data of the input image data to be input are added in accordance with a predetermined frequency division clock, and N−1 pixel data of the N pixel data are respectively stored in the memory means. Written in position,
The digital image signal is controlled so that an average value of the N pixel data is written at a position of the memory means in which the remaining one of the N pixel data is to be written. Memory device. The present invention is also a writing method for writing data to the memory in this way.
[0008]
In the invention of claim 2, the signal processing means for processing the digital image signal in real time and the memory means for writing the output data of the signal processing means are configured on a common semiconductor substrate,
When the input image data is used as the first layer image data, the signal processing means uses the average value of every N pixel data spatially adjacent to the first layer to obtain one pixel in the second layer. An encoding means for generating data and performing hierarchical encoding,
Dividing clock generating means for generating a predetermined divided clock obtained by dividing a clock synchronized with input image data,
In accordance with a predetermined frequency-divided clock, N pieces of pixel data of input image data to be inputted are added, and each of N-1 pieces of pixel data and N pieces of pixel data out of N pieces of pixel data. Each difference value from the average value is written at a predetermined position in the memory means,
Of the N difference values, the position of the memory means to the remaining one of the difference value is written, for digital image signals, wherein the average value of N pieces of pixel data is controlled to be written Memory device. The present invention is also a writing method for writing data to the memory in this way.
[0009]
According to the invention of claim 4 , the signal processing means for real-time processing to which the read output is supplied together with the memory means in which the data obtained by processing the digital image signal is written is configured on a common semiconductor substrate.
When the input image data is used as the first layer image data , the signal processing means uses the average value of every N pixel data spatially adjacent to the first layer to obtain one pixel in the second layer. Decoding means corresponding to hierarchical encoding for generating data ,
Frequency-divided clock generating means for generating a predetermined frequency-divided clock obtained by frequency-dividing the clock input to the memory ;
In the second layer corresponding to the first layer of the N-1 pieces of pixel data and N pieces of pixel data of the first hierarchy read out from a predetermined position in the memory means in accordance with a predetermined frequency-divided clock 1 by calculating the number of pixel data, among the N pixel data of the first hierarchy in which writing to the memory means it is omitted, and a data reproducing means for restoring the remaining one pixel data,
A memory device for digital image signals. The present invention is also a reading method for reading data in this way.
[0010]
Upper level data is formed by the average value data of a plurality of data included in a predetermined area of the hierarchy, and the higher level data is written into the memory instead of a part of the data of the higher level. Each layer of data can be formed from the read output of the memory. Therefore, even when writing data of a plurality of layers, it is possible to prevent the memory capacity from increasing beyond the capacity required for the original image data. In addition, a signal processing circuit and a semiconductor memory can be configured as a one-chip IC circuit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In the present invention, a signal processing circuit that performs real-time signal processing and a semiconductor memory are configured on a common semiconductor substrate, thereby forming a one-chip IC circuit. In this embodiment, a signal processing circuit for hierarchical encoding and hierarchical decoding of an image signal and a semiconductor memory (RAM) constitute a one-chip IC circuit. In FIG. 1, a hierarchically encoded signal processing circuit and a semiconductor memory 1 are integrated on a single chip. Image data obtained by quantizing one sample into a predetermined number of bits (for example, 8 bits) is supplied from an input terminal indicated by 2 at a predetermined sampling frequency (for example, 13.5 MHz). A clock synchronized with the input image data is supplied to the input terminal 3. The input image data is supplied in the order of raster scanning of the television.
[0012]
This embodiment is composed of a minimum number of layers, that is, a first layer composed of input image data and a second layer having a lower resolution. Hierarchical coding will be described by taking as an example a case where the number is composed of first, second, and third hierarchies.
[0013]
In FIG. 2, a partial image (8 × 8 pixels) in the first layer is shown at the bottom. In FIG. 2, one square represents one pixel. An average value is calculated for every four pixels in the first layer (2 × 2 pixels). For example, an average value m1 (= 1/4 · (a + b + e + f)) of a, b, e, and f is calculated. Therefore, the portion corresponding to (8 × 8 pixels) is (4 × 4 pixels). An image is formed in the second layer by the average value thus calculated.
[0014]
Next, four average values of (2 × 2) spatially adjacent in the second hierarchy are calculated. 2, M1 (= 1/4 · (m1 + m2 + m3 + m4) is shown. The average value calculated in this way constitutes an image of the third layer, where (8 The area of (× 8 pixels) becomes the area of (2 × 2 pixels) Although not shown, it is possible to construct an image of a higher hierarchy by calculating the average value as described above. As can be seen from Fig. 2, as the hierarchy changes, the number of pixels decreases to 1/4, 1/16, .... In other words, if the area of the image is constant, the resolution decreases at the same rate. If the distance between the pixels is constant, the size of the image is reduced at the same rate.
[0015]
Hierarchical coding that forms an image of a higher hierarchy with the above average value has an advantage that the number of transmission pixels does not increase when transmitting image data of a plurality of hierarchies. In the example of FIG. 2, instead of transmitting the hatched pixels, upper layer data may be transmitted. For example, the second layer data m1 may be transmitted instead of the first layer pixel data f. On the receiving side, the pixel data d whose transmission is omitted is obtained as (f = 4m1- (a + b + e)). Furthermore, instead of the pixel data p (or second layer data m4) in the lower right corner of (4 × 4 pixels) including the first layer pixel data a to f, the third layer data M1 is transmitted. Similarly to the above, the pixel data m4 of the second hierarchy can be calculated, the data of the second hierarchy can be decoded, and the pixel data p of the first hierarchy can be decoded. Note that the position of the pixel for which transmission is omitted is not limited to the position of the lower right corner.
[0016]
Returning to FIG. 1, an embodiment of the present invention will be described. Clocks synchronized with input data from the input terminal 3 are divided by ½ by frequency dividing circuits 4 and 5, respectively. Assuming that the sampling frequency is Fs, a clock with a frequency of 1/2 · Fs is generated from the frequency dividing circuit 4. Further, the frequency dividing circuit 5 generates a clock having a frequency of 1/2 · Fh, where the horizontal scanning frequency is Fh.
[0017]
Input image data is supplied to a one-pixel delay circuit 6, an adder 7, an adder 10, an adder 13 and a selection circuit 15. The output of the one-pixel delay circuit 6 is supplied to the adder 7. The output of the adder 7 is supplied to the 1-line delay circuit 9 via the selection circuit 8. An adder 10 adds the input data and the output of the line delay circuit 9. The output of the adder 10 is supplied to the one-pixel delay circuit 12 via the selection circuit 11. An adder 13 adds the input data and the output of the one-pixel delay circuit 12.
[0018]
The output of the adder 13 is supplied to the selection circuit 15 via a division circuit 14 that performs division by ¼. The selection circuit 15 selects input data and an output of the division circuit 14. Output data of the selection circuit 15 is supplied as write data to the semiconductor memory 1. The semiconductor memory 1 is supplied with a clock from the input terminal 3, and although not shown, a write address and a read address are generated from the clock, and a control signal for controlling writing / reading is generated.
[0019]
A clock of 1/2 · Fs is supplied from the frequency dividing circuit 4 to the selection circuits 8 and 11. The selection circuits 8 and 11 select and output the respective outputs of the adders 7 and 10 for each period of two pixels by this divided clock. Accordingly, the outputs of the selection circuits 8 and 11 change every two pixel periods. The selection circuit 15 is supplied with clocks having frequencies of 1/2 · Fs and 1/2 · Fh from the frequency dividing circuits 4 and 5, respectively. The input data and the output of the divider circuit 14 are alternately selected for each line, and in the period of the line for selecting the output of the divider circuit 14, the selection circuit 14 Select an output. Accordingly, the output of the selection circuit 15 changes every two pixel periods in the selected line.
[0020]
The operation of the above embodiment of the present invention will be described. As an example, in the pixel arrangement as shown in FIGS. 2 and 3, output data is generated from each circuit as shown in FIG. 1 at the timing when the pixel data f is supplied to the input terminal 2. First, the previous pixel data e is generated at the output of the one-pixel delay circuit 6, and the output of the adder 7 is (e + f). The selection circuit 8 selects the output of the adder 7 every two pixel periods. The data (e + f) is data at a selected timing, and the added output of (f + g) in the period after the next one pixel is data at a timing not selected. Therefore, the 1-line delay circuit 9 generates an addition output (a + b) one line before. Accordingly, an adder output of (a + b + f) is generated from the adder 10.
[0021]
The selection circuit 11 to which the output of the adder 10 is supplied also selects the output of the adder 10 every two pixel periods at the same timing (phase) as the selection circuit 8 and supplies it to the one-pixel delay circuit 12. From the one-pixel delay circuit 12, data (a + b + e) is generated. Since this data and the input data are added by the adder 13, an output of (a + b + e + f) is generated from the adder 13. The output of the adder 13 is converted by the divider circuit 14 into 1/4 · (a + b + e + f) (= m1) data. The selection circuit 15 selects the average value data m1 instead of the input pixel data f and supplies it to the semiconductor memory 1. In the semiconductor memory 1, the average value m1 is written at the address where the pixel data f is to be written.
[0022]
As a result of the above-described write operation, the semiconductor memory 1 stores the average data m1 and m2 of the second layer instead of the pixel data of the lower right corner of each of the (2 × 2 pixels) area as shown in FIG. , M3, ... are written. Without increasing the capacity of the semiconductor memory 1, the first and second layer data generated from the input image data in real time can be written to the semiconductor memory 1.
[0023]
FIG. 4 shows an example of the configuration on the reading side of the semiconductor memory 1 written as described above. A sampling clock synchronized with the read data of the semiconductor memory 1 is supplied from the input terminal 3, and by the frequency dividing circuits 4 and 5, as described above, the clock having the frequency of 1/2 · Fs and the frequency of 1/2 · Fh are supplied. Each frequency clock is formed. Read data from the semiconductor memory 1 is supplied to a one-pixel delay circuit 16, an adder 17, an adder 20, a quadruple multiplier circuit 24, and a selection circuit 25, respectively.
[0024]
The configuration on the reading side is the same as the configuration on the writing side shown in FIG. That is, a one-pixel delay circuit 16 corresponding to the one-pixel delay circuit 6 of FIG. 1, an adder 17 corresponding to the adder 7, a selection circuit 18 corresponding to the selection circuit 8, an adder 20 corresponding to the adder 10, and a selection circuit. 11, a selection circuit 21 corresponding to 11, a one-pixel delay circuit 22 corresponding to the pixel delay circuit 12, and a selection circuit 25 corresponding to the selection circuit 15 are provided. On the write side, an adder 13 is provided, whereas on the read side, as shown in FIG. 4, a subtracter 23 is provided and a division circuit 14 is provided. A quadruple multiplication circuit 24 is provided.
[0025]
In the configuration on the readout side, output data is obtained from each circuit as shown in FIG. 4 at the timing when the data m1 of the second hierarchy is read from the semiconductor memory 1 instead of the pixel data f. The operation is the same as that of the writing side in FIG. The multiplication circuit 24 generates 4m1, and the subtracter 23 performs a subtraction operation of 4m1- (a + b + e). Accordingly, pixel data f is obtained from the subtracter 23, selected by the selection circuit 25, and taken out to the output terminal 25.
[0026]
As described above, the image data of the first layer is read to the output terminal 25. When outputting the data of the second hierarchy, although not shown, a selection circuit for selecting only the data of the second hierarchy may be provided as the read output of the semiconductor memory 1. Two layers of data can also be read in parallel. The configuration on the write side in FIG. 1 and the configuration on the read side shown in FIG. 4 are almost the same as described above. Moreover, the configurations of the adder 13 and the subtracter 23 are common as hardware, and the division circuit 14 and the multiplication circuit 24 differ only in the direction of 2-bit shift, and are common as hardware. It is. As described above, the writing side and the reading side can be realized as a common hardware, and the scale of hardware for performing hierarchical encoding and decoding processing can be reduced.
[0027]
FIG. 5 shows another embodiment of the present invention. FIG. 5 shows a signal processing configuration for writing encoded data of three layers to the semiconductor memory 1. The configuration for forming the second layer data from the first layer data (input image data) is the same as that shown in FIG. Accordingly, the components in FIG. 5 corresponding to the components in FIG. 1 are denoted by the same reference numerals having the subscript “a”, and detailed description thereof will be omitted. However, only the output of the adder 14a is supplied to the selection circuit 15a, and second-layer data (m1, m2, m3, m4,...) Is output from the selection circuit 15a.
[0028]
Further, for the third layer encoding, the frequency divider 4b is connected to the frequency divider 4a, and the frequency divider 5b is connected to the frequency divider 5a. A clock with a frequency of 1/4 · Fs is generated from the frequency dividing circuit 4b, and a clock with a frequency of 1/4 · Fh is generated from the frequency dividing circuit 5b. A clock having a frequency of 1/4 · Fs and a clock having a frequency of 1/4 · Fh are supplied to the selection circuits 8b and 15b, respectively.
[0029]
Input image data (first layer data) and second layer data from the selection circuit 15 a are supplied to the selection circuit 15 b, and output data of the selection circuit 15 b is written to the semiconductor memory 1. The data of the second layer is also supplied to the 2-pixel delay circuit 6b, the adder 7b, the adder 10b, and the adder 13b. A two-pixel delay circuit 6b, an adder 7b, a selection circuit 8b, a two-line delay circuit 9b, an adder 10b, a selection circuit 11b, and a two-pixel delay circuit with the same connection relationship as the configuration for forming the second layer data 12b, an adder 13b, a division circuit 14b, and a selection circuit 15b are provided. For example, at the timing when pixel data p is supplied to the input terminal 2 at the output of the division circuit 14b, data of the third layer of 1/4 · (m1 + m2 + m3 + m4) = M1 is generated. The selection circuit 15b selects M1 and supplies it to the semiconductor memory 1.
[0030]
The selection circuit 15b selects the data of the second layer from the selection circuit 15a at the timing corresponding to the position of the data of the second layer. The input data is selected at the timing corresponding to the position of the input data of the first hierarchy. Therefore, in the semiconductor memory 1, as shown in FIG. 6, for each area of (2 × 2 pixels), instead of the pixel data of the first layer, the data m1, m2, m3,. Are written in the third layer data M1, M2,... Instead of the second layer data for each area of (4 × 4 pixels). The configuration for reading the data of the semiconductor memory 1 written in this way can be configured in the same manner as that on the writing side, although not shown.
[0031]
In the present invention, difference data for the average value may be transmitted together with the average value. That is, difference data (Δa = a−m1, Δb = b−m1, Δc = c−m1) is transmitted together with the average value m1 of the pixel data a, b, c, and d as the first layer data. In addition, difference data (Δm1 = m1−M1, Δm2 = m2−M1, Δm3 = m3−M1) is transmitted together with the average values of m1, m2, m3, and m4 as the second layer data. On the receiving side, Δd can be obtained by Δd = − (Δa + Δb + Δc) from the relationship of Δa + Δb + Δc + Δd = a + b + c + d−4m1 = 0. In this way, data of a plurality of layers can be transmitted without increasing the number of transmission pixels. Also, since the image has local correlation, the value of the difference data is generally small, and the image can be further compressed by a method such as requantization with a smaller number of bits.
[0032]
In the present invention, in consideration of an increase in the word length of the average value data, a larger number of bits than the number of bits of the input pixel data may be assigned to the average value data. Furthermore, the data of each layer may be transmitted after being subjected to compression encoding, variable length encoding, or the like. Furthermore, the average value is not limited to the simple average value, and a weighted average value may be formed.
[0033]
In the present invention, only the semiconductor memory and the signal processing circuit on the reading side may be configured as an IC circuit. In this case, multiple layers of image data are written in advance in the semiconductor memory, and the semiconductor memory functions as a ROM.
[0034]
【The invention's effect】
As described above, according to the present invention, it is not necessary to increase the memory capacity when hierarchically encoded data is stored. Further, in the present invention, since the signal processing circuit for hierarchical encoding or hierarchical decoding is configured on the same substrate as the semiconductor memory, the hardware scale can be reduced and the space can be reduced in size. There are advantages you can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a writing side according to an embodiment of the present invention.
FIG. 2 is a schematic diagram for explaining hierarchical encoding according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a part of data written to a semiconductor memory in one embodiment of the present invention;
FIG. 4 is a block diagram showing a configuration of a writing side according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a writing side according to another embodiment of the present invention.
FIG. 6 is a schematic diagram showing a part of data written to a semiconductor memory in another embodiment of the present invention.
[Explanation of symbols]
1 Semiconductor Memory 2 Image Data Input Terminal 3 Clock Input Terminal

Claims (8)

The signal processing means for processing the digital image signal in real time and the memory means for writing the output data of the signal processing means are configured on a common semiconductor substrate, and the signal processing means converts the input image data into the first image data. A code for performing hierarchical encoding by generating one pixel data of the second hierarchy based on an average value of every N pieces of spatially adjacent pixel data of the first hierarchy when the image data of the hierarchy is used. Means for
Dividing clock generating means for generating a predetermined divided clock obtained by dividing a clock synchronized with the input image data,
The N pixel data of the input image data to be input is added according to the predetermined frequency-divided clock, and each of N−1 pixel data of the N pixel data is Written in place in the memory means,
The digital value is controlled so that an average value of the N pixel data is written at a position of the memory means in which the remaining one of the N pixel data is to be written. Memory device for image signals. The signal processing means for processing the digital image signal in real time and the memory means for writing the output data of the signal processing means are configured on a common semiconductor substrate, and the signal processing means converts the input image data into the first image data. A code for performing hierarchical encoding by generating one pixel data of the second hierarchy based on an average value of every N pieces of spatially adjacent pixel data of the first hierarchy when the image data of the hierarchy is used. Means for
Dividing clock generating means for generating a predetermined divided clock obtained by dividing a clock synchronized with the input image data,
The N pixel data of the input image data to be input are added according to the predetermined frequency-divided clock, and each of the N-1 pixel data of the N pixel data is Each difference value from the average value of N pixel data is written in a predetermined position of the memory means,
Of the N difference values, digital, characterized in that the position of said memory means to the remaining one of the difference value is written, is controlled so that the average value of the N pixel data is written Memory device for image signals. The memory device for a digital image signal according to claim 1 or 2,
A memory device for digital image signals, wherein the average value of the N pieces of pixel data is obtained by division by bit shift. Together with the memory means in which the data obtained by processing the digital image signal is written, the signal processing means for real-time processing to which the read output is supplied is configured on a common semiconductor substrate,
When the input image data is used as the first layer image data, the signal processing means uses one of the second layers based on an average value of every N pixel data spatially adjacent to the first layer. Decoding means corresponding to hierarchical encoding for generating the pixel data of
A frequency-divided clock generating means for generating a predetermined frequency-divided clock obtained by frequency-dividing the clock input to the memory;
The first hierarchy N-1 pixel data and the first hierarchy N pixel data read from a predetermined position of the memory means in response to the predetermined frequency division clock. By calculating one pixel data of the second hierarchy, the remaining one pixel data is restored from the N pixel data of the first hierarchy in which writing to the memory means is omitted. Data reproduction means;
A memory device for digital image signals. The memory device for a digital image signal according to claim 5,
The digital image signal memory device, wherein the data reproduction means includes a multiplier for performing multiplication by bit shift. In a writing method in which a digital image signal is processed in real time and data obtained by signal processing is written to a memory means configured on a common semiconductor substrate.
When the input image data is the image data of the first layer, one pixel data of the second layer is generated by the average value of every N pixel data spatially adjacent to the first layer. So that hierarchical encoding is performed,
Generate a predetermined divided clock obtained by dividing the clock synchronized with the input image data,
The N pixel data of the input image data to be input is added according to the predetermined frequency-divided clock, and each of N−1 pixel data of the N pixel data is Written in place in the memory means,
Among the N pixel data, writing, characterized in that the position of said memory means to the remaining one pixel data is written, is controlled so that the average value of the N pixel data is written Method. In a writing method in which a digital image signal is processed in real time and data obtained by signal processing is written to a memory means configured on a common semiconductor substrate.
When the input image data is the image data of the first layer, one pixel data of the second layer is generated by the average value of every N pixel data spatially adjacent to the first layer. So that hierarchical encoding is performed,
Generate a predetermined divided clock obtained by dividing the clock synchronized with the input image data,
The N pixel data of the input image data to be input are added according to the predetermined frequency-divided clock, and each of the N-1 pixel data of the N pixel data is Each difference value from the average value of N pixel data is written in a predetermined position of the memory means,
Of the N difference values, writing, characterized in that the position of said memory means to the remaining one of the difference value is written, is controlled so that the average value of the N pixel data is written Method. In a reading method in which data is read out from a memory means in which data obtained by processing a digital image signal is written by a signal processing means configured on a semiconductor substrate common to the memory means,
When the input image data is the image data of the first hierarchy, one pixel data of the second hierarchy is generated by the average value of every N pixel data spatially adjacent to the first hierarchy. Do not perform decoding corresponding to hierarchical coding,
Generate a predetermined divided clock obtained by dividing the clock synchronized with the input image data,
The first hierarchy N-1 pixel data and the first hierarchy N pixel data read from a predetermined position of the memory means in response to the predetermined frequency division clock. By calculating one pixel data of the second hierarchy, the remaining one pixel data is restored from the N pixel data of the first hierarchy in which writing to the memory means is omitted. A reading method comprising a data reproduction step.

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