JP4157256B2 - Memory block and semiconductor memory device using the memory block - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to an embedded semiconductor memory device integrated on the same semiconductor chip as a logic circuit or the like. More specifically, the present invention relates to a layout configuration of a semiconductor memory device.
[0002]
[Prior art]
FIG. 10 shows an overall configuration of a semiconductor memory device integrated with a conventional logic circuit. In FIG. 10, the conventional semiconductor memory device 1 receives an external control signal EXCMD, an external address signal from the logic circuit 10. Controlled by EXADD, data transfer is performed via the logic circuit and external data buses DIOa-DIOf. The conventional semiconductor memory device 1 is provided corresponding to each of the memory cell arrays 3a-3f and the memory cell arrays 3a-3f each consisting of memory cells arranged in a matrix, and via internal data buses DLa-DLf, Data input / output circuits 4a-4f for outputting read data from selected memory cells and writing external data, row decoders 5a-5c for selecting word lines from the memory cell arrays 3a-3f, external control signals and external address signals And a control circuit 6 that controls the data input / output circuit and the row decoder.
[0003]
FIG. 11 is a configuration diagram of a data input / output circuit in the conventional semiconductor memory device 1. As shown in FIG. 11, the data input / output circuit 4 includes a data bus selection circuit 41 for selecting a data bus corresponding to the bus width of the external data bus DIO from each internal data bus DL, and a memory cell via the internal data bus DL. A read amplifier / write buffer 42 for amplifying read data and writing data, and a data input / output buffer circuit 43 for inputting / outputting external read / write data via an external data bus DIO.
[0004]
FIG. 12 is a configuration diagram of the control circuit 6 in the conventional semiconductor memory device 1. As shown in FIG. 12, the control circuit 6 receives the external control signal EXCMD, the address buffer circuit 62 that captures the external address signal EXADD, and the input buffer circuit output signal INCMD, and decodes the command. The command decoder 63 receives the column address signal YADD for selecting the internal data bus, receives column predecoders 64a to 64c for predecoding, the output signal CMD of the command decoder and the output signals PYa to PYc from the column predecoder. Data system control circuits 65a-65c for fetching and controlling data input / output circuits, and row predecoders 66a-66c for receiving a row address signal XADD for selecting a word line from the address buffer circuit and performing predecoding. ing. Reference numeral 7 denotes an internal power supply circuit, which generates a VBB potential for suppressing a leak current of the memory cell transistor, a precharge potential of a bit line, etc., and transmits it to the memory cell array through a power supply line (not shown).
[0005]
Next, the basic operation of the semiconductor memory device 1 will be described taking a read operation as an example.
[0006]
First, the external control signal EXCMD and the external address signal EXADD are taken into the input buffer circuit 61 and the address buffer circuit 62, respectively, at the rising edge of the clock. The fetched external control signal is input to the command decoder 63 through the input buffer, decoded, and identified as a read operation. Row predecode signals PXa to PXc output from the row predecoders 66a to 66c are input to the row decoder, a designated word line is selected from the memory cell arrays 3a to 3f, and read data from the memory cells are shown in the figure. Amplified by a sense amplifier that is not connected to the data bus.
[0007]
On the other hand, an internal command signal CMD and column predecode signals PYa-PYc, which are output signals from the command decoder, are input to the data system control circuits 65a-65c, and data bus selection and reading are performed in each circuit in the data input / output circuit. A control signal for controlling amplifier driving or the like is output from the data system control signal. In the figure, this control signal is shown as IOCNTa-IOCNTc.
[0008]
In the data input / output circuit, the data bus selection circuit selects an internal data bus corresponding to the bit width. The read data from the selected data bus is latched by the read amplifier circuit, amplified by the control signal output from the data system control circuit, and transferred to the data input / output buffer circuit. The transfer data is output from the input / output buffer circuit to the logic circuit via the external data bus.
[0009]
[Problems to be solved by the invention]
Here, as shown in FIG. 10, a case where a logic circuit and a semiconductor memory device are integrated on one chip is considered. The logic circuit 10 and the semiconductor memory device 1 exchange data via data buses DIOa to DIOf. As an advantage of integrating the logic circuit and the semiconductor memory device on the same chip, data can be exchanged without using external pins, so that high-speed data transfer between them can be realized, or the wiring pitch of the external data bus is shortened. In other words, the bit width can be expanded.
[0010]
By the way, a conventional semiconductor memory device for mixed use is composed of a control circuit, a data input / output circuit (hereinafter referred to as “peripheral circuit”) and a memory cell array determined for each product type, so that the logic circuit is relatively large. When a large memory capacity is required, generally, a countermeasure has been taken in which only the memory capacity is increased in the row direction while the peripheral circuit is fixed.
[0011]
However, with such a change in memory capacity, the operation speed of the semiconductor memory device itself deteriorates due to an increase in the load of the data bus due to an increase in the internal data bus length or a delay in the row predecoding signal transmitted through the row decoder. In particular, there is a problem that the data transfer capability is lowered.
[0012]
In addition, when the control circuit is arranged in the column direction as in the prior art, the wiring length from the external input to the data system control circuit or the row decoder is increased, and between the circuits in the control circuit There is also a problem that a large wiring area is required for wiring.
[0013]
Furthermore, in order to make full use of the high bit width which is an advantage of integration of the semiconductor memory device and the logic circuit, it is necessary to be able to flexibly change the bit width corresponding to each logic circuit.
[0014]
In order to solve the above-described problems, the present invention can easily change the configuration of the memory capacity and the bit width without deteriorating the operation speed, and has a circuit and layout configuration suitable for integration with a logic circuit. It is an object to provide a semiconductor memory device having the above.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a memory block according to the present invention is arranged corresponding to a memory cell array composed of memory cells arranged in a matrix, and amplifies read data from the memory cell array and writes external data. A data input / output circuit having a function to perform, and a row decoder having a function of selecting a word line from the memory cell array, receiving an external control signal and an external address signal, and controlling read and write operations to the selected memory cell Is a memory block that performs read and write operations to a selected memory cell by an external control signal and an external address signal, and a data input / output circuit controlled by the control circuit includes a memory cell array On the internal data bus arranged in a certain direction above And a plurality of data bus selection circuits having a function of selecting a designated data bus, and provided corresponding to the number of data buses selected by the plurality of data bus selection circuits. A plurality of read amplifier / write buffer circuits having a function of writing external data, and a data input / output buffer circuit provided corresponding to the plurality of read amplifiers / write buffer circuits and having a function of inputting / outputting read / write data to / from the outside In the direction of data transfer from the corresponding memory cell array, a plurality of data bus selection circuits, a plurality of read amplifier / write buffer circuits, and a plurality of data input / output buffer circuits are arranged in the corresponding memory cell array width in this order. Each of the memory cell arrays further includes a redundant relief fuse disposed adjacent to a side to which the external data bus of the data input / output circuit is connected, and the data input / output circuit is constituted by the redundant relief fuse. Has a decoding circuit for decoding the relief signal It is characterized by that.
[0016]
With this configuration, by arranging each circuit in the data transfer direction, the data transfer can be speeded up and a layout configuration suitable for a semiconductor memory device having a wide bit width can be realized.
[0017]
In the memory block according to the present invention, it is preferable that the data input / output circuit further includes a circuit having a function of changing a bit width by a control signal from the outside or the inside. This is because different bit widths can be easily configured in the same semiconductor memory device.
[0018]
The memory block according to the present invention has a function of configuring a plurality of bit widths by arranging a plurality of read amplifier / write buffer circuits and a plurality of data input / output buffer circuits in the extension direction of the internal data bus. It is preferable. This is because a semiconductor memory device having an arbitrary bit width corresponding to the logic circuit to be coupled can be easily designed.
[0021]
In the memory block according to the present invention, a plurality of memory cell arrays are disposed adjacent to the row decoder, a data input / output circuit disposed corresponding to the memory cell array is disposed adjacent to the control circuit, and the control circuit includes An input buffer circuit having a function of taking in an external control signal, an address buffer circuit having a function of taking in an external address signal, a command decode circuit having a function of decoding an output signal from the input buffer circuit, and data from the address buffer circuit A column predecoder having a function of receiving a column address signal for selecting a bus and predecoding the column address signal, and a function of receiving an output signal and a column predecode signal from a command decode circuit and controlling a data input / output circuit A data system control circuit having A row predecoder having a function of receiving a row address signal for selecting a word line to be output from the memory, predecoding the row address signal, and outputting a row predecode signal to the row decoder; The input buffer circuit, the command decode circuit, the column predecoder, the data system control circuit, and the row predecoder are preferably arranged in this order. By arranging the circuits constituting the control circuit in the order of critical paths with the width of the row decoder, the wiring length between the circuits in the control circuit can be extremely shortened, and the circuit operation can be speeded up. Because it can. In addition, since they are arranged in a certain direction, wiring of each circuit inside the control circuit and wiring from the data system control circuit to the data input / output circuit are facilitated.
[0022]
Next, in order to achieve the above object, the semiconductor memory device according to the present invention includes the memory block described above. Two Arranged adjacently, each memory block is controlled by the same external control signal and external address signal, and arbitrary data is transferred to each memory cell array in each memory block using each external input / output data bus of each memory block. It has a function of performing a read / write operation.
[0023]
With this configuration, it is possible to increase the memory capacity without deteriorating the operation speed of the semiconductor memory device.
[0024]
In the semiconductor memory device according to the present invention, it is preferable that the external control signal and the external address signal are branched inside a predetermined memory block and input to other memory blocks. This is because the logic circuit coupled to the outside can control all the memory blocks constituting the semiconductor memory device through only one interface related to the external control signal.
[0025]
The semiconductor memory device according to the present invention is preferably constituted by a memory block surrounded by a power supply line applied from the outside. This is because the power source of the semiconductor memory device can be strengthened and noise can be reduced.
[0026]
Further, in the semiconductor memory device according to the present invention, the memory block outputs data in synchronization with a clock, data input and output signal lines for normal operation and test mode, a latch circuit that latches output data during a test, and the like. It is preferable that two adjacent memory blocks have a function of performing a test using the same data input and output signal lines. This is because the number of test pins to be controlled during the test can be reduced.
[0027]
The semiconductor memory device according to the present invention is responsive to the detection level from the detection circuit in only one internal power supply circuit among the internal power supply circuits provided in the memory block. It is preferable that the output circuit operates. This is because the internal voltage level in the semiconductor memory device can be adjusted by adjusting only one detection circuit.
[0028]
In the semiconductor memory device according to the present invention, it is preferable to operate only one detection circuit among the detection circuits in the internal power supply circuit provided in the memory block provided in the semiconductor memory device. This is because it is possible to prevent the occurrence of a through current due to an adverse effect of the non-detection circuit or a variation in detection level due to process variations.
[0029]
The semiconductor memory device according to the present invention further includes a circuit that automatically determines the operation / non-operation of the detection circuit in the internal power supply circuit provided in the memory block based on the arrangement information of the adjacent memory block. Is preferred. This is because a semiconductor memory device that operates only one detection circuit among all the internal power supply circuits in the semiconductor memory device can be easily realized.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, a semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, a semiconductor memory device 1 has a configuration in which a plurality of memory blocks 2a, 2b and 2c which can operate independently are arranged adjacent to each other.
[0031]
Here, each memory block 2a-2c is surrounded by an externally applied power source. The semiconductor memory device 1 is coupled to the logic circuit 10 via an external control signal EXCMD, an external address signal EXADD, and external data buses DIOa to DIOf. That is, the semiconductor memory device 1 has only one input interface related to the external control signal EXCMD and the external address signal EADD from the logic circuit 10, and these external signals are, for example, the fourth layer metal wiring in the memory block 2b. And are input to the memory blocks 2a and 2c. On the other hand, since the external data buses DIOa to DIOf are arranged corresponding to the memory cell arrays 3a to 3f, any data can be read out from the memory cell arrays 3a to 3f in the memory blocks 2a to 2c. Writing is performed.
[0032]
Next, taking the memory block 2a as an example, the configuration of each memory block will be described. As shown in FIG. 2, the memory block 2a includes memory cell arrays 3a and 3b made up of memory cells arranged in a matrix, and is provided corresponding to the memory cell array, and selected memory cells via internal data buses DLa and DLb. Data input / output circuits 4a and 4b for amplifying and outputting read data and writing external data, a row decoder 5a for selecting a word line from the memory cell array, an external control signal and an external address signal, and a data input / output circuit 4a and 4b and a control circuit 6a for controlling the row decoder 5a. Reference numeral 7a denotes an internal power supply circuit for transmitting a potential generated in the memory block. Reference numerals 8a and 8b denote redundant relief fuses, which are arranged corresponding to the memory cell array.
[0033]
The data input / output circuits 4a and 4b are connected via data bus selection circuits 41a and 41b for selecting a data bus corresponding to the bus width of the external data buses DIOa and DIOb from the internal data buses DLa and DLb, and the internal data buses DLa and DLb. Read amplifier / write buffer circuits 42a and 42b for amplifying read data from memory cells and writing data, and data input / output buffer circuit 43a for exchanging data with external devices via external data buses DIOa and DIOb And 43b, which are arranged as shown in FIG.
[0034]
FIG. 3 shows a detailed arrangement of the control circuit 6a. As shown in FIG. 3, the control circuit 6a has an input buffer circuit 61a that takes in an external command signal EXCMD branched from the adjacent memory block 2a from the surface facing the logic circuit 10, and an external buffer that is also branched from the memory block 2a. An address buffer circuit 62a that captures the address signal EXADD, a command decoder 63a that decodes the signal INCMD output from the input buffer, and a column address signal YADD that is output from the address buffer 62a and selects the internal data bus, A column predecoder 64a that performs decoding, a data system control circuit 65a that takes in an output signal CMD from the command decoder and an output signal PY from the column predecoder, and outputs a control signal IOCNT for controlling the data input / output circuit; It takes in a row address signal for selecting a word line from the memory cell array, and a row predecoder 66a for outputting the row predecode signal PX in the row decoder.
[0035]
As shown in FIG. 2 and FIG. 3, since the data input / output circuits 4a and 4b are arranged in the direction of data transfer according to the width of the memory cell array, the data transfer of the data input / output circuits 4a and 4b is speeded up. In addition, an optimal layout arrangement of the data input / output circuits 4a and 4b for realizing a wide bit width suitable for logic mixed mounting can be realized.
[0036]
The control circuit 6a is laid out in the order of critical paths in the width of the row decoder from the input buffer circuit 61a and the address buffer circuit 62a, which are external signal capturing circuits serving as inputs, to the row predecoder 66a serving as an output, and Since the wiring length is shortened, the critical path is speeded up.
[0037]
Further, in the data system control circuit, the output signals from the column predecoder 64a and the command decoder 63a are connected with a short wiring length, and these wirings are all arranged in a certain direction from the input buffer to the row decoder. Speeding up the circuit operation by reducing the wiring delay and wiring to each circuit in the control circuit and wiring from the data system control circuit to each circuit in the data input / output circuit are facilitated.
[0038]
The memory blocks 2a-2c having such a configuration are arranged as shown in FIG. The external control signal and the external address signal are input to one semiconductor memory device from one interface and branched in the memory block 2b constituting the semiconductor memory device 1, and an input buffer circuit and an address buffer circuit of each memory block Is input.
[0039]
Each memory block is designed so that it can operate independently. Therefore, the original operation speed is degraded by adopting a configuration in which external signals are internally branched and input to each memory block for control. Therefore, the capacity of the semiconductor memory device 1 can be increased. At this time, the wiring region for wiring the external control signal and the external address signal input to the control circuit in each memory block is formed by wiring on the peripheral circuit by using, for example, a fourth layer metal wiring. Thus, an increase in area due to wiring of external signals can be prevented.
[0040]
In addition, normal mode signal lines that are used to control these external signals for normal operation and test mode signal lines that are used only during testing and are fixed to “high” or “low” during normal operation are alternately arranged. As a result, wiring delay due to crosstalk between the wirings is reduced. Further, in the region where the external signal on the peripheral circuit is not wired, the power supply line is wired on the mesh of the entire semiconductor memory device 1 using the fourth layer metal wiring, so that the power supply is strengthened.
[0041]
Further, since each memory block is surrounded by a power line, the power line is further strengthened at the boundary of each memory block. Further, the enclosed power supply line has an effect of reducing noise between the memory cell arrays or data input / output circuits in the adjacent memory blocks. Furthermore, the semiconductor memory device 1 having such a configuration makes it possible to easily design a memory block having an arbitrary capacity by simply arranging a plurality of memory blocks and wiring external signals.
[0042]
As described above, according to the first embodiment, a plurality of memory blocks each having a function of independently operating a semiconductor memory device are arranged adjacent to each other, and an external input signal is provided inside the memory block constituting the semiconductor memory device. The data is read and written to each memory cell array via the logic circuit and each external data bus without deteriorating the operation speed of the memory block. The memory capacity of the semiconductor memory device can be increased.
[0043]
In addition, the control circuit of each memory block is arranged in the order of the critical path and the input buffer, command decoder, column predecoder, column control circuit, and row predecoder in accordance with the width of the row decoder. Peripheral circuits can be speeded up by shortening the wiring length between each circuit, and wiring from the data system control circuit to the data input / output circuit is facilitated by arranging each wiring of the control circuit in the column direction. Become.
[0044]
Further, by arranging the data input / output circuit in the order of the memory cell array, the data bus selection circuit, the read amplifier / write buffer circuit, and the data input / output buffer circuit, the data transfer speed can be increased. By surrounding the power supply line, the power supply of the entire semiconductor memory device is strengthened.
[0045]
(Embodiment 2)
FIG. 4 is a configuration diagram of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 4, the semiconductor memory device 1 has a configuration in which memory blocks 2a-2c are arranged adjacent to each other. Internal power supply circuits 7a-7c indicate internal power supply circuits provided in each memory block, and each detection level VDECa-VDECc output from the detection circuits 71a-71c in each internal power supply circuit is only in the memory block 1. Combined as one detection level VDEC, this common detection level VDEC is input to the output circuits 72a to 72c of all internal power supply circuits provided in the semiconductor memory device, and the internally generated potential VOUT is transmitted to each memory block. The
[0046]
Reference numeral 73 denotes an internal power supply operation determination circuit which outputs a determination signal VOPa-VOPc to the detection circuit based on the adjacent information of the memory block and gives instructions regarding the operation and non-operation of the detection circuit.
[0047]
FIG. 5 is a diagram showing a specific configuration of the internal power supply operation determination circuit. In FIG. 5, reference numerals 73a to 73c denote internal power supply operation determination circuits provided in the internal power supply circuits in the memory blocks 2a to 2c. 91a to 91c take in adjacent information of each memory block and The determination circuit which determines non-operation and instruct | indicates is shown. Reference numerals 92a to 92c denote adjacent information output circuits for supplying adjacent information to adjacent memory blocks. The operation of the internal power supply operation determination circuit will be specifically described below.
[0048]
The decision circuits 91a to 91c are latch circuits that use a power-on reset signal as an input to the gate of the first stage inverter. The source side of the P-channel transistor constituting the inverter is adjacent to the adjacent memory block. Output signals in the information output circuits 92a to 92c are connected.
[0049]
The adjacent information output circuits 92a to 92c are configured such that resistors Ra to Rc are coupled to the external power supply VDD and arranged at the end of the memory block by, for example, a fourth layer metal wiring. The power-on reset signal input to the determination circuits 91a to 91c is a signal that maintains the “high” level when the power is turned on and falls to “low” after a predetermined time has elapsed.
[0050]
In other words, each determination circuit in the internal power supply determination circuit is latched with “high” data when the power is turned on. Thereafter, when the power-on reset signal falls to “low”, the adjacent information of the memory block, that is, the internal power supply operation determination circuits 73b to 73c in which the memory block is adjacent to the upper side in FIG. Since VDD is input to the source potential of the P-channel transistor of the first stage inverter, “low” is latched in the determination circuit when the power-on reset signal falls to “low”.
[0051]
On the other hand, in FIG. 7, since the adjacent information is not input to the internal power supply operation determination circuit 73 in the memory block arranged at the upper end of the semiconductor memory device, the source potential of the P channel transistor constituting the first stage inverter is “OPEN”. Even if the power-on reset signal falls to “low”, the latched “high” data continues to be latched as it is. An output signal from the latch circuit is input to a detection circuit inside the internal power supply circuit, and the operation / non-operation of the detection circuit is determined.
[0052]
For this reason, among all internal power supply circuits in the semiconductor memory device, only the detection circuit inside the internal power supply circuit in the memory block at the upper end in FIG. 7 operates, and the detection levels of the respective internal power supply circuits are combined. In the semiconductor memory device, the output level of each internal power supply circuit is determined by only one detection level. As a result, when taking measures to adjust the voltage level using a fuse, etc., all the internal power supply circuits determine the output potential in response to a single detection level, so all the detection circuits in the memory block are adjusted. The detection level may be adjusted only for the detection circuit that determines the detection level.
[0053]
In addition, since only one detection circuit is operated in the semiconductor memory device and the other detection circuits are not operated, the detection level due to process fluctuations is reduced by combining the detection levels as well as reducing the power consumption. It is possible to prevent the occurrence of a through-current that flows due to variations in the current. Further, by providing the internal power supply operation determination circuit, a semiconductor memory device that operates only one detection circuit among all internal power supply circuits in the semiconductor memory device can be easily realized.
[0054]
As described above, according to the second embodiment, among all the internal power supply circuits of the memory block constituting the semiconductor memory device, all the internal power supplies are detected according to the detection levels output from the detection circuit inside the single internal power supply generation circuit. In order to determine the generated potential of the circuit, the internal potential generated in the internal power supply circuits of all the memory blocks constituting the semiconductor memory device can be adjusted by adjusting the detection level of only one detection circuit. In addition, each internal power supply circuit is provided with an internal power supply operation determination circuit to operate the detection circuit of the internal power supply circuit of only one memory block among all the memory blocks constituting the semiconductor memory device based on adjacent information. By combining the detection levels, it is possible to prevent the occurrence of a through current that flows due to variations in the detection levels caused by process variations.
[0055]
In the second embodiment, the detection circuit inside the internal power supply circuit in the leftmost memory block is operated in the memory blocks constituting the semiconductor memory device, but by changing the internal power supply operation determination circuit, The detection circuit inside the internal power supply circuit of any memory block constituting the semiconductor memory device may be operated.
[0056]
(Embodiment 3)
FIG. 6 shows a main part of the semiconductor memory device according to the third embodiment of the present invention, which is composed of memory blocks 2a and 2b. In the semiconductor memory device according to the third embodiment, the 1-bit test data input signal PDIN and the test data output signal PDO are stored in the memory block 2a as in the case of the external control signal and the external address signal as in the first embodiment. And branch to the inside to be wired to each memory block. In the memory blocks 2a and 2b, in order to reduce the number of test pins at the time of inspection, a memory cell array and bits are decoded by a decoding circuit (not shown), and inspection is performed by inputting and outputting 1-bit data.
[0057]
In FIG. 6, reference numerals 100a-100q and 101a-101q denote data output buffer circuits in the memory blocks 2a and 2b, respectively, which are turned on when “high” is input to the input OUTEN, and “Hi−” at the “low” input. Z ”state. The decode signal PT from the control signal is input to OUTEN of each data output buffer circuit, and only one output buffer circuit is turned on, and the others are set to the “Hi-Z” state. Outputs from the output buffer circuits are coupled to one wiring as PDOUTa and PDOUTb and input to the test data latch circuits 102a and 102b. The test data latch circuit includes a DFF circuit that outputs data in synchronization with the rising edge of the clock. The transfer instruction circuits 103a and 103b are composed of a tristate buffer and a switch 104, and control data output to the outside by a control signal PDOEN1 or PDOEN2 from the control circuit. Hereinafter, the data output operation during the test will be specifically described with reference to a timing chart (FIG. 7). Here, it is assumed that the semiconductor memory device has the memory blocks 2a and 2b having the latency 2.
[0058]
First, it is assumed that a read command is input to the memory blocks 2a and 2b in clock cycles #a and #b. For read data in clock cycle #a, output signals PDOUTa and PDOUTb from the output buffer are determined by the rising edge of clock cycle #c after two cycles. Therefore, the test data latch circuits 102a and 102b can take the output signals PDOUTa and PDOUTb during the clock falling period of the clock cycle #b, receive the rising edge of the clock cycle #c, and transfer the output signals PDOBa and PDOBb to the transfer circuit. Output to.
[0059]
The transfer circuits 103a and 103b are controlled by control signals PDOEN1 and PDOEN2 selected by the switches 104a and 104b, respectively. PDOEN1 and PDOEN2 are pulse signals synchronized with the rising edge and the falling edge, respectively. Therefore, the output signal DQa # of the memory block 2a is synchronized with the rising edge of the test data output signal clock cycle #c on the data output signal line PDO. The output signal DQB # a of the memory block 2b is output in synchronization with the falling edge of the clock cycle #c.
[0060]
Hereinafter, the read data DQa # b and DQb # b of the memory blocks a and b are output in synchronization with the read data in the clock cycle #b in synchronization with the rising and falling edges of the clock cycle #d. . For this reason, there is only one output signal line for the test data necessary for the inspection of the memory blocks 2a and 2b.
[0061]
As described above, according to the third embodiment, the data input / output circuit receives the decode signal for decoding the output bit output from the control signal, and only one of them is turned on, and the others are set to “Hi− The data output buffer circuit in the “Z” state, the test data latch circuit that latches the output data of the data output buffer circuit in the test mode, and the output data from the test data latch circuit are shared by the adjacent memory blocks by the control signal Reduce the number of test pins to be controlled during testing, because the output data of the adjacent memory block is divided into the rising edge and falling edge of the clock by the transfer circuit that outputs to the test mode data output signal line It becomes possible.
[0062]
(Embodiment 4)
FIG. 8 shows a main part of the semiconductor memory device according to the fourth embodiment of the present invention. Reference numeral 4 denotes a data input / output circuit, which includes a data bus selection circuit 41, a read amplifier / write buffer circuit 42, a data input circuit. An output buffer circuit 43 and a decode circuit 44 that decodes the redundancy relief signal ROM output from the redundancy relief fuse, and 8 is a redundancy relief fuse. The redundancy relief signal output from the redundancy relief fuse is decoded by a decoding circuit to rescue the internal data bus unit.
[0063]
For this reason, the data input / output circuit is arranged in order of the data bus selection circuit 41, the decode circuit 44, the read amplifier / write buffer circuit 42, and the data input / output buffer circuit 43 from the memory cell array. Arranged adjacent to the output buffer circuit 43.
[0064]
Conventionally, since it is necessary to make the fuse interval wider than the wiring interval, it has been difficult to arrange the fuses corresponding to each memory cell array when the bit width is expanded. However, by providing the data input / output circuit 4 with the decode circuit 44 for decoding the relief information ROM output from the redundancy relief fuse 8 in this way, the number of fuses can be greatly reduced, and the redundancy relief fuse 8 can be replaced with the data. By arranging it adjacent to the outermost part of the input / output circuit 4, it is possible to secure a sufficient wiring area for providing an external logic circuit and a wide data bus width even if a fuse is arranged corresponding to each memory cell array.
[0065]
In the fourth embodiment, the output bit width to the outside can be changed according to the application by the bit control signal output from the data system control circuit.
[0066]
FIG. 9 is a main part configuration diagram of a memory block in the semiconductor memory device according to the fourth embodiment. In FIG. 9, it is assumed that the memory block has a 128-bit internal data bus and the external data bus can be changed to 16 or 8 bits. Here, a read operation will be described as an example, and an operation with a bit width of 16 bits or 8 bits will be described.
[0067]
First, read data of the selected memory cell in the memory cell array corresponding to the external address signal is output to the internal data bus. The internal data bus is selected from 128 to 16 in response to a data bus selection signal from the control circuit. The 16 read amplifier / write buffer circuits 421a to 421q provided corresponding to the selected 16 buses are driven by read amplifier drive signals, respectively, and the amplified read data DLOa to DLOq are respectively output buffers. Transferred to circuits 111a-111q. The output buffer circuit is controlled by a bit width control signal IOCHG from the control circuit. When IOCHG is “low”, “high” is input to OUTEN of the output buffer circuit, and all 16 output buffer circuits are turned on. When “high”, only eight bits selected for the bit selection address PTADD are in a conductive state, and the others are output to be “Hi-Z”. In the external data bus DIO, two adjacent data buses are connected by an N-channel transistor, and when the bit control signal IOCHG becomes “high”, the adjacent output data signal lines are short-circuited and the same data is output.
[0068]
In addition, the read amplifier / write buffer circuit and the input / output buffer circuit in the data input / output circuit are formed into cells by each of the 16 read amplifier circuits and the input / output buffer circuit as set here, and a larger bit width is required. When designing a semiconductor memory device, it is possible to easily design a memory block corresponding to a required bit width while maintaining the data transfer speed by arranging the circuit cells in the row direction.
[0069]
As described above, according to the fourth embodiment, the number of fuses can be reduced by providing a decode circuit for decoding a relief signal from the redundancy relief fuse in the data input / output circuit. Since it is arranged adjacent to the outermost part of the output circuit, a sufficient wiring area for providing a wide data bus width with the outside can be secured even if a fuse is arranged corresponding to each memory cell array.
[0070]
In addition, the bit control signal and the bit selection signal are used to conduct part or all of the data input / output buffer circuit in the data input / output circuit, the others are set to “Hi-Z”, and the external data bus is controlled. The bit width can be easily changed.
[0071]
Furthermore, each of the plurality of read amplifier / write buffer circuits and data input / output buffer circuits is made into cells, and each circuit cell is arranged in the row direction as necessary, so that it is possible to easily perform the necessary external operation while maintaining the data transfer rate. A memory block corresponding to the bit width can be easily designed.
[0072]
In the fourth embodiment, the bit control signal is generated internally, but it may be controlled from the outside, and the bit width is input together with the external address signal for selecting the bit. It goes without saying that a plurality of bit configurations may be selected.
[0073]
【The invention's effect】
As described above, according to the memory block of the present invention, the memory cell array is arranged corresponding to the memory cell array in which the memory cells are arranged on the matrix, and the data input / output circuit transfers data from the memory cell array to the external data bus. A data input / output circuit having a configuration arranged in order, a row decoder for selecting a word line from the memory cell array, an external control signal and an address signal are fetched, and the data input / output circuit and the row decoder are controlled to face the logic circuit. The layout design can be performed easily, and high-speed operation and high-speed data transfer are made up of a control circuit arranged in the order of critical paths from to the row decoder and a redundant relief fuse corresponding to the memory cell array. It becomes possible to do.
[0074]
In addition, the data input / output circuit can easily change the bit width by a control signal from the control circuit, and the data input / output circuit can be easily configured by arranging a plurality of circuit cells in the data input / output circuit. Thus, it is possible to realize a memory block having an arbitrary bit configuration.
[0075]
According to the semiconductor memory device of the present invention, a plurality of the above-described memory blocks are arranged adjacent to each other, and an external control signal and an external address signal are branched inside the memory block and input to each memory block. With the configuration of controlling, high-speed operation can be performed even when the memory capacity is increased.
[0076]
Furthermore, according to the semiconductor memory device of the present invention, by including the determination circuit that determines the operation / non-operation of the internal power supply circuit based on the adjacent information of the memory block, the detection circuit of the internal power supply circuit in all the memory blocks Among them, only one detection circuit is operated, and the output circuit in all internal power supply circuits is operated according to the detection level, thereby detecting only one detection circuit among the detection circuits of a plurality of internal power supply circuits. Thus, it becomes possible to adjust the internally generated potential of the entire semiconductor memory device.
[0077]
According to the semiconductor memory device of the present invention, the input / output data signal at the time of the test is wired to each memory block, and the data is output in synchronization with the latch circuit that latches the output data of the data output buffer circuit and the clock. By providing the transfer circuit, the test can be performed with fewer test pins at the time of the test. Furthermore, it is possible to easily design a semiconductor memory device having a bit width and a memory capacity as required.
[Brief description of the drawings]
1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a configuration diagram of a memory block according to the first embodiment of the present invention.
FIG. 3 is a schematic configuration diagram of a control circuit in the memory block according to the first embodiment of the present invention;
FIG. 4 is a schematic configuration diagram of an internal power supply circuit in the semiconductor memory device according to the second embodiment of the present invention;
FIG. 5 is a configuration diagram of an internal power supply operation determination circuit in the semiconductor memory device according to the second embodiment of the present invention;
6 is a configuration diagram of an output buffer circuit in a semiconductor memory device according to a third embodiment of the present invention; FIG.
FIG. 7 is a timing chart showing a data output operation during a test in the semiconductor memory device according to the third embodiment of the present invention;
FIG. 8 is a schematic configuration diagram of a memory block according to a fourth embodiment of the present invention.
FIG. 9 is a configuration diagram of a data output circuit in the memory block according to the fourth embodiment of the present invention;
FIG. 10 is an overall configuration diagram of a conventional semiconductor memory device.
FIG. 11 is a configuration diagram around a data input / output circuit in a conventional semiconductor memory device.
FIG. 12 is a configuration diagram of a control circuit in a conventional semiconductor memory device.
[Explanation of symbols]
1 Semiconductor memory device
2 memory blocks
3, 3a-3f Memory cell array
4, 4a-4f Data input / output circuit
41, 41a, 41b Data bus selection circuit
42, 42a, 42b, 421a-421q Read amplifier / write buffer circuit
43, 43a, 43b Data input / output circuit
44 Redundant relief information decoding circuit
5a, 5b, 5c row decoder circuit
6, 6a, 6b, 6c control circuit
61, 61a Input buffer circuit
62, 62a Address buffer circuit
63, 63a Command decode circuit
64, 64a, 64b, 64c Column predecoder
65, 65a, 65b, 65c Data system control circuit
66, 66a, 66b, 66c Row predecoder
7, 7a, 7b, 7c Internal power supply circuit
71a, 71b, 71c Detection circuit in internal power supply circuit
72a, 72b, 72c Output circuit in internal power supply circuit
73a, 73b, 73c Internal power supply operation determination circuit in internal power supply circuit
8, 8a, 8b, 8c Redundant relief fuse
91a, 91b, 91c determination circuit
92a, 92b, 92c Adjacent information output circuit
100a-100q output buffer circuit
101a-101q output buffer circuit
102a, 102b Test data latch circuit
103a, 103b Transfer circuit
DL, DLa-DLf Internal data bus
DIO, DIOa-DIOf External data bus
EXCMD External control signal
EXADD external address signal
INCMD internal command signal
CMD command decode signal
XADD row address signal
YADD column address signal
IOCNYT, IOCNTa, IOCNTb, IOCNTc Data system control signal
PX, PXa, PXb, PXc Row predecode signal
PY, PYa, PYb, PYc Column predecode signal
VOUT Internally generated potential
VDEC, VDECa, VDECb, VDECc detection level
VOPa, VOPb, VOPc operation instruction signal
Ra, Rb, Rc resistance
POR power-on reset signal
PDOUTa, PDOUTb Output signal from data output buffer
Output signal from PDOBa, PDOBb test data latch circuit
PDOEN1, PDOEN2 Data transfer control signal
PDO External data output signal
PT, PTADD bit selection decode signal
DQa # a, DQa # b, DQb # a, DQb # b Output data
IOCHG bit width control signal

Claims (11)

A memory cell array composed of memory cells arranged in a matrix;
A data input / output circuit which is arranged correspondingly and has a function of amplifying read data from the memory cell array and writing external data;
A row decoder having a function of selecting a word line from the memory cell array;
A control circuit that receives an external control signal and an external address signal and controls read and write operations to the selected memory cell is further provided, and the selected memory cell is controlled by the external control signal and the external address signal. A memory block that performs read and write operations of
The data input / output circuit controlled by the control circuit is provided corresponding to an internal data bus arranged in a certain direction on the memory cell array, and has a function of selecting a specified data bus. Circuit,
A plurality of read amplifier / write buffer circuits provided corresponding to the number of data buses selected by the plurality of data bus selection circuits, and having a function of amplifying read data of the memory cell array and writing external data;
A data input / output buffer circuit provided corresponding to the plurality of read amplifier / write buffer circuits and having a function of inputting / outputting read / write data to / from the outside;
In the direction of data transfer from the corresponding memory cell array, the plurality of data bus selection circuits, the plurality of read amplifier / write buffer circuits, and the plurality of data input / output buffer circuits are arranged in the corresponding memory cell array width ,
Each of the memory cell arrays further includes a redundant relief fuse arranged adjacent to the side to which the external data bus of the data input / output circuit is connected, and the data input / output circuit is repaired by the redundant relief fuse. A memory block having a decoding circuit for decoding a signal.   2. The memory block according to claim 1, wherein the data input / output circuit further includes a circuit having a function of changing a bit width by a control signal from the outside or the inside.   3. The memory block according to claim 2, wherein the plurality of read amplifier / write buffer circuits and the plurality of data input / output buffer circuits are arranged in the extension direction of the internal data bus, thereby having a function of configuring a plurality of bit widths. A plurality of the memory cell arrays are disposed adjacent to the row decoder;
The data input / output circuit disposed corresponding to the memory cell array is disposed adjacent to the control circuit;
An input buffer circuit having a function of taking in the external control signal, an address buffer circuit having a function of taking in the external address signal, and a command decoding circuit having a function of decoding an output signal from the input buffer circuit A column predecoder having a function of receiving a column address signal for selecting a data bus from the address buffer circuit and predecoding the column address signal, an output signal from the command decode circuit, and the column predecode signal A data system control circuit having a function of controlling the data input / output circuit, a row address signal for selecting a word line output from the address buffer, and predecoding the row address signal; Row predeco to the row decoder It has a row pre-decoder has a function of outputting a de signal,
2. The memory block according to claim 1, wherein the input buffer circuit, the command decode circuit, the column predecoder, the data system control circuit, and the row predecoder are arranged in this order in the row decoder direction. The two memory blocks according to claim 1 are arranged adjacent to each other, each of the memory blocks is controlled by the same external control signal and external address signal, and each external input / output data bus of each of the memory blocks is used. A semiconductor memory device having a function of performing a read / write operation of arbitrary data to each of the memory cell arrays in each of the memory blocks.   6. The semiconductor memory device according to claim 5, wherein the external control signal and the external address signal are branched inside the predetermined memory block and input to each of the other memory blocks.   6. The semiconductor memory device according to claim 5, wherein said memory block is surrounded by a power supply line applied from outside.   6. The output circuit of the internal power supply circuit of the entire semiconductor memory device operates in response to a detection level from a detection circuit in only one of the internal power supply circuits provided in the memory block. The semiconductor memory device described.   9. The semiconductor memory device according to claim 8, wherein only one of the detection circuits among the detection circuits in an internal power supply circuit provided in the memory block provided in the semiconductor storage device is operated.   The semiconductor memory device according to claim 9, further comprising a circuit that automatically determines operation / non-operation of a detection circuit within an internal power supply circuit provided in the memory block based on arrangement information of the adjacent memory block.   A determination circuit that automatically determines operation / non-operation of a detection circuit in an internal power supply circuit provided in the memory block based on arrangement information of adjacent memory blocks, and includes internal power supplies of all the memory blocks; 6. The semiconductor memory device according to claim 5, wherein an output circuit of the circuit operates in response to a detection level output from a detection circuit in only one internal power supply circuit that operates in accordance with an output signal from the determination circuit.

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