JP4151449B2

JP4151449B2 - Channel control device, data transfer device, and channel control method

Info

Publication number: JP4151449B2
Application number: JP2003084793A
Authority: JP
Inventors: 利男木村
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 2003-03-26
Filing date: 2003-03-26
Publication date: 2008-09-17
Anticipated expiration: 2023-03-26
Also published as: JP2004295323A

Description

【０００１】
【発明の属する技術分野】
この発明は、チャネルコントロール装置の動作指示と、主記憶装置のメモリリプライデータと、をチャネル装置に転送するデータ転送装置に関し、特に、メモリリプライデータの転送によって、動作指示の転送が遅らされることを防止するデータ転送装置に関する。
【０００２】
【従来の技術】
従来のデータ転送装置２を図２を参照して説明する。主記憶装置１０からのメモリリプライデータがチャネルコントロール装置６０の作用により、レジスタ６２に格納され、セレクタ６８及びダウンデータバス４０を介してチャネル装置５１乃至５ｎにデータ転送される。このデータ転送中に、マイクロプログラム制御部６１がチャネル装置５１に動作指示を発行する場合、該動作指示をレジスタ６４に格納して、ビジーフラグ６３をオンにセットする。優先順位判定回路６７は、レジスタ６２のメモリリプライデータと、レジスタ６４の動作指示と、が競合した場合、メモリリプライデータを優先してデータ転送する指示をセレクタ６８に出す。このため、メモリリプライデータが連続して転送している間は、動作指示がレジスタ６４で待ち合わせさせられる。この待ち合わせ中は、ビジーフラグ６３はオンのままである。
【０００３】
上述の説明のように、従来のチャネルコントロール装置６０においては、メモリリプライデータが連続している間は、チャネル装置５１への動作指示が待ち合わせさせられる結果、データのオーバランといった事象が生じる問題がある（例えば、特許文献１参照）。
【０００４】
【特許文献１】
特開２０００−４７９７３号公報（図３及び従来技術の説明）。
【０００５】
【発明が解決しようとする課題】
上述の課題を解決するため、データ転送装置で、チャネル装置への動作指示と、データ転送と、が競合して動作指示が待ち合わせさせられているとき、予め、マイクロプログラム制御部から初期値を設定したカウントダウンタイマを起動し、当該タイマの値が「０」となったとき、主記憶装置からのメモリリプライデータが予めマイクロプログラム制御部が指定したチャネル装置へのものであれば、動作指示の優先順位を上げて、強制的にメモリリプライデータの転送に割り込ませて転送することにより、動作指示の待ち合わせ時間を低減する。
【０００６】
この発明目的は、マイクロプログラム制御部が発行した動作指示がメモリリプライデータと競合し、動作指示が待ち合わせさせられて、一定時間経過した場合、メモリプライデータと、該動作指示と、の優先順位を変更することにより、動作指示発行の待ち合わせ時間を短縮して転送し、オーバーランなどの事象が発生することを防止する。
【０００７】
【課題を解決するための手段】
そのため、この発明の、チャネルコントロール装置が、自身が発行する動作指示と、主記憶装置のメモリリプライデータと、をチャネル装置にダウンデータバスを介してデータ転送するデータ転送装置において、前記メモリリプライデータの転送と、前記動作指示の転送と、が競合して前記チャネル装置に対する前記動作指示が遅らされるとき、前記動作指示を、前記メモリリプライデータの転送に所定の遅れ以内に割り込ませ、前記チャネル装置に送出するチャネルコントロール装置を有することを特徴とする。
【０００８】
更に、前記動作指示は、送出先のチャネル装置のチャネル番号を含んで発行されることを特徴とする。
【０００９】
更に、前記メモリリプライデータは、送出先のチャネル装置のチャネル番号と、メモリリプライデータ自身が有効である示す有効データと、転送するデータと、を含むことを特徴とする。
【００１０】
更に、前記チャネルコントロール装置は、前記主記憶装置のメモリリプライデータを受け取って、一時記憶するレジスタと、前記レジスタのメモリリプライデータを移送して保持する一時保持レジスタと、前記チャネル装置に動作指示を発行するマイクロプログラム制御部と、前記動作指示を保持する動作指示レジスタと、前記動作指示が発行されたことを示すビジーフラグと、前記動作指示対象のチャネル装置のチャネル番号を保持するチャネル番号レジスタと、前記レジスタのチャネル番号と、前記チャネル番号レジスタのチャネル番号と、を比較し一致を検出する比較器と、前記マイクロプログラム制御部が動作指示発行から、所定の経過時間を検出するタイマと、前記タイマが所定時間の経過の検出出力と、ビジーフラグの出力と、前記比較器のチャネル番号一致出力と、前記レジスタの有効データ出力と、によって、前記動作指示を前記メモリリプライデータより優先して選択し、前記ビジーフラグをオフする優先順位判定回路と、前記優先順位判定回路の優先順位出力によって、前記動作指示レジスタの動作指示と、前記レジスタのメモリリプライデータと、前記一時保持レジスタのメモリリプライデータと、から一つを選択し、前記チャネル装置に送出するセレクタと、を備えることを特徴とする。
【００１１】
更に、前記優先順出力は、前記ビジーフラグの出力がないとき、前記レジスタのメモリリプライデータを選択し、前記ビジーフラグの出力があり、かつタイマ出力及び前記比較器出力並びに前記レジスタの有効データ出力があるとき、前記動作指示レジスタの動作指示を選択し、前記動作指示が選択された次のサイクルでは、前記一時保持レジスタのメモリリプライデータを選択することを特徴とする。
【００１２】
更に、前記セレクタは、前記優先順位出力によって、前記レジスタのメモリリプライデータの連続する転送出力に前記動作指示を割り込ませて転送出力させ、前記動作指示の割り込み転送出力によって、保留されたメモリリプライデータを前記一時保持レジスタから転送出力させ、以後は前記レジスタのメモリリプライデータを転送出力させる切り替えを行うことを特徴とする。
【００１３】
【発明の実施の形態】
この発明について、図面を参照して説明する。発明の実施の一形態を示す図１を参照すると、データ転送装置１は、主記憶装置１０と、チャネルコントロール装置２０と、ダウンデータバス４０と、複数のチャネル装置５１乃至５ｎと、を備え、チャネルコントロール装置２０に、主記憶装置１０と、ダウンデータバス４０と、を直接接続し、ダウンデータバス４０を介してチャネル装置５１乃至５ｎを接続している。
【００１４】
チャネルコントロール装置２０は、マイクロプログラム制御部２１と、レジスタ２２と、ビジーフラグ２３と、動作指示レジスタ２４と、一時保持レジスタ２５と、タイマ２６と、優先順位判定回路２７と、セレクタ２８と、チャネル番号レジスタ２９と、比較器３０と、を含む。各チャネル装置５１乃至５ｎからのメモリリクエストは、図示しないパスを介してチャネルコントロール装置２０で優先順位がとられて主記憶装置１０に送出される。
【００１５】
メモリリクエストに対する主記憶装置１０からのメモリリプライデータは、レジスタ２２に格納された後、セレクタ２８とレジスタ２５に送出される。レジスタ２５は、レジスタ２２のデータを移送した同一のデータである。セレクタ２８は、優先順位判定回路２７の指示により、動作指示レジスタ２４、レジスタ２２、一時保持レジスタ２５の内から、いずれか一つを選択しチャネル装置に送出する。
【００１６】
マイクロプログラム制御部２１は、チャネル装置５１乃至５ｎに動作指示を発行する場合、その動作指示に対応するタイマ値をタイマ２６に設定し、ビジーフラグ７を「１」にセットするとともに動作指示レジスタ２４に、動作指示を格納する。動作指示レジスタ２４に格納された動作指示は、セレクタ２８で、動作指示レジスタ２４が選択されてチャネル装置５１乃至５ｎに送出されるまで、動作指示レジスタ２４に保持される。
【００１７】
セレクタ２８で動作指示レジスタ２４が選択されると、優先順位判定回路２７によって、ビジーフラグ２３が「０」にリセットされる。ビジーフラグ２３が「１」となると、タイマ２６は、カウントダウンを開始して値が「０」になると、優先順位判定回路２７に通知する。チャネル番号レジスタ２９には、マイクロプログラム制御部２１から動作指示を発行する対象のチャネル番号が書き込まれ、主記憶装置１０からのメモリリプライデータがレジスタ２２に格納される度に、比較器３０がチャネル番号レジスタ２９のチャネル番号と、メモリリプライデータ内に保持されている対象のチャネル装置５１乃至５ｎのチャネル番号と、を比較し、両者のチャネル番号が一致すると、同一のチャネル装置５１に対して競合が生じたことになり、優先順位判定回路２７に該競合を通知する。
【００１８】
優先順位判定回路２７は、動作指示レジスタ２４の動作指示と、レジスタ２２のメモリリプライデータと、が競合した場合、通常で有ればレジスタ６のメモリリプライデータを優先させるが、動作指示レジスタ２４に動作指示が格納されており、かつビジーフラグ２３が「１」で、タイマ２６の値が「０」で、かつ比較器１４でチャネル番号を比較した結果が一致した場合、セレクタ２８に動作指示レジスタ２４を選択させ、ビジーフラグ２３を「０」にリセットする。その後、優先順位判定回路２８はセレクタ２８に、一時保持レジスタ２５を選択させ、送出が保留させられていたメモリリプライデータを送出する。
【００１９】
次に、この実施の形態の動作について説明する。各チャネル装置５１乃至５ｎからの主記憶装置１０へのメモリリクエストに対するメモリリプライデータは、主記憶装置１０からレジスタ２２に送出される。メモリリプライデータには、メモリリクエストを発行し、メモリリプライデータを受け取るべきチャネル装置５１のチャネル番号２２１と、該メモリリプライデータが有効であることを示す有効データ２２２と、を含んでいる。主記憶装置１０からチャネル装置５1に連続して、メモリリプライデータが送出されている場合、毎サイクルごとにレジスタ２２にメモリリプライデータが順次に格納される。このため、この間に、マイクロプログラム制御部２１からチャネル装置５１への動作指示がレジスタ２４に発行され、ビジーフラグ２３が「１」にセットされたとき、セレクタ２８で、優先順位はレジスタ２２のメモリリプライデータを通常高くしているため、動作指示がレジスタ２４で待ち合わせさせられる。タイマ２６は、動作指示に対応してマイクロプログラム制御部２１から設定された値をカウントダウンし、カウントが尽きて値が「０」になると、優先順位判定回路２７に通知する。
【００２０】
比較器３０は、マイクロプログラム制御部２１から、動作指示に対応するチャネル番号レジスタ２９のチャネル番号と、レジスタ２２の主記憶装置１０からのメモリリプライデータのチャネル番号を示す部分と、を比較し、両者の値が一致した場合は、優先順位判定回路２７へ通知する。セレクタ２８は、優先順位判定回路２７からの指示により、レジスタ２２にリプライデータがある場合で、マイクロプログラム制御部２１からのチャネル装置５１への動作指示が動作指示レジスタ２４に存在せず、かつビジーフラグ２４が「０」の場合と、前記動作指示が動作指示レジスタ２４に格納発行されていて、ビジーフラグ７が「１」であるが、タイマ２６の値が「０」でない場合と、前述の場合で、タイマ２６の値が「０」であるが、比較器３０でのチャネル番号の比較結果が不一致の場合は、レジスタ２２のメモリリプライデータを選択し、メモリリプライデータをダウンデータバス４０へ送出する。また、セレクタ２８は、優先順位判定回路２７からの指示により、ビジーフラグ２３が「１」で、タイマ２６の値が「０」で、かつ、比較器３０でのチャネル番号の比較結果が一致した場合は、セレクタ１２での動作指示レジスタ２４の優先順位をあげ、セレクタ２８にレジスタ２４を選択させるとともに、ビジーフラグ２３をリセットする。セレクタ２８で選択された動作指示レジスタ２４の動作指示は、ダウンデータバス４０を介して指定のチャネル装置５１へ送出される。
【００２１】
優先順位判定回路２７は、前記の動作指示レジスタ２４を選択した次のサイクルでは、一時保持レジスタ２５の保留されていたメモリリプライデータをセレクタ２８に選択させ、ダウンデータバス４０を介して指定のチャネル装置５１へ送出する。
【００２２】
【発明の効果】
以上説明したように、この発明の効果は、動作指示の発行待ち合わせが一定時間を越えたとき、競合するメモリリプライデータを保留して、動作指示の発行を優先させて、待ち合わせる時間を短縮することができるので、データ転送におけるオーバーランを防止できる。
【図面の簡単な説明】
【図１】この発明の実施の一形態を示す図である。
【図２】従来技術による構成を例示する図である。
【符号の説明】
１データ転送装置
１０主記憶装置
２０チャネルコントロール装置
２１マイクロプログラム制御部
２２レジスタ
２３ビジーフラグ
２４動作指示レジスタ
２５一時保持レジスタ
２６タイマ
２７優先順位判定回路
２８セレクタ
２９チャネル番号レジスタ
３０比較器
４０ダウンデータバス
５１乃至５ｎチャネル装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer device that transfers an operation instruction of a channel control device and memory reply data of a main storage device to a channel device, and in particular, transfer of an operation instruction is delayed by the transfer of memory reply data. The present invention relates to a data transfer device that prevents this.
[0002]
[Prior art]
A conventional data transfer apparatus 2 will be described with reference to FIG. Memory reply data from the main storage device 10 is stored in the register 62 by the operation of the channel control device 60, and is transferred to the channel devices 51 to 5n via the selector 68 and the down data bus 40. When the microprogram control unit 61 issues an operation instruction to the channel device 51 during this data transfer, the operation instruction is stored in the register 64 and the busy flag 63 is set to ON. When the memory reply data in the register 62 and the operation instruction of the register 64 conflict, the priority determination circuit 67 issues an instruction to the selector 68 to preferentially transfer the memory reply data. For this reason, while the memory reply data is continuously transferred, an operation instruction is made to wait in the register 64. During this waiting time, the busy flag 63 remains on.
[0003]
As described above, the conventional channel control device 60 has a problem that an event such as data overrun occurs as a result of the operation instruction to the channel device 51 being kept waiting while the memory reply data is continuous. (For example, refer to Patent Document 1).
[0004]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-47973 (FIG. 3 and description of the prior art).
[0005]
[Problems to be solved by the invention]
In order to solve the above-mentioned problem, when the operation instruction to the channel device and the data transfer conflict with each other in the data transfer device, the initial value is set in advance from the microprogram control unit. When the countdown timer is started and the value of the timer reaches “0”, if the memory reply data from the main storage device is for the channel device designated in advance by the microprogram control unit, the operation instruction is given priority. The waiting time for the operation instruction is reduced by raising the rank and forcibly interrupting and transferring the memory reply data.
[0006]
The object of the present invention is to set the priority of the memory ply data and the operation instruction when the operation instruction issued by the microprogram control unit competes with the memory reply data and the operation instruction is waited for a certain period of time. By changing it, the waiting time for issuing the operation instruction is shortened and transferred to prevent an event such as an overrun from occurring.
[0007]
[Means for Solving the Problems]
Therefore, in the data transfer device according to the present invention, in which the channel control device transfers the operation instruction issued by itself and the memory reply data of the main storage device to the channel device via the down data bus, the memory reply data When the operation instruction for the channel device is delayed due to a conflict between the transfer of the operation instruction and the transfer of the operation instruction, the operation instruction is interrupted to the transfer of the memory reply data within a predetermined delay, and It has a channel control device for sending to a channel device.
[0008]
Further, the operation instruction is issued including a channel number of a destination channel device.
[0009]
Further, the memory reply data includes a channel number of a destination channel device, valid data indicating that the memory reply data itself is valid, and data to be transferred.
[0010]
Further, the channel control device receives the memory reply data of the main storage device, temporarily stores a register, a temporary holding register that transfers and holds the memory reply data of the register, and gives an operation instruction to the channel device. A microprogram control unit to issue, an operation instruction register for holding the operation instruction, a busy flag indicating that the operation instruction has been issued, a channel number register for holding a channel number of the channel device to be operated, A comparator that compares a channel number of the register with a channel number of the channel number register and detects a match; a timer that detects a predetermined elapsed time from the microprogram control unit issuing an operation instruction; and the timer Is the detection output when the predetermined time has passed, the output of the busy flag, A priority determination circuit that selects the operation instruction in preference to the memory reply data and turns off the busy flag based on the comparator channel number coincidence output and the valid data output of the register; and the priority determination A selector that selects one of the operation instruction of the operation instruction register, the memory reply data of the register, and the memory reply data of the temporary holding register according to the priority output of the circuit, and sends it to the channel device; It is characterized by providing.
[0011]
Further, the priority order output selects the memory reply data of the register when there is no output of the busy flag, has the output of the busy flag, and has the timer output, the comparator output, and the valid data output of the register The operation instruction of the operation instruction register is selected, and the memory reply data of the temporary holding register is selected in the next cycle when the operation instruction is selected.
[0012]
Further, the selector causes the operation instruction to be interrupted and transferred to a continuous transfer output of the memory reply data of the register by the priority output, and the memory reply data held by the interrupt transfer output of the operation instruction is output. Is transferred from the temporary holding register and thereafter, the memory reply data of the register is transferred and output.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described with reference to the drawings. Referring to FIG. 1 showing an embodiment of the invention, a data transfer device 1 includes a main storage device 10, a channel control device 20, a down data bus 40, and a plurality of channel devices 51 to 5n. The main storage device 10 and the down data bus 40 are directly connected to the channel control device 20, and the channel devices 51 to 5 n are connected via the down data bus 40.
[0014]
The channel control device 20 includes a microprogram control unit 21, a register 22, a busy flag 23, an operation instruction register 24, a temporary holding register 25, a timer 26, a priority determination circuit 27, a selector 28, a channel number. A register 29 and a comparator 30 are included. The memory requests from the channel devices 51 to 5n are sent to the main storage device 10 by the channel control device 20 through a path (not shown).
[0015]
Memory reply data for the memory request from the main storage device 10 is stored in the register 22 and then sent to the selector 28 and the register 25. The register 25 is the same data obtained by transferring the data in the register 22. The selector 28 selects any one of the operation instruction register 24, the register 22, and the temporary holding register 25 according to an instruction from the priority determination circuit 27 and sends it to the channel device.
[0016]
When the microprogram control unit 21 issues an operation instruction to the channel devices 51 to 5n, the timer value corresponding to the operation instruction is set in the timer 26, the busy flag 7 is set to “1”, and the operation instruction register 24 is set. Stores operation instructions. The operation instruction stored in the operation instruction register 24 is held in the operation instruction register 24 until the selector 28 selects the operation instruction register 24 and sends it to the channel devices 51 to 5n.
[0017]
When the operation instruction register 24 is selected by the selector 28, the priority determination circuit 27 resets the busy flag 23 to “0”. When the busy flag 23 becomes “1”, the timer 26 starts counting down and notifies the priority determination circuit 27 when the value becomes “0”. The channel number register 29 is written with a channel number to which an operation instruction is issued from the microprogram control unit 21, and each time the memory reply data from the main storage device 10 is stored in the register 22, the comparator 30 The channel number of the number register 29 is compared with the channel numbers of the target channel devices 51 to 5n held in the memory reply data. Therefore, the priority determination circuit 27 is notified of the conflict.
[0018]
When the operation instruction of the operation instruction register 24 and the memory reply data of the register 22 conflict with each other, the priority determination circuit 27 gives priority to the memory reply data of the register 6 if it is normal. When the operation instruction is stored, the busy flag 23 is “1”, the value of the timer 26 is “0”, and the channel number comparison result by the comparator 14 matches, the operation instruction register 24 is sent to the selector 28. And the busy flag 23 is reset to “0”. After that, the priority determination circuit 28 causes the selector 28 to select the temporary holding register 25 and sends the memory reply data whose sending has been suspended.
[0019]
Next, the operation of this embodiment will be described. Memory reply data for memory requests from the channel devices 51 to 5n to the main storage device 10 is sent from the main storage device 10 to the register 22. The memory reply data includes a channel number 221 of the channel device 51 that should issue a memory request and receive the memory reply data, and valid data 222 indicating that the memory reply data is valid. When the memory reply data is continuously sent from the main storage device 10 to the channel device 51, the memory reply data is sequentially stored in the register 22 every cycle. Therefore, during this period, when the operation instruction from the microprogram control unit 21 to the channel device 51 is issued to the register 24 and the busy flag 23 is set to “1”, the priority is set to the memory reply of the register 22 by the selector 28. Since the data is normally high, an operation instruction is made to wait in the register 24. The timer 26 counts down the value set from the microprogram control unit 21 in response to the operation instruction, and notifies the priority determination circuit 27 when the count is exhausted and the value becomes “0”.
[0020]
The comparator 30 compares the channel number of the channel number register 29 corresponding to the operation instruction from the microprogram control unit 21 with the portion indicating the channel number of the memory reply data from the main storage device 10 of the register 22, If both values match, the priority determination circuit 27 is notified. In response to an instruction from the priority determination circuit 27, the selector 28 has a reply data in the register 22, the operation instruction from the microprogram control unit 21 to the channel device 51 does not exist in the operation instruction register 24, and the busy flag 24 is “0”, the operation instruction is stored and issued in the operation instruction register 24, and the busy flag 7 is “1”, but the value of the timer 26 is not “0”, and the above case. If the value of the timer 26 is “0” but the comparison result of the channel number in the comparator 30 does not match, the memory reply data in the register 22 is selected and the memory reply data is sent to the down data bus 40. . Further, the selector 28 is in response to an instruction from the priority determination circuit 27 when the busy flag 23 is “1”, the value of the timer 26 is “0”, and the channel number comparison result in the comparator 30 matches. Raises the priority of the operation instruction register 24 in the selector 12, causes the selector 28 to select the register 24, and resets the busy flag 23. The operation instruction of the operation instruction register 24 selected by the selector 28 is sent to the designated channel device 51 via the down data bus 40.
[0021]
In the next cycle in which the operation instruction register 24 is selected, the priority determination circuit 27 causes the memory reply data held in the temporary holding register 25 to be selected by the selector 28 and the designated channel via the down data bus 40. Send to device 51.
[0022]
【The invention's effect】
As described above, the effect of the present invention is that when the operation instruction issuance wait exceeds a certain time, the competing memory reply data is suspended, and the operation instruction issuance is prioritized to shorten the waiting time. Therefore, overrun in data transfer can be prevented.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration according to a conventional technique.
[Explanation of symbols]
1 Data Transfer Device 10 Main Storage Device 20 Channel Control Device 21 Micro Program Control Unit 22 Register 23 Busy Flag 24 Operation Instruction Register 25 Temporary Holding Register 26 Timer 27 Priority Determination Circuit 28 Selector 29 Channel Number Register 30 Comparator 40 Down Data Bus 51 To 5n channel equipment

Claims

Connected to a plurality of channel devices via a bus and connected to a main storage device, a microprogram control unit, a register for storing memory reply data from the main storage device in response to a memory request, and memory reply data from the register Temporary holding register to store, busy flag, operation instruction register, channel number register, comparator for comparing channel number from channel number register with channel number included in memory reply data from register, timer, priority determination circuit And a selector that selects one of the operation register, the register, and the temporary holding register according to a selection instruction from the priority determination circuit, and the microprogram control device issues an operation instruction to the channel device. The operation The timer value corresponding to the indication is set in the timer to start counting, the busy flag is set to a value indicating busy, the operation instruction is set in the operation instruction register, and the operation instruction is issued to the channel number register When a channel number indicating a target channel device is set and continuous memory reply data is sent from the main storage device to the first channel device, the continuous memory reply data is sent every cycle. The first channel device specified by the first channel number included in the memory reply data by sequentially selecting the continuous memory reply data from the register with the selector. A channel control device for sequentially sending to
The microprogram control unit issues an operation instruction to the second channel device, stores an operation instruction to the second channel device in the operation register, and stores the second instruction in the channel number register. A second channel number indicating a channel device is stored, a value indicating busy is set in the busy flag, a timer value corresponding to an operation instruction to the second channel device is set in the timer, and counting starts Control
When there is memory reply data in the register and there is no operation instruction in the operation instruction register and the busy flag does not indicate busy, or there is memory reply data in the register and there is an operation instruction in the operation instruction register and the busy flag Indicates that the timer count is not exhausted, or the memory reply data is present in the register, the operation instruction is present in the operation instruction register, the busy flag indicates busy, and the timer is exhausted, If the comparison result between the first channel number and the second channel number does not match in the comparator, the priority determination circuit selects the memory reply data from the register Outputs instructions to the selector,
When there is an operation instruction in the operation instruction register, the busy flag indicates busy, and the timer count is exhausted, and the comparison result between the first channel number and the second channel number matches in the comparator The priority order determination circuit outputs a selection instruction for selecting an operation instruction from the operation instruction register to the selector,
In the next cycle in which the selection instruction for selecting the operation instruction is output, the selection instruction for selecting the memory reply data from the temporary holding register is output,
In accordance with a selection instruction of the priority determination circuit, the selector selects either the operation instruction from the operation instruction register, the memory reply data from the register, or the memory reply data from the temporary holding register. Selecting and outputting to the first channel device indicated by the first or second channel number or the second channel device via the bus;
A channel control device characterized by that.

A data transfer device comprising: the main storage device; a plurality of the channel devices; and the channel control device according to claim 1 .

Connected to a plurality of channel devices via a bus and connected to a main memory, a microprogram control unit, and memory reply data from the main memory for a memory request A register to store, a temporary holding register to store memory reply data from the register, a busy flag, an operation instruction register, a channel number register, a channel number from the channel number register, and a channel number included in the memory reply data from the register And a selector for selecting any one of the operation register, the register, and the temporary holding register according to a selection instruction from the priority determination circuit. When a device issues an operation instruction to the channel device, a timer value corresponding to the operation instruction is set in the timer to start counting, a value indicating busy is set in the busy flag, and the operation instruction register Set the instruction, the channel When a channel number indicating a channel device to which the operation instruction is issued is set in the signal register, and continuous memory reply data is sent from the main storage device to the first channel device, the continuous number is transmitted every cycle. The memory reply data to be stored is sequentially stored in the register every cycle, the successive memory reply data from the register is sequentially selected by the selector, and is designated by the first channel number included in the memory reply data. A channel control method in a channel control device for sequentially sending to the first channel device,
The microprogram control unit issues an operation instruction to the second channel device, stores an operation instruction to the second channel device in the operation register, and stores the second instruction in the channel number register. A second channel number indicating a channel device is stored, a value indicating busy is set in the busy flag, a timer value corresponding to an operation instruction to the second channel device is set in the timer, and counting starts A step of performing control,
When there is memory reply data in the register and there is no operation instruction in the operation instruction register and the busy flag does not indicate busy, or there is memory reply data in the register and there is an operation instruction in the operation instruction register and the busy flag Indicates that the timer count is not exhausted, or the memory reply data is present in the register, the operation instruction is present in the operation instruction register, the busy flag indicates busy, and the timer is exhausted, If the comparison result is a case where the comparison result between the first channel number and the second channel number does not match, the priority determination circuit selects the memory reply data from the register Outputs instructions to the selector,
When there is an operation instruction in the operation instruction register, the busy flag indicates busy, and the timer count is exhausted, and the comparison result between the first channel number and the second channel number matches in the comparator The priority order determination circuit outputs a selection instruction for selecting an operation instruction from the operation instruction register to the selector,
In a next cycle in which a selection instruction for selecting the operation instruction is output, a step of outputting a selection instruction for selecting the memory reply data from the temporary holding register;
According to a selection instruction of the priority determination circuit, the selector selects either the operation instruction from the operation instruction register, the memory reply data from the register, or the memory reply data from the temporary holding register. Selecting and outputting via the bus to the first channel device indicated by the first or second channel number, or to the second channel device;
A channel control method comprising:

Connected to a plurality of channel devices via a bus and connected to a main storage device, a microprogram control unit, a register for storing memory reply data from the main storage device in response to a memory request, and memory reply data from the register Temporary holding register to store, busy flag, operation instruction register, channel number register, comparator for comparing channel number from channel number register with channel number included in memory reply data from register, timer, priority determination circuit And a selector that selects one of the operation register, the register, and the temporary holding register according to a selection instruction from the priority determination circuit, and the microprogram control device issues an operation instruction to the channel device. The operation Set the timer value corresponding to shown to the timer counting open Set a value indicating busy in the busy flag, set the operation instruction in the operation instruction register, set a channel number indicating a channel device to which the operation instruction is issued in the channel number register, and When continuous memory reply data is sent from the main memory to the first channel device, the continuous memory reply data is sequentially stored in the register every cycle, and the selector selects the register from the register. A channel control program in a channel control device that sequentially selects the continuous memory reply data and sequentially sends them to the first channel device designated by a first channel number included in the memory reply data. ,
A second instruction to issue an operation instruction to the second channel device, to store an operation instruction to the second channel device in the operation register, and to indicate the second channel device in the channel number register; Storing a channel number, setting a value indicating busy in the busy flag, setting a timer value corresponding to an operation instruction to the second channel device in the timer, and performing a control to start counting, Let the microprogram controller execute
When there is memory reply data in the register and there is no operation instruction in the operation instruction register and the busy flag does not indicate busy, or there is memory reply data in the register and there is an operation instruction in the operation instruction register and the busy flag Indicates that the timer count is not exhausted, or the memory reply data is present in the register, the operation instruction is present in the operation instruction register, the busy flag indicates busy, and the timer is exhausted, If the comparison result between the first channel number and the second channel number does not match in the comparator,
A selection instruction for selecting the memory reply data from the register is output to the selector,
When there is an operation instruction in the operation instruction register, the busy flag indicates busy, and the timer count is exhausted, and the comparison result between the first channel number and the second channel number matches in the comparator The priority order determination circuit outputs a selection instruction for selecting an operation instruction from the operation instruction register to the selector,
In the next cycle in which a selection instruction for selecting the operation instruction is output, a step of outputting a selection instruction for selecting the memory reply data from the temporary holding register is executed by the priority determination circuit.
According to the selection instruction of the priority determination circuit, the operation instruction from the operation instruction register, the memory reply data from the register, or the memory reply data from the temporary holding register is selected and the first Outputting to the first channel device indicated by the first or second channel number or the second channel device via the bus;
Is executed by the selector.