JP4145695B2 - Piezoelectric oscillator - Google Patents

Piezoelectric oscillator Download PDF

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JP4145695B2
JP4145695B2 JP2003097418A JP2003097418A JP4145695B2 JP 4145695 B2 JP4145695 B2 JP 4145695B2 JP 2003097418 A JP2003097418 A JP 2003097418A JP 2003097418 A JP2003097418 A JP 2003097418A JP 4145695 B2 JP4145695 B2 JP 4145695B2
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circuit
piezoelectric
inverter
oscillation
series
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JP2004048668A (en
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富雄 佐藤
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Miyazaki Epson Corp
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Miyazaki Epson Corp
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Description

【0001】
【発明の属する技術分野】
本発明は、圧電発振器に関し、さらに詳しくは、圧電発振器の省電力化を図った回路構成に関するものである。
【0002】
【従来の技術】
近年では、携帯電話や携帯情報端末機器などの移動体通信用機器が、一般的に広く利用されるようになってきている。このような移動体通信用として使用される半導体集積回路に内蔵された発振回路としては、特開2000−299612公報にあるようなインバータ発振回路がある。図3は、従来技術のインバータ発振回路の一例である。本回路は入出力間を高抵抗R11により接続した信号反転増幅器10の出力端子11より、コンデンサC11を介して接地すると共に、圧電振動子Xtalと周波数調整用コンデンサC14を介して信号反転増幅器10の入力端子12に接続し、更にその入力端子12をコンデンサC12を介して接地する。尚、出力信号は抵抗R12とコンデンサC13の直列回路を介して取り出す構成になっている。更にまた圧電発振器には、通常、圧電発振起動をより短時間の間で立ち上げるのに十分な駆動能力を備えたCMOSインバータを使用するのが一般的である。そのため本来であれば、圧電発振回路は、起動後の定常発振状態においては、大きな駆動能力を必要としないにも拘わらず、駆動能力が高いCMOSインバータの動作に伴い、無駄な電力消費が発生してしまい、この結果、移動体通信機器の電池寿命を短くしてしまっているという問題があった。また、定常発振状態において圧電素子を必要以上に強励振させることになるので、圧電素子に生じる機械的ストレスが大きく、圧電発振器として優れたエージング特性が得られない場合があった。
【特許文献1】
特開2000−299612公報
【0003】
【発明が解決しようとする課題】
このように、図3の従来回路では、上述した通り、低消費電流化が困難であったと共に、並列共振回路により発振出力に同調させて出力を取り出すため、振動子電流を抑圧することは困難であった。
本発明は、かかる課題に鑑み、簡単な回路構成で圧電振動子の電流を低減した圧電発振器を提供することを目的とする。
【0004】
【課題を解決するための手段】
本発明はかかる課題を解決するために、請求項1は、所定の周波数で励振される圧電素子を備えた圧電振動子と、該圧電素子に電流を流して前記圧電素子を励振させる信号反転増幅器と、を備えた圧電発振器であって、入出力間を高抵抗により接続した前記信号反転増幅器の出力端子を容量と並列同調回路とを直列接続した回路を介して接地し、前記容量と並列同調回路の接続点をダイオード・クランプ回路を介して接地すると共に、前記接続点を2つの直列接続された容量を介して前記信号反転増幅器の入力端子に接続し、前記直列接続された2つの容量の接続点を前記圧電振動子と周波数調整素子を介して接地したことを特徴とする。従来のハートレー型インバータ発振回路は、負荷容量を大きくするために直列共振に近い定数設定にすることにより、負性抵抗を大きくして発振の起動を容易にしている。しかし、圧電振動子に流れる電流はインバータの入出力間のレベルで決まるため、利得が高いインバータでは電流抑制の効果は低かった。そこで、本発明ではインバータの出力からコンデンサを介してクランプ回路を接地することにより、本課題を解決するものである。
かかる発明によれば、クランプ回路をインバータの出力からコンデンサを介して接地することにより、圧電振動子の両端をクランプすると共に、インバータのインピーダンスを急激に低下させて発振利得を低下させるので、圧電振動子に流れる電流抑制効果を高めることができる。
【0005】
請求項2は、前記ダイオード・クランプ回路は、2つのダイオードを互いに極性が異なるように並列接続したものであることを特徴とする。
発振波形は基本的に交流である。従って、両極の波形毎にクランプをかける必要がある。そこでダイオードを互いに逆極性にして並列に接続することにより実現できる。
かかる発明によれば、発振波形の両極でクランプをかけるので、クランプ量が大きく、しかも、バランスよくクランプすることができる。
請求項3は、前記2つの容量の接続点から見た場合、前記2つの容量の1つと前記並列同調回路により直列共振回路を構成することを特徴とする。
直列共振回路は、発振周波数に共振するとインピーダンスが最小となり、回路電流が最大となる。これにより、負性抵抗が増加して発振の起動を容易にすることができる。
かかる発明によれば、圧電振動子のループ内に直列共振回路を形成するので、負性抵抗が増加して発振の起動を容易にすることができる。
請求項4は、前記圧電振動子が水晶振動子であることを特徴とする。
かかる発明によれば、圧電振動子に水晶振動子を使用することにより、安価で、周波数安定度の高い発振器を実現することができる。
【0006】
【発明の実施の形態】
以下、本発明を図に示した実施形態を用いて詳細に説明する。但し、この実施形態に記載される構成要素、種類、組み合わせ、形状、その相対配置などは特定的な記載がない限り、この発明の範囲をそれのみに限定する主旨ではなく単なる説明例に過ぎない。また、以下の実施形態では圧電発振器(振動子)の一例として水晶発振器について説明しているが、本発明は水晶以外の圧電発振器一般に適用可能である。
図1は、本発明の実施形態に係るクランプ回路付インバータ発振回路の回路図である。尚、以下に回路要素符号と共に一例として示した回路素子値は後述する発振器電気的特性を確認した際の設計条件である。このインバータ発振回路は、入出力間を高抵抗R1により接続したインバータ1の出力端子2より、コンデンサC1を介してコンデンサC2とインダクタL1を並列接続した並列同調回路を直列接続して接地し、この直列接続の接続点よりダイオードD1、D2を互いに極性を異なるように並列接続して接地する。またコンデンサC3とC4を介してインバータ1の入力端子3に接続し、前記直列接続されたコンデンサC3とC4の接続点より圧電振動子Xtalと周波数調整用コンデンサC7を介して接地する。尚、この回路では出力を抵抗R2とコンデンサC6の直列回路を介して取り出す構成になっている。
【0007】
次に、本実施形態の動作について説明するが、発振動作については周知の技術であるのでここでは詳細な説明は省略する。先ず、インバータ1に電源VCC5Vが投入されると、圧電素子Xtalの固有振動数に従って振動を開始し、インバータ1の出力端子2にレベルの高い電圧が発生する。その電圧の交流分はコンデンサC1を通過して並列同調回路L1、C2とクランプダイオードD1、D2に入力される。クランプダイオードD1、D2において、電圧が正極であればダイオードD2により導通され、電圧が負極であればダイオードD1により導通されダイオードの特性から各ダイオードの順方向電圧は所定の電圧(約0.7V)以上に上がらない。したがってインバータ1の出力端2から圧電素子Xtalに供給されようとする帰還信号が一定の励振レベルを越えるとダイオードD1、D2が導通して、±0.7Vp−p以上に励振レベルが大きくなることはない。この結果インバータ1の入出力間のインピーダンスが急激に低下して発振利得が急激に低下するので、圧電素子Xに流れる電流を大幅に抑制することができる。
尚、本実施形態の発振回路の各定数は、R1:100kΩ、R2:10kΩ、C1:100pF、C2:180pF、C3:30pF、C4:6pF、C6:10000pF、C7:100pF、L1:1μH、D1、D2:1SS315、Xtal:At−cut 1st 10MHz、インバータ1:TC7SU04Fである。
【0008】
図2は、図1のクランプ回路付インバータ発振回路の負性抵抗値と発振器の入力レベルとの関係を表す図である。横軸は発振器(インバータ回路)の入力レベル(mV)、縦軸は負性抵抗(Ω)である。図2の符号15が本発明の回路の特性であり、符号16は従来回路の特性である。この図から明らかなように符号16の従来回路の特性は、負性抵抗が略大きな値で一定であり、発振器の入力レベルにより大きく影響を受けない。それに比べて符号15の本発明は、発振器の入力レベルが300mV以上から負性抵抗が減少する特性を呈し、それにより振動子電流を抑圧していることが解る。このようにクランプ回路により振幅を抑圧することにより、急激に負性抵抗を減少させその結果振動子電流を抑圧するものである。
以上本発明の実施形態について説明したが、本発明はインバータ発振回路の入力と接地間に振動子を挿入するところに特徴があり、クランプ回路の形態、インバータ回路の構成は本実施形態で説明したものに限らず、他の形態、回路構成でも本発明の主旨を逸脱するものではない。
【0009】
【発明の効果】
以上記載のごとく請求項1の発明によれば、クランプ回路をインバータの出力からコンデンサを介して接地することにより、圧電振動子の両端をクランプすると共に、インバータのインピーダンスを急激に低下させて発振利得を低下させるので、圧電振動子に流れる電流抑制効果を高めることができる。
また請求項2では、発振波形の両極でクランプをかけるので、クランプ量が大きく、しかも、バランスよくクランプすることができる。
また請求項3では、発振波形の片極でクランプをかけるので、多少発振利得の低下は低くなるが、部品コストが低減した分コストダウンとなる。
また請求項4では、圧電振動子に水晶振動子を使用することにより、安価で、周波数安定度の高い発振器を実現することができる。
【図面の簡単な説明】
【図1】本発明の実施形態に係るクランプ付インバータ発振回路の回路図である。
【図2】本発明の図1のクランプ回路付インバータ発振回路の負性抵抗値と発振器の入力レベルとの関係を表す図である。
【図3】従来技術のインバータ発振回路の実施回路図である。
【符号の説明】
Xtal 圧電素子
C1、C2、C3、C4、C6、C7 コンデンサ
D1、D2 ダイオード
1 インバータ
R1 帰還抵抗器
R2 固定抵抗器
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a piezoelectric oscillator, and more particularly, to a circuit configuration for reducing power consumption of a piezoelectric oscillator.
[0002]
[Prior art]
In recent years, mobile communication devices such as mobile phones and portable information terminal devices have been widely used. As an oscillation circuit built in a semiconductor integrated circuit used for such mobile communication, there is an inverter oscillation circuit as disclosed in Japanese Patent Application Laid-Open No. 2000-299612. FIG. 3 is an example of a conventional inverter oscillation circuit. This circuit is grounded via the capacitor C11 from the output terminal 11 of the signal inverting amplifier 10 whose input and output are connected by a high resistance R11, and the signal inverting amplifier 10 via the piezoelectric vibrator Xtal and the frequency adjusting capacitor C14. The input terminal 12 is connected, and the input terminal 12 is grounded via the capacitor C12. The output signal is extracted through a series circuit of a resistor R12 and a capacitor C13. In addition, it is common to use a CMOS inverter having a sufficient driving capability to start up the piezoelectric oscillation in a shorter time. For this reason, the piezoelectric oscillation circuit normally consumes unnecessary power in association with the operation of the CMOS inverter having a high driving capability in spite of not requiring a large driving capability in the steady oscillation state after starting. As a result, there has been a problem that the battery life of the mobile communication device has been shortened. In addition, since the piezoelectric element is strongly excited more than necessary in a steady oscillation state, mechanical stress generated in the piezoelectric element is large, and an excellent aging characteristic as a piezoelectric oscillator may not be obtained.
[Patent Document 1]
JP 2000-299612 A
[Problems to be solved by the invention]
As described above, in the conventional circuit of FIG. 3, as described above, it is difficult to reduce the current consumption, and it is difficult to suppress the vibrator current because the output is extracted in synchronization with the oscillation output by the parallel resonance circuit. Met.
The present invention has been made in view of the above problems, and an object thereof is to provide a piezoelectric oscillator in which the current of the piezoelectric vibrator is reduced with a simple circuit configuration.
[0004]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a piezoelectric vibrator having a piezoelectric element excited at a predetermined frequency, and a signal inverting amplifier for exciting the piezoelectric element by passing a current through the piezoelectric element. A grounded output terminal of the signal inverting amplifier having a high resistance connected between the input and output through a circuit in which a capacitor and a parallel tuning circuit are connected in series, and the capacitor and the parallel tuning. The connection point of the circuit is grounded via a diode clamp circuit, and the connection point is connected to the input terminal of the signal inverting amplifier via two series-connected capacitors. The connection point is grounded via the piezoelectric vibrator and the frequency adjusting element. The conventional Hartley-type inverter oscillation circuit makes it easy to start oscillation by increasing the negative resistance by setting a constant close to series resonance in order to increase the load capacity. However, since the current flowing through the piezoelectric vibrator is determined by the level between the input and output of the inverter, the current suppression effect is low in an inverter having a high gain. Accordingly, the present invention solves this problem by grounding the clamp circuit from the output of the inverter via a capacitor.
According to this invention, since the clamp circuit is grounded from the output of the inverter via the capacitor, both ends of the piezoelectric vibrator are clamped, and the impedance of the inverter is drastically reduced to lower the oscillation gain. The effect of suppressing the current flowing through the child can be enhanced.
[0005]
According to a second aspect of the present invention, the diode clamp circuit is formed by connecting two diodes in parallel so that their polarities are different from each other.
The oscillation waveform is basically an alternating current. Therefore, it is necessary to clamp each waveform of both poles. Therefore, it can be realized by connecting the diodes in opposite polarities in parallel.
According to this invention, since clamping is performed at both poles of the oscillation waveform, the clamping amount is large and the clamping can be performed with a good balance.
According to a third aspect of the present invention, when viewed from the connection point of the two capacitors, a series resonance circuit is constituted by one of the two capacitors and the parallel tuning circuit.
When the series resonant circuit resonates at the oscillation frequency, the impedance is minimized and the circuit current is maximized. As a result, the negative resistance can be increased and the oscillation can be easily started.
According to this invention, since the series resonance circuit is formed in the loop of the piezoelectric vibrator, the negative resistance can be increased and the oscillation can be easily started.
According to a fourth aspect of the present invention, the piezoelectric vibrator is a quartz crystal vibrator.
According to this invention, it is possible to realize an inexpensive and high frequency stability oscillator by using a crystal resonator as the piezoelectric resonator.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. . In the following embodiments, a crystal oscillator is described as an example of a piezoelectric oscillator (vibrator), but the present invention is applicable to general piezoelectric oscillators other than crystals.
FIG. 1 is a circuit diagram of an inverter oscillation circuit with a clamp circuit according to an embodiment of the present invention. In addition, the circuit element value shown as an example with the circuit element code | symbol below is a design condition at the time of confirming the oscillator electrical characteristic mentioned later. In this inverter oscillation circuit, a parallel tuning circuit in which a capacitor C2 and an inductor L1 are connected in parallel through a capacitor C1 is connected in series from an output terminal 2 of the inverter 1 whose input and output are connected by a high resistance R1, and this is grounded. The diodes D1 and D2 are connected in parallel so as to have different polarities from the connection point of series connection, and are grounded. Further, it is connected to the input terminal 3 of the inverter 1 via the capacitors C3 and C4, and is grounded via the piezoelectric vibrator Xtal and the frequency adjusting capacitor C7 from the connection point of the capacitors C3 and C4 connected in series. In this circuit, the output is taken out through a series circuit of a resistor R2 and a capacitor C6.
[0007]
Next, the operation of this embodiment will be described. Since the oscillation operation is a well-known technique, a detailed description thereof will be omitted here. First, when the power supply VCC5V is input to the inverter 1, vibration starts according to the natural frequency of the piezoelectric element Xtal, and a high level voltage is generated at the output terminal 2 of the inverter 1. The AC component of the voltage passes through the capacitor C1 and is input to the parallel tuning circuits L1, C2 and the clamp diodes D1, D2. In the clamp diodes D1 and D2, when the voltage is positive, the diode D2 conducts, and when the voltage is negative, the diode D1 conducts, and the forward voltage of each diode is a predetermined voltage (about 0.7V) from the characteristics of the diode. It doesn't go up any more. Therefore, when the feedback signal to be supplied from the output terminal 2 of the inverter 1 to the piezoelectric element Xtal exceeds a certain excitation level, the diodes D1 and D2 are turned on, and the excitation level becomes larger than ± 0.7 Vp-p. There is no. As a result, the impedance between the input and output of the inverter 1 is drastically lowered and the oscillation gain is drastically lowered, so that the current flowing through the piezoelectric element X can be significantly suppressed.
The constants of the oscillation circuit of this embodiment are as follows: R1: 100 kΩ, R2: 10 kΩ, C1: 100 pF, C2: 180 pF, C3: 30 pF, C4: 6 pF, C6: 10000 pF, C7: 100 pF, L1: 1 μH, D1 , D2: 1SS315, Xtal: At-cut 1st 10 MHz, inverter 1: TC7SU04F.
[0008]
FIG. 2 is a diagram showing the relationship between the negative resistance value of the inverter oscillation circuit with a clamp circuit of FIG. 1 and the input level of the oscillator. The horizontal axis is the input level (mV) of the oscillator (inverter circuit), and the vertical axis is the negative resistance (Ω). Reference numeral 15 in FIG. 2 is a characteristic of the circuit of the present invention, and reference numeral 16 is a characteristic of the conventional circuit. As is clear from this figure, the characteristic of the conventional circuit of reference numeral 16 is that the negative resistance is substantially constant at a large value and is not greatly affected by the input level of the oscillator. On the other hand, it can be seen that the present invention of reference numeral 15 exhibits the characteristic that the negative resistance decreases when the input level of the oscillator is 300 mV or more, thereby suppressing the vibrator current. Thus, by suppressing the amplitude by the clamp circuit, the negative resistance is drastically reduced, and as a result, the vibrator current is suppressed.
Although the embodiment of the present invention has been described above, the present invention is characterized in that a vibrator is inserted between the input of the inverter oscillation circuit and the ground, and the configuration of the clamp circuit and the configuration of the inverter circuit have been described in the present embodiment. The present invention is not limited to this, and other forms and circuit configurations do not depart from the spirit of the present invention.
[0009]
【The invention's effect】
As described above, according to the first aspect of the present invention, the clamp circuit is grounded from the output of the inverter through the capacitor to clamp both ends of the piezoelectric vibrator, and the impedance of the inverter is drastically reduced to thereby reduce the oscillation gain. Therefore, the effect of suppressing the current flowing through the piezoelectric vibrator can be enhanced.
Further, in the second aspect, since clamping is performed at both poles of the oscillation waveform, the clamping amount is large and the clamping can be performed with a good balance.
According to the third aspect of the present invention, since clamping is performed with one pole of the oscillation waveform, the decrease in the oscillation gain is somewhat reduced, but the cost is reduced by reducing the component cost.
According to the fourth aspect of the present invention, an inexpensive and high frequency stability oscillator can be realized by using a crystal resonator as the piezoelectric resonator.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an inverter oscillation circuit with a clamp according to an embodiment of the present invention.
2 is a diagram illustrating a relationship between a negative resistance value of the inverter oscillation circuit with a clamp circuit of FIG. 1 and an input level of the oscillator according to the present invention. FIG.
FIG. 3 is an implementation circuit diagram of a conventional inverter oscillation circuit.
[Explanation of symbols]
Xtal Piezoelectric element C1, C2, C3, C4, C6, C7 Capacitor D1, D2 Diode 1 Inverter R1 Feedback resistor R2 Fixed resistor

Claims (4)

所定の周波数で励振される圧電素子を備えた圧電振動子と、該圧電素子に電流を流して前記圧電素子を励振させる信号反転増幅器と、を備えた圧電発振器であって、
入出力間を高抵抗により接続した前記信号反転増幅器の出力端子を容量と並列同調回路とを直列接続した回路を介して接地し、前記容量と並列同調回路の接続点をダイオード・クランプ回路を介して接地すると共に、前記接続点を2つの直列接続された容量を介して前記信号反転増幅器の入力端子に接続し、前記直列接続された2つの容量の接続点を前記圧電振動子と周波数調整素子を介して接地したことを特徴とする圧電発振器。
A piezoelectric oscillator comprising: a piezoelectric vibrator including a piezoelectric element excited at a predetermined frequency; and a signal inverting amplifier for exciting the piezoelectric element by passing a current through the piezoelectric element,
The output terminal of the signal inverting amplifier connected between the input and output with a high resistance is grounded through a circuit in which a capacitor and a parallel tuning circuit are connected in series, and the connection point of the capacitor and the parallel tuning circuit is connected through a diode clamp circuit. And connecting the connection point to the input terminal of the signal inverting amplifier via two series-connected capacitors, and connecting the connection point of the two capacitors connected in series to the piezoelectric vibrator and the frequency adjusting element. Piezoelectric oscillator characterized by being grounded via
前記ダイオード・クランプ回路は、2つのダイオードを互いに極性が異なるように並列接続したものであることを特徴とする請求項1に記載の圧電発振器。2. The piezoelectric oscillator according to claim 1, wherein the diode clamp circuit includes two diodes connected in parallel so as to have different polarities. 前記2つの容量の接続点から見た場合、前記2つの容量の1つと前記並列同調回路により直列共振回路を構成することを特徴とする請求項1に記載の圧電発振器。2. The piezoelectric oscillator according to claim 1, wherein when viewed from a connection point of the two capacitors, a series resonance circuit is configured by one of the two capacitors and the parallel tuning circuit. 前記圧電振動子が水晶振動子であることを特徴とする請求項1乃至3の何れか一項に記載の圧電発振器。The piezoelectric oscillator according to claim 1, wherein the piezoelectric vibrator is a crystal vibrator.
JP2003097418A 2003-03-31 2003-03-31 Piezoelectric oscillator Expired - Fee Related JP4145695B2 (en)

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