JP4128657B2 - Audio compression / decompression apparatus and recording medium - Google Patents

Description

【００３３】
８は乗加算回路であり、ＲＯＭ７内の乗算係数Filter[k] を用いて、ＲＡＭ６にバッファリングされた音声信号に対して式（３）もしくは式（２−１）、（２−１）の演算を実行する。
これらのＲＡＭ６、ＲＯＭ７および乗加算回路８をダウンサンプリング用として用いるかアップサンプリング用として用いるかは、後述する制御信号生成回路５より与えられる制御信号に応じて切り替える。
【００３４】
再び図１に戻り、２は信号圧縮回路であり、上記フィルタ回路１によりダウンサンプリングされたＰＣＭ音声信号を、例えばＡＤＰＣＭ圧縮方式に従って圧縮する。例えば、上記フィルタ回路１でサンプリングレートを半分に落とされた音声信号の１サンプル当たりのデータ長を１６ビットから半分の８ビットに圧縮することにより、サンプリングレートが２２．０５ＫＨｚでデータ長が１サンプル当たり８ビットの音声圧縮信号を生成する。なお、圧縮方式はこのＡＤＰＣＭやＤＰＣＭには限定されない。
【００３５】
また、３は信号伸長回路であり、上記信号圧縮回路２と逆の処理を行うことにより、入力された音声圧縮信号を伸長する。すなわち、入力された音声圧縮信号の１サンプル当たりのデータ長を８ビットから１６ビットに変換する。音声伸長時においてフィルタ回路１は、信号伸長回路３より入力された音声信号のサンプリングレートを２２．０５ＫＨｚから４４．１ＫＨｚにアップサンプリングし、元のＰＣＭ音声信号を生成して再生音声として出力する。
【００３６】
このように、音声圧縮を行うときは、フィルタ回路１はダウンサンプル回路として動作し、データの流れは図１に水平の実線矢印で示した通りとなる。一方、音声伸長を行うときは、フィルタ回路１はアップサンプル回路として動作し、データの流れは図１に垂直の実線矢印で示した通りとなる。
【００３７】
４は制御回路であり、本実施形態による音声圧縮伸長装置の全体、つまりフィルタ回路１、信号圧縮回路２および信号伸長回路３の動作を制御する。この制御回路４は制御信号生成回路５を備えており、フィルタ回路１をダウンサンプリング用として用いるかアップサンプリング用として用いるかの切り替えを制御するための制御信号を生成する。
【００３８】
音声圧縮と音声伸長の動作速度が全く同じ場合、つまり音声の入力レートと出力レートとが全く同じ場合には、アップサンプリングとダウンサンプリングの処理比率は一定である。そのため、フィルタ回路１の動的な切り替えに関して完全に一定のスケジュールを組むことができる。本実施形態で示した例で言うと、２ＰＣＭ当たりに１回、式（３）と式（２−１）、式（２−２）の組みとを実行することになる。
【００３９】
しかしながら、図６に例示した装置のように、音声圧縮と音声伸長の相対速度が動的に変化する場合（例えば、入力音声のデータソースがＣＤ等のストレージであり、そのストレージから本実施形態の音声圧縮伸長装置へのデータ入力速度にジッタを含んでいる場合や、話速変換装置等のように音声の出力速度を加減する場合、もしくはこの２つの特徴を併せ持つ場合など）は、アップサンプリングとダウンサンプリングの処理比率は一定ではなくなる。この場合に制御回路４は、例えば、信号圧縮回路２および信号伸長回路３のそれぞれから入力される要求の順番に従って、フィルタ回路１の動作状態を切り替えるようにすることが可能である。
【００４０】
なお、本実施形態の音声圧縮伸長装置を図６のように構成する場合は、図１の信号圧縮回路２と信号伸長回路３との間に図示しないバッファメモリが設けられ、信号圧縮回路２から出力された音声圧縮信号がバッファメモリに一時格納された後、信号伸長回路３に入力されることになる。
【００４１】
以上説明したように、従来は別々に構成していた図１２のハードウェアと図１３のハードウェアとを統合（共用）してフィルタ回路１を構成すると、ＲＡＭの容量については、別々に構成した場合には各々１６ワードのＲＡＭが２つ必要であったのに対して、統合した場合には３２ワードのＲＡＭが１つで済む。合計のＲＡＭ容量は変わらないが、本実施形態によれば、小容量のメモリを２つ設ける必要がなく、中容量のメモリを１つだけ設ければ良いので、デコード回路内のメモリに必要な面積が減るというメリットがある。
【００４２】
また、ＲＯＭの容量については、別々に構成した場合には各々３２ワードのＲＯＭが２つ必要であったのに対して、統合した場合には３２ワードのＲＯＭが１つで済む。これにより、ＲＯＭのハードウェア量を１／２に削減することができる。さらに、乗算器については、別々に構成した場合には各々に必要であったのに対して、統合した場合には１つで済む。これにより、乗算器のハードウェア量も１／２に削減することができる。
【００４３】
ダウンサンプル回路とアップサンプル回路の両者を共用・統合することにより、制御回路４は複雑になり、単位時間当たりに必要とする処理能力も両者の和の分だけ必要となるが、ハードウェア量の削減は生産コストに直結するため、その利点は上述の欠点を補ってあまりあるものである。
【００４４】
なお、以上の実施形態において、制御信号生成回路５は、ダウンサンプリングおよびアップサンプリングの要求順序に従ってフィルタ回路１の動作を動的に切り替えることについて述べた。ところが、ダウンサンプリング要求が続く場合には、アップサンプリングを用いた音声伸長処理が行われず、再生音声が途切れてしまうという不都合が発生する場合がある。そこで、以下に、フィルタ回路１の動的なスケジューリング方法についての他の例を示す。
【００４５】
図３は、制御信号生成回路５の構成例を示す図である。図３において、１１は調停回路であり、信号圧縮回路２および信号伸長回路３より制御回路４を介してダウンサンプリング要求１６およびアップサンプリング要求１７の双方の要求が与えられる場合に、どちらの要求に応えるかを調停するためのものである。この調停方法としては、例えば以下に述べるような処理方法が考えられる。
【００４６】
▲１▼あらかじめ優先順位を設定し、優先順位の高い方を選択する。例えば、現在音声を再生しているシステムの場合は、この方式を使用してアップサンプリングを優先的に選択するようにすることにより、再生音声の中断を防止することができる。
【００４７】
▲２▼以前に選択された状態を保存しておき、それと異なる方もしくはそれと同じ方を選択する。すなわち、調停回路１１において、同じ要求が所定回数続いて来ているかどうかを判断し、続いていれば前回と異なる方の要求を選択し、続いていなければ前回と同じ方の要求を選択するようにする。このようにすることにより、ダウンサンプリングとアップサンプリングとをできるだけ均等に選択することができ、再生音声の中断を極力防止することができる。
【００４８】
▲３▼乱数回路等を使用してランダムに選択するようにする。ここで、ダウンサンプリングを選択する場合とアップサンプリングを選択する場合との比率が同じになるような疑似乱数を発生させることにより、上記▲２▼の方法のように以前の選択状態を保持しなくても、ダウンサンプリングとアップサンプリングとの処理比率としてできるだけ１：１に近いものを実現することができ、再生音声の中断を極力防止することができる。
【００４９】
▲４▼ＲＡＭ６にバッファリングされている音声信号の残り状態を見て選択するようにする。すなわち、ＲＡＭ６にバッファリングされている音声伸長信号DSPCM'の残りが少なくなったときに、アップサンプリングを行わずにダウンサンプリングを行って音声圧縮を行うと、再生音声が途切れてしまう恐れがある。よってこの場合は、アップサンプリングを優先的に行うように選択する。
【００５０】
次いで、１２は制御信号生成回路５の内部状態を格納するためのフリップフロップであり、２ビットの状態レジスタ１３と、４ビットのカウンタ１４とを備える。上記状態レジスタ１３は、フィルタ回路１の動作状態（ダウンサンプリング状態、アップサンプリング状態、未動作状態の何れか）を情報として格納するものである。また、カウンタ１４は、各状態における処理の長さをカウントするものである。
【００５１】
上述したように、本実施形態で示すアップサンプリングおよびダウンサンプリングの式は、処理の１単位が１６ステップであり、ダウンサンプリングの式（３）ではこの“処理の１単位”を２回まとめて実施しており、アップサンプリングの式（２−１）および式（２−２）では、各々“処理の１単位”を１回ずつ実施している。
【００５２】
フィルタ回路１の動作を設計する上で、全体の動作が上記の“処理の１単位”もしくはそれの複数単位で周期的に動作するように設計することは、ハードウェア量の削減、設計の簡易化の双方でメリットがある。フィルタ回路１の動的なスケジューリングを行う場合においても、この“処理の１単位”毎に処理を行うことは有効であり、図３はこの方法について説明している。
【００５３】
すなわち、状態レジスタ１３の値が“00”の場合はアイドル状態（未動作状態）を示し、“01”の場合はアップサンプリング状態を示し、“10”の場合はダウンサンプリングの前半状態を示し、“11”の場合はダウンサンプリングの後半状態を示している。この状態レジスタ１３の値は、カウンタ１４の値が“15”となった次のサイクルにおいて、調停回路１１での調停結果に応じて変更される。
【００５４】
つまり、ダウンサンプリング、アップサンプリング双方の要求がない場合は、状態レジスタ１３の値は“00”に変更される。また、ダウンサンプリング要求、アップサンプリング要求の一方のみが立っている場合は、その要求に合わせて状態レジスタ１３の値は“01”または“10”の何れかとなる。また、ダウンサンプリング、アップサンプリング双方の要求がある場合には、上記した▲１▼〜▲４▼の何れかの処理方法により調停された結果に応じて、状態レジスタ１３の値は“01”または“10”の何れかとなる。また、状態レジスタ１３の値が“10”であった場合は、状態レジスタ１３の値は次のサイクルでは無条件で“11”に変更される。
【００５５】
なお、この“処理の１単位”の長さは、本実施形態に示すフィルタ回路１を使用した場合の例であり、他のフィルタを使用した場合には、長さが変わったり、場合によってはこのような区切りの良い長さが無い場合もある。
【００５６】
次いで、１５はランダムゲートであり、上述したフリップフロップ１２の値（状態レジスタ１３およびカウンタ１４の値）から、フィルタ回路１の動作状態を選択するための実際の制御信号を生成し、出力する。フィルタ回路１がこの制御信号に従って動作することにより、１つのフィルタ回路１をダウンサンプリングとアップサンプリングとで共用することができる。
【００５７】
なお、この図３に示した各ブロックは、本実施形態においてはハード的に構成しているが、ＣＰＵ、ＲＯＭおよびＲＡＭ等からなるマイクロコンピュータシステムによって構成し、その動作をＲＯＭやＲＡＭに格納された作業プログラムに従って実現するようにしても良い。
【００５８】
この場合、上記作業プログラム自体が上述した実施形態の機能を実現することになり、そのプログラム自体、およびそのプログラムをコンピュータに供給するための手段、例えばかかるプログラムを格納した記録媒体は本発明を構成する。かかるプログラムを記憶する記録媒体としては、上記ＲＯＭやＲＡＭの他に、例えばフロッピーディスク、ハードディスク、光ディスク、光磁気ディスク、ＣＤ−ＲＯＭ、ＣＤ−Ｉ、ＣＤ−Ｒ、ＣＤ−ＲＷ、ＤＶＤ、ｚｉｐ、磁気テープ、あるいは不揮発性のメモリカード等を用いることができる。
【００５９】
以上の実施形態では、フィルタ回路１内の乗算器をダウンサンプリング用とアップサンプリング用に用いているが、フィルタ形状の特徴を利用して乗算器を他の用途に使用することも可能である。図４および表１に示した通り、フィルタの値はindex= 0,1,5,9,13,17,21,25,29 で０である。フィルタの値が０の場合は、乗算結果は当然０になる。よって、乗加算を行う場合に、乗算結果が０であるので乗加算の結果は加算器に入れられた値のままとなる。
【００６０】
そこで、フィルタの値が０の場合は加算器をバイパスさせる制御信号を出力するための制御回路を設けることにより、この値を乗算するサイクルでは乗算器は未使用状態となり、他の用途で使用することが可能とある。例えば、信号圧縮回路２における信号圧縮の処理に乗算器を使用することができる。特に、index=1,5,9,13,17,21,25,29については、周期的にフィルタの値が０となっているため、制御回路が比較的容易に設計できる。
【００６１】
【発明の効果】
本発明は上述したように、入力された音声信号のサンプリングレートを落とすダウンサンプリングの処理および伸長された音声信号のサンプリングレートを上げるアップサンプリングの処理を行うフィルタ回路を備え、フィルタ回路は、入力された音声信号及びアップサンプリングの処理を行う音声信号をバッファリングする一時記憶装置と、ダウンサンプリングおよびアップサンプリングの演算を行う乗加算回路と、ダウンサンプリングおよびアップサンプリングの演算において使用される乗算係数が格納される記憶装置とを有しているので、音声圧縮と音声伸長とで必要とするハードウェア量を削減することができ、全体の回路規模を小さくすることができる。
【００６２】
また、本発明の他の特徴によれば、信号圧縮回路において音声信号を圧縮する速度と信号伸長回路において音声信号を伸長する速度とが異なる速度で上記信号圧縮回路と上記信号伸長回路とが同時に動作する場合において、フィルタ回路にダウンサンプリング処理をさせるかアップサンプリング処理をさせるかの切り替えの制御信号を生成し、フィルタ回路を動的にスケジューリングして時分割動作させる制御手段を備えているので、フィルタ回路を信号圧縮回路および信号伸長回路の動作速度に合わせて適切に使い回すことができ、伸長されて出力される音声が途切れてしまうという不都合も防止することができる。
【図面の簡単な説明】
【図１】本発明による音声圧縮伸長装置の一実施形態を示す図である。
【図２】図１に示したフィルタ回路の構成例を示す図である。
【図３】図１に示した制御信号生成回路の構成例を示す図である。
【図４】ＲＯＭに格納されるフィルタ係数の形状の例を示す図である。
【図５】従来の音声圧縮伸長装置の構成例を示す図である。
【図６】従来の音声圧縮伸長装置の他の構成例を示す図である。
【図７】従来の音声圧縮装置の構成例を示す図である。
【図８】従来の音声伸長装置の構成例を示す図である。
【図９】ＰＣＭとＤＳＰＣＭとの位置関係を示す図である。
【図１０】従来のダウンサンプル回路の構成例を示す図である。
【図１１】 tmp[][] の計算内容を示す図である。
【図１２】従来のダウンサンプル回路の他の構成例を示す図である。
【図１３】従来のアップサンプル回路の構成例を示す図である。
【符号の説明】
１ フィルタ回路
２ 信号圧縮回路
３ 信号伸長回路
４ 制御回路
５ 制御信号生成回路
６ ＲＡＭ
７ ＲＯＭ
８ 乗加算回路
１１ 調停回路
１２ フリップフロップ
１３ 状態レジスタ
１４ カウンタ
１５ ランダムゲート
１６ ダウンサンプリング要求
１７ アップサンプリング要求[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an audio compression / decompression apparatus and a recording medium, and is particularly suitable for an audio compression / decompression apparatus that includes an audio compression circuit and an audio expansion circuit in one apparatus and uses them simultaneously.
[0002]
[Prior art]
Conventionally, when audio signals are transmitted and stored, as shown in FIG. 5 for the purpose of reducing the amount of transmission data and extending the storage time for storage media (memory, tape, disk, etc.). The voice is compressed and decompressed. In FIG. 5, the audio compression signal generated by the audio compression device 51 is transmitted through a transmission path (not shown) or stored in a storage medium (not shown).
[0003]
For example, when considering PHS, the voice compression apparatus 51 of FIG. 5 is in the transmission-side PHS terminal, and the voice expansion apparatus 52 is in the reception-side PHS terminal. Then, the audio compression signal generated from the input audio by the audio compression device 51 on the transmission side is transmitted through the telephone line, decompressed by the audio expansion device 52 on the reception side, and output as reproduced audio. In this example, the audio compression device 51 and the audio expansion device 52 are provided in different terminals, but may be provided in the same casing.
[0004]
For example, an audio reproducing device or an audio recording / reproducing device having a function of compressing and storing an audio signal in a memory medium such as a DRAM, a magnetic tape, or a recording medium such as a disk, and expanding and reproducing it as necessary Then, the audio compression device 51 and the audio expansion device 52 are provided in the same casing.
[0005]
In this case, as shown in FIG. 6, a buffer memory 61 and a buffer memory control device 62 are disposed between the audio compression device 51 and the audio expansion device 52, and by using this buffer memory 61, an audio signal is input. A system that can temporarily change the output rate (input / output speed) can also be configured. In such a configuration, the audio compression device 51 and the audio expansion device 52 are used simultaneously.
[0006]
As the above-described audio compression / decompression method, there is a method in which two types of compression / decompression algorithms of downsampling / upsampling and signal compression / signal expansion are used in combination. An example of the downsampling / upsampling method is a method using only the low frequency side of a QMF filter (Quadrature Miller filterbank). As an example of the signal compression / decompression method, an ADPCM (Adaptive-Differential-Pulse Code Modulation) compression method is given as an example.
[0007]
This ADPCM compression method adaptively sets the quantization step size (scaling factor) according to the waveform amplitude in DPCM (Differential-PCM), which is a technique for quantizing the difference between adjacent sample values when sampling a waveform. It is a method to change. For example, where the amplitude is large, the step size is increased so that changes in the waveform can be followed.
[0008]
FIG. 7 is a diagram illustrating a configuration example of a voice compression apparatus using a method using both down-sampling and signal compression, and FIG. 8 illustrates a configuration example of a voice expansion apparatus using a method using both up-sampling and signal expansion. FIG. For example, in the audio compression apparatus shown in FIG. 7, a PCM audio signal PCM [j] (j is a value representing the number of each sample point) having a sampling rate of 44.1 KHz and a data length of 16 bits per sample is represented by downsampling. The signal is input to the circuit 71, and the sampling rate is reduced from 44.1 KHz to 22.05 KHz, which is a half.
[0009]
The audio signal whose sampling rate has been reduced to half by the downsampling circuit 71 is compressed by the signal compression device 72 according to, for example, the ADMCM system, and the data length per sample is reduced from 16 bits to half, ie, 8 bits. In this manner, an audio compression signal having a sampling rate of 22.05 KHz and a data length of 8 bits per sample is generated and output. As a result, the data amount is compressed to ¼ as a whole.
[0010]
Further, the voice decompression apparatus shown in FIG. 8 performs the reverse process of the voice compression apparatus shown in FIG. That is, the input audio compression signal is expanded by the signal expansion device 81, and the data length per sample is returned from 8 bits to 16 bits. Then, the upsampling circuit 82 returns the sampling rate from 22.05 KHz to 44.1 KHz, and the original PCM audio signal PCM [j] is output as reproduced audio.
[0011]
Equation (1) shown below represents the operation of the down-sample circuit 71 shown in FIG. 7, and Equations (2-1) and (2-2) represent the up-sample circuit 82 shown in FIG. It represents the operation of.
DSPCM [j] = ΣFilter [k] * PCM [2 * j + k] (1)
(k = 0 ~ 31)
PCM '[2 * l] = ΣFilter [m * 2] * DSPCM' [l + m] (2-1)
(m = 0-15)
PCM '[2 * l + 1] = ΣFilter [m * 2 + 1] * DSPCM' [l + m] ...... (2-2)
(m = 0-15)
[0012]
In the above equation (1), Filter [] indicates the coefficient of the downsampling filter, PCM [] indicates the input PCM audio signal, and DSPCM [] indicates the downsampled PCM audio signal. In the equations (2-1) and (2-2), DSPCM ′ [] is a downsampled PCM audio signal (however, the value after being compressed and expanded by the signal compression device 72 and the signal expansion device 81). Filter [] indicates the coefficient of the upsampling filter, and PCM '[] indicates a PCM audio signal (reproduced audio) generated by upsampling the DSPCM' [].
[0013]
FIG. 9 is a diagram showing the positional relationship between the PCM [] and DSPCM []. As can be seen from FIG. 9, every time the PCM [] index advances by 2, one DSPCM [] signal is generated, and the data amount is compressed to ½. In addition, by overlapping the PCM [] area necessary for generating one DSPCM [], the original signal can be cleanly divided into a plurality of frequency bands and compressed.
[0014]
The downsampling / upsampling method can be interpreted as a filter when using any of the methods including the QMF filter described above, but in order to obtain a good compression result, a method with good frequency decomposition performance is used. It is necessary to select. To that end, it is possible to adopt a method with a certain degree of order (the order here is the number of taps in the digital filter and indicates how many times the original signal is obtained) as the configuration of the filter. is necessary. In addition, since the multiplication coefficient is not a relatively simple coefficient but a complex value such as a real number, it is difficult to configure with only an adder, and a ROM and a multiplier for storing the multiplication coefficient are necessary. Become.
[0015]
FIG. 10 is a diagram illustrating a hardware configuration for executing the downsampling of Expression (1). In FIG. 10, 101 is a RAM for temporarily buffering an input PCM audio signal PCM [j], and 102 is a ROM for storing a multiplication coefficient Filter [k] of a downsampling filter. The multiplier / adder circuit 103 uses the multiplication coefficient Filter [k] in the ROM 102 to perform the calculation of the expression (1) on the PCM audio signal PCM [j] buffered in the RAM 101. This calculation is performed based on the control signal generated by the control signal generation circuit 104.
[0016]
In this case, the sizes of the RAM 101 and the ROM 102 are both at least 32 words corresponding to k = 0 to 31 in the equation (1).
By the way, the capacity of the RAM 101 can be reduced to ½ by transforming the equation (1) into the following equation (3).
tmp [2 * j] [0] = Filter [0] * PCM [2 * j] + Filter [1] * PCM [2 * j + 1],
tmp [2 * j] [n] = tmp [2 * j-2] [n-1] + Filter [n * 2] * PCM [2 * j] + Filter [n * 2 + 1] * PCM [2 * j + 1] (n = 1-15) ...... (3)
FIG. 11 shows the calculation contents of tmp [] [].
[0017]
That is, at the input timing of a PCM audio signal (when processing an index number with a PCM in FIG. 11), there are a maximum of 16 signals (the maximum number of overlapping areas is 16). The actual RAM capacity is only [n] of tmp [2 * j] [n] (n = 0 to 15), and only 16 words. FIG. 12 is a diagram showing a hardware configuration example for executing the downsampling process according to the equation (3).
[0018]
In this case, when the input PCM audio signal is sent in units of one, the number of times of data access to the RAM 121 is doubled compared to the case of FIG. 10, but by processing in units of two, FIG. In this case, the number of accesses is the same as in the above case, and disadvantages such as an increase in power consumption due to an increase in the number of data accesses can be avoided.
[0019]
Next, FIG. 13 shows a hardware configuration example for executing upsampling in accordance with the above equations (2-1) and (2-2). In FIG. 13, 131 is a RAM for temporarily buffering the input downsampled PCM audio signal DSPCM ′ [j], and 132 is for storing a multiplication coefficient Filter [k] of the upsampling filter. ROM.
[0020]
The multiplier / adder circuit 133 uses the multiplication coefficient Filter [k] in the ROM 132 to perform the expressions (2-1) and (2) on the downsampled PCM audio signal DSPCM ′ [j] buffered in the RAM 131. -2) is executed. This calculation is performed based on the control signal generated by the control signal generation circuit 134. When the upsampling circuit is realized as shown in FIG. 13, the capacity of the RAM 131 is at least 16 words corresponding to m = 0 to 15, and the capacity of the ROM 132 is at least 32 words corresponding to k = 0 to 31. is there.
[0021]
[Problems to be solved by the invention]
As can be seen from the above description, the conventional audio compression / decompression apparatus requires RAM, ROM, and multiplier for both down-sampling and up-sampling when the above-described audio compression apparatus and audio expansion apparatus are operated simultaneously. there were. For this reason, there is a problem that the amount of hardware becomes very large and the circuit scale of the entire apparatus becomes large.
[0022]
The present invention has been made to solve such a problem. The audio compression apparatus and the audio expansion apparatus are realized by a single piece of hardware, and the amount of hardware required is reduced. The purpose is to reduce the circuit scale.
[0023]
[Means for Solving the Problems]
  An audio compression / decompression apparatus according to the present invention includes a filter circuit that performs a downsampling process that lowers a sampling rate of an input audio signal and an upsampling process that increases a sampling rate of the expanded audio signal, and downsampling in the filter circuit. A signal compression circuit that compresses the processed audio signal, and the audio signal compressed by the signal compression circuit is expanded.Output to the filter circuitThe audio signal is compressed by the signal decompression circuit and the signal compression circuit.YouAudio signal is decompressed in the above signal decompression circuitYouWhen the signal compression circuit and the signal decompression circuit operate simultaneously at a speed different from the speed to be generated, a control signal for switching whether the filter circuit performs a downsampling process or an upsampling process is generated, and Control means for dynamically scheduling the filter circuit to perform time-sharing operation, and the filter circuit includes a temporary storage device for buffering the input audio signal and the audio signal for performing the upsampling process; And a multiplication / addition circuit for performing the downsampling and upsampling operations, and a storage device for storing a multiplication coefficient used in the downsampling and upsampling operations.
[0024]
  The control means performs request arbitration to selectively operate a process having a higher priority set in advance when there is a request for both downsampling from the signal compression circuit and upsampling from the signal decompression circuit. Means may be provided. In addition, when the control means requires both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit, the control means selects a process that is different from or the same as the previously selected state. Request arbitration means may be provided so as to operate automatically. Further, the control means generates a random number so that the processing ratio of both becomes approximately 1: 1 when there is a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit. You may provide the request arbitration means to operate the sampling process or the upsampling process at random. In addition, the control means, when there is a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit, an audio signal for performing the up-sampling process buffered in the temporary storage device. There may be provided request arbitration means for selectively operating the upsampling process when the number is small.
[0025]
  Further, the computer-readable recording medium of the present invention includes a filter circuit that performs a downsampling process that lowers a sampling rate of an input audio signal and an upsampling process that increases a sampling rate of an expanded audio signal, and the filter A signal compression circuit for compressing the audio signal down-sampled in the circuit, and decompressing the audio signal compressed in the signal compression circuitOutput to the filter circuitA signal decompression circuit that performs the downsampling and upsampling operations, and the filter circuit performs a downsampling and upsampling operation. A computer-readable recording medium that records a program for controlling a voice compression / decompression apparatus having a multiplier / adder circuit and a storage device that stores a multiplication coefficient used in the downsampling and upsampling operations, Audio signal is compressed in the above signal compression circuitYouAudio signal is decompressed in the above signal decompression circuitYouWhen the signal compression circuit and the signal decompression circuit operate simultaneously at a speed different from the speed to be generated, a control signal for switching whether the filter circuit performs a downsampling process or an upsampling process is generated, and A computer-readable recording medium having recorded thereon a program for causing a computer to execute a control procedure for dynamically scheduling a filter circuit to perform time-sharing operation.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration example of an audio compression / decompression apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes a filter circuit which executes the downsampling process shown in the above equation (3) and the upsampling process shown in the equations (2-1) and (2-2). is there.
[0028]
That is, when performing the downsampling process according to the expression (3), the sampling rate of the input PCM audio signal is reduced from, for example, 44.1 KHz to 22.05 KHz, which is a half. On the other hand, when the upsampling process is performed according to Expression (2-1) and Expression (2-2), the sampling rate of the expanded audio signal is increased from, for example, 22.05 KHz to the original 44.1 KHz.
[0029]
The down-sampling circuit of FIG. 12 and the up-sampling circuit of FIG. 13 described as conventional examples have many parts that share the necessary hardware resources with RAM, ROM, and multiplier. Also, the filter coefficient values that must be stored in the ROM are the same in both FIG. 12 and FIG. Therefore, in the present embodiment, by sharing or integrating the circuits used in these in the filter circuit 1, the entire hardware scale can be reduced.
[0030]
FIG. 2 is a diagram illustrating an example of a hardware configuration of the filter circuit 1. In FIG. 2, reference numeral 6 denotes a RAM, which temporarily buffers the input PCM audio signal PCM [] and the value of tmp [] [] calculated according to the equation (3) at the time of downsampling. At the time of sampling, the input downsampled PCM audio signal DSPCM ′ [] is temporarily buffered.
[0031]
Reference numeral 7 denotes a ROM for storing a multiplication coefficient Filter [k] of a filter commonly used for downsampling and upsampling. FIG. 4 is a diagram showing an example of the shape of the multiplication coefficient Filter [k] of the filter stored in the ROM 7. Table 1 below shows the multiplication coefficient Filter [k] for realizing the shape of FIG. ] Value. In the digital system, an index value index obtained by converting an actual value into a binary number is used.
[0032]
[Table 1]

[0033]
Reference numeral 8 denotes a multiplication / addition circuit, which uses the multiplication coefficient Filter [k] in the ROM 7 to calculate the audio signal buffered in the RAM 6 according to the equation (3) or the equations (2-1) and (2-1). Perform the operation.
Whether these RAM 6, ROM 7 and multiplier / adder circuit 8 are used for downsampling or upsampling is switched according to a control signal supplied from a control signal generation circuit 5 described later.
[0034]
Returning to FIG. 1 again, reference numeral 2 denotes a signal compression circuit, which compresses the PCM audio signal downsampled by the filter circuit 1 according to, for example, the ADPCM compression method. For example, by compressing the data length per sample of the audio signal whose sampling rate has been halved by the filter circuit 1 from 16 bits to half 8 bits, the sampling rate is 22.05 KHz and the data length is 1 sample. An 8-bit audio compression signal is generated. Note that the compression method is not limited to ADPCM or DPCM.
[0035]
Reference numeral 3 denotes a signal decompression circuit, which decompresses the input audio compression signal by performing processing reverse to that of the signal compression circuit 2. That is, the data length per sample of the input audio compression signal is converted from 8 bits to 16 bits. At the time of audio expansion, the filter circuit 1 upsamples the sampling rate of the audio signal input from the signal expansion circuit 3 from 22.05 KHz to 44.1 KHz, generates the original PCM audio signal, and outputs it as reproduced audio.
[0036]
Thus, when audio compression is performed, the filter circuit 1 operates as a downsampling circuit, and the data flow is as shown by the horizontal solid arrows in FIG. On the other hand, when performing voice decompression, the filter circuit 1 operates as an upsampling circuit, and the data flow is as shown by the vertical solid arrows in FIG.
[0037]
Reference numeral 4 denotes a control circuit that controls the operation of the entire audio compression / decompression apparatus according to the present embodiment, that is, the filter circuit 1, the signal compression circuit 2, and the signal expansion circuit 3. The control circuit 4 includes a control signal generation circuit 5, and generates a control signal for controlling switching between using the filter circuit 1 for downsampling or upsampling.
[0038]
When the voice compression and voice decompression speeds are exactly the same, that is, when the voice input rate and the voice output rate are exactly the same, the processing ratio of upsampling and downsampling is constant. For this reason, a completely fixed schedule can be set for the dynamic switching of the filter circuit 1. In the example shown in the present embodiment, the combination of Expression (3), Expression (2-1), and Expression (2-2) is executed once per 2 PCM.
[0039]
However, as in the apparatus illustrated in FIG. 6, when the relative speed of voice compression and voice expansion changes dynamically (for example, the data source of the input voice is a storage such as a CD, and from this storage, If the data input speed to the voice compression / decompression device includes jitter, or if the voice output speed is increased / decreased, such as a speech speed converter, or if both of these features are combined, then upsampling The downsampling processing ratio is not constant. In this case, for example, the control circuit 4 can switch the operation state of the filter circuit 1 in accordance with the order of requests input from the signal compression circuit 2 and the signal expansion circuit 3.
[0040]
When the audio compression / decompression apparatus of this embodiment is configured as shown in FIG. 6, a buffer memory (not shown) is provided between the signal compression circuit 2 and the signal expansion circuit 3 of FIG. The output audio compression signal is temporarily stored in the buffer memory and then input to the signal decompression circuit 3.
[0041]
As described above, when the filter circuit 1 is configured by integrating (sharing) the hardware shown in FIG. 12 and the hardware shown in FIG. 13 that have been configured separately, the RAM capacity is configured separately. In some cases, two 16-word RAMs are required, whereas in the case of integration, only one 32-word RAM is required. Although the total RAM capacity does not change, according to the present embodiment, it is not necessary to provide two small-capacity memories, and only one medium-capacity memory needs to be provided, which is necessary for the memory in the decoding circuit. There is an advantage that the area is reduced.
[0042]
Further, regarding the ROM capacity, two 32-word ROMs are required when separately configured, whereas only one 32-word ROM is required when integrated. Thereby, the hardware amount of ROM can be reduced to 1/2. Further, as for the multipliers, they are necessary for each when they are configured separately, but only one multiplier is required when they are integrated. Thereby, the hardware amount of the multiplier can be reduced to ½.
[0043]
By sharing and integrating both the down-sampling circuit and the up-sampling circuit, the control circuit 4 becomes complicated, and the processing capacity required per unit time is also required by the sum of the two. Since the reduction is directly linked to the production cost, the advantages are much more than the above-mentioned drawbacks.
[0044]
In the above embodiment, it has been described that the control signal generation circuit 5 dynamically switches the operation of the filter circuit 1 according to the order of downsampling and upsampling. However, when the downsampling request continues, the audio decompression process using upsampling is not performed, and there may be a problem that the reproduced audio is interrupted. Therefore, another example of the dynamic scheduling method of the filter circuit 1 will be shown below.
[0045]
FIG. 3 is a diagram illustrating a configuration example of the control signal generation circuit 5. In FIG. 3, reference numeral 11 denotes an arbitration circuit. When both the downsampling request 16 and the upsampling request 17 are given from the signal compression circuit 2 and the signal decompression circuit 3 via the control circuit 4, It is for mediating whether to respond. As this arbitration method, for example, a processing method described below can be considered.
[0046]
(1) Priorities are set in advance and the higher priority is selected. For example, in the case of a system that is currently reproducing audio, interruption of reproduced audio can be prevented by using this method to preferentially select upsampling.
[0047]
(2) Save the previously selected state and select a different one or the same one. That is, in the arbitration circuit 11, it is determined whether or not the same request has continued for a predetermined number of times, and if it continues, the request different from the previous one is selected, and if it does not continue, the same request as the previous one is selected. To. By doing so, downsampling and upsampling can be selected as evenly as possible, and the interruption of the reproduced sound can be prevented as much as possible.
[0048]
(3) A random number circuit or the like is used for random selection. Here, by generating pseudo-random numbers that have the same ratio between when downsampling is selected and when upsampling is selected, the previous selection state is not maintained as in method (2) above. However, the processing ratio of downsampling and upsampling can be as close to 1: 1 as possible, and interruption of the reproduced sound can be prevented as much as possible.
[0049]
(4) The remaining state of the audio signal buffered in the RAM 6 is selected for selection. That is, when the remaining audio decompression signal DSPCM ′ buffered in the RAM 6 is reduced, if the audio compression is performed by downsampling without performing upsampling, the reproduced audio may be interrupted. Therefore, in this case, selection is performed so that upsampling is performed preferentially.
[0050]
Next, 12 is a flip-flop for storing the internal state of the control signal generation circuit 5, and includes a 2-bit status register 13 and a 4-bit counter 14. The state register 13 stores the operation state (down sampling state, up sampling state, or non-operation state) of the filter circuit 1 as information. The counter 14 counts the length of processing in each state.
[0051]
As described above, in the upsampling and downsampling equations shown in this embodiment, one unit of processing is 16 steps, and in the downsampling equation (3), this “one unit of processing” is performed twice. In the upsampling equations (2-1) and (2-2), “one unit of processing” is performed once.
[0052]
In designing the operation of the filter circuit 1, designing the entire operation to operate periodically in the above-mentioned “one unit of processing” or a plurality of units thereof reduces the amount of hardware and simplifies the design. There is merit in both. Even when dynamic scheduling of the filter circuit 1 is performed, it is effective to perform processing for each “unit of processing”, and FIG. 3 illustrates this method.
[0053]
That is, when the value of the status register 13 is “00”, it indicates an idle state (non-operating state), “01” indicates an upsampling state, “10” indicates a first half state of downsampling, “11” indicates the second half of downsampling. The value of the status register 13 is changed according to the arbitration result in the arbitration circuit 11 in the next cycle when the value of the counter 14 becomes “15”.
[0054]
That is, if there is no request for both downsampling and upsampling, the value of the status register 13 is changed to “00”. Further, when only one of the downsampling request and the upsampling request is set, the value of the status register 13 is either “01” or “10” according to the request. If there is a request for both downsampling and upsampling, the value of the status register 13 is “01” or according to the result of arbitration by any one of the processing methods (1) to (4) described above. It will be either “10”. When the value of the status register 13 is “10”, the value of the status register 13 is unconditionally changed to “11” in the next cycle.
[0055]
Note that the length of “one unit of processing” is an example when the filter circuit 1 shown in the present embodiment is used, and when other filters are used, the length may change or in some cases. There may be no such good length of separation.
[0056]
Next, 15 is a random gate, which generates and outputs an actual control signal for selecting the operation state of the filter circuit 1 from the values of the flip-flop 12 (the values of the state register 13 and the counter 14). When the filter circuit 1 operates according to this control signal, one filter circuit 1 can be shared by downsampling and upsampling.
[0057]
Each block shown in FIG. 3 is configured in hardware in this embodiment, but is configured by a microcomputer system including a CPU, ROM, RAM, and the like, and the operation is stored in the ROM or RAM. It may be realized according to the work program.
[0058]
In this case, the work program itself realizes the functions of the above-described embodiments, and the program itself and means for supplying the program to a computer, for example, a recording medium storing the program constitutes the present invention. To do. As a recording medium for storing such a program, in addition to the ROM and RAM, for example, floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-I, CD-R, CD-RW, DVD, zip, A magnetic tape or a non-volatile memory card can be used.
[0059]
In the above embodiment, the multiplier in the filter circuit 1 is used for down-sampling and up-sampling. However, it is also possible to use the multiplier for other purposes using the characteristics of the filter shape. As shown in FIG. 4 and Table 1, the value of the filter is 0 at index = 0,1,5,9,13,17,21,25,29. When the filter value is 0, the multiplication result is naturally 0. Therefore, when performing multiplication and addition, since the multiplication result is 0, the result of multiplication and addition remains the value entered in the adder.
[0060]
Therefore, by providing a control circuit for outputting a control signal for bypassing the adder when the filter value is 0, the multiplier is not used in the cycle of multiplying this value, and is used for other purposes. It is possible. For example, a multiplier can be used for signal compression processing in the signal compression circuit 2. In particular, for index = 1, 5, 9, 13, 17, 21, 25, 29, the filter value is periodically 0, so that the control circuit can be designed relatively easily.
[0061]
【The invention's effect】
  As described above, the present inventionA filter circuit that performs a downsampling process that lowers the sampling rate of the input audio signal and an upsampling process that increases the sampling rate of the expanded audio signal is provided, and the filter circuit processes the input audio signal and upsampling A temporary storage device for buffering the audio signal, a multiplication and addition circuit for performing downsampling and upsampling operations, and a storage device for storing a multiplication coefficient used in the downsampling and upsampling operations BecauseVoice pressureShrinkageVoice extensionLong andThe amount of hardware required can be reduced, and the overall circuit scale can be reduced.
[0062]
  According to another aspect of the invention, the audio signal is compressed in the signal compression circuit.YouSpeed and signal decompression circuit decompresses audio signalYouWhen the signal compression circuit and the signal expansion circuit operate simultaneously at a speed different from the speed at which the filter circuit operates, the filter circuit generates a control signal for switching whether the filter circuit performs the downsampling process or the upsampling process, Since the control means for dynamically scheduling and time-sharing operation is provided, the filter circuit can be appropriately used according to the operation speed of the signal compression circuit and the signal decompression circuit, and the decompressed audio is output. It is also possible to prevent the inconvenience of being interrupted.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of an audio compression / decompression apparatus according to the present invention.
2 is a diagram illustrating a configuration example of a filter circuit illustrated in FIG. 1. FIG.
FIG. 3 is a diagram illustrating a configuration example of a control signal generation circuit illustrated in FIG. 1;
FIG. 4 is a diagram illustrating an example of the shape of filter coefficients stored in a ROM.
FIG. 5 is a diagram illustrating a configuration example of a conventional audio compression / decompression apparatus.
FIG. 6 is a diagram showing another configuration example of a conventional audio compression / decompression apparatus.
FIG. 7 is a diagram illustrating a configuration example of a conventional audio compression apparatus.
FIG. 8 is a diagram illustrating a configuration example of a conventional audio decompression apparatus.
FIG. 9 is a diagram illustrating a positional relationship between PCM and DSPCM.
FIG. 10 is a diagram illustrating a configuration example of a conventional down-sample circuit.
FIG. 11 is a diagram illustrating calculation contents of tmp [] [].
FIG. 12 is a diagram illustrating another configuration example of a conventional down-sample circuit.
FIG. 13 is a diagram illustrating a configuration example of a conventional up-sampling circuit.
[Explanation of symbols]
1 Filter circuit
2 signal compression circuit
3 signal expansion circuit
4 Control circuit
5 Control signal generation circuit
6 RAM
7 ROM
8th power addition circuit
11 Arbitration circuit
12 Flip-flop
13 Status register
14 counter
15 Random gate
16 Downsampling request
17 Upsampling request

Claims (6)

A filter circuit that performs a downsampling process that lowers the sampling rate of the input audio signal and an upsampling process that increases the sampling rate of the expanded audio signal;
A signal compression circuit for compressing the audio signal down-sampled in the filter circuit;
A signal decompression circuit that decompresses the audio signal compressed in the signal compression circuit and outputs the decompressed signal to the filter circuit ;
In the case where the aforementioned signal compression circuit and the signal expanding circuit speed and different speeds you extended audio signal in the velocity and the signal expanding circuit you compress speech signals are operated simultaneously in the signal compression circuit, the filter circuit Generating a control signal for switching whether to perform the downsampling process or the upsampling process, and dynamically scheduling the filter circuit to perform time division operation, and
The filter circuit includes: a temporary storage device that buffers the input audio signal and an audio signal that performs the upsampling process; a multiplication and addition circuit that performs the downsampling and upsampling operations; the downsampling and And a storage device for storing a multiplication coefficient used in the upsampling operation.   The control means performs request arbitration to selectively operate a process having a higher priority set in advance when there is a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit. The audio compression / decompression apparatus according to claim 1, further comprising: means.   When there is a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit, the control means selectively selects a different process or the same process depending on a previously selected state. The audio compression / decompression apparatus according to claim 1, further comprising request arbitration means configured to operate.   When there is a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit, the control means generates a random number so that the processing ratio of both is approximately 1: 1. The audio compression / decompression apparatus according to claim 1, further comprising request arbitration means for causing processing or upsampling processing to operate at random.   When the control means has a request for both down-sampling from the signal compression circuit and up-sampling from the signal decompression circuit, and there are few audio signals to be subjected to the up-sampling process buffered in the temporary storage device The audio compression / decompression apparatus according to claim 1, further comprising request arbitration means for selectively operating the upsampling process. A filter circuit that performs a downsampling process that lowers the sampling rate of the input audio signal and an upsampling process that increases the sampling rate of the expanded audio signal;
A signal compression circuit for compressing the audio signal down-sampled in the filter circuit;
A signal decompression circuit that decompresses the audio signal compressed in the signal compression circuit and outputs it to the filter circuit ;
The filter circuit includes: a temporary storage device that buffers the input audio signal and an audio signal that performs the upsampling process; a multiplication and addition circuit that performs the downsampling and upsampling operations; the downsampling and A computer-readable recording medium storing a program for controlling an audio compression / decompression apparatus having a storage device for storing a multiplication coefficient used in the upsampling operation,
In the case where the aforementioned signal compression circuit and the signal expanding circuit speed and different speeds you extended audio signal in the velocity and the signal expanding circuit you compress speech signals are operated simultaneously in the signal compression circuit, the filter circuit A computer which records a program for generating a control signal for switching between downsampling processing and upsampling processing and causing the computer to execute a control procedure for dynamically scheduling the filter circuit to perform time division operation A readable recording medium.

Images