JP4127934B2 - Microcontroller and rewriting method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcontroller and a method for rewriting the program, and more particularly to a microcontroller incorporating a nonvolatile memory (flash memory) that can be electrically erased and rewritten for storing programs and a method for rewriting the program.
[0002]
[Prior art]
In recent years, so-called AV devices such as television receivers, VTRs, DVD players, audio components, satellite broadcast receivers, CATV terminals, etc., which have an internal microprocessor system (hereinafter referred to as a microcontroller), home appliances, and electronic devices such as automobile electronics Is generalized. These include a CPU for controlling various circuits and devices constituting the electronic device and a program memory such as a PROM for storing the program of the CPU inside the electronic device. Various circuits / devices provided inside the electronic device are controlled through the connected paths.
[0003]
In addition, as electronic devices become more sophisticated, the specifications become more complex, and the control of the various circuits and devices required for microcontrollers is becoming more complex every year. As a result, defects (so-called bugs) caused by the microcontroller software are discovered after electronic devices are shipped to the market or immediately before shipment, and functional specification changes frequently occur, thereby integrating the functions of electronic devices. There is a situation in which it is frequently necessary to change the program of the microcontroller CPU that is managed and controlled.
[0004]
Recently, an electrically rewritable EEPROM or flash memory has been used instead of a fixed memory such as a mask ROM as a program memory for storing a program of the microcontroller, and the memory is not physically exchanged. In addition, the program can be modified while being mounted on the electronic device.
[0005]
A conventional microcontroller described in Japanese Patent Laid-Open No. 8-6919 (Document 1), which uses a flash memory as a program memory and controls rewriting of a program stored in the flash memory, has at least a central processing on a single semiconductor chip. A device (CPU) and a nonvolatile flash memory that can be rewritten by electrically erasing and writing information (data) to be processed by the CPU are mounted, and a kind of serial communication for rewriting data in the flash memory A rewrite operation mode for rewriting using asynchronous communication is provided, and the baud rate (bit rate) of the asynchronous communication is automatically adjusted to the bit rate of the transfer source.
[0006]
In this case, in the rewrite operation mode, the CPU rewrites the data in the flash memory and controls the serial communication, and the flash memory or the mask ROM holds firmware that is a program for controlling the CPU.
[0007]
When the rewrite operation mode is activated, data in the flash memory other than the area holding the control program is confirmed, and if there is already written data, the area other than the area holding the control program is erased.
[0008]
This type of program rewrite control is generally performed by interruption. An interrupt is a program that forcibly suspends a running program in order to respond to an asynchronous or exceptional event that occurs during program execution. It is to automatically transfer control to the routine. At that time, the CPU state is automatically saved so that the program being executed at the time of interruption can be restarted later.
[0009]
The cause of interrupt generation is classified according to whether or not it is related to the program being executed at the time of the interrupt occurrence. If there is a relation, it is called indexing and is not related to the program being executed. It is common to call an external factor an interrupt. Here, an interrupt caused by this definition, that is, an external factor via a communication device such as serial communication is considered.
[0010]
In general, there are a plurality of interrupts, such as input / output relations, timer relations, and other equipment relations, in addition to the communication device described above. An interrupt controller is provided for selecting the highest level interrupt request according to the interrupt level and making an interrupt request to the CPU.
[0011]
Regarding the priority level and priority level of interrupts, when multiple interrupt causes occur at the same time, the priority issue of which interrupt will occur first and other interrupt causes during the processing of an interrupt When this occurs, there is a problem of whether or not to cause a higher level of urgency and cause another interruption. The general method is to determine the priority and level of interrupts for each cause (group), set the normal program other than interrupt processing as the lowest level, and interrupts belonging to higher interrupt levels are lower. This is a method that allows interrupts during level processing. In the following description, the priority is referred to as an interrupt order, and the level is referred to as an interrupt level.
[0012]
Referring to FIG. 7 showing a block diagram of a conventional microcontroller (hereinafter referred to as a microcomputer) described in Document 1, this conventional microcontroller includes a central processing unit (CPU) 3 coupled to an internal bus and a control for controlling the CPU 3. A serial communication interface (SCI) for performing asynchronous communication between the flash memory 1 storing the program, a timer 30 for measuring a communication data rate (bit rate) between the host computer 8 to be described later, and the host computer 8. ) 60, a random access memory (RAM) 9 functioning as a buffer for temporarily storing data from the flash memory 1, and an operation mode signal input from the mode terminal to determine whether, for example, a rewrite operation mode is instructed Decoder With the door, for example, it is connected through SCI60 to a host computer 8 such as an external personal computer. For storing the control program, a mask ROM 10 indicated by a dotted line may be used instead of the flash memory 1.
[0013]
Next, with reference to FIG. 7 and FIG. 8 showing the process in a flowchart, the rewriting method of the program of the conventional microcontroller will be described. Although not particularly specified in Reference 1, the microcomputer is externally inserted by interruption. When the operation mode signals MDO to MD2 to be set to the rewrite operation mode are received and the operation mode signals MDO to MD2 are decoded by the decoder 7, it is determined that the instruction is the rewrite operation mode with the above settings. The control program stored in the flash memory 1 is executed by reset (REST) start (step P1). This corresponds to setting the rewrite mode by interrupting the CPU 3 with the operation mode signals MDO to MD2.
[0014]
Further, when the control program is started, data is continuously transmitted from the host computer 8 at a predetermined bit rate (step P2), and the CPU 3 sets the LOW period of the data transmitted by the host computer 8 by the input carburetor function of the timer 30. Measurement is performed using the internal clock signal CK (step P3: measurement process). In this case, the input cab terminal of the timer 30 is allocated to the RXD terminal. Then, a value to be set in the bit rate register in the SCI 60 is calculated from the measured value of the data LOW period (step P3: calculation process). This calculation process is performed by the CPU 3, and the obtained value is set in the bit rate register in the SCI 60 (step P3: setting process).
[0015]
Subsequently, when the adjustment is completed to the same bit rate as the bit rate transferred by the host computer 8, the microcomputer transmits a signal of completion of adjustment to the host computer 8 via the transmission line SL (step P5: notification process). The host computer 8 outputs a signal indicating that the adjustment completion signal has been normally received to the microcomputer via the reception line RL (step P5: confirmation process).
[0016]
Further, the host computer 8 notifies the transfer byte number N of the user program to be transferred next (step P5: notification process), and thereafter sequentially transmits the program set by the user. At this time, the microcomputer receives the user program transmitted by the host computer (step P5: reception process) and further transfers it to the RAM 9 (step P6: transfer process). Then, the CPU 3 calculates the number of remaining bytes of the transfer (step P6: remaining byte number calculation process), and repeats it until the transfer of the user program is completed (step P7).
[0017]
Before executing the transferred user program, it is confirmed whether or not the data written in the flash memory 1 exists (steps P8 and P9). If the data has already been written (step P9). The data in all memory blocks is erased (step P10).
[0018]
On the other hand, if no data has been written, the last instruction in the program in the test area in the flash memory 1 is executed to branch to the RAM 9 area, and the user program transferred into the RAM 9 is executed ( Step P11). Thereby, the flash memory 1 can be rewritten.
[0019]
As described above, in the conventional microcontroller, the interrupt to the flash memory rewrite mode is set by the operation mode signals MDO to MD2, and when the flash memory rewrite mode is determined as a result of the recognition of the interrupt, the CPU 3 performs a reset start. The control program (firmware) stored in the flash memory 1 is executed, and data transfer conditions such as the flash memory rewrite data transmission / reception data rate and signal format are set in the dedicated communication terminal SCSI 60 according to the instructions of the firmware. After initialization, the flash memory rewrite data is received under the set data transfer conditions, and the flash memory 1 is rewritten.
[0020]
As described above, in the conventional microcontroller and its program rewriting method, when an interrupt for rewriting the built-in flash memory occurs, data transfer conditions such as a data transfer rate are set in a dedicated communication terminal each time. Rewriting of the flash memory has started from the implementation of initialization.
[0021]
On the other hand, the interrupt vector (combination of the operation mode signals MDO to MD2 in the above-described conventional example), which is the format of the interrupt request signal for setting the interrupt process when the interrupt occurs, depends on the use of the microcomputer. Since the interrupt priority or interrupt level of various serial or parallel communication devices (hereinafter referred to as communication devices) is not constant and varies, it differs depending on the type of microcomputer. For example, the interrupt priority of a communication device is the highest in a certain product, and the interrupt priority of a communication device is set to the lowest in another product.
[0022]
Generally, when the internal flash memory needs to be rewritten, the cause of the interrupt for this rewrite has a higher priority than the cause of other interrupts, and the above rewrite processing is being executed by this interrupt. Must be set to the highest interrupt level that does not accept other interrupts.
[0023]
For this reason, the firmware in the microcomputer's built-in flash memory or mask ROM has a fixed communication device interrupt priority for each type of built-in microcomputer corresponding to the occurrence of an interrupt for rewriting the flash memory. There is a problem that the interrupt design and the interrupt level, for example, the interrupt vector must be changed to the highest interrupt priority and the highest interrupt level, and the design TAT (turnaround time) is prolonged. was there.
[0024]
In addition, there is a problem that design quality is deteriorated due to an increase in bugs and the like by changing firmware for each kind of microcomputer.
[0025]
Here, as is well known, a vector refers to an array of data in which individual items are arranged in order according to a single index or subscript. Therefore, the interrupt vector refers to an instruction and data array related to interrupts arranged in a predetermined order.
[0026]
[Problems to be solved by the invention]
The above-described conventional microcontroller and its program rewriting method perform initialization including setting of data transfer conditions such as a data transfer rate in a dedicated communication terminal each time an interrupt for rewriting the built-in flash memory occurs. The interrupt vector, which is the format of the interrupt request signal for setting the interrupt processing when an interrupt occurs, is a communication device for each product type depending on the application of the microcomputer. The firmware, which is the rewrite control software for the above rewrite control, does not depend on the original interrupt priority level for each type of built-in microcomputer. In response to the occurrence of an interrupt to rewrite the flash memory Bell, must only be designed to change for example the highest level, TAT of the design has a drawback that prolonged.
[0027]
In addition, there is a drawback that the design quality is lowered by changing the firmware for each kind of microcomputer.
[0028]
The object of the present invention is to automatically set the interrupt priority level of a communication device to a predetermined level when an interrupt for rewriting the internal flash memory occurs regardless of the type of microcomputer. It is an object of the present invention to provide a microcontroller and a program rewriting method that eliminates the need for specialized design, eliminates the TAT of the design, and eliminates the cause of the deterioration of the design quality.
[0029]
[Means for Solving the Problems]
The microcontroller according to the present invention has a built-in flash memory that is a nonvolatile memory that can be electrically erased and rewritten for storing programs, and a rewrite operation mode for correcting the program of the flash memory is set by an interrupt. In the microcontroller
A ROM that stores firmware that is a program of a series of operations for rewriting the flash memory and a control program for the operation of the communication means described later, or at least an interrupt vector for setting the control program,
A CPU that is a central processing unit that controls the rewrite procedure of the flash memory in accordance with the firmware read from the ROM;
Controlling the priority order of interrupt request signals sent from a plurality of built-in peripheral circuits in the normal operation mode in which the flash memory is not rewritten and notifying the CPU, and rewriting the flash memory In the rewrite mode, the interrupt request signal from the communication means, which will be described later, input in response to the supply of the rewrite mode signal linked to the rewrite mode setting is changed to a predetermined interrupt order and notified to the CPU. An interrupt controller to
A plurality of said peripheral circuits including input / output (I / O) circuits and timers;
Communication means for performing transmission including reception of rewrite data of the flash memory from an external host computer and reception preparation completion notification to the host computer;
It is configured with.
[0030]
Further, the interrupt controller changes the communication interrupt request signal, which is an interrupt request signal from the communication means input in response to the supply of the rewrite mode signal, to an interrupt order based on a predetermined criterion. An interrupt level conversion circuit for generating an interrupt execution request signal for requesting the CPU to execute interrupt may be provided.
[0031]
Further, the interrupt level conversion circuit selects the one having the highest priority among a plurality of interrupts simultaneously generated according to the priority of predetermined N (N is a positive integer) interrupt request signals. An interrupt priority determination circuit for outputting a selection interrupt request signal;
One of the selected interrupt request signal output from the interrupt priority determination circuit and the communication interrupt request signal from the communication means in response to the logic level of the rewrite mode signal is the interrupt execution request. A rewrite mode prioritizing circuit which selects and outputs as a signal.
[0032]
In addition, the interrupt level conversion circuit simultaneously responds according to the priority of N (N is a positive integer) predetermined interrupt request signals in response to the logic level when the rewrite mode signal is inactivated. Select the highest priority among a plurality of generated interrupts, output the interrupt execution request signal, and respond to the logic level at the time of activation of the rewrite mode signal. An interrupt priority determination circuit for forcibly changing the interrupt priority of a request signal to a lower priority;
Inverting the rewrite mode signal to generate an inverted rewrite mode signal, and in response to a logic level of the inverted rewrite mode signal when the rewrite mode signal is activated, a communication interrupt which is an interrupt request signal from the communication means A rewrite mode prioritizing circuit that sets the order of the embedded signals to the highest order.
[0033]
The program rewriting method of the microcontroller of the present invention incorporates a flash memory which is a nonvolatile memory that can be electrically erased and rewritten electrically for storing programs, and assigns a rewriting operation mode for correcting the program of the flash memory. In the microcontroller flash memory rewrite method set by
A first step of setting a logic level of a rewrite mode signal linked to the rewrite mode setting from L level to H level in a rewrite mode for rewriting the flash memory;
In response to the transition of the rewrite mode signal to the H level, an interrupt of communication means for performing transmission including reception of rewrite data of the flash memory from an external host computer and reception preparation completion notification to the host computer A second step of changing the priority of the request signal to the highest order;
A third step of reading a rewrite operation program in response to the supply of the interrupt execution request signal generated from the interrupt request signal of the communication means and initializing the CPU; and the host computer via the communication means A fourth step of waiting for an interrupt to receive the rewrite data of the flash memory supplied from
A fifth step in which the communication means receives the rewrite data which is interrupt data transmitted by the host computer;
A sixth step in which the CPU recognizes reception of the rewrite data in the communication means and performs rewrite processing of the flash memory based on the rewrite data;
A seventh step of repeating the process of receiving the rewrite data and rewriting the flash memory until receiving all the rewrite data;
It is characterized by including.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0035]
A microprocessor system (hereinafter referred to as a “microcontroller”) according to the present embodiment is provided in electronic equipment such as AV equipment, home appliances, and automobile electronics, and a CPU for controlling various circuits and devices constituting the electronic equipment. A non-volatile flash memory that is rewritable by electrical erasing and writing is built in as a program memory for storing the program, and is provided inside the electronic device by the CPU via a path connected to the CPU and the program memory. Various circuits and devices are controlled. Further, the flash memory can be modified in a state where it is mounted on an electronic device without being physically replaced.
[0036]
The rewrite operation mode for correcting the program is set by the external rewrite operation mode setting. In this rewrite operation mode, the flash memory data rewrite and serial communication are controlled by an interrupt corresponding to the rewrite operation mode. Is a CPU, and a firmware storing ROM holds firmware which is a program for controlling the CPU.
[0037]
When the rewrite operation mode is activated, the data in the flash memory is confirmed, and any data already written is erased.
[0038]
Next, referring to FIG. 1 in which the first embodiment of the present invention is shown in the same block by adding common reference characters / numerals to the same components as in FIG. 7, the present embodiment shown in FIG. The microcontroller of the embodiment includes a flash memory 1 that is an electrically erasable and erasable nonvolatile memory storing a program of a CPU 3 to be described later, and a series of operation programs (firmware for rewriting a predetermined area of the flash memory 1 ) And an ROM (Read Only Memory) 2 storing an interrupt vector corresponding to a CSI 6 control program, which will be described later, a central processing unit (CPU) 3 that controls the rewrite procedure of the flash memory 1 according to the firmware, and a flash In the normal operation mode in which the memory 1 is not rewritten, a plurality of later-described microcontrollers are incorporated The priority order of the interrupt request signal (interrupt vector) sent from the peripheral circuit 5 is controlled and notified to the CPU 3, and the rewrite mode setting when rewriting the flash memory 1 is linked to the rewrite mode setting. An interrupt controller 4 for changing an interrupt request signal from a CSI 6 (to be described later) input in response to the supply of the rewrite mode signal MS to an interrupt rank and an interrupt level based on a certain standard and notifying the CPU 3; Receiving rewrite data DW of flash memory 1 from a plurality of peripheral circuits 5 which are various units such as input / output (I / O) circuits and timers incorporated in the microcontroller and a host computer 8 outside the microcontroller. Or to send DA for acknowledgment (reception preparation completion notification / reception confirmation) to the host computer 8 As a communication device for use, the clock synchronous serial interface corresponding to the clocked communication system is a type of serial communication (CSI: Clocked Sirial Interface) and a 6.
[0039]
In FIG. 1, data not directly related to the present invention, control signal and address transmission internal bus, input / output (I / O) circuit, timer, clock generation circuit, and data from the flash memory 1, ROM 2 or CPU 3 are shown. As for the common components normally provided in this type of microcomputer such as a RAM and a register for temporarily holding the memory, the output of the interrupt request signal is shown as the peripheral circuit 5 and is not shown.
[0040]
The flash memory 1 is a full-face flash memory in which information can be rewritten by electrical batch erasure and writing, and in a state where a microcontroller is mounted on the host system, a specified area is controlled based on the control of the CPU 3. The stored information can be rewritten. Rewriting is not performed for areas other than those specified above that are not subject to rewriting.
[0041]
The memory cell of the flash memory 1 is typically composed of an insulated gate field effect transistor having a two-layer gate structure. A P-type diffusion layer formed on the P-type silicon substrate, a low-concentration N-type diffusion layer formed on the P-type silicon substrate, and an N-type formed on each of the P-type diffusion layer and the N-type diffusion layer A floating gate having a diffusion layer and formed on the P-type silicon substrate through a thin insulating film (for example, 10 nm), a control gate formed on the floating gate through an oxide film, and a source and a drain .
[0042]
Information stored in the memory cell is substantially held in the transistor as a change in threshold voltage. Unless otherwise specified, a case where a transistor for storing information (hereinafter referred to as a storage transistor) is an N-channel type in a memory cell will be described below.
[0043]
The operation of writing information to the memory cell is realized by applying a high voltage to the control gate and drain and injecting electrons from the drain side to the floating gate by avalanche injection. By this writing operation, the threshold voltage of the memory transistor as viewed from its control gate becomes higher than that of the memory transistor in the erased state where the programming operation is not performed.
[0044]
On the other hand, the erase operation is realized by applying a high voltage to the source and extracting electrons from the floating gate to the source side by a tunnel phenomenon. The threshold voltage seen from the control gate of the memory transistor is lowered by the erase operation.
[0045]
In both the write and erase states, the threshold value of the storage transistor is set to a positive voltage level. That is, the threshold voltage in the write state is increased and the threshold voltage in the erase state is decreased with respect to the word line selection level applied from the word line to the control gate. Since both the threshold voltages and the word line selection level have such a relationship, a memory cell can be configured with a single transistor without employing a selection transistor.
[0046]
In the memory cell array using the memory cell, in the memory cells arranged in a matrix in the X and Y directions, the control gates of the storage transistors in the same row are respectively connected to the corresponding word lines, and the drains of the storage transistors arranged in the same column. Each region (input / output node of the memory cell) is connected to a corresponding data line, and the source region is coupled to the source line. By applying the high voltage corresponding to erasure to the source line, the memory cells connected to the source line, that is, the memory cells in the entire row are erased collectively. Therefore, it is possible to erase the memory cells whose sources are commonly connected via at least the source line. Therefore, the size of the memory block to be collectively erased can be arbitrarily set by changing the number of source lines connected in common and the number of memory cells connected to the same source line.
[0047]
In addition to the above firmware, the ROM 2 stores an interrupt vector corresponding to a control program for the CSI 6 corresponding to at least one communication device set at the time of firmware design, here, the clock synchronous communication method. This interrupt vector designates the address of a control program that controls the communication procedure of CSI6 when an interrupt is generated in CSI6. This control program is stored in the ROM 2 itself or an area not to be rewritten in the flash memory 1.
[0048]
In the normal operation mode, which is not the rewrite mode of the flash memory 1, the CPU 3 controls various circuits and devices that constitute an electronic device that is a host system on which the microcontroller is mounted. In the rewrite mode, the flash memory is in accordance with the firmware. 1 rewrite procedure is controlled.
[0049]
The interrupt controller 4 uses an interrupt request signal INT3 of CSI6 inputted in response to the supply of the rewrite mode signal MS of the flash memory 1 as will be described later based on an interrupt rank and an interrupt level based on certain criteria. For convenience, an interrupt level conversion circuit 41 that changes to the highest and highest priority levels and generates an interrupt execution request signal IM is provided.
[0050]
Referring to FIG. 2 showing the configuration of the interrupt level conversion circuit 41 in block form, the interrupt level conversion circuit 41 has a plurality of simultaneous generations according to the priority order of a plurality of predetermined interrupt request signals INT0 to INTN. Interrupt priority determination circuit 411 for selecting the highest priority among the interrupts and outputting the selected interrupt request signal VI, and interrupt priority determination in response to the logic level of the rewrite mode signal MS supplied from the outside A rewrite mode prioritizing circuit 412 is provided which selects and outputs either the selected interrupt request signal VI from the circuit 411 or the interrupt signal VC from the CSI 6 as the interrupt execution request signal IM.
[0051]
In the present embodiment, for convenience of explanation, the number N of interrupt request signals (positive integer), that is, the number of priority levels is set to four levels INT0 to INT3 in descending order from the top, and during normal operation, that is, flash When the memory is not rewritten, the interrupt level of the communication device CSI6 is set to INT3 which is the lowest level.
[0052]
For example, as shown in FIG. 3, the interrupt order determination circuit 411 can be realized by a combination of logic circuits such as a NAND circuit and a NOR circuit.
[0053]
Referring to FIG. 3 which is a circuit diagram showing a configuration example of an interrupt priority determination circuit 411 based on a combination of logic circuits, an inverter G411 for inverting an interrupt request signal INT0B (B represents low active or signal inversion), and this inverter A 2-input NOR circuit G412 that obtains a negative OR (hereinafter referred to as NOR logic) of the output signal of G411 and the interrupt request signal INT1B, and a 2-input that obtains a negative logical product (hereinafter referred to as NAND logic) of the interrupt request signals INT0B and INT1B. NAND circuit G413, a 2-input NOR circuit G414 for obtaining the NOR logic of the output signal of the NAND circuit G413 and the interrupt request signal INT2B, and a 3-input NAND for obtaining the NAND logic of the interrupt request signals INT0B, INT1B, INT2B Circuit G415, output signal of NAND circuit G415 and interrupt request signal INT3B A two-input NOR circuit G416 that obtains the NOR logic of the inverter, a four-input OR circuit G417 that obtains an OR logic of the outputs of the inverters G411, NOR circuits G412, G414, and G416 and outputs a selection interrupt request signal VI that is an output; Is provided.
[0054]
Also, interrupt priority information obtained by adding weighting information based on each preset interrupt priority to information of interrupt requests generated by each of the plurality of peripheral circuits 5 is stored in a table composed of a mask ROM or the like. Alternatively, the interrupt priority level of the input interrupt request signal may be determined by referring to this interrupt priority information.
[0055]
Referring to FIG. 2 again, the rewrite mode prioritizing circuit 412 includes a transfer gate M41 that cuts off the interrupt request signal INT3 in response to the logic level of the rewrite mode signal MS, and an inverter G41 that inverts the rewrite mode signal MS. And a transfer gate M42 for turning off the selected interrupt request signal VI supplied from the interrupt priority determination circuit 411 in response to the logic level of the inverted signal of the rewrite mode signal MS which is the output of the inverter G41. The output terminals of the transfer gates M41 and M42 are connected in common to output an interrupt execution request signal IM as an output. The transfer gates M41 and M42, for example, connect each drain and source to the input and output of the interrupt request signal to be transmitted, respectively, and receive supply of the rewrite mode signal MS / inversion signal of the rewrite mode signal MS to each gate. You may comprise by a MOS transistor.
[0056]
Next, the operation of the microcontroller of this embodiment will be described. Control of program rewriting of the flash memory 1 of the present embodiment is performed by the interrupt described in the related art. An interrupt is a program that forcibly suspends a running program in order to respond to an asynchronous or exceptional event that occurs during program execution. It is to automatically transfer control to the routine. At that time, the CPU state is automatically saved so that the program being executed at the time of interruption can be restarted later.
[0057]
The cause of interrupt generation is classified according to whether or not it is related to the program being executed at the time of the interrupt occurrence. If there is a relation, it is called indexing and is not related to the program being executed. It is common to call an external factor an interrupt. In the present embodiment, an interrupt caused by this definition, that is, an external factor via a communication device such as serial communication is considered.
[0058]
Regarding the priority level and priority level of interrupts, when multiple interrupt causes occur at the same time, the priority issue of which interrupt will occur first and other interrupt causes during the processing of an interrupt When this occurs, there is a problem of whether or not to cause a higher level of urgency and cause another interruption. The general method is to determine the priority and level of interrupts for each cause (group), set the normal program other than interrupt processing as the lowest level, and interrupts belonging to higher interrupt levels are lower. This is a method that allows interrupts during level processing. This method is also used in this embodiment. In the description of the operation of the present embodiment, the priority is referred to as an interrupt order, and the level is referred to as an interrupt level.
[0059]
Next, the operation of the present embodiment will be described with reference to FIGS. 1, 2, and 3. First, in the normal operation in which the flash memory 1 is not rewritten, the rewrite mode signal MS is inactivated. L level corresponding to. As a result, the CPU 3 enters the normal operation mode. At the same time, the interrupt level conversion circuit 41 of the interrupt controller 4 changes the interrupt priority from the interrupt request signal INT0 having the highest interrupt priority to the lowest INT3, that is, the interrupt request signal VC from the CSI6. In response, the highest one of a plurality of simultaneously generated interrupts is selected and a corresponding interrupt execution request signal IM is generated.
[0060]
As described above, the interrupt level determination circuit 411 of the interrupt level conversion circuit 41 selects the highest one among a plurality of interrupts simultaneously generated according to the priority levels of the plurality of interrupt request signals INT0 to INTN. Select and output a selection interrupt request signal VI.
[0061]
For convenience of explanation, it is assumed that inverted interrupt request signals INT0B to INT3B, which are inverted signals of the interrupt request signals INT0 to INT3, are supplied to all input terminals of the interrupt priority determination circuit 411 via an inverter (not shown). . These inversion interrupt request signals INT0B to INT3B are assumed to be in an active state, that is, low active when they are at the L level.
[0062]
When an L-level inverted interrupt request signal (hereinafter abbreviated as interrupt request signal) INT0B is supplied to the interrupt priority determination circuit 411, the interrupt request signal INT0B is input to the inverter G411, NAND circuits G413, and G415, respectively. . The inverter G411 supplies an H level output signal to one input terminal of the NOR circuit G412 and the first input terminal of the OR circuit G417. At this time, the NOR circuit G412 outputs an L level output signal regardless of whether or not the interrupt request signal INT1B supplied to the other input terminal is input, that is, regardless of the H level / L level. When the interrupt request signal INT0B is at the H level, the NOR circuit G412 outputs an H level output signal when the interrupt request signal INT1B is at the L level, and an L level output signal when the interrupt request signal INT1B is at the H level. To output to the OR circuit G417. That is, the interrupt request signal INT0B has a higher priority than the interrupt request signal INT1B.
[0063]
The interrupt request signal INT1B is input to the NOR circuit G412, NAND circuits G413 and G415, respectively. The interrupt request signal INT2B is input to the NOR circuit G414 and NAND circuit G415, respectively. The interrupt request signal INT3B is input only to the NOR circuit G416.
[0064]
Since the NAND circuit G413 sets the output signal to the L level only when both of the interrupt request signals INT0B and INT1B are at the H level, and the output signal is set to the H level in the other cases, the NOR circuit G414 has the interrupt request signal INT0B. , INT1B outputs an output signal corresponding to the level of the interrupt request signal INT2B only when both are in the H level, that is, in the inactive state. That is, the interrupt request signal INT2B has a lower priority than the interrupt request signals INT0B and INT1B.
[0065]
Since the NAND circuit G415 sets the output signal to the L level only when the interrupt request signals INT0B, INT1B, and INT2B are at the H level, and the output signal is set to the H level in the other cases, the NOR circuit G416 When the three request signals INT0B, INT1B, and INT2B are at the H level, that is, in the inactive state, the output signal corresponding to the level of the interrupt request signal INT3B, that is, when the interrupt request signal INT3B is at the L level. When the H level output signal and the interrupt request signal INT3B are at the H level, the L level output signal is output. That is, the interrupt request signal INT3B has a lower priority than the interrupt request signals INT0B, INT1B, and INT2B.
[0066]
Therefore, the interrupt priority order decreases in the order of INT0B, INT1B, INT2B, INT3B.
[0067]
For example, when the interrupt request signal INT3B and the interrupt request signal INT0B are simultaneously input to the interrupt priority determination circuit 411 (that is, set to L level), the interrupt request signal INT0B has a higher priority. The output of the inverter G411 corresponding to the interrupt request signal INT0B becomes H level, while the output of the NOR circuit G416 corresponding to the interrupt request signal INT3B remains at L level. Further, since the interrupt request signal INT2B does not have an interrupt request and remains at the H level, the output of the corresponding NOR circuit G414 becomes the L level.
[0068]
The OR circuit G417 takes the OR logic of the output signals of the inverter G411, NOR circuits G412, G413, and G416. Therefore, in this case, the selection interrupt request signal VI is output corresponding to the H level of the inverter G411. Therefore, the interrupt request signal INT0B is output as the selected interrupt request signal VI.
[0069]
In the rewrite mode prioritization circuit 412, the selection interrupt request signal VI received from the interrupt priority determination circuit 411 is input to the transfer gate M42. Further, the interrupt request signal INT3 is input to the transfer gate M41. Since the logic level of the rewrite mode signal MS is L level, the transfer gate M41 receiving the supply of the rewrite mode signal MS to the control terminal (in the case of a MOS transistor) is cut off, while the rewrite mode signal is applied to the control terminal. The transfer gate M42 that receives the inverted rewrite mode signal MSB obtained by inverting the signal MS by the inverter G41 becomes conductive. Therefore, the interrupt request signal INT3 is blocked by the transfer gate M41, and the selected interrupt request signal VI that has passed through the transfer gate M42 is output as the interrupt execution request signal IM.
[0070]
The CPU 3 performs a normal operation including an interrupt operation in response to the supply of the interrupt execution request signal IM.
[0071]
Next, a description will be given of an operation when rewriting the flash memory 1 with reference to FIG. 4 showing a process in the case of automatically performing interrupt switching. When rewriting the flash memory 1, First, the rewrite mode signal MS is set from L level (non-supply state or inactive state) to H level (supply state or active state). When the rewrite mode signal MS becomes H level (step S1), the interrupt level conversion circuit 41 of the interrupt controller 4 has the lowest interrupt priority, that is, the interrupt priority of the interrupt request signal VC of CSI6 of INT3. Is changed to the highest rank (step S2).
[0072]
At the same time, the CPU 3 enters the rewrite mode, the interrupt request signal VC from the CSI 6 is handled with the highest priority, and the interrupt level conversion circuit 41 of the interrupt controller 4 enters a state for generating the interrupt execution request signal IM. .
[0073]
In the rewrite mode priority circuit 412 of the interrupt level conversion circuit 41, the selected interrupt request signal VI received from the interrupt priority determination circuit 411 is input to the transfer gate M42. Further, the interrupt request signal INT3, that is, the interrupt request signal VC from the CSI 6 is input to the transfer gate M41. Since the logic level of the rewrite mode signal MS is H level, the transfer gate M41 that receives the supply of the rewrite mode signal MS to the control terminal becomes conductive, while the transfer gate M41 receives the supply of the inverted rewrite mode signal MSB to the control terminal. The gate M42 is cut off. Therefore, the selected interrupt request signal VI is blocked by the transfer gate M42, and the interrupt request signal INT3 that has passed through the transfer gate M41, that is, the interrupt request signal VC from the CSI 6 is output as the interrupt execution request signal IM.
[0074]
Next, the CPU 3 reads the rewrite operation program PR from the ROM 2 in response to the supply of the interrupt execution request signal IM generated from the interrupt request signal VC of the CSI 6 output from the interrupt controller 4, and initializes the CPU 3. After going through (Step S3), it enters a state of waiting for interrupt data supplied from the external host computer 8 via the CSI 6, that is, rewrite data DW of the flash memory 1, that is, an interrupt wait state (Step S4).
[0075]
Further, the CPU 3 notifies the host computer 8 via the CSI 6 of this interrupt waiting state, that is, that reception preparation is completed (acknowledgement). The host computer 8 transmits the rewrite data DW in response to the acknowledgment of the reception preparation completion notification. Next, the CSI 6 receives rewrite data DW of the flash memory 1 which is interrupt data from the host computer 8 (step S5).
[0076]
Since the CSI 6 is a clock synchronous serial interface, data and this communication clock are transmitted in synchronization with the communication clock signal generated on the transmission side, here, the host computer 8, and received on the reception side, ie, the CSI 6. Data is received in synchronization with the communication clock. Accordingly, initialization such as bit rate adjustment as in the asynchronous mode is unnecessary, and data transfer processing can be performed immediately after the completion of the reception preparation.
[0077]
The CPU 3 recognizes the reception of the rewrite data DW at the CSI 6 via the interrupt controller 4, reads the rewrite data DW from the CSI 6, and performs the rewrite processing of the flash memory 1 based on this rewrite data (step S6).
[0078]
The process of receiving the rewrite data DW and rewriting the flash memory 1 is repeated until all the rewrite data DW is received (step S7).
[0079]
The process ends when all the flash memory 1 has been rewritten.
[0080]
Next, referring to FIG. 5 showing a flowchart of the erasing process that is the first process of the rewriting process of the flash memory 1, the erasing process of the flash memory 1 will be described. A block (area) to be designated is designated (step S11). Further, the CPU 3 sets the flash memory 1 to the erase mode (step S12).
[0081]
Subsequently, the CPU 3 waits for a predetermined number of cycles with the software timer during the erasure time T (step S13), and releases the erase mode of the flash memory 1 after the lapse of T time (step S14).
[0082]
Further, the flash memory 1 is set to the erase verify mode (step S15), and the block to be erased is read (step S16).
[0083]
When all addresses are read and erased to the state of “1” (step S17), the CPU 3 cancels the erase verify mode (step S18), and further cancels the designation of the erase block (step S19). Erasing is complete.
[0084]
On the other hand, if all addresses have not been read in step S17, the address is incremented (step S20), and then the processing from reading the block in step S16 is repeated.
[0085]
In this case, the erasing time T is a time for changing the memory cell from the written state (high threshold region VthH) to the erased state (low threshold region VthL).
[0086]
This erase time T varies depending on the process technology of the memory cell. For example, the high threshold region VthH is 4.5 V or more, the low threshold region VthL is 2.5 V or less, and it takes 10 ms to change from the high threshold region VthH to the low threshold region VthL.
[0087]
After completion of the erase process, the CPU 3 transfers the rewrite data DW from the CSI 6 to the flash memory 1, and the flash memory 1 receives the transfer of the rewrite data DW and performs a write process to the area after the erase is completed.
[0088]
In the present embodiment, a clock synchronous serial interface (CSI) is used as a communication device. However, the communication device is not limited to this CSI, and the asynchronous communication (UART: Universal Asynchronous Receiver / Transmitter) as described in the related art. I and 2-wire bidirectional serial communication system ² A serial communication system such as C (Inter-IC) or a parallel communication system by transmission of general parallel data may be used. Further, two or more of these communication methods may be supported, and one of them may be selectively used depending on the communication partner.
[0089]
Further, although the case where the number of interrupt request signals of the interrupt controller of the present embodiment is four has been described, it is obvious that the number of interrupt request signals can be arbitrarily set without being limited to this.
[0090]
Next, the interrupt level conversion circuit 41A, which characterizes the second embodiment of the present invention, is referred to FIG. Then, the difference of the interrupt level conversion circuit 41A of the present embodiment shown in this figure from the first embodiment described above is that each of the interrupt rank determination circuit 411 and the rewrite mode prioritization circuit 412 is replaced with each other. In response to the logic level (H level) at the time of activation of the rewrite mode signal MS, the interrupt order determination circuit 411A forcibly changes the interrupt order to a lower order, and the rewrite mode signal MS is inverted and inverted rewrite Write that generates the mode signal MSB and sets the order of the interrupt request signal INT3 corresponding to the interrupt signal VC from the CSI 6 in response to the logic level of the inverted rewrite mode signal MSB It is to comprise each example mode priority circuit 412A.
[0091]
The difference between the interrupt priority determination circuit 411A and the interrupt priority determination circuit 411 is that a two-input NAND circuit G11A for obtaining the NAND logic of the interrupt request signal INT0B and the rewrite mode signal MS is replaced by a NAND circuit instead of the inverter G411. Instead of G413, a 3-input NAND circuit G413A for obtaining NAND logic with the rewrite mode signal MS in addition to the interrupt request signals INT0B and INT1B is added to the rewrite mode signal MS with the interrupt request signals INT0B, INT1B and INT2B. The 4-input NAND circuit G415A for obtaining the NAND logic obtains the OR logic of the outputs of the NOR circuits G412, G414, G416 and the NOR circuit G419, which will be described later, and outputs an interrupt execution request signal IM as an output. Each circuit G417A is provided.
[0092]
The rewrite mode prioritizing circuit 412A is an inverter G418 that inverts the rewrite mode signal MS to generate an inverted rewrite mode signal MSB, and a 2-input NOR circuit that obtains the NOR logic of the interrupt request signal INT3B and the inverted rewrite mode signal MSB. G419.
[0093]
Similarly to the first embodiment, all the input terminals of the interrupt order determination circuit 411A according to the present embodiment are connected to an inverted interrupt that is an inverted signal of the interrupt request signals INT0 to INT3 via an inverter (not shown). Assume that the request signals INT0B to INT3B are supplied. It is assumed that the inversion interrupt request signals INT0B to INT3B are in an active state, that is, low active when they are at the L level.
[0094]
The operation of the present embodiment will be described. First, in the normal operation mode in which the rewrite mode signal MS is at the L level corresponding to the inactivation of the rewrite mode signal MS, the rewrite mode prioritizing circuit 412A has the inverted rewrite mode signal whose logic level is the H level. Output MSB. Therefore, the NOR circuit G419 outputs an L level regardless of the logic level of the interrupt request signal INT3B.
[0095]
On the other hand, the NAND circuit G411A, G413A, G415A of the interrupt order determination circuit 411A receives the L-level rewrite mode signal MS, so that the interrupt order determination circuit 411A determines the interrupt order determination according to the first embodiment. The same operation as that of the circuit 411 is performed. Accordingly, the interrupt request signals INT0B, INT1B, INT2B, and INT3B are selected from the higher order in order of priority, and the interrupt execution request signal IM is output from the OR circuit G417A.
[0096]
That is, the NAND circuit G411A outputs an H level when the logic level of the interrupt request signal INT0B is L, which is the same operation as the inverter G411 in the first embodiment. Similarly, NAND circuits G413A and G415A perform the same operation as NAND circuits G413 and G415, respectively.
[0097]
Next, when the rewrite mode signal MS is activated and becomes H level corresponding to the rewrite mode of the flash memory, the rewrite mode prioritizing circuit 412A outputs the inverted rewrite mode signal MSB whose logic level is L level. Therefore, the NOR circuit G419 changes its output logic level according to the logic level of the interrupt request signal INT3B, and outputs an output signal whose logic level is H level when the logic level of the interrupt request signal INT3B is L level.
[0098]
On the other hand, since the NAND circuit G411A, G413A, G415A of the interrupt order determination circuit 411A receives the H-level rewrite mode signal MS, the output logic levels of these NAND circuits G411A, G413A, G415A are the interrupt request signals INT0B, The L level is output regardless of the logic levels of INT1B, INT2B, and INT3B. As a result, the output logic levels of the NOR circuits G412, G414, and G416 become L level regardless of the logic levels of the interrupt request signals INT0B, INT1B, INT2B, and INT3B. Therefore, the OR circuit G417A outputs the corresponding interrupt execution request signal IM when the logic level of the interrupt request signal INT3B is L level, that is, when there is an interrupt request.
[0099]
【The invention's effect】
As described above, the microcontroller of the present invention and the method for rewriting the program include the firmware for rewriting the flash memory and the ROM storing the control program for the operation of the communication means or at least the interrupt vector for setting the control program. Controls the priority order of interrupt request signals sent from a plurality of built-in peripheral circuits in the normal operation mode, notifies the CPU, and rewrite mode linked to the rewrite mode setting in the flash memory rewrite mode An interrupt controller for changing the interrupt request signal from the communication means input in response to the signal supply to a predetermined interrupt order and notifying the CPU is provided. Set the interrupt priority to the above-mentioned predetermined interrupt priority, for example, the highest priority Since the communication means is controlled dynamically by the control program corresponding to the interrupt vector, the design TAT can be shortened by eliminating the need for a dedicated firmware design regardless of the type of microcontroller. effective.
[0100]
In addition, since there is no need to change the firmware for each type of microcontroller, it is possible to apply a standardized design from which bugs and the like have been sufficiently removed, thereby eliminating the design quality degradation factor.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a microcontroller of the present invention.
2 is a block diagram showing an example of a configuration of an interrupt level conversion circuit in FIG. 1; FIG.
FIG. 3 is a circuit diagram showing an example of a configuration of an interrupt order determination circuit in FIG. 2;
FIG. 4 is a flowchart showing an example of the operation in the microcontroller of the present embodiment and the program rewriting method thereof.
FIG. 5 is a flowchart showing an example of an erasing operation in the program rewriting method of the present embodiment.
FIG. 6 is a circuit diagram showing an example of a configuration of an interrupt level conversion circuit that characterizes the second embodiment of the microcontroller of the present invention;
FIG. 7 is a block diagram showing an example of a conventional microcontroller and a method for rewriting the program.
FIG. 8 is a flowchart showing an example of operation in a conventional microcontroller and its program rewriting method.
[Explanation of symbols]
1 Flash memory
2 ROM
3 CPU
4 Interrupt controller
5 Peripheral circuits
6 CSI
7 Decoder
8 Host computer
9 RAM
30 timer
60 SCI
41, 41A Interrupt level conversion circuit
411,411A Interrupt ranking determination circuit
412A 412A Rewrite mode priority circuit
G41, G411, G418 inverter
G412, G414, G416, G419 NOR circuit
G413, G415, G411A, G413A, G415A NAND circuit
G417, G417A OR circuit
M41, M42 Transfer gate

Claims (9)

In a microcontroller that has a built-in flash memory that is an electrically erasable and rewritable nonvolatile memory for program storage, and a rewrite operation mode for modifying the program of the flash memory is set by an interrupt.
A ROM that stores firmware that is a program of a series of operations for rewriting the flash memory and an interrupt vector that sets a control program for the operation of the communication means described below,
A CPU that is a central processing unit that controls the rewrite procedure of the flash memory in accordance with the firmware read from the ROM;
Communication means for performing transmission including reception of rewrite data of the flash memory from an external host computer and reception preparation completion notification to the host computer;
A plurality of peripheral circuits including input / output (I / O) circuits and timers;
In the normal mode in which the flash memory is not rewritten, an interrupt request signal sent from the plurality of peripheral circuits is notified to the CPU according to a predetermined priority order, and the flash memory is rewritten. In a certain rewrite mode, in response to the supply of the rewrite mode signal linked to the rewrite mode setting, the communication means interrupt request signal is higher than the communication means interrupt order determined by the priority order. A microcontroller comprising: an interrupt controller that changes and notifies the CPU .   The CPU changes the communication interrupt request signal, which is an interrupt request signal from the communication means input in response to the supply of the rewrite mode signal, to an interrupt order based on a predetermined criterion. 2. The microcontroller according to claim 1, further comprising an interrupt level conversion circuit for generating an interrupt execution request signal for requesting interrupt execution. The interrupt level conversion circuit selects and selects the highest priority among a plurality of interrupts simultaneously generated according to the priority of predetermined N (N is a positive integer) interrupt request signals. An interrupt order determination circuit for outputting an interrupt request signal;
One of the selected interrupt request signal output from the interrupt priority determination circuit and the communication interrupt request signal from the communication means in response to the logic level of the rewrite mode signal is the interrupt execution request. A rewrite mode prioritizing circuit which selects and outputs as a signal;
The microcontroller according to claim 2, further comprising: When N is 4 and the interrupt order determination circuit is in a normal operation mode in which the flash memory is not rewritten, an inverted signal of the highest priority interrupt request signal among the four interrupt request signals. An inverter that inverts a first inversion interrupt request signal;
A first logical OR of the output signal of the inverter and a second inverted interrupt request signal that is an inverted signal of the interrupt request signal of the second priority order among the four interrupt request signals. A NOR circuit;
A first NAND circuit that takes a negative logical product of the first inverted interrupt request signal and the second inverted interrupt request signal;
An OR operation is performed between the output of the first NAND circuit and a third inverted interrupt request signal that is an inverted signal of the interrupt request signal of the third priority among the four interrupt request signals. A second NOR circuit;
A third inversion which is an inverted signal of the interrupt request signal of the third priority among the first inverted interrupt request signal, the second inverted interrupt request signal, and the four interrupt request signals. A second NAND circuit that performs a NAND operation with the interrupt request signal;
An OR operation is performed between the output of the second NAND circuit and a fourth inverted interrupt request signal which is an inverted signal of the interrupt request signal having the fourth priority order among the four interrupt request signals. A third NOR circuit;
An OR circuit that generates the selection interrupt request signal by performing a logical sum of the output of the inverter and the outputs of the first to third NOR circuits;
The microcontroller according to claim 3, further comprising: A first transfer gate that interrupts the communication interrupt request signal in response to a logic level of the rewrite mode signal;
An inverter that inverts the rewrite mode signal and outputs an inverted rewrite mode signal;
The selected interrupt whose output terminal is connected in common with the output terminal of the first transfer gate and is supplied from the interrupt priority determining circuit in response to the logic level of the inverted rewrite mode signal which is the output of the inverter 4. The microcontroller according to claim 3, further comprising: a second transfer gate that cuts off the request signal, and outputting the interrupt execution request signal from the output terminal. The interrupt level conversion circuit is simultaneously generated according to the priority order of N interrupt request signals determined in advance (N is a positive integer) in response to the logic level when the rewrite mode signal is inactivated. Select the highest priority among a plurality of interrupts, output the interrupt execution request signal, and respond to the logic level when the rewrite mode signal is activated, the interrupt request signal with the highest priority An interrupt priority determination circuit for forcibly changing the interrupt priority to a lower priority;
Inverting the rewrite mode signal to generate an inverted rewrite mode signal, and in response to a logic level of the inverted rewrite mode signal when the rewrite mode signal is activated, a communication interrupt which is an interrupt request signal from the communication means Rewrite mode prioritizing circuit that sets the order of the embedded signal to the highest order,
The microcontroller according to claim 2, further comprising: When N is 4 and the interrupt order determination circuit is in a normal operation mode in which the flash memory is not rewritten, an inverted signal of the highest priority interrupt request signal among the four interrupt request signals. A first NAND circuit that performs a NAND operation between a first inversion interrupt request signal and the rewrite mode signal;
A negative logical sum of the output signal of the first NAND circuit and a second inverted interrupt request signal that is an inverted signal of the interrupt request signal of the second priority among the four interrupt request signals. A first NOR circuit to take;
A second NAND circuit that performs a negative logical product of the first inverted interrupt request signal, the second inverted interrupt request signal, and the rewrite mode signal;
An OR operation is performed between the output of the second NAND circuit and a third inverted interrupt request signal that is an inverted signal of the interrupt request signal of the third priority among the four interrupt request signals. A second NOR circuit;
A third inversion which is an inverted signal of the interrupt request signal of the third priority among the first inverted interrupt request signal, the second inverted interrupt request signal, and the four interrupt request signals. A third NAND circuit that takes a negative logical product of an interrupt request signal and the rewrite mode signal;
An OR operation is performed between the output of the third NAND circuit and a fourth inverted interrupt request signal which is an inverted signal of the fourth priority interrupt request signal among the four interrupt request signals. A third NOR circuit;
An OR circuit that generates the selection interrupt request signal by ORing the outputs of the first NAND circuit, the outputs of the first to third NOR circuits, and the output of the rewrite mode priority circuit; With
The rewrite mode prioritizing circuit inverts the rewrite mode signal and outputs an inverted rewrite mode signal; and
A fourth NOR circuit that performs a negative OR of the inverted rewrite mode signal and the communication interrupt request signal;
The microcontroller according to claim 6, further comprising:   2. The microcontroller according to claim 1, wherein the communication unit includes a clock synchronous serial interface corresponding to a clock synchronous communication system which is a kind of serial communication. Built-in flash memory, which is an electrically erasable and rewritable non-volatile memory for storing programs, and rewriting the flash memory of a microcontroller that is set by an interrupt to rewrite the flash memory program. In the method
A first step of setting a logic level of a rewrite mode signal linked to the rewrite mode setting from L level to H level in a rewrite mode for rewriting the flash memory;
In response to the transition of the rewrite mode signal to the H level, an interrupt of communication means for performing transmission including reception of rewrite data of the flash memory from an external host computer and reception preparation completion notification to the host computer A second step of changing the priority of the request signal from a predetermined rank to the highest rank;
A third step of reading the rewrite operation program in response to the supply of the interrupt execution request signal generated from the interrupt request signal of the communication means and initializing the CPU;
A fourth step of waiting for an interrupt for receiving rewrite data of the flash memory supplied from the host computer via the communication means;
A fifth step in which the communication means receives the rewrite data which is interrupt data transmitted by the host computer;
A sixth step in which the CPU recognizes reception of the rewrite data in the communication means and performs rewrite processing of the flash memory under the rewrite data;
A seventh step of repeating the reception of the rewrite data and the rewrite process to the flash memory until receiving all the rewrite data;
A method of rewriting a flash memory of a microcontroller, comprising:

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