JP4122720B2 - Simulation method and design method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transistor model for a circuit simulator, and more particularly to a practical and accurate transistor model for a circuit simulator used for a thin film transistor circuit simulator.
[0002]
[Prior art]
A circuit simulator is an important tool in the research and development of transistor processes, devices, and circuits. Its purpose is to improve development efficiency, realize optimal design, and present research guidelines. The transistor circuit simulator requires a practical and accurate transistor model.
[0003]
On the other hand, thin film transistors, which are listed as a kind of transistor, are widely used in display devices and sensors, and the range of use is expected to expand further in the future. In particular, according to the polycrystalline silicon thin film transistor, not only a pixel but also a drive circuit can be configured. The circuit simulator described above is indispensable for designing the drive circuit.
[0004]
As a transistor model for a circuit simulator for a thin film transistor, a model that is considered to be the best at present is a model that combines a multi-transistor model and an effective conductance model (multi-transistor effective conductance model). For the multi-transistor model, see MJ Quinn, IDRC '94, 402 (1994), MJ Quinn, AMLCD '94, 160 (1994), MJ Quinn, EuroDisplay '96 WORKSHOP, 49 (1996). Thin film transistors are characterized by a relatively high channel resistance even in the on state and a large gate insulating film capacitance due to a long channel length. For this reason, it becomes necessary to treat the transistor as a transmission line. In the circuit simulator, a model of the effect of this transmission line is a multi-transistor model. FIG. 1 shows a multi-transistor model. In the multi-transistor model, one transistor is represented by a structure in which a plurality of sub-transistors 18 are connected in series, and a gate insulating film capacitor 19 is connected to each sub-transistor 18. Here, the number of sub-transistors 18 is five, but the number of sub-transistors 18 is not limited as long as it is two or more. With the multi-transistor model, the voltage dependency and frequency dependency of the gate insulating film capacitance of the thin film transistor can be accurately reproduced. In particular, a long-channel thin film transistor has a relatively high channel resistance and a relatively large gate insulating film capacitance, so that voltage dependency and frequency dependency are increased, and it is significant to use a multi-transistor model.
[0005]
For effective conductance models, see MJ Izzard, Jpn. J. Appl. Phys. 30, L170 (1991), MJ Quinn, IDRC '94, 402 (1994), MJ Quinn, AMLCD '94, 160 (1994), MJ Quinn , EuroDisplay '96 WORKSHOP, 49 (1996), M. Kimura, AMLCD 98, 181-184 (1998). There are a wide variety of device structures and manufacturing processes for thin film transistors, and the characteristics differ greatly depending on the device structure and manufacturing process. Furthermore, there are currently many unclear points regarding carrier conduction in amorphous silicon / polycrystalline silicon used in thin film transistors. Therefore, at present, there is no unified basic equation / physical equation that represents the characteristics. Therefore, one of practical models is the effective conductance model. Since the effective conductance model uses actual transistor characteristics as they are, any characteristics can be expressed correctly. It can be said that it is a practical model.
[0006]
FIG. 2 shows the operation of the multi-transistor effective conductance model for the long channel transistor. The graph corresponds to each Vgs, the horizontal axis represents Vds, and the vertical axis represents Ids. First, transistor characteristics are prepared. In the sub-transistor, the channel width (W) is the same as that of the original transistor, but the channel length (L) is 1/5 of that of the original transistor. Therefore, the characteristics of the sub-transistor shown in this graph are five times that of the original transistor. The characteristic of the kth sub-transistor is a function expressed by the following equation.
Ik = Ids (Vgs, Vk) -Ids (Vgs, Vk-1)
Here, Vgs is the gate-source voltage of the original transistor, Vk is the potential of the kth internal node, V0 is equal to the source potential of the original transistor, and V5 is equal to the drain potential of the original transistor. This will be described with reference to FIG. First, select the Ids-Vds graph corresponding to Vgs. Then, the current value Ids (Vgs, Vk) corresponding to the internal node voltage Vk and the current value Ids (Vgs, Vk-1) corresponding to the internal node voltage Vk-1 are read. These differences are Ik. In the steady state, I1 = I2 = I3 = I4 = I5. V1, V2, V3, V4, and V5 giving this condition are internal node potentials in the steady state.
[0007]
FIG. 3 shows the internal node potential for the long channel transistor. FIG. 2 and FIG. 3 are in a mirror relationship. This internal node potential distribution is very similar to the channel potential obtained by device simulation (such as Silvaco International's Atlas) and analytical considerations (submicron device 2, Shoji Tanaka, Maruzen, etc.).
[0008]
FIG. 4 shows an example of the voltage dependency and frequency dependency of the gate insulating film capacitance based on the multi-transistor effective conductance model. In FIG. 4, Vds = 10V and Cox is a gate insulating film capacitance calculated geometrically. This result agrees well with the actual measurement value.
[0009]
[Problems to be solved by the invention]
The multi-transistor model does not work correctly for short channel transistors. Here, the short channel transistor refers to a transistor having a kink effect. The kink effect refers to a phenomenon in which Ids does not saturate even in the original saturation region, and Ids rapidly increases as Vds increases. FIG. 5 shows the operation of the multi-transistor effective conductance model for the short channel transistor. FIG. 6 shows the internal node potential for the short channel transistor. The distribution of the internal node potential is obtained by the same consideration as the case of obtaining the internal node potential for the normal transistor described above. According to the above-described device simulation and analytical considerations, the channel potential should have a distribution similar to that of the long channel transistor even for the short channel transistor. The internal node potential based on the multi-transistor effective conductance model for a short channel transistor is completely different from the channel potential based on device simulation and analytical considerations, and is incorrect.
[0010]
As described above, since the distribution of the internal node potential is not correct, the charge / discharge charge to the gate electrode required for operating the transistor cannot be simulated correctly. Therefore, the evaluation results in the transient analysis (ring oscillator oscillation frequency, maximum shift register operating frequency, etc.) become incorrect. In particular, the short channel thin film transistor has a relatively large kink effect, so that the validity of the multi-transistor model is easily lost.
[0011]
FIG. 7 shows a comparison between the simulation result of the oscillation frequency of the ring oscillator and the actual measurement value based on the multi-transistor effective conductance model. In the multi-transistor model, the charge / discharge charge cannot be correctly simulated, and the oscillation frequency of the ring oscillator is higher than the actual measurement value.
[0012]
Therefore, the object of the present invention is to accurately reproduce the voltage dependence and frequency dependence of the gate insulating film capacitance as it appears in a long channel transistor in a transistor model for a circuit simulator, and at the same time, an internal node that appears as a short channel transistor. The object is to obtain a correct simulation result even in transient analysis by correctly simulating the distribution of potential.
[0013]
[Means for Solving the Problems]
One aspect of the simulation method according to the present invention is a circuit simulation method including a first transistor and a second transistor, wherein the channel length of the second transistor is shorter than the channel length of the first transistor. One transistor has no kink effect, and the second transistor has a kink effect. The multi-transistor model is used for the first transistor, and the voltage dependency and frequency of the gate insulating film capacitance of the first transistor are used. And regenerating the distribution of the internal node potential of the second transistor using a monotransistor model for the second transistor.
In the simulation method, the multi-transistor model assumes that one transistor is a plurality of sub-transistors connected in series, reads the internal node potential of each of the plurality of sub-transistors, It is preferable to use a distribution.
In the simulation method, it is preferable that the first transistor is formed in a pixel portion and the second transistor is formed in a driver portion.
In the simulation method, the channel length of the first transistor is preferably 4 μm or more.
In the simulation method, the channel length of the second transistor is preferably 4 μm or less.
One aspect of the design method according to the present invention is to design a circuit including the first transistor and the second transistor using the simulation method.
[0014]
One aspect of the transistor model for a circuit simulator according to the present invention is a monotransistor model in which a single transistor is represented by a single transistor as it is, and a single transistor is connected to a plurality of sub-transistors in series. When a model represented by a structure in which a gate insulating film capacitance is connected to each sub-transistor is defined as a multi-transistor model, a mono-transistor model and a multi-transistor model are selectively used for each transistor. A transistor model for a circuit simulator, characterized in that
According to this configuration, the monotransistor model is used for transistors that can be correctly simulated by the monotransistor model, and the multitransistor model is used for transistors that can be correctly simulated by the multitransistor model. It is possible to simulate correctly.
[0015]
In the transistor model for circuit simulator, in the monotransistor model, it is preferable that the gate insulating film capacitance is connected between the gate electrode and the source electrode.
[0016]
According to this configuration, in the monotransistor model, the gate insulating film capacitance is not underestimated, and the design is on the safe side.
[0017]
In the transistor model for the circuit simulator, it is preferable that a monotransistor model is used for a transistor having a kink effect, and a multi-transistor model is used for a transistor having no kink effect.
[0018]
According to this configuration, the monotransistor model is used for a transistor having a kink effect that can be correctly simulated by the monotransistor model, and the multitransistor is used for a transistor having no kink effect that can be correctly simulated by the multitransistor model. By using the model, it is possible to correctly simulate all the transistors.
[0019]
In the transistor model for the circuit simulator, it is preferable to use a monotransistor model for a short channel transistor and a multi-transistor model for a long channel transistor.
[0020]
Here, the short channel transistor is defined as a transistor in which the electric field at the drain end is high and impact ionization occurs under the operating conditions used, and the kink effect is likely to occur. On the other hand, a long channel transistor is defined as a transistor in which the electric field at the drain end is low and collision ionization does not occur under the operating conditions used, and the kink effect is unlikely to occur.
[0021]
According to this configuration, by using a monotransistor model for a short channel transistor that can be correctly simulated by a monotransistor model, and using a multitransistor model for a long channel transistor that can be correctly simulated by a multitransistor model, It is possible to correctly simulate all transistors.
[0022]
It is preferable to apply the transistor model for circuit simulator to a thin film transistor.
[0023]
According to this configuration, it is possible to correctly simulate all transistors for thin-film transistors, which often include transistors that can be correctly simulated by the monotransistor model and transistors that can be correctly simulated by the multi-transistor model. It becomes.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described. This embodiment assumes a thin film transistor, but the idea of the present invention is also effective for a bulk transistor, an SOI (Silicon On Insulator) transistor, and the like.
[0025]
FIG. 8 shows a circuit for performing circuit simulation in this embodiment. This circuit relates to a display with a built-in driver, and assumes a case where circuit simulation of the driver portion and the pixel portion is performed simultaneously. The shift register 21, the buffer 22, and the analog switch 23 are built-in drivers arranged around the display portion. The pixel transistor 24 is disposed in each pixel inside the display portion.
[0026]
As for the thin film transistors existing in the built-in drivers such as the shift register 21, the buffer 22, and the analog switch 23, since a high on-state current is important, a thin film transistor having a relatively short channel (about 4 microns or less) is often used. . In this case, since a kink effect exists, it is necessary to use a monotransistor model. Since the voltage dependency and frequency dependency of the gate insulating film capacitance are not large, it is not necessary to use a multi-transistor model. Therefore, a monotransistor model is used. FIG. 9 shows a monotransistor model. The gate insulating film capacitor is connected between the gate electrode and the source electrode. In these circuits, the potential of the source electrode is fixed or little changed, while the potential of the drain electrode varies following the potential of the gate electrode. Therefore, when the same gate insulating film capacitance is connected, the charge / discharge charge to the gate electrode and the source electrode is larger than the charge / discharge charge between the gate electrode and the drain electrode. Therefore, as in the present embodiment, the gate insulating film capacitance is connected between the gate electrode and the source electrode, so that the charge / discharge current is not underestimated and the design is on the safe side. Note that the gate insulating film capacitor is not connected between the gate electrode and the source electrode, but is connected between the gate electrode and the drain electrode, or between the gate electrode and the source electrode and between the gate electrode and the drain electrode. A part of the idea of the present invention is also effective in the case where a half is connected between the electrodes.
[0027]
Regarding the pixel transistor 24, since it is important to have a small off-state current, a thin film transistor having a relatively long channel (about 4 microns or more) is often used. In this case, since the voltage dependency and frequency dependency of the gate insulating film capacitance are increased, it is necessary to use a multi-transistor model. Since there is no kink effect, there is no need to use a monotransistor model. Therefore, a multi-transistor model is used. The multi-transistor model is as described above (FIG. 1).
[0028]
FIG. 10 shows a comparison between the simulation result of the oscillation frequency of the ring oscillator and the actual measurement value based on the monotransistor effective conductance model. This circuit is different from the circuit shown in FIG. 8, but is sufficient to explain the effect of using the monotransistor model. In the monotransistor model, the oscillation frequency of the ring oscillator and the operation limit frequency of the shift register are lower than the actually measured values. Although it cannot be said that the simulation is completely correct, it is possible to design on the safe side by designing with a monotransistor model.
[Brief description of the drawings]
FIG. 1 shows a multi-transistor model.
FIG. 2 is a diagram showing the operation of a multi-transistor effective conductance model for a long channel transistor.
FIG. 3 is a diagram showing an internal node potential for a long channel transistor.
FIG. 4 is a diagram illustrating an example of voltage dependency and frequency dependency of a gate insulating film capacitance according to a multi-transistor effective conductance model.
FIG. 5 is a diagram showing the operation of a multi-transistor effective conductance model for a short channel transistor.
FIG. 6 is a diagram showing an internal node potential for a short channel transistor.
FIG. 7 shows a comparison between a simulation result of a multi-transistor effective conductance model and an actual measurement value of the oscillation frequency of the ring oscillator.
FIG. 8 is a diagram illustrating a circuit that performs circuit simulation.
FIG. 9 shows a monotransistor model.
FIG. 10 shows a comparison between a simulation result of a monotransistor effective conductance model and an actual measurement value of the oscillation frequency of the ring oscillator.
[Explanation of symbols]
11 Gate electrode 12 Gate insulating film 13 Source electrode 14 Source region 15 Drain electrode 16 Drain region 17 Channel region 18 Subtransistor 19 Gate insulating film capacitance
T1 1st sub-transistor
T2 Second sub-transistor
T3 3rd sub-transistor
T4 4th sub-transistor
T5 5th sub-transistor
V0 0th internal node potential
V1 First internal node potential
V2 Second internal node potential
V3 Third internal node potential
V4 Fourth internal node potential
V5 5th internal node potential
I1 1st sub-transistor current
I2 Second sub-transistor current
I3 3rd sub-transistor current
I4 4th sub-transistor current
I5 5th sub-transistor current 21 Shift register 22 Buffer 23 Analog switch 24 Pixel transistor

Claims (6)

A simulation method of a circuit including a first transistor and a second transistor,
  The channel length of the second transistor is shorter than the channel length of the first transistor, the first transistor does not generate a kink effect, and the second transistor generates a kink effect,
  Reproducing the voltage dependence and frequency dependence of the gate insulating film capacitance of the first transistor using a multi-transistor model for the first transistor;
  Reproducing the internal node potential distribution of the second transistor using a monotransistor model for the second transistor,
  A simulation method characterized by that. The simulation method according to claim 1,
  The multi-transistor model assumes that one transistor is a plurality of sub-transistors connected in series, reads the internal node potential of each of the plurality of sub-transistors, and uses the distribution of each internal node potential Is,
  A simulation method characterized by that. In the simulation method according to claim 1 or 2,
  The first transistor is formed in a pixel portion, and the second transistor is formed in a driver portion;
  A simulation method characterized by that. In the simulation method according to any one of claims 1 to 3,
  The channel length of the first transistor is 4 μm or more.
  A simulation method characterized by that. In the simulation method according to any one of claims 1 to 4,
  The channel length of the second transistor is 4 μm or less.
  A simulation method characterized by that. A circuit including the first transistor and the second transistor is designed using the simulation method according to any one of claims 1 to 5.
  A design method characterized by that.

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