JP4118252B2 - Power semiconductor switching device - Google Patents

Description

  The present invention relates to a power semiconductor switching device, and more particularly to a gate driver that cuts off a high current flowing through a thyristor such as a GCT (gate commutation turn-off) thyristor, a GTO (gate turn-off) thyristor, or an electrostatic induction thyristor (SITH).

  The power semiconductor switching device has a gate driver that turns on and off the thyristor. The gate driver includes a plurality of capacitors connected in parallel and a plurality of switching transistors (MOSFETs) connected in series to the capacitors.

  An example of a prior art power semiconductor switching device comprising a thyristor 211 and a gate driver is shown in FIGS. 17a and 17b. This gate driver includes a capacitor 222 and a MOSFET 223 mounted on a substrate 210. Each capacitor has a capacitance of 220 μF to 2200 μF, and has a cylindrical shape with two terminal wires extending from one end thereof. Therefore, the size of each capacitor is thick, and the height Tc of the capacitor 222 measured from the surface of the substrate 210 is about 15 mm to 20 mm. The height Tt of the thyristor 211 measured from the surface of the substrate 210 is about 15 mm to 20 mm. As described above, the height Tc of the capacitor 222 is substantially the same as the height Tt of the thyristor 211. Such a large capacitor is required to quickly charge the capacitor with sufficient charge to obtain sufficient capacitance to turn off the thyristor 211 quickly. Such a gate driver is disclosed in Patent Document 1 issued on October 27, 2000.

  During operation, the thyristor 211 and the MOSFET 223 generate heat. The temperature of the thyristor rises to a high temperature, for example 100 ° C. For this reason, it is preferable to provide a heat sink above the thyristor 211 where the anode is disposed. When a planar heat sink is provided on the top of the thyristor 211, such a heat sink is disposed very close to the top of the capacitor. Such a heat sink also serves as an electrical connection plate for the anode of the thyristor 211. For this reason, the voltage difference between the heat sink and the capacitor rises as high as several thousand volts. When the distance between the heat sink and the capacitor is short, for example, less than 10 mm, an undesirable discharge occurs between the heat sink and the capacitor, causing serious damage to the power semiconductor switching device. For this reason, an air gap insulation must be provided between the heat sink and the capacitor. In the prior art power semiconductor switching device of FIGS. 17a and 17b, a planar heat sink cannot be provided on the anode of the thyristor. Instead, cup-shaped heat sinks or dish-shaped heat sinks were used.

Another prior art gate driver is disclosed in US Pat. In this document, a capacitor and a MOSFET are provided inside the casing of the thyristor. This faces many tough problems in allocating sufficient total capacitance.
Japanese Patent No. 3124513 European Patent EP 0328778

  Prior art gate drivers have the problem of using large capacitors. When a small capacitor is used, another problem arises that the capacitor cannot be refreshed in a very short time, for example, 100 μs to 200 μs, that is, cannot be charged to a required level. Also, such a large capacitor hindered the thermal convection around the thyristor.

  The present invention solves the above problem by providing a gate driver having a small capacitor, such as a ceramic capacitor, along with a charger that quickly charges the capacitor.

According to the present invention, a power semiconductor switching device comprises:
A power semiconductor switching element housed in a pressure contact type package having an anode, a cathode, and a gate;
Forward bias driver means;
Reverse bias driver means having a plurality of capacitors connected in parallel to each other and a plurality of MOSFETs connected in series between the gate and the capacitor, respectively.
A fast charging circuit for charging the capacitor within a predetermined short time tCmin;
A mounting substrate that supports the power semiconductor switching element, the capacitor, and the MOSFET;
The capacitor and the MOSFET are a thin pulse capacitor and a thin MOSFET, respectively, and the height of the capacitor and the MOSFET measured from a plane defined by the surface of the cathode of the switching element is lower than the height of the power semiconductor switching element. Are arranged around the power semiconductor switching element,
Further, the total capacitance of the capacitor is selected so that the voltage of the capacitor exhibits a voltage drop of 1 V or more during the turn-off of the switching element at the highest specific turn-off current and voltage condition.

  Since a thin pulse capacitor and a thin MOSFET are used, when a planar heat sink is provided on the power semiconductor switching element, a sufficient air gap can be provided between the capacitor and the thin MOSFET.

First Embodiment Referring to FIGS. 1a, 1b, 1c, 1d, and 1e, a power semiconductor switching device according to a first embodiment is shown. This power semiconductor switching device has a mounting substrate 7 on which the power semiconductor switching element 1 is mounted. The power semiconductor switching element 1 is a thyristor such as a GCT (gate commutation turn-off) thyristor, a GTO (gate turn-off) thyristor, or an electrostatic induction thyristor (SITH). The power semiconductor switching element 1 is accommodated in a drum-type pressure contact package. As best illustrated in FIG. 1e, the power semiconductor switching element 1 has an anode 18 at one end, a cathode 19 at the other end, and a gate 20 extending from the center of the package. The total height HGCT of the power semiconductor switching element 1 measured between the anode and the cathode is 22 mm to 27 mm.

  A capacitor 4 and a switching transistor 5 are mounted on the mounting substrate 7 along the periphery of the power semiconductor switching element 1. The switching transistors 5 are preferably arranged in a line along the inner ring, and the capacitors 4 are preferably arranged in a line along one or more outer rings.

  The capacitor 4 is a thin pulse capacitor, preferably a tantalum electrolytic capacitor. Other types of capacitors such as ceramic capacitors and foil capacitors can be used as long as the capacitors are thin. The thin capacitor is small in size, for example, has a height Tc of less than 8 mm, preferably 4 mm, and is preferably a surface mount type. One thin capacitor has a capacitance of 10 μF to 50 μF, and its rated voltage exceeds 20V.

  The switching transistor 5 is also a thin transistor such as a MOSFET. A thin transistor is a transistor having a small size, for example, a height TMOS of less than 8 mm, preferably 4 mm, and more preferably a surface-mount transistor. In the example shown in FIG. 1e, Tc = 4 mm and TMOS = 5 mm.

  In use, the power semiconductor switching device is provided with a planar heat sink 21 attached to the anode 18 of the power semiconductor switching element 1 in order to uniformly remove the heat accumulated in the power semiconductor switching element 1. The heat sink 21 is not indispensable for the power semiconductor switching device when the power semiconductor switching device is manufactured. However, when the power semiconductor switching device is mounted on a power conversion device or the like, the heat sink 21 must be used.

  The planar heat sink 21 is made of metal and serves as an electrical connector for the anode 18 of the switching element 1. A similar sink 116 is attached to the cathode 19 of the power semiconductor switching element 1 for heat removal. The planar heat sink 116 is made of metal and serves as an electrical connector for the cathode 19 of the switching element 1. The distance between the upper surface of the mounting substrate 7 and the upper surface of the heat sink 116 is indicated by HPCB and is from the highest point of the mounted element 4 or 5, the highest point of the transistor 5 in the example of FIG. The distance is indicated by Hoff.

There may be a voltage difference DV of about several thousand volts between the heat sink 21 and the capacitor 4 or the transistor 5. For this reason, it is necessary to provide a sufficient air gap between the heat sink 21 and the capacitor 4 or the transistor 5 whichever is higher. Since the 1.5 mm air gap can block 1000 volts, the air gap height Tt can be calculated by the following equation.
Tt = 1.5 × DV / 1000
The air gap must be about 9.75 mm to block 6500 volts. Therefore, for safety, the air gap Tt must be 10 mm to 15 mm. Tt is the higher measurement distance of the transistor 5 or the capacitor 4 from the surface of the anode 18.

  Referring to FIG. 2a, a circuit diagram of the power semiconductor switching device of the first embodiment is shown. The power semiconductor switching element 1 has an anode 18 and a cathode 19, which are connected to a load (not shown). A plurality of reverse bias driver units 90 are connected in parallel between the gate 20 and the cathode 19 of the power semiconductor switching element 1. One reverse bias driver unit 90 includes a switching transistor 5, a gate resistor 102, and a capacitor 4. The switching transistor 5 has a drain connected to the gate 20 of the switching element 1, a source connected to the capacitor 4, and a gate connected to the gate resistor 102. As shown in FIG. 1d, the capacitor 4 is formed by six thin pulse capacitors 4a, 4b, 4c, 4d, 4e and 4f connected in parallel. The number of thin pulse capacitors included in one reverse bias driver unit is not limited to 6, and any other number may be selected. According to one embodiment, the number of reverse bias driver units 90 is 35 units. Depending on the design, the number of reverse bias driver units can vary, for example, between 5 and 50. Therefore, as is apparent from the above, the reverse bias driver unit includes a plurality of thin pulse capacitors connected in parallel to each other and a plurality of switching transistors 5 connected in series between the gate and the capacitor of the switching element 1, that is, MOSFET. The MOSFETs are connected in parallel to each other to define the MOSFET array 101.

  As shown in FIG. 2a, according to the present invention, the charger 6 is connected to the capacitor 4 of one reverse bias driver unit, and the capacitor 4 is connected for a time tCmin shorter than the minimum time between two successive turn-off points 8,13. Charge. The capacitor 4 of one reverse bias driver unit is connected in parallel with the capacitor 4 of another reverse bias driver unit. For this reason, all capacitors 4 are connected in parallel to form an array 100 of capacitors connected between lines 111 and 112. The charger 6 charges all the capacitors 4 connected in parallel at the same time for a short time tCmin. The charger 6 is further connected to an external power source. Details of the charger 6 will be described later.

  As shown in FIG. 2 a, the forward bias driver 2 including the pre-driver generates a control signal that turns the switching element 1 on and off via lines 104 and 103. The line 104 is connected to the gate of the switching element 1, and the line 103 is connected to each gate / resistor 102 and then to the gate of the switching transistor 5. Power for forward bias driver 2 is supplied from charger 6 via line 106. Control information 105 is added to the forward bias driver 2 to control the timing for generating the control signal.

  Referring to FIG. 1 a, the forward bias driver 2 and the charger 6 are provided at positions away from the switching element 1 on the mounting substrate 7. The circuit connection as shown in FIG. 2a is achieved by a multilayer circuit provided in the mounting substrate 7 as shown in FIG. 1e.

  The operation of this power semiconductor switching device will be described with reference to FIGS. 2b, 2c and 2d.

  It is assumed that switching element 1, that is, GCT is on at time t0, and capacitor 4 is fully charged to a predetermined voltage VC. At time ta, the turn-off signal is generated by the forward bias driver 2, and this signal is applied to the gate of the MOSFET 5 through the line 103 and the resistor 102. For this reason, all the MOSFETs 5 are turned on to supply the discharge current IG from the capacitor 4 to the gate of the switching element 1. Therefore, at time ta, the turn-off pulse 9 (FIG. 2c) is observed at the gate of the switching element 1, and the capacitor 4 is discharged as shown by the voltage drop 10 (FIG. 2d). Therefore, the GCT is turned off as indicated by the descending line 8 at time ta. Thereafter, since the charger 6 supplies a charging current, the capacitor 4 is rapidly charged to a predetermined voltage VC within a predetermined time tCmin from the time ta as indicated by the voltage increase 11 and the saturation 12.

  At time tb, a turn-on signal is generated by the forward bias driver 2 and applied to the gate of GCT 1 via line 104. For this reason, GCT1 is turned on again.

  At time tc, a second turn-off signal is generated to turn off the GCT as described above. Note that the time difference between the two continuous turn-off signals from the forward bias driver 2, for example, between the two turn-off pulses 9 and 14 varies depending on the control information 105, but is set to be equal to or greater than tCmin.

  The fast charger 6 is designed to reach the end 12 of the first pulse capacitor voltage reset process before the demand for the second turn-off switching 13 occurs. In this way, the fast charger 6 can definitely charge the capacitor 4 before the next turn-off switching request occurs. By using such a charger 6, the turn-off of the power semiconductor switching element 1 is definitely achieved even though the total capacitance of the thin capacitor 4 is small.

  According to the present invention, any type of thin MOSFET 5 and thin pulse capacitor 4 may be provided around the power semiconductor switching element 1. Since the number of MOSFETs 5 is smaller than that of the capacitor 4, the thin MOSFET 5 suffices to have a smaller space than the thin pulse capacitor 4. Therefore, as shown in FIGS. 1a and 1d, the elements 4 and 5 are arranged in concentric rings, the thin MOSFET 5 is located in the inner ring, and the thin pulse capacitor 4 is located in one or more outer rings. Yes.

  Since a thin pulse capacitor and a thin MOSFET are used, when a planar heat sink is provided on the power semiconductor switching element, a sufficient air gap can be provided in the entire capacitor and the thin MOSFET. This avoids unwanted discharge between the heat sink and the capacitor or MOSFET.

Second Embodiment The power semiconductor switching device can be mounted on various types of power semiconductor switching circuits, such as a DC chopper, a current source inverter, and a voltage source inverter. The time tCmin is shorter than the minimum time between two successive turn-off points 8 and 13, but if so, it is strongly dependent on the control algorithm of such an electronic circuit.

  For example, in DC choppers and current source inverters, the rate of increase of the anode current is such that the anode current can definitely be maintained below the rated turn-off capability of the power semiconductor switching device when it is regularly turned on and off at a constant switching frequency. May be limited. In such a case, as is apparent from FIG. 2b, tCmin may be set to a value equal to or less than tCmin = 1 / switching frequency.

  In contrast, in the voltage source inverter, there is no such strong limit on the rate of increase of the anode current. As a result, in the event of a sudden load short circuit, the voltage source inverter controller should generate a turn-off command in a very short time after a regular turn-off operation to protect the converter. In such a case, tCmin may be set to 500 μs or less, preferably 50 μs to 200 μs. Thus, according to the present invention, the charger 6 can charge the capacitor 4 with the predetermined voltage VC within tCmin, that is, within 500 μs.

  Therefore, the second embodiment is suitable for application in voltage source inverters and circuits having similar timing requirements.

Third Embodiment Referring to FIGS. 3a, 3b and 3c, a third embodiment of a power semiconductor switching device is shown. In FIGS. 1a, 1b and 1c, a thin tantalum electrolytic capacitor 4 is used, but in FIGS. 3a, 3b and 3c, a ceramic multilayer large capacity capacitor 22 is used.

  Such ceramic capacitors have a long life and withstand high temperatures. For this reason, the third embodiment of the power semiconductor switching device has high stability.

Fourth Embodiment Referring to FIGS. 4a, 4b, 4c, 4d, 4e and 4f, a fourth embodiment of a power semiconductor switching device is shown. In the fourth embodiment, the thin MOSFET 5 is mounted on the upper side of the mounting substrate 7, while the thin pulse capacitor 4 is mounted on the lower side of the substrate.

  This arrangement saves space. In addition, the parasitic inductance of the gate circuit is reduced. The drain of the thin MOSFET 5 on the upper side of the substrate can be directly connected to the gate of the power semiconductor switching element 1, the thin pulse capacitor can be directly connected to the cathode of the switching element 1, and the thin pulse capacitor 4 By connecting the source of the thin MOSFET 5 with the through hole in the substrate 7, this loop is closed.

Fifth Embodiment Referring to FIGS. 5a, 5b, 5c and 5d, a fifth embodiment of a power semiconductor switching device is shown. In the fifth embodiment, the energy storage means 23 is connected between the input lines 17 of the charger 6.

  As shown in FIG. 5b, GCT1 is turned off three times as indicated by lines 8, 13 and 24. The time between lines 8 and 13 can be tCmin and the time between lines 13 and 24 can be tCmin. Such a quick turn-off repeats to protect the converter from a sudden short circuit of the load. When the sudden load short circuit is restored, the next turn-off of GCT1 can occur in a longer time, eg, 1 ms from line 24.

  As is apparent from the above, the energy storage means 23 can maintain at least three full charge cycles 8, 13 and 24 with each cycle time being as short as tCmin. In this case, the power supply (not shown) connected to the charger 6 need only have sufficient output power to charge the capacitor 4 with a regular charging time, also called average switching cycle time tCav, which is 1 ms to 4 ms. .

  Since the energy storage means 23 is provided in the fifth embodiment, the charger 6 can instantaneously distribute power. For this reason, the capacitor 4 is reliably charged many times, for example, three times repeatedly at the minimum time tCmin. Can do.

Sixth Embodiment Referring to FIGS. 6a, 6b, 6c and 6d, a sixth embodiment of a power semiconductor switching device is shown. In this embodiment, details of the charger 6 will be described.

  As shown in FIG. 6 a, charger 6 includes a voltage regulator controller 30 connected between line 17 and transistor 29. Regulator controller 30 and transistor 29 constitute a high current, low dropout linear regulator. Using transistor 29 and regulator controller 30, the starting voltage VES of energy storage means 23 (shown by line 31) is significantly higher than the starting voltage VC of thin pulse capacitor 4 (shown by line 32). As a result, a sufficient dI / dt of the parasitic inductance of a circuit (not shown) is generated, and a sufficient voltage difference is maintained to ensure fast charging of the thin pulse capacitor 4.

  According to the sixth embodiment of the power semiconductor switching device, the charger 6 can be formed with a simple circuit. For this reason, a power semiconductor switching device can be produced cost-effectively.

Seventh Embodiment Referring to FIGS. 7a, 7b, 7c and 7d, a seventh embodiment of a power semiconductor switching device is shown. In this embodiment, the charger 6 is modified.

  As shown in FIG. 7 a, the charger 6 is a high-speed type that includes a boost inductor 33, a boost switching transistor 34, a boost diode 35, a current sensing resistor 113, and a boost converter controller 114. It is formed by a boost converter (boost converter). The boost inductor 33 and boost diode 35 are connected in series on one of the lines 17 and the boost switching transistor 34 is connected between the lines 17. The boost converter controller 114 detects the current flowing through the current sensing resistor 113 and supplies a switching signal to the transistor 34 to control the boosted voltage.

  A high speed boost converter, also known as a high current boost type chopper, allows the input voltage VES to be below the output voltage VC as shown in FIG. 7d. Sufficient energy is stored in the energy storage means 23. For this reason, even after three consecutive turn-off operations 8, 13 and 24 having a minimum time tCmin between the turn-off operations, the energy storage means 23 is positively shown by the line 36 after the third boost reset operation indicated by the lines 26 and 27. Voltage still remains.

  Loss can be reduced by the fast boost converter of FIG. For this reason, a circuit element is not heated highly and the lifetime of a circuit element can be extended.

Eighth Embodiment Referring to FIGS. 8a, 8b, 8c and 8d, an eighth embodiment of a power semiconductor switching device is shown. In this embodiment, the charger 6 is further modified.

  As shown in FIG. 8a, the charger 6 is formed by a buck converter (step-down converter) also known as a buck-type chopper. The buck converter includes a buck switching transistor 38, a buck diode 39, a buck inductor 40, and a buck switching control unit 37. The back switching transistor 38 and the back inductor 40 are connected in series on one of the lines 17, and the back diode 39 is connected to the cathode bus 112 and the inductor 40. The back switching control unit 37 detects a voltage difference between the source bus 111 and the cathode bus 112 and a current flowing through the back switching transistor 38 and the back inductor 40 and supplies a switching signal to the transistor 38. .

  The energy storage means 23 is selected so that the voltage of the energy storage means 23 remains higher than the voltage level of the thin pulse capacitor 4 even after the third back reset operation indicated by the lines 26 and 27.

  With the embodiment of FIGS. 8a-8d, three continuous turn-off processes can be performed.

Ninth Embodiment Referring to FIGS. 9a, 9b, 9c, 9d and 9e, a ninth embodiment of a power semiconductor switching device is shown. In this embodiment, the charger 6 is further modified.

  The charger 6 shown in FIG. 9 a is similar to that shown in FIG. 8 a, but further includes a current sensing resistor 42 inserted in series with the inductor 40. The current flowing through the current sensing resistor 42 is monitored by the back timing current controller 115. The back timing current controller 115 is provided with a timer. Other configurations are the same as those shown in FIG. 8a.

  Since the buck converter operates in continuous mode, it may be preferable to apply a current controller. In this embodiment, current detection is performed by the current sensing resistor 42 applicable to high-speed current change.

  By using the current sensing resistor 42, a chopper current control unit using bang-bang control becomes possible. However, the fast charger 6 according to the present embodiment is capable of controlling a current exceeding 100 A and an off time of the back switching transistor shorter than 1 μs. For this reason, simple bang-bang control faces challenges. Such a problem is solved in a reliable manner by the operation mode of the ninth embodiment.

  This operation is illustrated in Figures 9b-9e. The first pulse capacitor discharge 10 initiates a first switching cycle at 43. The inductor current IL flowing through the inductor 40 rises, and the voltage V (RS) across the resistor 42 rises. As soon as the voltage V (RS) reaches the predetermined level V1, the buck switching transistor 38 is turned off and IL is redirected to the buck diode 39. Eventually IL falls.

  At the first turn-off 44, a timer is started to start a second switching cycle after a predetermined time 46. The predetermined time 46 is an off time when the charging of the capacitor 4 is cut off. In this way, the capacitor is charged by the breaking current. This process is then repeated until the end of the first pulse capacitor voltage reset process at time 12.

  In this embodiment, since the charging current is detected in the charger 6, charging can be executed with high accuracy.

Tenth Embodiment Referring to FIGS. 10a, 10b, 10c and 10d, a tenth embodiment of a power semiconductor switching device is shown. In this embodiment, the charger 6 is modified.

  The charger 6 shown in FIG. 10 a is the same as that shown in FIG. 8 a except that a fixed timing controller 47 is provided instead of the back switching control unit 37. The fixed timing controller 47 measures an on-time time 49 and an off-time time 50. Other configurations are the same as those shown in FIG. 8a.

  A rapid comparator is required to reach the voltage level V1 (FIG. 9e). High speed operation limits the sensitivity of this type of comparator. Therefore, the voltage V1 must be set to a very high level, for example, V1 = 100 mV. In a state involving a large current, the current sensing resistor 42 (FIG. 9a) causes a large amount of loss. For this reason, the current sensing resistor is not provided in the tenth embodiment.

  According to the tenth embodiment, the fixed timing controller 47 controls both the on-time time 49 and the off-time time 50. Each of the on-time times is a time during which the charging current IL increases, and the off-time time is a time during which the charging current IL decreases or stays until it becomes equal to zero. After the first discharge 10 of the pulse capacitor 4, the fixed timing controller 47 begins to apply the ON signal to the back switching transistor 38 for the ON time time 49. In this way, the first charging pulse 48 is generated. The peak current 52 of the first charging pulse 48 is given by the value of the buck inductor 40. The voltage difference VES−VC during the first charging pulse time, ie during the on-time time 49, is approximately equal to the amount indicated by the arrow 51. The voltage difference VES−VC is a difference between the input voltage VES to the charger 6 and the output voltage VC of the charger 6.

  The value of the peak current 52 of the first charging pulse is selected in response to a voltage reset indicated by the line 11 of the capacitor 4.

  After the on-time time 49, when the fixed timing controller 47 turns off the buck switching transistor 38, the off-time time 50 starts simultaneously. The off-time time 50 is selected such that during that time 50 the current IL can be reduced to zero. Eventually, the discontinuous switching mode is guaranteed, and the capacitor 4 is charged by the breaking current. The second charging pulse 53 can then start from IL = 0.

  After finishing off-time period 50, fixed timing controller 47 initiates second charge pulse 53 by turning on back switching transistor 38 during on-time period 49. The peak current 55 of the second charging pulse is given by the value of the buck inductor 40. The voltage difference VES-VC during the second charging pulse time, ie during the on-time time 49, is approximately equal to the amount indicated by the arrow 54.

  Since the value of VES decreases compared with the value in the first charging pulse 48 and the voltage VC increases, the voltage difference VES−VC in the second charging pulse (arrow 54) is equal to the first charging pulse (arrow). 51) smaller than the voltage difference. As a result, the peak current 55 of the second charge pulse is smaller than the peak current 52 of the first charge pulse. This charging of the capacitor 4 is completed at time 12.

  According to the present embodiment, since a resistor such as the resistor 42 in FIG. 9a is not used, power loss in the charger 6 can be improved.

Eleventh Embodiment Referring to FIGS. 11a, 11b, 11c and 11d, an eleventh embodiment of a power semiconductor switching device is shown. In this embodiment, the charger 6 is modified.

  The charger 6 in FIG. 11 a is the same as that in FIG. 10 a except that a voltage control timing controller 56 is provided instead of the fixed timing controller 47. Other configurations are the same as those shown in FIG. 10a.

According to the tenth embodiment, in order to achieve fast charging, the maximum to minimum ratio of voltage difference VES-VC must be kept below a certain rate. For example, according to the tenth embodiment, the following condition must be satisfied.
Maximum (VES-VC) / Minimum (VES-VC) ≦ 2
Therefore, in the tenth embodiment, only a narrow range of VES and VC can be handled satisfactorily.

In the eleventh embodiment, the voltage control timing controller 56 monitors the voltage difference VES−VC. The on-time time ton is approximately equal to the reciprocal of the voltage difference VES-VC as given by the following function.
ton≈k1 × 1 / (VES-VC)
Here, k1 is a constant.

As a result, the on-time time ton1 of the first charging pulse is shorter than the on-time time ton2 of the second charging pulse. The on-time time ton5 of the last charge pulse of the first pulse capacitor voltage reset becomes the longest. The relationship is as follows.
ton1 <ton2 <ton3 <ton4 <ton5

On the other hand, the current rise rate dIL / dt during the on-time period is basically basically that the voltage drop at the back switching transistor 38 is generally much smaller than VES-VC in order to keep the loss small. It is directly proportional to VES-VC. The peak current of each pulse is expressed as Ipeak = dIL / dt × ton
Can be calculated.

For this reason, the peak current Ipeak of all the charging pulses is maintained at the same value as shown below.
Peak current 60 of the first charging pulse
≒ Peak current 64 of second charge pulse
≒ Peak current 68 of the final charge pulse

  According to this embodiment, the charger 6 can supply a wide range of input voltages with low loss.

Twelfth Embodiment Referring to FIGS. 12a and 12b, a twelfth embodiment of power semiconductor switching is shown. In this embodiment, the charger 6 and the energy storage means 23 are provided in separate compartments 69 and 70, respectively.

  The section 69 including the charger 6 is fixed on the mounting substrate 7, but the energy storage means 23, that is, the section 70 including one or more capacitors, is detachably mounted on the mounting substrate 7.

  Compartment 70 may include electrolytic capacitors or other types of capacitors for charge storage. Such capacitors have a limited lifetime. After a certain operating time, the compartment 70 with the capacitor 23 can be easily replaced without affecting the power semiconductor switching element 1 and other elements during normal maintenance.

  The compartment 70 may be disposed adjacent to the compartment 69 on the same mounting substrate 7 or may be disposed outside the mounting substrate 7 as shown in FIGS. 13a and 13b.

  According to this embodiment, the capacitor in the energy storage means 23 can be easily replaced.

Thirteenth Embodiment Referring to FIGS. 14a, 14b and 14c, a thirteenth embodiment of a power semiconductor switching device is shown. In this embodiment, the array of thin MOSFETs 5 connected to the resistor 102 is divided into two halves 72 and 74. The first half array 72 is arranged in a line along the first semicircle around the power semiconductor switching element 1, and the second half array 74 is arranged in a line along the second semicircle around the same. It is out. The pre-driver included in the forward bias driver 2 is taken out from the section of the forward bias driver 2 and provided at the end of each half. A pre-driver 71 for the first half array 72 and a pre-driver 73 for the second half array 74 are provided on the substrate 7 along opposite sides.

  This embodiment reduces the capacitive load on the pre-driver to 50% and reduces the length of the low inductance gate connection by about 50%. Further, simultaneous driving of all MOSFETs and homogeneous turn-off driving of the power semiconductor switching element 1 can be realized.

Fourteenth Embodiment Referring to FIGS. 15a, 15b, 15c, 15d and 15e, a fourteenth embodiment of a power semiconductor switching device is shown, which is a modification of the thirteenth embodiment. A screw-in type GCT1 is employed. The mounting substrate 7 has a hole for accommodating the screw-in type GCT 1. The gate ring 77 and the cathode ring 76 are fixed to the gate and the cathode of GCT1, respectively. A ring cutting portion 78 extending in the radial direction is formed around the cathode ring 77. A ring cutting portion 78 extending in the radial direction is formed around the gate ring 76.

  The mounting substrate 7 is formed with a cutting portion 79 extending from the hole to the edge of the mounting substrate 7. Such a cut 79 is possible because the array of thin MOSFETs and thin pulse capacitors is divided into a first half array 72 and a second half array 74.

  A hole formed in the mounting substrate 7 to accommodate the GCT 1 is sized to fit the screw portion. Since the mounting substrate 7 has the cutting portion 79 and the gate ring and the cathode ring have the cutting portion 78, the cutting edge portion of the cathode ring 76 is slid under the mounting substrate 7 through the cutting edge portion of the mounting substrate 7. The GCT 1 can be screwed into the hole of the mounting board 7 by rotating the GCT 360 degrees.

  According to this embodiment, the power semiconductor switching element, that is, the GCT can be easily mounted.

Fifteenth Embodiment Referring to FIG. 16, a fifteenth embodiment of a power semiconductor switching device is shown. In this embodiment, the forward bias driver 2 and the high-speed charger 6 are mounted on a mounting board 80 that is separated from the mounting board 7 on which the GCT 1 and the reverse bias driver unit 90 are mounted. A low impedance connection 81 is provided for connecting the two substrates.

  According to this embodiment, the forward bias driver 2 and / or the fast charger 6 can be easily replaced. Further, very few elements are directly connected to the power semiconductor switching element 1. Also, these elements can be designed very reliably.

In any of the above-described embodiments, the power semiconductor switching element 1 such as GCT has at least one of the following characteristics.
1) The rated current ITGQM of GCT is 4 kA or 6 kA or more.
2) During GCT turn-off, the gate peak current IGpeak is IGpeak ≧ 1.1 × ITGQM.
3) The charging rate QG through the gate is 2.5 μC / A × ITGQ or more.
4) The gate driver can be turned off at least three times at the maximum allowable pulse frequency with the rated current ITGQM. This means that the total ΔVC ≦ 1V.
5) The GCT can accommodate a planar heat sink.
6) The gate current change dIG / dt immediately after the start of the gate current IG is dIG / dt ≧ 2 × ITGQM / 500 ns, where ITGQM is the rated anode turn-off current of the GCT.
7) The resistance element of the gate driver composed mainly of the resistance of the capacitor and the resistance of the MOSFET, Rternal, is 2 V / Ipeak or less.
8) Circuit heterogeneity of turn-off current is less than ± 5%.
9) The lifetime of GCT exceeds 20 years at a temperature of 50 ° C.

  The present invention is applicable to a power semiconductor switching device.

1 is a plan view showing the structure and arrangement of a power semiconductor switching device according to a first embodiment of the present invention. 1b is a side view of the power semiconductor switching device shown in FIG. 1b is an enlarged partial side view of the power semiconductor switching device shown in FIG. It is a partial top view which shows an example of one reverse bias driver unit. It is sectional drawing of the part shown to FIG. 2a is a circuit diagram of the power semiconductor switching device according to the first embodiment of the present invention, FIG. 2b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching device of FIG. 2a, and FIG. 2a is a timing chart showing a gate current of the power semiconductor switching element of FIG. 2a, and FIG. 2d is a timing chart showing discharging and charging of the pulse capacitor of FIG. 2a. It is a top view which shows the structure and arrangement | positioning of the power semiconductor switching device by the 3rd Embodiment of this invention. FIG. 3b is a side view of the power semiconductor switching device shown in FIG. 3a. FIG. 3b is an enlarged partial side view of the power semiconductor switching device shown in FIG. 3a. It is a top view which shows the structure and arrangement | positioning of the power semiconductor switching device by the 4th Embodiment of this invention. FIG. 4b is a side view of the power semiconductor switching device shown in FIG. 4a. FIG. 4b is an enlarged partial side view of the power semiconductor switching device shown in FIG. 4a. It is a partial top view of one reverse bias driver unit. 4d is a cross-sectional view of the portion shown in FIG. 4d. FIG. 4d is a bottom view of the portion shown in FIG. 4d. FIG. 5a is a circuit diagram according to a fifth embodiment of the present invention, FIG. 5b is a timing chart showing turn-on and turn-off states of the power semiconductor switching element of FIG. 5a, and FIG. 5c is a power semiconductor of FIG. FIG. 5d is a timing chart showing the discharge and charging of the pulse capacitor of FIG. 5a. 6a is a circuit diagram according to a sixth embodiment of the present invention, FIG. 6b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching element of FIG. 6a, and FIG. 6c is the power semiconductor of FIG. 6a. FIG. 6D is a timing chart showing the discharge and charging of the pulse capacitor of FIG. 6A. 7a is a circuit diagram according to a seventh embodiment of the present invention, FIG. 7b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching element of FIG. 7a, and FIG. 7c is the power semiconductor of FIG. 7a. FIG. 7d is a timing chart showing the discharging and charging of the pulse capacitor of FIG. 7a. 8a is a circuit diagram according to an eighth embodiment of the present invention, FIG. 8b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching element of FIG. 8a, and FIG. 8c is the power semiconductor of FIG. 8a. FIG. 8d is a timing chart showing the gate current of the switching element, and FIG. 8d is a timing chart showing discharging and charging of the pulse capacitor of FIG. 8a. 9a is a circuit diagram according to a ninth embodiment of the present invention, FIG. 9b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching element of FIG. 9a, and FIG. 9c is the charger of FIG. 9a. FIG. 9d is a timing chart showing the inductor current flowing through the inductor in the charger of FIG. 9a, and FIG. 9e is the both ends of the resistance in the charger of FIG. 9a. It is a timing chart which shows the voltage of. FIG. 10a is a circuit diagram according to a tenth embodiment of the present invention, FIG. 10b is a timing chart showing turn-on and turn-off states of the power semiconductor switching element of FIG. 10a, and FIG. 10c is a charger of FIG. 10a. FIG. 10d is a timing chart showing the inductor current flowing through the inductor in the charger of FIG. 10a. 11a is a circuit diagram according to an eleventh embodiment of the present invention, FIG. 11b is a timing chart showing the turn-on and turn-off states of the power semiconductor switching element of FIG. 11a, and FIG. 11c is the charger of FIG. 11a. FIG. 11d is a timing chart showing the voltage difference between the input and output of the charger of FIG. 11a, and FIG. 11e is an inductor in the charger of FIG. 11a. 6 is a timing chart showing the inductor current flowing through. It is a top view which shows arrangement | positioning of the power semiconductor switching device by the 12th Embodiment of this invention. FIG. 12b is a side view of the power semiconductor switching device shown in FIG. 12a. It is a top view which shows arrangement | positioning of the power semiconductor switching device by the modification of the 12th Embodiment of this invention. FIG. 13b is a side view of the power semiconductor switching device shown in FIG. 13a. It is a top view which shows arrangement | positioning of the power semiconductor switching device by the 13th Embodiment of this invention. FIG. 14b is a side view of the power semiconductor switching device shown in FIG. 14a. It is a circuit diagram of the power semiconductor switching device by the 13th Embodiment of this invention. It is a top view which shows the power switching element in the screwed-type housing | casing by the 14th Embodiment of this invention. FIG. 15b is a side view of the power switching element shown in FIG. 15a. FIG. 15b is an enlarged partial side view of the power switching element shown in FIG. 15a. It is a top view which shows the power semiconductor switching device of the 14th Embodiment of this invention without a power switching element. It is a top view which shows the power semiconductor switching device of the 14th Embodiment of this invention which inserted the power switching element. It is a top view which shows the electric power semiconductor switching device by 15th Embodiment of this invention. 1 is a prior art power semiconductor switching device.

Explanation of symbols

1: Power semiconductor switching element 2: Forward bias drive circuit and control unit 3: Reverse bias drive circuit 4: Thin pulse capacitor 5: Thin MOSFET
6: Fast charging circuit 7: Mounting board 8: First turn-off switching time point 9: First turn-off gate current pulse 10: First pulse capacitor discharge 11: First pulse capacitor voltage reset 12: First pulse End of capacitor voltage reset process 13: Second turn-off switching time point 14: Second turn-off gate current pulse 15: Second pulse capacitor discharge 16: Second pulse capacitor voltage reset 17: Charger power supply connection 18: Anode Terminal 19: Cathode terminal 20: Gate terminal 21: Edge of heat sink 22: Ceramic multilayer large capacity capacitor 23: Energy storage means 24: Third turn-off switching time point 25: Third turn-off gate current pulse 26: Third pulse Capacitor discharge 27: No. 3 pulse capacitor voltage reset 28: Pulse capacitor voltage after third reset 29: Transistor 30: Regulator 31: Starting voltage of energy storage means 32: Starting voltage of thin pulse capacitor 33: Boost inductor 34: Boost switching Transistor 35: Boost diode 36: Voltage of energy storage after the third boost reset operation 37: Buck switching control unit 38: Buck switching transistor 39: Buck diode 40: Buck inductor 41: Third Energy storage voltage after back reset operation 42: Current sensing resistor 43: Start of first switching cycle 44: First turn-off 45: Zero inductor current 46: Default time 47: Fixed timing control -48: First charging pulse 49: On time 50: Off time 51: VES-VC in the first charging pulse
52: Peak current of the first charging pulse 53: Second charging pulse 54: VES-VC in the second charging pulse
55: Peak current of the second charging pulse 56: Voltage control timing controller 57: First charging pulse 58: VES-VC in the first charging pulse
59: On-time of the first charging pulse 60: Peak current of the first charging pulse 61: Second charging pulse 62: VES-VC in the second charging pulse
63: On-time of the second charge pulse 64: Peak current of the second charge pulse 65: Final charge pulse of the first pulse capacitor voltage reset 66: VES-VC at the final charge pulse
67: Final charge pulse on-time 68: Peak current of final charge pulse 69: Charge converter 70: Input capacitor bank 71: Left pre-driver 72: Left MOSFET half circle 73: Right pre-driver 74: Right MOSFET half circle 75: Screwing Power semiconductor element 76: cathode ring 77: gate ring 78: ring cutting part 79: mounting board cutting part 80: second mounting board 81: low impedance connection 90: reverse bias driver unit 100: pulse capacitor bank 101: MOSFET bank 102: MOSFET gate resistance 103: MOSFET gate bus 104: Forward bias output 105: Control unit input 106: Voltage power supply line 107, 107a: Cathode contact via 108, 108a, 108b: Source bus contact Via 109: MOSFET gate bus contact via 110: Cathode connection plate 111: Source bus 112: Cathode bus 113: Current sensing resistor 114: Boost converter controller 115: Back timing current controller 210: Substrate 211: Thyristor 222: Capacitor 223: MOSFET

Claims (17)

A power semiconductor switching element (1) housed in a pressure contact type package having an anode, a cathode, and a gate;
Forward bias driver means (2) for turning on the power semiconductor switching element;
Reverse bias driver means (3) for turning off the power semiconductor switching element, comprising a plurality of capacitors (4) connected in parallel to each other and a plurality of MOSFETs connected in series between the gate and the capacitors, respectively; ,
Charger means for charging the pre-Symbol capacitor (6),
A mounting substrate (7) that supports the power semiconductor switching element, the capacitor, and the MOSFET;
Wherein said capacitor MOSFET, together with a thin pulse capacitors and thin MOSFET respectively, the height of the capacitor and MOSFET measured from the plane defined by the surface of the cathode of the power semiconductor switching devices than the height of the power semiconductor switching devices Arranged around the power semiconductor switching element to be low ,
Further, the total capacitance of the capacitor, the voltage of the capacitor after the turn-off of the power semiconductor switching element is configured as shown above the voltage drop 1V,
The charger means starts the supply of a charging current to the capacitor after the power semiconductor switching element is turned off, and charges the capacitor for the voltage drop within a predetermined short time tCmin. apparatus.

  The power semiconductor switching device according to claim 1, wherein the predetermined short time tCmin is 500 μs or less.   The power semiconductor switching device according to claim 1, wherein the predetermined short time tCmin is 50 μs to 200 μs.   The thin pulse capacitor and the thin MOSFET are arranged in an array concentrically around the power semiconductor switching element so that the thin MOSFET is arranged in an inner ring and the thin pulse capacitor is arranged in an outer ring. The power semiconductor switching device according to claim 1.   The power semiconductor switching device according to claim 1, wherein the thin pulse capacitor is a ceramic multilayer capacitor.   The power semiconductor switching device according to claim 1, wherein the thin pulse capacitor is disposed on one side of the mounting substrate, and the thin MOSFET is disposed on the other side of the mounting substrate.   The power semiconductor switching device according to claim 1, further comprising energy storage means (23) connected to the charger means.   The power semiconductor switching device according to claim 1, wherein the charger means comprises a high current low dropout linear regulator (29, 30).   The power semiconductor switching device according to claim 1, wherein the charger means comprises a boost converter (113, 114, 33, 34, 35).   2. The power semiconductor switching device according to claim 1, wherein the charger means comprises a buck converter (38, 39, 40, 42).   11. The power semiconductor switching device of claim 10, wherein the buck converter includes a current sensing resistor (42) and a timer (115) that times off time (46).   11. The power semiconductor switching device according to claim 10, wherein the buck converter includes a timer (47) for timing an on-time time (49) and an off-time time (50).   13. The on-time time is set in inverse proportion to a voltage difference (VES-VC) between an input voltage (VES) to the charger means and an output voltage of the charger means. Power semiconductor switching device.   The power semiconductor switching device according to claim 7, wherein the energy storage unit is detachably provided on a mounting board.   The array of thin MOSFETs and thin pulse capacitors is divided into a first half array (72) and a second half array (74), and the first half array includes a first pre-driver (71). The power semiconductor switching device according to claim 4, wherein a second pre-driver (73) is provided in the second half array.   The power semiconductor switching device according to claim 15, wherein the mounting board has a hole and a cut portion extending from the hole to an edge of the mounting board. The power semiconductor switching device according to claim 1, wherein the forward bias driver means (2) and the charger means (6) are mounted on a mounting board (80) remote from the mounting board (7).

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