JP4111304B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dynamic memory and a semiconductor device using the dynamic memory, and particularly provides a dynamic memory suitable for high-speed and low-power applications and a semiconductor device using the dynamic memory.
[0002]
[Prior art]
The operation waveform of a conventional dynamic memory (hereinafter referred to as DRAM) in which information is stored by a memory cell consisting of one NMOS transistor and one capacitor is, for example, written by Kiyoo Ito, "Ultra LSI Memory", Bafukan, p86 As described, it operates as in FIG. That is, during a read operation, the word line WL is asserted to read a signal from the memory cell to the bit lines BL and / BL, and then the sense amplifier is activated at a predetermined time φA to amplify the bit line signal. As a result, the data is fixedly output after the row address access time (tRAC) from the start of access. Further, it takes time until tRAS for rewriting to the memory cell, and then a precharge time (tRP) is required as a precharge time for the bit line and the like.
[0003]
On the other hand, the write operation is basically the same as the read operation, but the data of the selected memory cell is driven by driving the bit line in accordance with the write data after the sense amplifier is driven.
[0004]
Further, these dynamic memories require a refresh operation in order to hold information in the memory cells.
[0005]
[Problems to be solved by the invention]
In the above conventional dynamic memory,
(1) During a read operation, the amplitude of the bit line must be increased in order to rewrite to the memory cell. This increases the cycle time (tRC) represented by tRAS + tRP.
[0006]
(2) During the write operation, the non-selected memory cell needs to perform the same operation as the read operation, so that the write cycle time tRC also becomes longer as in the read operation.
[0007]
(3) When the dynamic memory is completely pipelined for the above (1) and (2), the pipeline pitch becomes long.
[0008]
(4) Because refresh is necessary, contention occurs between access to dynamic memory other than refresh (external access) and access for refresh, resulting in performance degradation.
[0009]
The problem arises.
[0010]
[Means for Solving the Problems]
The main means used in the present invention to solve the above problems are as follows. That is, in a semiconductor device, a memory circuit including a plurality of memory cells provided at intersections of a plurality of bit lines and a plurality of word lines, and for instructing the memory circuit to perform either reading or writing Internal command for instructing the memory circuit to read or write at the change point of the second clock having a frequency higher than that of the first clock. And an access control circuit for supplying to the memory circuit as an internal address, wherein the access control circuit is configured to change the second clock at a change point of the second clock at a timing when the external command and the external address are not supplied. A refresh control circuit for performing a refresh operation of the memory cell is further included.
[0011]
With the above configuration, the memory circuit can conceal the refresh operation from the outside because the refresh operation can be performed as an internal operation separated from the external control even if a memory cell that needs to be refreshed is used.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings. The circuit elements constituting each block in the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). The circuit symbols of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that do not have a circle on the gate represent N-type MOSFETs (NMOS), and are distinguished from P-type MOSFETs (PMOS) that have a circle on the gate. Hereinafter, in order to call a MOSFET, it will be simplified and called a MOS or a MOS transistor. However, the present invention is not limited to a field effect transistor including an oxide film insulating film provided between a metal gate and a semiconductor layer, and a general FET such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used. Applied to the circuit.
[0013]
Note that the meaning of a latch and a flip-flop or register is strictly different, but here they are represented as a latch unless otherwise specified.
[0014]
<Example 1>
FIG. 1 shows a typical embodiment of the present invention. The memory device of the present invention includes a dynamic memory 100 and a cache memory 110. 111 in the cache memory 110 indicates a valid bit, and 112 and 113 indicate the address and data of each entry in the cache memory. Reference numeral 114 denotes a bus connected to the cache memory 110, 115 denotes a bus connected to the dynamic memory 100, and 116 denotes a bus controller thereof.
[0015]
The dynamic memory 100 performs an operation as shown in FIG. That is, at the time of read operation, the sense amplifier is activated with φA after asserting the word line WL. As a result, data DO is output after tRAC from the input of the address. At this time, unlike the conventional dynamic memory, the rewrite operation of amplifying the read signal to the bit line and writing to the memory cell is not performed.
[0016]
Therefore, it is not necessary to amplify data to the bit lines BL and / BL as in the prior art, and the power required for charging and discharging the bit lines can be reduced. Further, no time corresponding to the conventional tRAS shown in FIG. Although tRP is required as a precharge time for the bit line or the like, since the bit lines BL and / BL remain at a small amplitude, precharge can be performed in a short time.
[0017]
On the other hand, in the write operation, only the word line WL of the selected memory cell is asserted, and as soon as the word line WL is asserted, the bit lines BL and / BL are driven according to the write data.
[0018]
Since rewriting to the memory cell is not performed at the time of reading, destructive reading is performed. The cache memory 110 is used to protect the data. Data read from the dynamic memory 100 is sent to the cache memory 110. The cache memory 110 stores the read data in a certain entry, and at that time, sets the Valid bit of the entry. Further, when the cache memory is replaced, with respect to an entry in which the Valid bit is set, new data is stored in the entry and at the same time, the stored data is written back to the dynamic memory 100. (Control is performed like a write-back method using a write-allocate write method.)
By controlling in this way, data read from the dynamic memory 100 by destructive reading is stored in one entry of the cache memory 110, and when the cache memory 110 is evicted (replaced), the Valid bit is set. Therefore, writing back to the dynamic memory 100 is performed. In this way, the original data is never lost only by reciprocating between the dynamic memory 100 and the cache memory 110.
[0019]
The data flow between the dynamic memory 100 and the cache memory 110 is performed by the bus controller 116. If the dynamic memory 100 and the cache memory 110 can be directly connected to each other by one bus, the data flow shown in FIG. It goes without saying that the bus controller is not particularly necessary.
[0020]
For the sense amplifier of the dynamic memory 100 of the present invention, a direct sense type sense amplifier described in, for example, Kiyoo Ito, “VLSI LSI”, Bafukan, p165 is suitable. In this direct sense system, the memory cell signal can be directly taken out to the common data output line without waiting for the sense amplifier to amplify data on the bit line, and high speed operation is possible. When this direct sense method is used in a conventional dynamic memory, an amplifier for rewriting to a memory cell is required in parallel with the sense amplifier, but this rewriting amplifier is not necessary in the dynamic memory of the present invention.
[0021]
FIG. 4 shows an embodiment in which this direct sense type sense amplifier is applied to the dynamic memory 100 of the present invention. MC is a dynamic memory cell, 301 is an equalizer circuit, 302 is a direct sense sense amplifier circuit, 303 is a write amplifier circuit, 304 is a word driver circuit, 305a to 305d are word lines, BL and / BL are bit lines, EQ Represents an equalizer circuit activation signal, SA represents a sense amplifier circuit activation signal, and WA represents a write amplifier circuit activation signal. RO and / RO are output lines from the sense amplifier circuit, WI and / WI are input lines to the write amplifier circuit, and I / O lines (input / output lines) are formed by two dual rail signals. Yes. The feature is that there is no rewrite amplifier circuit. Here, an example in which the output line and the input line are separated is shown, but they may be shared. That is, the input / output lines may be two pairs separated for writing and reading, or may be common to one pair.
[0022]
As described above, in the dynamic memory 100 of the present invention, tRC can be significantly shortened as compared with the conventional dynamic memory. When this feature is used, when the dynamic memory 100 is pipelined as shown in FIG. 5, the pipeline pitch can be reduced. In FIG. 5, reference numeral 200 denotes a configuration example when the dynamic memory of the present invention is pipelined. 201 is an address latch, 202 is an address decoder, 203 is an address driver, 204 is a sense amplifier and write amplifier, 205 is an input data DI latch, 206 is a write buffer, 207 is an I / O that amplifies the signals on the I / O lines 210 and 211 Line amplifiers 208 and 209 are bit line pairs BL and / BL, 210 and 211 are I / O line pairs, 212 is a word line, and 213 is a memory cell.
[0023]
The clock CLK is input to 201, 205, and 207 and has a two-stage pipeline structure.
[0024]
At the time of reading, the address latched by 201 is decoded, and one of the word lines 212 is selected and asserted. The memory cell information output to the bit lines BL and / BL is amplified by 204. The amplified memory cell data is latched by the next clock 207 and output as output data DO.
[0025]
FIG. 5B illustrates the above read method as a timing chart. The read address Ra1 is input at the rising edge indicated by # 1 of the clock CLK, and the data Rd1 is output at # 2. Since the data Rd1 is determined in # 3, the device or circuit that issued the read request in # 1 can read the data from the dynamic memory 100 with the latency 2. Similarly, data Rd2 corresponding to the read address Ra2 input at # 2 is output at # 3, and the data can be read at # 4. In response to a read request, data is taken in after two clocks, so the read latency is 2.
[0026]
At the time of writing, after the address latched by 201 is decoded, one of the word lines 212 is selected and asserted. At the same time, the write data is latched by 205 and the bit lines BL and / BL are driven by 206. By this operation, writing to the memory cell is performed.
[0027]
FIG. 5C illustrates the above writing method as a timing chart. The write address Wa1 is input at the rising edge indicated by # 1 of the clock CLK, and the write data Wd1 is input at # 1 at the same time. The write operation is completed by the next clock # 2, and the next write address Wa2 and write data Wd2 are input at # 2. The write latency is 0 because the write request can be completed with the same clock as the address input.
[0028]
In the above two operations, the precharge operation of the bit lines BL, / BL and I / O lines is omitted, but the method is not particularly limited. It may be performed between the rising edge of the clock CLK and the assertion of the word line.
[0029]
The conventional dynamic memory has a drawback that since the tRC is long, the pipeline pitch becomes long even if it is pipelined. Conventionally, methods such as multi-bank interleaving have been used to conceal this defect, but there are problems such as pipeline disruption when access to the same bank continues, and bank control becomes complicated. There was a drawback.
[0030]
FIG. 6 shows an embodiment in which the write latency and read latency of the dynamic memory in FIG. 5 are the same. In order to make the definition of latency accurate, the definition of latency used in the present application will be described. Read latency is the number of clocks from the clock edge at which the read request is made to the clock edge until data can be taken in. Write latency is the clock from the clock edge at which the write request is made to the clock edge at which write data is input. Is a number.
[0031]
221 is a read address latch, 222, 223 and 224 are write address latches, and 225 is a selector. A broken line with an arrow represents a clock line and is controlled by the write data control unit 226 as shown below. Compared with FIG. 5, the address latch 201 is replaced with a read address latch 221, write address latches 222 to 224, and a selector 225. The input clock of the address latch and the input clock of 205 are controlled by the write data control unit 226 as follows.
[0032]
When a write address is input, the address is delayed by the write address latches 222-224. Write data input after two clocks from the input of the write address is latched by 205 and is in a write ready state. At the timing when there is a write access request next to this write access, data is written to the memory cell with write latency 0 based on the address latched in 224 and the data latched in 205. Therefore, the write operation is performed at the time of the write access after or after the write access. (The actual write operation to the memory cell is performed at the time of the subsequent write request including the time when the write address and the write data are gathered, so that the so-called delayed write is performed.) The write latency is 0 and the read latency is 2. By controlling with the configuration as shown in FIG.
[0033]
FIG. 6B is a timing chart illustrating the reading method. The reading method is basically the same as that shown in FIG. That is, the read address Ra1 is input at the rising edge indicated by # 1 of the clock CLK, and the data Rd1 is output at # 2. Since the data Rd1 is determined in # 3, the circuit device that has issued the read request (Ra1) in # 1 can read the corresponding data (Rd1) with latency 2. Similarly, data Rd2 corresponding to the read address Ra2 input at # 2 is output at # 3 and can be read at # 4. In response to a read request, data is taken in after two clocks, so the read latency is 2.
[0034]
On the other hand, FIG. 6C illustrates the above writing method as a timing chart. The write address Wa1 is input at the rising edge indicated by # 1 of the clock CLK and is latched by the write address latch 222. It is latched by the write address latch 223 at # 2 and by the write address latch 224 at # 3. At # 3, the write data Wd1 is simultaneously latched by the input data DI latch 205 and is in a write ready state. When a write address including # 3 is input thereafter, writing to the memory cells of Wa1 and Wd1 is executed. Since the write data is taken in the second clock from the write address input, the write latency is 2.
[0035]
Needless to say, in order to realize the write latency 2 as shown in FIG. 6C, the input data DI latch 205 is assumed to have a read request in # 3 of FIG. 6C. Must have a structure capable of latching up to two write data. The structure is not particularly limited, but can be easily realized with a FIFO buffer or the like.
[0036]
By controlling the write and read latencies in this way, a plurality of access requests and refresh requests from the CPU and bus master can be input to the dynamic memory without disturbing the pipeline. Further, the device / circuit using the dynamic memory of the present invention can completely grasp not only the read latency but also the write latency. Therefore, it is easy to input the write data into the dynamic memory with the same latency as the read latency, thereby increasing the pipeline filling rate when read and write are mixed. In particular, when the output data line DO and the input data line DI of the dynamic memory are shared as input / output data lines, the above effect is significant because the input data and the output data need to be separated and transmitted in a time division manner. Become. Also, at the time of so-called read-modify-write access, it is necessary to write the data after processing it using the read data. Therefore, if the read latency and the write latency are the same, the pipeline filling rate is increased. Can do.
[0037]
In the method of FIG. 6, the information is actually written to the memory after the write access at least two clocks later. Therefore, when there is a read access request for the same address requested for writing after the write access request, attention must be paid to data coherency. For example, there are the following solutions.
[0038]
(1) If there is a read access request (Ra2) at the same address one clock after the write access request (Wa1), the write data (Wd1) corresponding to the write access request (Wa1) is supported by the read access request (Ra2) Output as read data (Rd2). However, since the write data (Wd1) has not yet been written to the dynamic memory cell, the write data (Wd1) is input at the next clock after the read access request (Ra2), and then the write data is output at the next clock. (Wd1) may be forwarded and output as read data (Rd2) corresponding to the read access request (Ra2).
[0039]
(2) If there is a read access request (Ra2) at the same address two clocks after the write access request (Wa1), the write access request (Wd1) corresponding to the write access request (Wa1) input at that clock is requested. What is necessary is just to forward and output as read data (Rd2) corresponding to the read access request (Ra2) at the next clock of (Ra2).
[0040]
FIG. 7 shows the above forward circuit added to FIG. 231 is an address comparator, 232 is a selector, and 233 is a latch. The address comparator 231 compares the address information stored in the write address latches 222 to 224 with the address requested to be read, and there is an access request to an address that has not been written to the memory cell. In this case, the corresponding read data is forwarded from the input data DI latch 205 to 223 using the selector 232.
[0041]
The structure of the embodiment of FIG. 7 is not limited as long as the operations (1) and (2) can be realized.
[0042]
The number of pipeline stages and the method of cutting the pipeline in the dynamic memory of the present invention shown in FIGS. 5 to 7 are not particularly limited to the illustrated method. For example, a latch may be provided between the word line decoder 202 and the word line driver 203 to increase the number of pipeline stages, or the sense amplifier 204 may be used as a pipeline latch to increase the number of pipeline stages. Needless to say, increasing the number of pipeline stages can shorten the pipeline pitch and increase the operating frequency.
[0043]
Since the dynamic memory of the present invention is used for destructive reading, it is basically necessary to assert only the word line connected to the memory cell storing the data to be read. If only the word line is asserted without being read, the contents of the memory cell are destroyed on the word line, and the contents of the memory cell are not read from the dynamic memory, so they are lost from the entire system using the dynamic memory. Will be. Therefore, if the bit width of the data to be read at a time is small and the number of memory cells to be selected is small, the word line is divided into many sub word lines and only the word line connected to the memory cell storing the read data is decoded. Need to be asserted. (Hereinafter, this is called a word line division problem.) This division of the word line leads to an increase in area. However, if the number of memory cells read at a time is increased, the number of divisions can be reduced even if the word lines are divided, so that the area does not increase. There are the following methods for this.
[0044]
(1) If the cache memory 110 is integrated on the same semiconductor chip as the dynamic memory 100, the line size of the cache memory is increased because there is no pin number bottleneck of the package storing the dynamic memory, and the selected memory is selected at once. The number of cells can be increased. In an extreme example, the memory cell of the cache memory may be laid out in parallel with the sense amplifier. The data width between the dynamic memory 100 and the cache memory 110 is increased (for example, 1024 bits), and the data width between the integrated semiconductor chip and the outside is set to a smaller data width (for example, 32 bits). Also good. The increase in the area of the dynamic memory 100 can be suppressed by avoiding the package pin number bottleneck.
[0045]
(2) When the cache memory 110 is implemented by using a CPU primary cache or secondary cache to make it a separate chip from the dynamic memory 100, the data transfer size between the cache memory 110 and the dynamic memory 100 only To increase. For example, when the cache memory 110 is realized by the secondary cache of the CPU, the line size of the secondary cache may be increased.
[0046]
Further, the data stored in the dynamic memory of the present invention exists in the cache memory 110 or the dynamic memory 100. Therefore, when there are a plurality of bus masters for these memory systems, a so-called coherency problem occurs. For example, this problem can be solved as follows.
[0047]
(1) If the cache memory 110 and the dynamic memory 100 are integrated on the same semiconductor chip and the chip is accessed only through the cache memory 110, there is no direct access to the dynamic memory 100. There is no coherency problem.
[0048]
(2) When the cache memory 110 and the dynamic memory 100 are formed on different chips, the cache memory 110 may be realized using a primary cache or secondary cache of the CPU. The dynamic memory 100 can be accessed directly from multiple CPUs, but coherency compensation methods such as snooping functions using the MESI protocol built into the CPU, primary cache or secondary cache controller can be used as they are. . When data is read from the dynamic memory 100, the Valid bit of the data entry is set, so the MESI protocol monitors the corresponding entry access of other CPUs.
[0049]
FIG. 8 shows an embodiment of a fully pipelined dynamic memory of the present invention when the cache memory 110 cannot be used. As described above, the dynamic memory of the present invention is destructive reading. Therefore, the read data does not exist in the dynamic memory. In FIG. 8, the dynamic memory is pipelined, and the write operation (Wa1, Wd1) of the data read to the same address is performed immediately after the read (Ra1, Rd1). (A) is a waveform when the embodiment of FIG. 5 is used. (B) is a waveform when using the embodiment in the case where the delayed write system shown in FIG. 6 or FIG. 7 is used. As described above, when the method of FIG. 6 or FIG. 7 is used, a new access request (Ra2) can be accepted at # 3, so that the access overhead can be suppressed to one clock. When there are a plurality of bus masters, the write access in the continuous read / write operation for rewriting needs to be performed with the highest priority in order to compensate for coherency. (Hereinafter, the data holding method of the destructive read memory cell using the pipeline is referred to as a pipeline rewrite method.)
The method of FIG. 8 can be used not only when the cache memory 110 cannot be used but also when the valid bit control cannot be used for the cache memory 110. Further, it can be used when the cache memory 110 is an instruction cache.
[0050]
The cache memory 110 of FIG. 1 may be integrated on the same semiconductor chip as the dynamic memory 100, but may be a separate chip.
[0051]
When the dynamic memory 100 is used as the main memory of the CPU, the cache memory 110 is optimally realized as the primary cache of the CPU. Alternatively, it may be realized as a memory system composed of a primary cache and a secondary cache of a CPU. In this case, the data read from the dynamic memory 100 is written to the primary cache, and when the data is erased from the primary cache, the data is written to the secondary cache, and the data is read from the secondary cache. However, it is optimal to control so that the data is written back to the dynamic memory 100 at the time of replacement. As described above, the area efficiency can be increased by using the cache memory 110 as the primary cache or the secondary cache of the CPU.
[0052]
Further, the number of cache memories 110 is not limited. Alternatively, the cache memory 110 may have a plurality of memory hierarchies. There may be two such as an instruction cache and a data cache. In the case of the data cache, the access method using the Valid bit described in FIG. 1 is used, and in the case of the instruction cache, the write access may be performed after the read access using the method described in FIG. Alternatively, two modes may be provided in the dynamic memory 100 to have a mode for accessing in the dynamic memory format of the present invention and a mode for accessing in the conventional dynamic memory format. If a mode with good access efficiency is selected according to the access contents, the dynamic memory 100 can be used more efficiently.
[0053]
In the above embodiment, an example is shown in which the Valid bit is used, but the presence or absence of the Valid bit is not particularly limited. Further, the line size, number of ways, capacity, etc. of the cache memory 110 are not particularly limited. Data that is destructively read from the dynamic memory 100 may be stored in the cache memory 110, and data that is evicted from the cache memory 110 may be stored in the dynamic memory 100. If there are two or more cache memories, control may be performed so that data is always present in the cache memory and the dynamic memory. In short, if the dynamic memory is destructively read and the read data is controlled to be stored in a memory other than the read dynamic memory (cache memory in the present invention) of the entire system using the dynamic memory, the system configuration is particularly limited. do not do.
[0054]
Further, the number of dynamic memories 100 is not limited. The method of the present invention may be applied to a plurality of dynamic memory chips, or the method of the present invention may be applied to some dynamic memories of the plurality of dynamic memory chips.
[0055]
Further, the structure of the memory cell of the cache memory 110 is not particularly limited. A dynamic type in which data is stored by accumulating charges in the capacitance may be used, an SRAM memory cell using poly resistors or TFTs, or a complete CMOS SRAM memory cell using six MOS transistors.
[0056]
The invention according to the first embodiment is summarized as follows.
[0057]
(1) A plurality of dynamic memory cells provided at intersections of a plurality of word lines and a plurality of bit lines, a plurality of sense amplifiers provided corresponding to each of the plurality of bit lines, and the plurality of senses In a semiconductor device including a dynamic memory having a plurality of input / output lines provided corresponding to each amplifier, the dynamic memory selects the word line and outputs a signal of the corresponding dynamic memory cell during a read operation. After reading to the corresponding plurality of bit lines, the signals read by the plurality of sense amplifiers are input to the bit lines without shifting to a rewrite period of the read signal to the dynamic memory cell. After amplification on the output line, the plurality of bit lines are precharged. (First readout mode)
(2) The dynamic memory further includes a write amplifier on the corresponding bit line,
During a write operation to the dynamic memory cell, the write amplifier outputs a write signal to the corresponding bit line immediately after or immediately before selecting the corresponding word line, and writes the signal to the dynamic memory cell. . (First writing mode)
(3) In addition, the semiconductor device of (1) to (2) further includes at least one cache configured by static memory cells, and in the operation of reading data from the dynamic memory, the dynamic method is used by the reading method. Data is read from the memory, the data is written to at least one of the caches, and when the data is erased from all the caches, the data is written back to the dynamic memory.
[0058]
(4) The dynamic memory described in (1) to (3) above includes a memory device including an address latch circuit that receives a row address for selecting a word line to be accessed among a plurality of word lines. The address latch circuit latches the row address at every changing point of the first clock signal having a predetermined cycle.
[0059]
(5) Further, the pipelined dynamic memory of (4) further includes a write delay circuit to which a first write address and first write data input at the time of the first write access are input, and the first write A write operation to the dynamic memory cell corresponding to the access is performed on the first write address and the first write data stored in the write delay circuit at the time of the second write access following the first write access.
[0060]
(6) The dynamic memory according to (5) further includes a forward circuit having an address comparator. In the read access, the forward circuit compares the input read address with the first write address by the address comparator. If there is a read access at the same address as the first write address between the first write access and the second write access, the first write data is output as read data corresponding to the read access.
[0061]
<Example 2>
A more specific embodiment of the pipelined DRAM (PDRAM) of the present invention is shown in FIG. M0 is an NMOS transistor and constitutes the memory cell MC1 together with the capacitor C0. BL1 to BLn are bit lines, WL1 to WLm are word lines, and the memory cells are connected at the intersections of the word lines and the bit lines. (For example, in the folded type bit line arrangement method described in page 90 of "VLSI LSI", Kiyoo Ito, Bafukan, 1994, a memory cell is always connected at the intersection of a bit line and a word line. In the present invention, these bit line arrangement methods are not particularly limited to those shown in FIG. 9. RAMP is a read amplifier, WAMP is a write amplifier, and LX-DEC is a word line decoder (word Line driver circuit). SARY1 to SARYx are subarrays composed of the circuits described above. WDATAL is write data latch, RDATAL is read data latch, WSEL is write data selector, RSEL is read data selector, Y-DEC is Y decoder (including Y driver), Y-ADRL is Y address latch, GX-DEC is global Word line decoder (row decoder including global word line driver), X-ADRL is X address latch (row address latch circuit), CRL is timing control circuit, GWL1 to GWLz are global word lines, DI1 to DIn are input data, DO1 ˜DOn is output data, ADD is an address (addresses are input without being multiplexed), WE is a write enable, CLK is a clock, and VPL is a plate voltage.
[0062]
The input address ADD is latched by X-ADRL and Y-ADRL every clock CLK cycle, and decoded by GX-DEC and Y-DEC. As a result of decoding by GX-DEC, one of the global word lines GWL1 to GWLz is selected. Y-DEC selects one of the subarrays SARY1 to SARYx as a result of decoding. LX-DEC receives the global bit lines GWL1 to GWLz and the decoding result of Y-DEC, and selects and drives one of the word lines WL1 to WLm in the selected subarray. The number of memory cells selected by the word line is the same as the number n of output or input data.
[0063]
At the time of reading, the storage information from the selected n memory cells is amplified by n read amplifiers RAMP. The amplified n pieces of data DO1a to DOna are input to the read data selector RSEL. RSEL selects and connects n data DO1a to DOna output from subarrays SARY1 to SARYx to n inputs of read data latch RDATAL according to the decode signal input from Y decoder Y-DEC. To do. The n pieces of data transferred to the read data latch RDATAL are latched by the read data latch RDATAL according to the clock CLK, and are output to the outside of the pipeline dynamic memory PDRAM as DO1 to DOn.
[0064]
At the time of writing, the input data DI1 to DIn are latched by the write data latch RDATAL according to the clock CLK and input to the write data selector WSEL. The write data selector WSEL selects a subarray that performs a write operation according to the decode signal input from the Y decoder Y-DEC, and inputs n data from the write data selector WSEL to n inputs from the subarrays SARY1 to SARYx. Select and connect to DI1a to DIna.
[0065]
The input n pieces of data DI1a to DIna are amplified by a write amplifier WAMP and written as storage information in n memory cells selected via a bit line.
[0066]
With the structure of the embodiment of FIG. 9, the operation shown in FIG. 3A or 3B can be realized by pulse driving the word lines WL1 to WLm for a predetermined period within the period of the clock CLK. Further, as described above, since the rewriting is not performed, the pulse width of the word line can be shortened, and the pipeline pitch (cycle of the clock CLK) determined thereby can be shortened. Since the structure of FIG. 9 is basically the same as the structure of the embodiment of FIG. 5A, when the reading method and the writing method are written in a timing chart, they are the same as FIG. 5B and FIG. 5C. Become.
[0067]
In FIG. 9, the problem of the word line division described above is solved by hierarchizing the word lines into global word lines GWL1 to GWLm and word lines WL1 to WLm. Here, the number of global word lines GWL1 to GWLm and the number of word lines WL1 to WLm are the same. However, if the number of decode address bits of the Y decoder is increased, the number of global word lines GWL1 to GWLm may be reduced from m. it can.
[0068]
Although a specific circuit diagram example of WAMP and RAMP is not shown in FIG. 9, for example, 303 of FIG. 4 can be used for WAMP, and 302 of FIG. 4 can be used for RAMP. In FIG. 9, WAMP and RAMP are arranged at both ends of the bit line, but this is a measure for making the drawing easier to see, and the actual circuit layout arrangement is not limited to this arrangement. WAMP and RAMP may be arranged so as to be connected to one end of the bit line as indicated by 303 and 302 in FIG. In this case, it goes without saying that the write data selector WSEL and the read data selector RSEL may be shared depending on the configuration. Furthermore, a so-called shared sense amplifier system in which bit lines are connected to both ends of RAMP and WAMP, and memory cells are connected to the respective bit lines may be used. As described above, the bit line structure, RAMP, and WAMP structure are not particularly limited to those shown in FIG. In addition, in FIG. 9, the precharge circuit indicated by 301 in FIG. 4 is not particularly shown, but this is also a measure for making the drawing easy to see, and is necessary for the operation of the memory circuit such as the precharge circuit in a proper place. Needless to say, an additional circuit may be added.
[0069]
<Example 3>
Next, an example of a refresh-free dynamic memory (RFPDRAM) using the pipelined dynamic memory shown in FIG.
[0070]
FIG. 10 is a diagram showing an embodiment of RFPDRAM. PDRAM corresponds to the pipeline dynamic memory shown in FIG. ASEL, DISEL, and WESEL are selectors, RFADDG is a refresh address generator, RFDATL is a refresh data latch (data latch circuit), REFSEQ is a refresh sequencer, FF1 is a flip-flop, and these circuits form the access control circuit ACCRL. ing. Here, the flip-flop FF1 is a flip-flop generally referred to, and the output Q is an input at the time when the clock input to the clock input indicated by a triangle symbol in the drawing transitions from “L” to “H”. Memorize D and output to Q, otherwise maintain Q output.
[0071]
ADD, DI, and DO are PDRAM address and data input / output terminals, respectively, each of which has a predetermined number of bits corresponding to the PDRAM capacity and the number of input / output bits. On the other hand, EADD, EDI, and EDO are RFPDRAM address and data input / output terminals, respectively, and each terminal has the same number of bits as PDRAM ADD, DI, and DO. WE and EWE indicate write enable signals for PDRAM and RFPDRAM, respectively. CLK, CLK1, and CLK2 indicate clock signals or clock terminals.
[0072]
The address EADD input to the refresh free dynamic memory RFPDRAM is input to the selector ASEL together with the output RFADD of the refresh address generator RFADDG, and is selectively connected to the address ADD of the PDRAM according to the value of the selector signal P1. Similarly, the input data DI input to the RFPDRAM is input to the selector DISEL together with the output RFDAT of the refresh data latch RFDATL, and is selectively connected to the input data DI of the PDRAM according to the value of the selector signal P1. Further, the write enable signal EWE input to the RFPDRAM is input to the selector WESEL together with the output RFWE of the refresh sequencer REFSEQ, and is selectively connected to the PDRAM write enable signal WE according to the value of the selector signal P1. PDRAM output data DO is input to RFPDRAM output data EDO and refresh data latch RFDATL. REFSEQ uses the clocks CLK1 and CLK2 input to RFPDRAM to control the refresh address generator RFADDG and the refresh data latches RFDATL and P1, thereby performing the control necessary for the PDRAM refresh operation. FIG. 11 shows a timing chart of the operation example.
[0073]
The clock CLK1 is a clock having a frequency twice as high as that of the clock CLK2, and the rising timings thereof coincide. Devices or circuits that use RFPDRAM connected to EADD, EDI, EDO, EWE, etc. (not shown in FIG. 19 for simplicity. Hereinafter, this is called an external device, and access from that external device to RFPDRAM) The external access request from the request is called an external access request.) Is captured at the rising edge of CLK2. Since the output P1 of FF1 in FIG. 10 is "H" at the rising timing of CLK2, the access request received at the rising timing of CLK2 is directly transmitted to the PDRAM for processing. Here, # 1 is a read request (Ra1), # 3 is a write request (Wa2), # 5 is a read request (Ra3), # 7 is a read request (Ra4), and # 9 is a read request (Ra5). In response to those access requests, RFPDRAM confirms the read data (Rd1) output with # 3, the write data (Wd2) input with # 3, the read data (Rd3) output with # 7, Read data (Rd4) output is confirmed with # 9, and read data (Rd5) output is confirmed with # 11. Regarding the read, latency 2 is output in terms of the frequency of CLK1, latency 1 in terms of the frequency of CLK2, and no-waiting output. For write, the latency is zero.
[0074]
As described above, an external access request to the pipeline dynamic memory PDRAM is generated only once every two periods in terms of CLK1 period. In FIG. 11, external access requests are generated only at odd-numbered clock rising edges, such as # 1, # 3, # 5, # 7,. Since the PDRAM is completely pipelined, an access request to the PDRAM can be made every cycle in the CLK1 period. On the other hand, in the configuration of FIG. 10, as described above, the external access request is issued only once every two cycles in the CLK1 cycle. The access control circuit ACCRL issues an access request for a refresh operation to the PDRAM between these external access requests (empty slots in the pipeline indicated by # 4, # 6, # 8, # 10,...). Hereinafter, the method will be described in detail with reference to FIG.
[0075]
The access control circuit ACCRL issues a refresh request to the PDRAM at a certain time interval so that the information stored in the pipeline dynamic memory PDRAM is not erased. In FIG. 11, a read request (Ra0) is issued at # 4 with respect to the refresh address RFADD generated by the refresh address generator RFADDG, and the read data (Rd0) is received at # 6 and stored in the refresh data latch RFDATL. . Next, in # 8, a write request (Wa0) is issued to the same address requested in the previous read, and the data (Wd0) stored in RFDATL is written. Through the above operation, rewriting of the memory cell in the PDRAM is executed. RFADDG then counts up RFADD. This operation is repeated by the refresh sequencer REFSEQ at predetermined time intervals, whereby the refresh operation for all the memory cells in the PDRAM is performed.
[0076]
According to the above-described embodiment, the refresh operation unique to the dynamic memory that stores information by the electric charge accumulated in the capacitance can be completely hidden from the device or circuit using the dynamic memory. Further, the same performance as the original pipeline dynamic memory PDRAM can be obtained with respect to the access speed (here, latency). (In the embodiment of FIG. 11, the read latency is 2 in terms of the CLK1 period, and the speed is not degraded.) On the other hand, the maximum access request frequency (freq1) that can be issued to the RFPDRAM is the highest access that can be originally accepted by the PDRAM. Half of the frequency (freq). However, since the pipeline frequency of the PDRAM (frequency of CLK1) can be sufficiently increased by pipelining, the access request frequency (freq1) to the RFPDRAM can also be increased to a level where there is no problem. For example, when the microprocessor is operating at 300 MHz as an external device using the refresh-free dynamic memory RFPDRAM, CLK can be used at 600 MHz and CLK1 can be used at 300 MHz.
[0077]
9 to 11 show an example in which the read latency of the pipeline dynamic memory PDRAM is 2 and the write latency is 0. However, the use of the refresh concealment method is not particularly limited to this latency. Needless to say. However, if the latency of the PDRAM converted to the CLK1 period is L, and the data exchange for the external access request is performed in the CLK2 period, the latency L1 converted to the CLK1 period is the number of L / 2 rounded up. become. Therefore, the CLK1 cycle conversion latency for data exchange in response to an external access request is L + 1 when L is an odd number.
[0078]
<Example 4>
The refresh concealment method is not particularly limited to the method shown in FIG. In the embodiment of FIG. 11, the PDRAM pipeline cycle is half the cycle of the external access request, and the external access request is # 1, # 3, # 5, # 7,. By limiting to this phase, there is an opportunity to perform a refresh operation with respect to CLK1, with phases # 4, # 6, # 8, and # 10. That is, the phase of the external access request and the phase of the access request accompanying the refresh operation are limited to different phases to avoid collision between the two. In this way, the access conflict between the two may be avoided by controlling the access between the two in different phases.
[0079]
Furthermore, if the pipeline cycle of the PDRAM is made shorter than the cycle of the external access request, the PDRAM refresh opportunity can be surely obtained even when the external access request is issued continuously. That is, the ratio between the pipeline frequency CLK1 as in the embodiment of FIG. 11 and the frequency of the clock signal CLK2 corresponding to the period for receiving the external access request does not have to be particularly double. For example, the ratio between the frequency of CLK1 and the frequency of CLK2 may be a rational number larger than 1, and may be 3/2 times. In this case, even when an external access request is issued to the RFPDRAM every CLK2 cycle, there is a period in which there is no external access request to the PDRAM once every three cycles in terms of the CLK1 cycle. When the previous frequency ratio is 1000/999 times, there is a period in which there is no external access request to the PDRAM once per 1000 periods in terms of CLK1 period. The refresh sequencer REFSEQ may issue an access request necessary for refresh to the PDRAM at a timing when there is no external access request. Since the refresh cycle is generally longer than the external access request cycle, the CLK1 frequency can be made sufficiently fast even if the ratio of the CLK1 frequency to the CLK2 frequency is only 1000/999 times different. The refresh operation can be performed with a sufficient period.
[0080]
As an example, FIGS. 12 and 13 show a more detailed embodiment in the case where the frequency ratio between CLK1 and CLK2 is 3/2. The embodiment of FIG. 12 differs from the embodiment of FIG. 10 in the following two points. (1) The circuit for generating the flip-flop FF1 that generates the selector ASEL, DISEL, and WESEL select signal P1 in FIG. 10 is composed of flip-flops FF2, FF3, and FF4 in FIG. 12, and P3 is the selector ASEL, DISEL , WESEL select signal. (2) EADD, EDI, EDO, and EWE are connected to the DO terminals of selector ASEL, selector DISEL, and selector WESEL through flip-flops FF5, FF6, latch TL1, and flip-flop FF7, respectively. Here, the output Q of the latch TL1 follows the data input to D as long as the clock input E is “H”. When the clock input E becomes “L”, the output Q maintains the Q output until the clock input E becomes “H”. As in the case of FIG. 10, the refresh sequencer REFSEQ is required for the refresh operation of the PDRAM by controlling the refresh address generator RFADDG and the refresh data latches RFDATL, P2, and P3 using the clocks CLK1 and CLK2 input to the RFPDRAM. Control. FIG. 13 shows a timing chart of the operation example.
[0081]
The clock CLK1 is a clock having a frequency 1.5 times that of the clock CLK2, and has a phase relationship as shown in FIG. As in the case of FIG. 11, the external access request is received by the flip-flops FF5, FF6, and FF7 at the rising timing of CLK2. Since the select signal P3 of the selectors ASEL, DISEL, and WESEL has a waveform as shown in FIG. 13, an external access request received at the rising timing of CLK2 is pipelined at the rising timing of CLK1 after that timing. It is thrown into the dynamic memory PDRAM. Here, read request (Ra1) at # 1 of CLK2, write request (Wa2) at # 2, read request (Ra3) at # 3, read request (Ra4) at # 4, and read request (Ra5) at # 5 Captured as an external access request, read request (Ra1) with # 2 of CLK1, write request (Wa2) with # 3, read request (Ra3) with # 5, read request (Ra4) with # 6, read with # 8 Request (Ra5) is captured in PDRAM. In response to these access requests, RFPDRAM determines the read data (Rd1) output at # 4 of CLK1, the write data (Wd2) input at # 3, the read data (Rd3) output at # 7, and the read at # 8. Data (Rd4) output confirmed, read data (Rd5) output confirmed at # 10. Each read data is confirmed by the read data (Rd1) output at # 3 of CLK2, via the latch TL1 to which the clock of P2 shown in FIG. Is output with the read data (Rd4) output confirmed with # 7, and with the read data (Rd5) output confirmed with # 7. Regarding the read, the signal is output with a latency of 2 in terms of the frequency of CLK2, a latency of 3 in terms of the frequency of CLK1, and no wait. For write, the latency is zero.
[0082]
As described above, the external access request to the pipeline dynamic memory PDRAM is generated only at a rate of two times in three periods in terms of the CLK1 period. In FIG. 13, an access request for an external access request is generated only at the rising edge of the clock twice in three times, as in CLK1, # 2, # 3, # 5, # 6,. Since the PDRAM is completely pipelined, an access request to the PDRAM can be made every cycle in the CLK1 period. On the other hand, in the configuration of FIG. 12 and FIG. 13, as described above, the external access request is issued only twice in 3 cycles at the CLK1 cycle. The access control circuit ACCRL issues an access request for a refresh operation to the PDRAM between these external access requests (empty slots in the pipeline indicated by # 4, # 7,... Of CLK1). Hereinafter, this method will be described in detail with reference to FIG.
[0083]
The access control circuit ACCRL issues a refresh request to the PDRAM at a certain time interval so that the information stored in the pipeline dynamic memory PDRAM is not erased. In FIG. 13, for the refresh address generated by the refresh address generator RFADDG, the read request (Ra0) is issued at # 4 of CLK1, the read data (Rd0) is received at # 6 of CLK1, and the refresh data latch RFDATL To store. Next, at # 1 of CLK1, a write request (Wa0) is issued to the same address requested for the previous read, and the data (Wd0) stored in the refresh data latch RFDATL is written. Through the above operation, rewriting of the memory cell in the PDRAM is executed. Thereafter, the refresh address generator RFADDG counts up the refresh address RFADD. This operation is repeated by the refresh sequencer REFSEQ at predetermined time intervals, whereby the refresh operation for all the memory cells in the PDRAM is performed.
[0084]
Similar to the case shown in FIGS. 11 and 12, the embodiment shown in FIGS. 12 and 13 uses the dynamic memory for the refresh operation peculiar to the dynamic memory for storing information by the electric charge accumulated in the capacitance. It can be completely hidden from devices and circuits. As for the access speed (here, latency), the read latency is 3 in terms of CLK1 and 2 in terms of CLK2. The refresh latency can be completely hidden by only increasing the read latency by one from the original latency of PDRAM.
[0085]
Even with a method other than the above, refresh can be performed by repeating a read request and a write request for refreshing between external access requests due to the feature of being completely pipelined. In addition, if the feature of being completely pipelined is used, there can be various methods of refresh means without disturbing external access requests. Various refresh methods may be combined. Of course, if the external access request and the refresh request collide, if it is permitted to delay the external access request, it is needless to say that there are various refresh methods.
[0086]
<Example 5>
In the embodiment of the refresh-free dynamic memory RFPDRAM shown in FIG. 10 and FIG. 12, the clocks CLK1 and CLK2 are input from the outside, but the clock supply form is not particularly limited. CLK2 may be generated from CLK1 using a frequency divider or the like, or CLK2 to CLK1 may be generated using a multiplier circuit (clock doubler) such as a PLL (phase locked loop). FIG. 14 shows an embodiment in which a clock distribution system using a PLL is added to FIG. CLKGEN is a clock generation circuit, here a clock doubler configured with a PLL structure. CLKSYS indicates a clock distribution system in the PDRAM. Although not particularly limited, a so-called H-tree type clock distribution system is used. What is indicated by a triangular symbol such as 406 is a clock buffer, which is a latch circuit using CLK1 indicated by 405a to 405g (in this case, a latch using a clock such as a latch, flip-flop, or selector). CLK1 is distributed with zero skew. The CLK1 is also distributed to the clock generation means 403 as CLK1a in the same phase as the latch circuits 405a to 405g. Further, the clock CLK2 is also input to the clock generation circuit CLKGEN. Since the clock generation circuit CLKGEN has a PLL structure, it has a phase comparison circuit. (1) The phase of CLK1a is the same as the phase of CLK2a, and (2) the frequency of CLK1a is twice the frequency of CLK2. Generate CLK1 to hold.
[0087]
As described above, in the PDRAM, CLK1 distributed with zero skew using the clock decomposition system is fed back to the clock generation circuit as CLK1a with the same zero skew, so that the phase of CLK2 input to the RFPDRAM is The phase of CLK1 received by the ~ 405g latch circuit can be the same. This makes it easy to secure setup margins and hold margins for various signals such as ADD, EADD, DO, EDO, DI, EDI, WE, and EWE, and allows PDRAM to operate at a higher frequency. In particular, when the area of the PDRAM is increased, a large delay occurs between the clock at the output point of the clock generation circuit CLKGEN and the clock received by the latch circuits 405a to 405g. growing.
[0088]
Note that the clock generation circuit shown in FIG. 14 is not limited to the PLL structure. A structure such as DLL (Delayed Docked Loop) or SMD (Synchronous Mirror Delay) may be used. The structure is not limited as long as the two input clock phases are matched to generate a clock having a desired frequency.
[0089]
<Example 6>
The refresh process in the refresh concealment method of the third and fourth embodiments can be used for a process for accessing the PDRAM other than the refresh. For example, it can be used for the rewrite access of the pipeline rewrite technique shown in FIG. In other words, the PDRAM may be used with a specification such that the external access frequency is smaller than the pipeline frequency determined by the PDRAM capability, and the above rewrite operation may be performed in a surplus time. Without using the cache 110, a complete high-speed pipeline of dynamic memory using destructive read memory cells can be realized.
[0090]
Note that the number of pipeline stages and the method of cutting the pipeline are not limited to the method of FIG. 9 or the method of FIG. 15 described later. For example, the clock CLK is input to the word line decoder LX-DEC to increase the number of pipeline stages by providing a latch function, or the number of pipeline stages can be increased by using the read amplifier RAMP or the write amplifier WAMP as a pipeline latch. Good. Needless to say, increasing the number of pipeline stages can shorten the pipeline pitch and increase the operating frequency.
[0091]
Furthermore, in the above-described embodiment of the pipeline dynamic memory PDRAM, an example is shown in which output data from the memory cell is output via a latch (hereinafter referred to as an output latch) when output from the PDRAM. For example, in the embodiment of FIG. 9, a read data latch RDATL is provided as an output latch. However, the presence or absence of the output latch is not particularly limited for realizing the refresh concealment method of the present invention. That is, the present invention can also be applied to a synchronous dynamic memory in a flow-through format. Of course, it goes without saying that the latency changes depending on the presence or absence of the output latch.
[0092]
In addition, in the embodiment of FIG. 9, a delayed write function as exemplified in the embodiments of FIGS. 6 and 7 can be added. Even in this case, the refresh concealment method of the present invention shown in FIGS. Needless to say, this can be realized by adding a small amount of circuit. By controlling the write latency to match the read latency, a plurality of access requests and refresh requests from a plurality of bus masters such as a CPU can be input to the dynamic memory without disturbing the pipeline. Although the output data line DO and the input data line DI are separated in FIG. 9, when the output data line DO and the input data line DI are shared as input / output data lines, the input data and the output data are sometimes transmitted. The effect of the delayed write function is increased because it is necessary to separate and transmit by division. Also, at the time of so-called read-modify-write access, it is necessary to write the data after processing it using the read data. Therefore, if the read latency and the write latency are the same, the pipeline filling rate is increased. Can do.
[0093]
Further, it goes without saying that the refresh concealment method can be implemented even if it is a pipelined dynamic memory, not the pipeline dynamic memory PDRAM shown in the embodiment of FIG. The PDRAM need not have a structure that does not perform rewriting as shown in FIG. When rewriting is performed, as shown in FIG. 2, since the assertion period of the word line becomes long, the pipeline pitch becomes long and it is difficult to increase the pipeline frequency. However, the refresh data latch RFDATL of FIGS. 10 and 12 is not necessary, and the refresh sequencer REFSEQ simply issues a read access request to the address generated by the refresh address generator RFADDG.
[0094]
Furthermore, in the above description, the refresh concealment method using the pipeline operation is described. However, the refresh concealment method can be used even in a dynamic memory that is not pipelined. For example, it can be realized by a so-called synchronous dynamic memory (SDRAM). (Note that with regard to the presence or absence of pipelining, column access is also pipelined with SDRAM, but in this application it means pipelining with row access.) That is, the cycle time determined by the ability of the circuit The cycle time of the external specification may be set large, and the refresh operation may be performed in the extra time. For example, the external access request cycle of the SDRAM may be doubled the access cycle that can be executed by the original SDRAM. In other words, the specification of the time interval (tRC = tRAS + tRP) from the bank active command to the bank active command to the same bank may be set to double the circuit capability. Then, in the time interval (2 × tRC), the precharge command can be executed from two bank active commands. Of the two bank active commands to the precharge command, processing for an external access request is performed once, and processing necessary for a refresh operation is performed when the other is required for refreshing. Since it is not pipelined, the cycle time is doubled, and the latency is nearly doubled including the delay of external access when access is made during the refresh operation. Although the performance will drop in terms of specifications, the refresh can be completely hidden, so a memory that is easy to use and easy to use can be realized.
[0095]
<Example 7>
In the embodiment of FIG. 9, a memory cell in which information is stored by a memory cell composed of one NMOS transistor and a capacitor is used as a memory cell for storing information. That is, it is assumed that a destructive read memory cell (hereinafter referred to as a 1T memory cell) in which information in the memory cell is destroyed by reading is used. The above invention is not particularly limited to the memory cell structure. For example, a non-destructive read memory cell (hereinafter referred to as 3T memory) that stores information by a memory cell composed of three NMOS transistors as described in 1970 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 42-43. It can also be applied to a dynamic memory using a cell). In addition, many dynamic memory cells such as a memory cell using four MOS transistors are conceivable. Also in 3T memory cells, it is the same as when the word line is divided into a read word line and a write word line, or when the bit line is divided into a read bit line and a write bit line. There may be various control methods such as The structure and control method of these memory cells are not limited.
[0096]
FIG. 15 shows an embodiment of a pipeline dynamic memory PDRAM using the 3T memory cell. MC2 is a 3T memory cell. Information is stored by the charge stored in the gate terminal of the NMOS transistor M2. Word lines WL1 to WLm and global word lines GWL1 to GWLz are controlled at a ternary level. At the intermediate potential, the current corresponding to the gate potential of the NMOS transistor M2 is read out to the bit line RBL through the NMOS transistor M1. At the time of writing, a high potential is applied to the word line WL to turn on the NMOS transistor M3, and a voltage is directly applied from the bit line WBL to the gate potential of the NMOS transistor M2.
[0097]
The embodiment of FIG. 15 differs from the embodiment of FIG. 9 in the following two points. (1) While the memory cell in FIG. 9 is a 1T memory cell, FIG. 15 uses a 3T memory cell. Therefore, the bit lines are divided into read bit lines RBL1 to RBLx and write bit lines WBL1 to WBLx. (2) In FIG. 9, the write data is amplified by the write amplifier WAMP after the write data selector WSEL and transmitted to the bit line, and the read data on the bit line is amplified by the read amplifier and then read data selector RSEL. It is output via. However, in FIG. 15, the write data is amplified by the write amplifier WAMP and then transmitted to the bit line via the write data selector WSEL, and the read data on the bit line is read via the read data selector RSEL. It is output after being amplified by. Therefore, one read amplifier RAMP or write amplifier WAMP is shared by a plurality of Y addresses. The read amplifier RAMP and the write amplifier WAMP are shared by a plurality of bit lines as shown in FIG. Such sharing of the read amplifier RAMP or the write amplifier WAMP has an advantage that the area that can be used for the layout of each amplifier can be increased as compared with the case where the amplifier is not shared. By using a large area for amplifier layout, the selection range of amplifier types is increased, and a high-speed amplifier such as a current sense amplifier can be used.
[0098]
As a 3T memory cell, for example, it has a read word line and a write word line as shown in Fig. 1.10 (a) on page 13 of Kiyoo Ito, published in 1994 by Baifukan, page 13 When 3T memory cells are used, the hierarchization of word lines as shown in FIG. 15 is not required for read word lines. This is because the 3T memory cell is a non-destructive read cell, and therefore it is allowed that there is a memory cell that is not read even when the word line is asserted.
[0099]
Like FIG. 9, FIG. 15 does not show a specific circuit diagram example of WAMP and RAMP, but the RAMP, WAMP structure and bit line structure are not particularly limited to the method shown in FIG. In FIG. 15, WAMP and RAMP are arranged at both ends of the bit line, but this is a measure for making the drawing easier to see, and the actual circuit layout arrangement is not limited to this arrangement. WAMP and RAMP may be arranged so as to be connected to one end of the bit line as indicated by 303 and 302 in FIG. In this case, it goes without saying that the write data selector WSEL and the read data selector RSEL may be shared depending on the configuration. Furthermore, a so-called shared sense amplifier system in which bit lines are connected to both ends of RAMP and WAMP, and memory cells are connected to the respective bit lines may be used. In addition, in FIG. 15, the precharge circuit indicated by 301 in FIG. 4 is not particularly illustrated, but this is also a measure for making the drawing easy to see and is necessary for the operation of the memory circuit such as the precharge circuit in a proper place. Needless to say, an additional circuit may be added.
[0100]
Even when a non-destructive read memory cell such as a 3T memory cell as shown in FIG. 15 is used for the pipeline dynamic memory PDRAM of the present invention, tRAS as shown in FIG. Operation can be realized. In this case, there is an advantage that the cache memory 110 need not be used. Needless to say, the pipeline operation of the present invention shown in FIGS. 5 to 14 can also be realized in the same manner as when 1T memory cells are used.
[0101]
FIG. 16 is a diagram showing an embodiment of a DRAM embedded logic LSI (EMCHP) equipped with the refresh-free dynamic memory RFPDRAM of the present invention. As the memory cell, the 3T memory cell shown in FIG. 15 is used. Note that, in the MOS symbols in FIGS. 15 and 16 and the like, the gate electrode with a white box like M512 is a high voltage MOS transistor composed of a thick gate oxide film of about 6.5 nm, for example. This indicates that the gate electrode indicated by a line, such as M522, is a MOS transistor composed of a thin gate oxide film of about 3.2 nm, for example.
[0102]
VDD and VSS are a core power supply and its ground, and VDDQ and VSSQ indicate an I / O power supply and its ground. For example, the core power supply voltage is 1.0V, and the I / O power supply voltage is 3.3V. OUT0 to OUTx are output signals, IN0 to INy are input signals, and I / O0 to I / Oz are input / output signals. PADCB indicates an I / O circuit for interfacing between a signal inside the chip and the outside of the chip, and 511 indicates a final stage driver circuit of the output circuit, which is a PMOS composed of a thick gate oxide film. A transistor M512 and an NMOS transistor M513 are included. Reference numeral 514 denotes a first-stage buffer circuit of the input circuit, which includes a PMOS transistor M515 formed of a thick gate oxide film and an NMOS transistor M516. (Although omitted for simplification in 514, the MOS transistor in the ESD element connected to the gate electrode of M515 or M516 to prevent electrostatic breakdown is also composed of a MOS transistor with a thick gate oxide film. LCB is a logic circuit composed of inverters, NAND gates, etc. FIG. 16 illustrates an inverter circuit 521 composed of a PMOS transistor M522 composed of a thin gate oxide film and an NMOS transistor M523. Examples of LCBs are 10,000 gates or more such as a microprocessor or DSP. The logic circuit, SRAM, etc. can be mentioned. Also, the 3T memory cell in RFPDRAM uses the same MOS transistor as the MOS transistor having a thick gate oxide thickness used in the I / O circuit. (NMOS transistors M1 and M3 in MC2 of FIG. 15 may be applied with a thick gate oxide film because there is a possibility that a high voltage is applied to them, but a high voltage is not applied to M2. Therefore, it may be composed of a MOS transistor having a thin gate oxide film according to a process problem and a memory cell size.)
In FIG. 16, a MOS transistor to which a high voltage may be applied between the gate and source electrodes or between the gate and drain electrodes of the MOS transistor is configured by a MOS transistor having a thick gate oxide film, and other MOS transistors are used. Uses a MOS transistor with a thin gate oxide film for speeding up as much as possible. By properly using the gate oxide film as shown in FIG. 16, the type of gate oxide film thickness can be limited to only two types for the entire chip, and the manufacturing process can be simplified.
[0103]
In general, when a dynamic memory using 1T memory cells and a logic LSI are mixedly mounted on one chip, there is a drawback that the manufacturing process becomes complicated. However, if a 3T memory cell is used as a memory cell of a dynamic memory as in the present invention, there is no need to form a capacitor in the memory cell, so that the process becomes more complicated than when a 1T memory cell is used. It can be kept low. Further, with the configuration as shown in FIG. 16, the transistors constituting the memory cell can be shared with the transistors used in the logic LSI and the I / O circuit. (However, in order to achieve both high speed and high retention time of the memory cell, the diffusion layer of the transistor in the 3T memory cell is not silicided, and the diffusion layer of the other transistors has a low resistance of the diffusion layer. Therefore, it is possible to perform a treatment such as silicidation.) This makes it possible to greatly reduce the complexity of the process due to the dynamic memory embedded in the logic LSI.
[0104]
The main effects of the above embodiments are as follows.
[0105]
(1) By making the dynamic memory destructive reading, there is no need to amplify data on the bit line, and no time corresponding to tRAS is required. Regarding the precharge time, since the bit line remains at a small amplitude, the precharge can be performed in a short time.
[0106]
(2) Due to (1), the cycle time tRC can be significantly shortened compared with the conventional dynamic memory. When this feature is used, when the dynamic memory is pipelined like a pipeline SRAM, the pipeline pitch can be reduced.
[0107]
(3) When a direct sense sense amplifier is used as a dynamic memory sense amplifier, a high-speed amplification operation is possible. When this direct sensing method is used in the conventional dynamic memory, an amplifier for rewriting to the memory cell is required in parallel with the sense amplifier. However, since it is not necessary in the dynamic memory of the present invention, the chip area can be reduced.
[0108]
(4) In the dynamic memory pipelined with the above configuration, the read latency and the write latency can be made the same. As a result, the pipeline filling rate when reading and writing coexist can be increased.
[0109]
(5) By refreshing the dynamic memory and adding the access control circuit ACCRL to the outside, the refresh operation of the dynamic memory can be hidden.
[0110]
(6) If the 3T memory cell is used, the above effect can be realized without using the cache 110.
[0111]
【The invention's effect】
According to the main effect of the present invention, the read / write cycle time of the dynamic memory cell can be shortened, so that a DRAM capable of high-speed operation can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing operation waveforms of a conventional dynamic memory.
FIG. 3 is a diagram showing an example of operation waveforms of the dynamic memory of the present invention.
FIG. 4 is a diagram showing an embodiment of a dynamic memory of the present invention using a direct sense type sense amplifier circuit;
FIG. 5 is a diagram showing an embodiment of a pipelined dynamic memory according to the present invention and operation waveforms thereof.
FIG. 6 is a diagram showing an embodiment of a dynamic memory in which the write latency and the read latency of the present invention are the same, and its operation waveform.
7 is a diagram showing an embodiment when a forward circuit is further added to the embodiment of FIG. 5; FIG.
FIG. 8 is a diagram showing an example of using the dynamic memory of the present invention when the cache memory cannot be used.
FIG. 9 is a diagram of an example of a pipelined dynamic memory.
FIG. 10 is a diagram of an example of a refresh-free dynamic memory in which an access control circuit that hides a refresh operation from the outside is added to a pipeline dynamic memory PDRAM.
FIG. 11 is a diagram of an example of the operation timing chart of FIG. 10;
12 is a diagram of an example of a refresh-free dynamic memory when the frequency ratio between CLK1 and CLK2 in FIG. 10 is 3/2. FIG.
13 is a diagram of an example of the operation timing chart of FIG. 12. FIG.
14 is a diagram showing an embodiment when the clock generation circuit of FIG. 10 is added.
FIG. 15 is a diagram of an example of a dynamic memory using pipelined 3T memory cells.
FIG. 16 is a diagram showing an embodiment of a DRAM-embedded logic LSI equipped with a refresh-free dynamic memory according to the present invention.
[Explanation of symbols]
100 …… Dynamic memory, 110 …… Cache memory, 200 …… Complete pipeline dynamic memory, 220 …… No wait access complete pipeline dynamic memory, 230 …… No wait access complete pipeline dynamic memory with forward circuit, 300… ... Dynamic memory using direct sense sense amplifiers, Ra1, Ra2 ... Read address, Wa1, Wa2 ... Write address, Rd1, Rd2 ... Read data, Wd1, Wd2 ... Write data, PDRAM ... Pipeline Dynamic memory, PFPDRAM …… Refresh-free dynamic memory, M0 …… NMOS transistor, C0 …… Capacitor, MC1 …… 1T memory cell, WL1 to WLm …… Word line, BL1 to BLn …… Bit line, RAMP …… Read amplifier , WAMP …… Write amplifier, LX-DEC …… Word line decoder (word line driver) SARY1 to SARYx ... subarray, WDATAL ... write data latch, RDATAL ... read data latch, WSEL ... write data selector, RSEL ... read data selector, Y-DEC ... Y decoder (Y Including driver), Y-ADRL ... Y address latch, GX-DEC ... Global word line decoder (global word line driver), X-ADRL ... X address latch, CRL ... Timing control circuit, GWL1 to GWLz ... ... Global word line, DI1 to DIn ... Input data, DO1 to DOn ... Output data, ADD ... Address, WE ... Write enable, CLK ... Clock, VPL ... Plate voltage, ASEL ... Address selector, DISEL …… Input data selector, WESEL …… Write enable signal selector, RFADDG …… Refresh address generator, RFDATL …… Refresh data latch, REFSEQ …… Riff Less sequencer, FF1 to FF7 ... flip-flop, ACCRL ... access control circuit, ADD and EDD ... address, DI and EDI ... input data, DO and EDO ... output data, TL1 ... latch, CLKGEN ... clock Generating circuit, CLKSYS ... clock distribution system, 406 ... clock buffer, 405a to 405g ... latch circuit using clock CLK (in this case, a circuit using a clock such as a latch, flip-flop, register or selector) It is written as a latch circuit. ), MC2 ... 3T memory cell, M1-M3 ... NMOS transistor, WBL1-WBLx ... Write bit line, RBL1-RBLx ... Read bit line, EMCHP ... DRAM mixed logic LSI, 510 ... I / O circuit, 520: Logic circuit, 511: Final driver circuit of output circuit, 514: First stage buffer circuit of input circuit, VDD: Core power supply voltage, VSS: Core ground voltage, VDDQ: I / O Power supply voltage, VSSQ …… I / O ground voltage.

Claims (13)

A plurality of memory cells provided at intersections of the bit lines and the plurality of word lines, a row decoder coupled to the plurality of word lines, and a row address latched in synchronization with a first clock to the row decoder A memory circuit including a row address latch circuit for supplying;
An access control circuit including a refresh control circuit including a refresh address generator, a refresh data latch, and a refresh sequencer ;
The access control circuit adjusts the timing of the external access request supplied in synchronization with the change point of the second clock so as to synchronize with the change point of the first clock, and supplies the request to the memory circuit.
Frequency of the first clock, rather higher than the frequency of the second clock,
The memory cell is a dynamic memory cell,
The refresh sequencer issues a read request to the memory circuit in synchronization with the change point of the first clock using the refresh address generated by the refresh address generator, and the data read from the selected memory cell Is stored in the refresh data latch,
By issuing a write request in synchronization with the change point of the first clock to the same refresh address requested to be read, and writing the data stored in the refresh data latch back to the memory cell, Perform a refresh operation on the selected memory cell,
A semiconductor device, wherein a refresh is performed within a predetermined time for memory cells corresponding to a plurality of addresses in the memory circuit while changing the refresh address by the refresh address generator . In claim 1,
The row address accompanying the external access request or refresh operation is latched in the memory circuit in synchronization with the change point of the first clock,
While the first clock changes n times, the second clock changes m times (where n and m are positive integers),
N is larger than m;
While the first clock changes n times, the total number of read or write requests accompanying the refresh operation does not exceed the number obtained by subtracting m from n, and the external access request exceeds m times. A semiconductor device characterized in that the semiconductor device is performed a number of times. In claim 2,
The semiconductor device, wherein m is half of the n. In claim 3 ,
The refresh control circuit receives the external access request at the rising edge of the second clock, and sets the row address associated with the external access request at the rising edge of the first clock corresponding to the rising edge of the second clock. A row address for refreshing at the rising edge of the first clock corresponding to the falling edge of the second clock without receiving the external access request at the falling edge of the second clock thereafter supplied to the address latch Is supplied to the row address latch. In claim 1,
The access control circuit further includes a clock generation circuit for receiving the second clock and generating the first clock;
The memory circuit further includes a clock distribution circuit for distributing and distributing the first clock in the memory circuit,
The clock generation circuit further includes a phase comparison circuit for comparing phases of the second clock and the first clock distributed and distributed via the clock distribution circuit and fed back. In claim 1,
Each of the plurality of memory cells includes a MISFET having a gate coupled to a corresponding word line and one of a source and a drain coupled to the bit line and a capacitor connected to the other of the source or the drain of the MISFET, A semiconductor device which stores information by electric charge stored in a capacitor. In claim 1,
Each of the plurality of memory cells is a non-destructive read memory cell. In claim 1,
The semiconductor device further includes an output circuit configured to include a first MISFET, and a logic gate circuit configured to include a second MISFET,
Each of the plurality of memory cells includes a third MISFET;
The gate oxide film thickness of the third MISFET is the same as the gate oxide film thickness of the first MISFET, and is larger than the gate oxide film thickness of the second MISFET. In claim 1,
The semiconductor device further includes an input circuit including a first MISFET and a logic gate circuit including a second MISFET,
Each of the plurality of memory cells includes a third MISFET;
The gate oxide film thickness of the third MISFET is the same as the gate oxide film thickness of the first MISFET, and is larger than the gate oxide film thickness of the second MISFET. A plurality of memory cells provided at intersections of the bit lines and the plurality of word lines, a row decoder coupled to the plurality of word lines, and a row address latched in synchronization with a first clock to the row decoder A memory circuit including a row address latch circuit for supplying;
An access control circuit,
The memory cell is a dynamic memory cell,
The period of the first clock is smaller than the period of the external access request,
The access control circuit includes a refresh control circuit including a refresh address generator, a refresh data latch, and a refresh sequencer,
The refresh sequencer issues a read request to the memory circuit in synchronization with a change point from the first clock using the refresh address generated by the refresh address generator, and is read from the selected memory cell. Storing data in the refresh data latch;
By issuing a write request in synchronization with the change point of the first clock to the same refresh address requested to be read, and writing the data stored in the refresh data latch back to the memory cell, Perform a refresh operation on the selected memory cell,
A semiconductor device, wherein a refresh is performed within a predetermined time for memory cells corresponding to a plurality of addresses in the memory circuit while changing the refresh address by the refresh address generator. In claim 10 ,
Each of the plurality of memory cells includes a MISFET having a gate coupled to a corresponding word line and one of a source and a drain coupled to the bit line and a capacitor connected to the other of the source or the drain of the MISFET, A semiconductor device which stores information by electric charge stored in a capacitor. In claim 10 ,
Each of the plurality of memory cells is a non-destructive read memory cell. In claim 11 ,
The bit line is separated into a first bit line for reading and a second bit line for writing,
Each of the plurality of memory cells is connected to a first MISFET having a gate coupled to a corresponding word line and one of a source or a drain coupled to the first bit line and the other of the source or the drain of the first MISFET. 2. A semiconductor device comprising: a second MISFET having a source or a drain; and a third MISFET having a gate coupled to the corresponding word line and one of the source or drain coupled to the gate of the second MISFET.

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