JP4105180B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device regarding the arrangement of an LSI chip and an electrode terminal of a scribe TEG (Test Element Group).

  In recent years, miniaturization and cost reduction of LSI chips have progressed, but the area occupied by electrode terminals in LSI chips and electrode terminals in scribe TEGs formed on scribe regions formed around LSI chips is large. This makes it difficult to reduce the size and cost of LSI chips.

  FIG. 5 is an enlarged plan view schematically showing a part of a conventional LSI chip and a scribe area formed on a wafer. FIG. 6 is a plan view schematically showing an enlarged part of the scribe TEG and LSI chip formed on the scribe region of FIG.

  As shown in FIG. 5, 40 is an LSI chip, 41 is an electrode terminal on the LSI chip, 42 is a seal ring formed along the outer periphery of the LSI chip 1, 43 is a scribe region, 44 is a scribe TEG, and 45 is a scribe. This is an electrode terminal of the TEG.

  The LSI chip 40 is formed in a lattice shape on the wafer surface, and a scribe region 43 for cutting the chip is formed around the LSI chip 40. Although not shown, the LSI chip 40 includes a circuit element such as a transistor and an electrode terminal 41 connected to the circuit element or an electrode terminal 41 not connected to the circuit element.

  A diffusion layer determined along the outer periphery of the LSI chip 40, a Cu wiring layer on the diffusion layer, and a seal ring 42 made of an aluminum wiring layer on the uppermost layer are formed. The seal ring 42 is formed so as to surround the LSI chip 40. A scribe TEG 44 is formed on the outer scribe region 43, and an evaluation element and an electrode terminal 45 are formed on the scribe TEG 44. .

  As shown in FIG. 6, 46 is an LSI chip, 47 is an electrode terminal on the LSI chip, 48 is a seal ring formed along the outer periphery of the LSI chip 1, 49 is a scribe TEG, 50 is an electrode terminal of the scribe TEG, Reference numeral 51 is a wiring for connecting each internal circuit in the LSI chip and the electrode terminal, 52 is a scribe TEG evaluation element, and 53 is a wiring for connecting the scribe TEG electrode terminal and the evaluation element.

  Conventionally, there is no wiring connected to the scribe TEG 49 formed on the scribe region across the seal ring 48 formed along the outer periphery of the LSI chip 46 from the LSI chip 46, and there is no wiring of the LSI chip electrode terminal 47 or the scribe TEG. The electrode terminal 50 was not shared as the electrode terminal of the LSI chip 46 and the scribe TEG 49.

  However, in order to reduce the area of the LSI chip, it is necessary to reduce the area occupied by the electrode terminals in the LSI chip. However, the electrode terminals in the LSI chip are restricted due to restrictions in electrical connection with the outside of the LSI chip. Therefore, it is difficult to reduce the area of the LSI chip, and also in the scribe TEG formed on the scribe region, the area occupied by the electrode terminals in the scribe TEG is small. Although it is necessary to reduce the size, it is not easy to reduce the area occupied by the electrode terminals in the scribe TEG due to the restrictions on the electrical connection with the outside at the time of TEG evaluation. Therefore, the area reduction of the scribe region is realized. It had the disadvantage of being difficult to do.

In order to solve this problem, there is a technique for reducing the area of an LSI chip by drawing out and forming electrode terminals provided in the LSI chip in a conventional scribe area in order to inspect an internal circuit in the LSI chip. Proposed.
JP-A-6-349926

  However, with the progress of miniaturization and cost reduction of LSI chips, the trend of increasing the area ratio of the electrode terminals on the LSI chip and the electrode terminals on the scribe TEG on the wafer does not stop. The problem that it is difficult to reduce the LSI chip area and reduce the cost due to the size of the electrode terminals in the scribe TEG is still a big problem.

  Accordingly, in view of the above problems, an object of the present invention is a semiconductor that suppresses increase in LSI chip area and cost due to electrode terminals on the LSI chip and the scribe TEG, and realizes reduction in LSI chip area and cost reduction. Is to provide a device.

  In order to solve the above problems, a semiconductor device according to claim 1 of the present invention includes an LSI chip formed by integrating an internal circuit composed of semiconductor elements and an inspection circuit used for the inspection of the internal circuit, and the periphery of the LSI chip. An evaluation element and a scribe TEG on which an electrode terminal is formed, and at least one of the electrode terminals in the scribe TEG includes the evaluation element in the scribe TEG and the LSI chip. Is electrically connected to the inspection circuit.

  The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein at least another one of the electrode terminals in the scribe TEG is electrically connected only to the inspection circuit in the LSI chip. .

  According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the electrode terminal in the scribe TEG electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip is switched. The switch is connected to either the evaluation element in the scribe TEG or the inspection circuit in the LSI chip.

  A semiconductor device according to a fourth aspect is the semiconductor device according to the second aspect, wherein the electrode terminal in the scribe TEG that is electrically connected only to the inspection circuit in the LSI chip is directly electrically connected to the inspection circuit. It is connected.

  A semiconductor device according to a fifth aspect is the semiconductor device according to the first, second, third, or fourth aspect, wherein the electrode terminal in the scribe TEG and the inspection circuit in the LSI chip are the uppermost layer wiring of the LSI chip. The uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip is electrically connected through a partly cut.

The semiconductor device according to claim 6 is formed by integrating internal circuits composed of semiconductor elements, formed on an LSI chip on which electrode terminals are formed, and a scribe region around the LSI chip, and an evaluation element is formed A scribing TEG, and at least one of the evaluation elements in the scribe TEG is electrically connected to an electrode terminal in the LSI chip, and the electrode terminal in the LSI chip and the evaluation element in the scribe TEG Are electrically connected through a part of the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip by partially cutting the uppermost layer wiring of the LSI chip .

  The semiconductor device according to claim 7 is the semiconductor device according to claim 6, wherein all evaluation elements in the scribe TEG are electrically connected to electrode terminals in the LSI chip, and electrodes are provided in the scribe TEG. There is no terminal.

  The semiconductor device according to claim 8 is provided on an LSI chip formed by integrating an internal circuit composed of semiconductor elements and an inspection circuit used for inspecting the internal circuit, and on which an electrode terminal is formed, and a scribe region around the LSI chip. And at least one of the electrode terminals in the LSI chip is electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip. ing.

  The semiconductor device according to claim 9 is the semiconductor device according to claim 8, wherein at least the other one of the electrode terminals in the LSI chip is electrically connected only to the evaluation element in the scribe TEG. .

  The semiconductor device according to claim 10 is the semiconductor device according to claim 8, wherein the electrode element in the LSI chip electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip is switched. The switch is connected to either the evaluation element in the scribe TEG or the inspection circuit in the LSI chip.

  The semiconductor device according to claim 11 is the semiconductor device according to claim 9, wherein the electrode terminal in the LSI chip that is electrically connected only to the evaluation element in the scribe TEG is directly and electrically connected to the evaluation element. It is connected.

The semiconductor device according to claim 12 is the semiconductor device according to claim 8 , 9, 10 or 11, wherein the electrode terminal in the LSI chip and the evaluation element in the scribe TEG are the uppermost layer wiring of the LSI chip. The uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip is electrically connected through a partially cut portion.

  According to the semiconductor device of the first aspect of the present invention, at least one of the electrode terminals in the scribe TEG is electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip. By connecting the electrode terminal in the scribe TEG to the inspection circuit in the LSI chip, the inspection circuit in the LSI chip can be evaluated with the electrode terminal in the scribe TEG, and the LSI is used to inspect the internal circuit in the LSI chip. The electrode terminals provided in the chip can be eliminated from the LSI chip. For this reason, it is possible to suppress an increase in the LSI chip area and an increase in cost due to the electrode terminals in the LSI chip, and to realize a reduction in the LSI chip area and a reduction in cost.

  In claim 2, since at least the other one of the electrode terminals in the scribe TEG is electrically connected only to the inspection circuit in the LSI chip, the inspection circuit is directly connected to the electrode terminal of the scribe TEG. Can do.

  The electrode element in the scribe TEG electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip is connected to the evaluation element in the scribe TEG or the inspection circuit in the LSI chip by a changeover switch. Therefore, the electrode terminal of the evaluation element in the scribe TEG and the electrode terminal of the inspection circuit in the LSI chip can be shared.

  According to a fourth aspect of the present invention, in the semiconductor device according to the second aspect, the electrode terminal in the scribe TEG that is electrically connected only to the inspection circuit in the LSI chip is preferably directly electrically connected to the inspection circuit. .

  In claim 5, the electrode terminal in the scribe TEG and the inspection circuit in the LSI chip partially use the uppermost layer wiring of the LSI chip and partially connect the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip. Therefore, the uppermost layer wiring that connects the electrode terminal in the scribe TEG and the inspection circuit in the LSI chip can correspond to a layout that straddles the uppermost layer wiring of the seal ring.

According to the semiconductor device of the present invention, since at least one of the evaluation elements in the scribe TEG is electrically connected to the electrode terminal in the LSI chip, the evaluation element in the scribe TEG is By connecting to the electrode terminals on the LSI chip, the electrode terminals on the scribe TEG can be eliminated. For this reason, it is possible to suppress the increase in LSI chip area and cost increase due to the electrode terminals in the scribe TEG, and to realize reduction in LSI chip area and cost reduction.
In addition, the electrode terminal in the LSI chip and the evaluation element in the scribe TEG partially cut the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip using the uppermost layer wiring of the LSI chip. Since it is electrically connected through the location, the uppermost layer wiring connecting the electrode terminal in the LSI chip and the evaluation element in the scribe TEG can cope with a layout straddling the uppermost layer wiring of the seal ring.

  According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, it is preferable that all evaluation elements in the scribe TEG are electrically connected to electrode terminals in the LSI chip, and no electrode terminals exist in the scribe TEG. .

  According to the semiconductor device of claim 8 of the present invention, at least one of the electrode terminals in the LSI chip is electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip. By connecting the evaluation element in the scribe TEG to the electrode terminal in the LSI chip, the electrode terminal in the scribe TEG can be eliminated. For this reason, it is possible to suppress an increase in LSI chip area and cost increase due to electrode terminals in the scribe TEG, and to realize reduction in LSI chip area and cost reduction.

  In claim 9, at least the other one of the electrode terminals in the LSI chip is electrically connected only to the evaluation element in the scribe TEG. Therefore, the evaluation element in the scribe TEG is directly connected to the electrode in the LSI chip. Can be connected to a terminal.

  The electrode element in the LSI chip electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip is connected to the evaluation element in the scribe TEG or the inspection circuit in the LSI chip by a changeover switch. Therefore, the electrode terminal of the evaluation element in the scribe TEG and the electrode terminal of the inspection circuit in the LSI chip can be shared.

  According to claim 11, in the semiconductor device according to claim 9, the electrode terminal in the LSI chip that is electrically connected only to the evaluation element in the scribe TEG is preferably directly electrically connected to the evaluation element. .

  In claim 12, the electrode terminal in the LSI chip and the evaluation element in the scribe TEG use the uppermost layer wiring of the LSI chip to partially connect the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip. Therefore, the top layer wiring that connects the electrode terminal in the LSI chip and the evaluation element in the scribe TEG can cope with the layout straddling the top layer wiring of the seal ring.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an enlarged plan view schematically showing a part of an LSI chip and a scribe area according to this embodiment. FIG. 2 is a plan view schematically showing an enlarged part of a chip in which the electrode terminals in the scribe TEG formed on the scribe region in FIG. 1 and the inspection circuit used for the inspection of each internal circuit in the LSI chip are connected. FIG.

  As shown in FIG. 1, 1 is an LSI chip, 2 is an electrode terminal on the LSI chip, 3 is a seal ring formed along the outer periphery of the LSI chip, 4 is a scribe region, 5 is a scribe TEG, and 6 is a scribe TEG. The electrode terminals 7 and 7 are wirings that connect the electrode terminals of the scribe TEG and an inspection circuit used for inspection of each internal circuit in the LSI chip.

  The LSI chip 1 is formed in a lattice shape on the wafer surface, and a scribe region 4 for cutting the chip is formed around the LSI chip 1. Although not shown, the LSI chip 1 includes a circuit element such as a transistor and an electrode terminal 2 connected to the circuit element or an electrode terminal 2 not connected to the circuit element.

  A diffusion layer determined along the outer periphery of the LSI chip 1, a Cu wiring layer on the upper layer, and a seal ring 3 made of an aluminum wiring layer on the uppermost layer are formed. The seal ring 3 is formed so as to surround the LSI chip 1. A scribe TEG 5 is formed on the outer scribe region 4, and an evaluation element and an electrode terminal 6 are formed on the scribe TEG 5. . A part of the electrode terminal 6 in the scribe TEG 5 is connected to a test circuit used for testing each internal circuit in the LSI chip 1 by a wiring 7.

  As shown in FIG. 2, 8 is an LSI chip, 9 is an electrode terminal on the LSI chip, 10 is a seal ring formed along the outer periphery of the LSI chip, 11 is a scribe TEG, and 12a and 12b are electrodes in the scribe TEG. Terminal, 13 is an evaluation element of the scribe TEG, 14 is a wiring for connecting each internal circuit in the LSI chip and the electrode terminal, 15 is a wiring for connecting the evaluation element of the scribe TEG and the electrode terminal, 16 is an electrode terminal of the scribe TEG A wiring 17 connects a test circuit used for testing each internal circuit in the LSI chip, and 17 is a changeover switch.

  When an inspection circuit used for inspecting each internal circuit in the LSI chip 8 is connected to the electrode terminal 12a to which the evaluation element 13 of the scribe TEG is connected, a changeover switch 17 is connected as a connection changeover means. The output signal is controlled to perform a predetermined measurement. That is, either the evaluation element 13 of the scribe TEG 11 or the inspection circuit used for the inspection of each internal circuit in the LSI chip 8 is selected by the changeover switch 17. The changeover switch 17 includes an input impedance control circuit and an output impedance control circuit.

  When an inspection circuit used to inspect each internal circuit in the LSI chip 8 is connected to the electrode terminal 12b not connected to the evaluation element 13 of the scribe TEG, the changeover switch 17 is not necessary, and the electrode terminal of the scribe TEG is directly connected. 12b.

  The wiring 16 for connecting the scribe TEG electrode terminals 12a and 12b and the inspection circuit used for the inspection of each internal circuit in the LSI chip 8 is formed of aluminum wiring, and is formed along the outer periphery of the LSI chip 8. Since the layout extends over the aluminum wiring on the top layer of the seal ring 10, the aluminum wiring layer on the top layer of the seal ring 10 is cut in the vicinity of the connection wiring 16 straddling the seal ring 10. As a result, the electrode terminals 12a and 12b in the scribe TEG and the inspection circuit in the LSI chip 8 are electrically connected to the inspection circuit in the LSI chip 8 through the portion where the uppermost layer wiring of the seal ring 10 is partially cut. Connected.

  According to the present embodiment, by connecting the electrode terminals in the scribe TEG formed on the scribe region to the inspection circuit used for inspecting each internal circuit in the LSI chip, the internal circuit in the LSI chip is inspected. In addition, since the electrode terminals provided in the LSI chip can be eliminated from the LSI chip, the area of the LSI chip can be reduced, the number of LSI chips obtained on the wafer can be increased, and the cost can be reduced.

In the scribe region, the electrode terminals of the scribe TEG and the electrode terminals for inspecting the internal circuit in the LSI chip are shared, so that the internal circuit in the LSI chip is not increased without increasing the number of electrode terminals of the scribe TEG. It is possible to increase the number of electrode terminals for inspecting.
(Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS.

  FIG. 3 is an enlarged plan view schematically showing a part of the LSI chip and the scribe area according to the present embodiment. FIG. 4 is a plan view schematically showing an enlarged part of a chip in which an electrode terminal in the LSI chip in FIG. 3 and an evaluation element in a scribe TEG formed on a scribe region are connected.

  As shown in FIG. 3, 21 is an LSI chip, 22 is an electrode terminal on the LSI chip, 23 is a seal ring formed along the outer periphery of the LSI chip, 24 is a scribe region, 25 is a scribe TEG, and 26 is a scribe TEG. This wiring connects the evaluation element and the electrode terminal on the LSI chip.

  The LSI chip 21 is formed in a lattice shape on the wafer surface, and a scribe region 24 for cutting the chip is formed around the LSI chip 21. Although not shown, the LSI chip 21 is formed with a circuit element such as a transistor and an electrode terminal 22 connected to the circuit element or an electrode terminal 22 not connected to the circuit element.

  A seal ring 23 is formed along the outer periphery of the LSI chip. A scribe TEG 25 is formed in a scribe region outside the LSI chip. An evaluation element is formed in the scribe TEG 25, and an electrode terminal for connecting the evaluation element Is not formed. The evaluation element in the scribe TEG 25 is connected to the electrode terminal 22 in the LSI chip 21.

  As shown in FIG. 4, 27 is an LSI chip, 28a and 28b are electrode terminals on the LSI chip, 29 is a seal ring formed along the outer periphery of the LSI chip, 30 is a scribe TEG, and 31 is an LSI chip. Wirings for connecting the internal circuit and the electrode terminals, 32a and 32b are evaluation elements for the scribe TEG, 33 is a wiring for connecting the evaluation element for the scribe TEG and the electrode terminals on the LSI chip, and 34a and 34b are changeover switches.

  When the electrode terminal 28a connected to each internal circuit in the LSI chip 27 is connected to the evaluation element 32a of the scribe TEG, a changeover switch 34a connected to the evaluation element 32a of the scribe TEG is connected, and each internal terminal in the LSI chip 27 is connected. The changeover switch 34b connected to the circuit is disconnected, and the input / output signals are controlled by the changeover switches 34a and 34b to perform a predetermined measurement. That is, either the evaluation element 32a of the scribe TEG or each internal circuit in the LSI chip 27 is selected by the changeover switches 34a and 34b. The changeover switches 34a and 34b are composed of an input impedance control circuit and an output impedance control circuit.

  When the electrode terminal 28b not connected to each internal circuit on the LSI chip 27 and the evaluation element 32b of the scribe TEG are connected, the changeover switches 34a and 34b are not necessary and are directly connected to the electrode terminal 28b of the LSI chip. The

  Further, the wiring 33 that connects the evaluation elements 32 a and 32 b of the scribe TEG and the electrode terminals 28 a and 28 b on the LSI chip is formed of aluminum wiring, and is the outermost of the seal ring 29 formed along the outer periphery of the LSI chip 27. Since the layout extends over the aluminum wiring in the upper layer, the aluminum wiring layer in the uppermost layer of the seal ring 29 is cut near the connection wiring 33 straddling the seal ring 29. Thereby, the electrode terminals 28a and 28b in the LSI chip 27 and the evaluation elements 32a and 32b in the scribe TEG are portions where the uppermost layer wiring of the seal ring 29 is partially cut using the uppermost layer wiring of the LSI chip. Is electrically connected through.

  According to the present embodiment, by connecting the evaluation element in the scribe TEG formed on the scribe region to the electrode terminal in the LSI chip, the electrode terminal in the scribe TEG formed on the scribe region to be cut is cut. Therefore, the evaluation element area and the number of evaluation elements in the scribe TEG can be increased without increasing the area of the scribe region, and the scribe region area can be reduced at the same time. The cost can be increased and the cost can be reduced.

  In addition, there is no electrode terminal occupying a large area of the metal material in the scribe TEG formed on the scribe region to be cut, so that prevention of chip contamination from the metal film by cutting the scribe region during dicing is improved.

  In the second embodiment, at least one of the evaluation elements in the scribe TEG is electrically connected to the electrode terminal in the LSI chip, and the other evaluation elements are the same as in the first embodiment. You may connect to the electrode terminal in scribe TEG. At least one of the electrode terminals in the LSI chip is electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip, and the other electrode terminals in the LSI chip are connected to the LSI chip. You may make it the structure connected to an internal circuit or not connected.

  The semiconductor device of the present invention realizes reduction of LSI chip area and cost reduction, and is useful for miniaturization of LSI chips.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 1 is an enlarged plan view of a main part of an LSI chip and a scribe TEG of a semiconductor device according to a first embodiment of the present invention. It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention. It is a principal part enlarged plan view of SI chip and scribe TEG of a semiconductor device concerning a 2nd embodiment of the present invention. It is a top view of the conventional semiconductor device. It is a principal part enlarged plan view of SI chip and scribe TEG of the conventional semiconductor device.

Explanation of symbols

1, 8, 21, 27, 40, 46 LSI chip 2, 9, 22, 28a, 28b, 41, 47 Electrode terminals 3, 10, 23, 29, 42, 48 on the LSI chip Along the outer periphery of the LSI chip Seal ring 4, 24, 43 formed Scribe area 5, 11, 25, 30, 44, 49 Scribe TEG
6, 12a, 12b, 45, 50 Scribing TEG electrode terminals 7, 16 Wirings 13, 32a, 32b, 52 for connecting the scribing TEG electrode terminals to the inspection circuit used for the inspection of each internal circuit in the LSI chip Evaluation elements 14, 31, 51 Wirings 15, 53 for connecting each internal circuit in the LSI chip and electrode terminals Evaluation lines for scribe TEGs, wirings 17, 34a, 34b for connecting the electrode terminals to the evaluation elements 26, 33 Evaluation of scribe TEGs Wiring that connects the element and the electrode terminal on the LSI chip

Claims (12)

An LSI chip formed by integrating an internal circuit composed of semiconductor elements and an inspection circuit used for the inspection of the internal circuit;
A scribe TEG formed on a scribe region around the LSI chip and having an evaluation element and an electrode terminal;
At least one of electrode terminals in the scribe TEG is electrically connected to an evaluation element in the scribe TEG and an inspection circuit in the LSI chip.   2. The semiconductor device according to claim 1, wherein at least one of the electrode terminals in the scribe TEG is electrically connected only to an inspection circuit in the LSI chip.   An electrode terminal in the scribe TEG electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip is connected to the evaluation element in the scribe TEG or the inspection circuit in the LSI chip by a changeover switch. The semiconductor device according to claim 1, which is connected to any one of the above.   The semiconductor device according to claim 2, wherein an electrode terminal in the scribe TEG that is electrically connected only to the inspection circuit in the LSI chip is directly electrically connected to the inspection circuit.   The electrode terminal in the scribe TEG and the inspection circuit in the LSI chip partially use the uppermost layer wiring of the LSI chip, and partially connect the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip. The semiconductor device according to claim 1, 2, 3, or 4, which is electrically connected through the cut portion. An LSI chip in which internal circuits made of semiconductor elements are integrated and formed with electrode terminals;
A scribe TEG formed on a scribe region around the LSI chip and formed with an evaluation element;
At least one of the evaluation elements in the scribe TEG is electrically connected to an electrode terminal in the LSI chip ,
The electrode terminal in the LSI chip and the evaluation element in the scribe TEG use the uppermost layer wiring of the LSI chip, and partially the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip. A semiconductor device, wherein the semiconductor device is electrically connected through the cut portion . All the evaluation elements in the scribe TEG are electrically connected to electrode terminals in the LSI chip,
The semiconductor device according to claim 6, wherein no electrode terminal exists in the scribe TEG. An LSI chip in which an internal circuit made of semiconductor elements and an inspection circuit used for inspection of the internal circuit are integrated and formed with electrode terminals;
A scribe TEG formed on a scribe region around the LSI chip and formed with an evaluation element;
At least one of the electrode terminals in the LSI chip is electrically connected to an evaluation element in the scribe TEG and an inspection circuit in the LSI chip.   The semiconductor device according to claim 8, wherein at least another one of the electrode terminals in the LSI chip is electrically connected only to an evaluation element in the scribe TEG.   The evaluation element in the scribe TEG and the inspection circuit in the LSI chip are electrically connected to the evaluation element in the scribe TEG and the inspection circuit in the LSI chip by means of a changeover switch. The semiconductor device according to claim 8, connected to any one of the above.   The semiconductor device according to claim 9, wherein an electrode terminal in the LSI chip that is electrically connected only to the evaluation element in the scribe TEG is directly electrically connected to the evaluation element. The electrode terminal in the LSI chip and the evaluation element in the scribe TEG use the uppermost layer wiring of the LSI chip, and partially the uppermost layer wiring of the seal ring formed along the outer periphery of the LSI chip. The semiconductor device according to claim 8 , 9, 10, or 11, which is electrically connected through the cut portion.

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