JP4103373B2 - Electroluminescence display device and method of manufacturing electroluminescence display device - Google Patents

Electroluminescence display device and method of manufacturing electroluminescence display device Download PDF

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JP4103373B2
JP4103373B2 JP2001342896A JP2001342896A JP4103373B2 JP 4103373 B2 JP4103373 B2 JP 4103373B2 JP 2001342896 A JP2001342896 A JP 2001342896A JP 2001342896 A JP2001342896 A JP 2001342896A JP 4103373 B2 JP4103373 B2 JP 4103373B2
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thin film
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film transistor
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JP2003150079A (en
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亜希子 中村
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は、エレクトロルミネッセンス素子及び薄膜トランジスタを備えたエレクトロルミネッセンス表示装置に関するものであり、特にポリシリコン薄膜トランジスタを用いた周辺駆動回路を内蔵した薄膜トランジスタアレイ及びアクティブマトリックス型エレクトロルミネッセンス表示装置に関するものである。
【０００２】
【従来の技術】
近年、エレクトロルミネッセンス（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ：以下、ＥＬと称する。）素子を用いたＥＬ表示装置が、ＣＲＴやＬＣＤに代わる表示装置として注目されている。特に、ＥＬ素子を駆動させるスイッチング素子として薄膜トランジスタ（Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ：以下ＴＦＴと称する。）を用いたアクティブマトリックス型ＥＬ表示装置の開発が活発に進めらている。
【０００３】
図３に一般的な従来の有機ＥＬ表示装置の構成図の一例を示す。同図中、１はゲート信号線、２はソース信号線、３は駆動電源線で、ゲート信号線１とソース信号線２及び駆動電源線３が交差する表示画面領域１１にはマトリックス状に画素トランジスタ４ａ及び４ｂと図中には示していないが蓄積容量等が配置されている。また、表示画面領域１１の周辺には、ゲート線駆動回路７及びソース線駆動回路８が配置されている。
【０００４】
まず、表示画面領域１１について説明する。１表示画素には、スイッチング素子である画素トランジスタ４ａと、有機ＥＬ素子を駆動する画素トランジスタ４ｂとが備えられている。スイッチング素子である画素トランジスタ４ａはソース信号線２と有機ＥＬ素子を駆動する画素トランジスタ４ｂに接続され、有機ＥＬ素子を駆動する画素トランジスタ４ｂは有機ＥＬ素子を駆動する駆動電源線３と後述の有機ＥＬ素子５の陽極５ａに接続されている。また、画素トランジスタ４ａ及び４ｂ上の表示画素領域１１には、開口率を向上させるために表面を平坦にする平坦化膜６が全面に設けられている。
【０００５】
次に、有機ＥＬ素子について説明する。有機ＥＬ素子５は、平坦化膜６上に設けられたＩＴＯ（Ｉｎｄｉｕｍ Ｔｈｉｎ Ｏｘｉｄｅ）からなる透明電極（有機ＥＬ素子の陽極）５ａ、ホール輸送層，発光層、電子輸送層（図示せず）及び陰極５ｂから構成される。有機ＥＬ素子５は、陽極５ａから注入されたホールと陰極５ｂから注入された電子が発光層内部で再結合し、発光層を形成する有機分子を励起する。この励起されたエネルギーが放射される過程で発光層から光が放たれ、この光が陽極５ａから絶縁性基板を介して外部へ放出され、発光されるものである。有機ＥＬ素子５の陽極５ａは各画素毎に形成され、陰極５ｂは表示画面領域１１と後述の周辺駆動回路領域１２を含む有機ＥＬ表示基板の全面に形成されている。
【０００６】
次に、周辺駆動回路領域１２について説明する。周辺駆動回路領域１２は、ゲート線駆動回路７とソース線駆動回路８で構成され、それぞれＣＭＯＳトランジスタの組み合わせで構成されている。ゲート線駆動回路７（回路は一部のみ図示）はゲート信号線１に接続されているが、ここではゲート線駆動回路７の内部構成等の説明は省略する。一方、ソース線駆動回路８はソース信号線２に接続されている。ソース信号線２は、ソース信号書き込みトランジスタであるトランスファゲートトランジスタ９ａに接続され、シフトレジスタ部９ｂからの制御信号により、トランスファゲートトランジスタ９ａが動作し、信号配線１０からのソース信号がソース信号線２に書き込まれる構成になっている。信号配線１０は白黒表示パネルでは図３に示したように１本であるが、カラー表示パネルではＲ，Ｇ，Ｂの３色に対応した３本の信号配線が必要である。一方、周辺駆動回路領域１２には、前述の平坦化膜６は配置しない。これは、平坦化膜６が周辺駆動回路上の全面に存在すると、平坦化膜６を通して有機ＥＬ素子５に水分が進入し、有機ＥＬ素子５が劣化するためである。
【０００７】
以上のような薄膜トランジスタ回路基板に周辺部材を加えて、有機ＥＬ表示装置が構成される。
【０００８】
【発明が解決しようとする課題】
しかしながら、前記のような有機ＥＬ表示装置では、周辺駆動回路領域に有機ＥＬ素子の陰極が全面に配置されるが、一方で平坦化膜は配置されない構成となっている。従って、周辺駆動回路上を覆う有機ＥＬ素子の陰極によって周辺駆動回路上の寄生容量が増大し、周辺駆動回路の駆動能力が著しく減少してしまう。
【０００９】
そこで、本発明は、周辺駆動回路領域上に有機ＥＬ素子の陰極と平坦化膜の両方を配置して、周辺駆動回路上と表示画面領域上の平坦化膜を分離するか、有機ＥＬ素子の陰極と平坦化膜の両方を配置しないようにすることによって、周辺駆動回路上の寄生容量を減らし、周辺駆動回路の駆動能力の低下を抑制できる有機ＥＬ表示装置を提供することを目的とする。
【００１０】
【課題を解決するための手段】
前記課題を解決するために、本発明の請求項１記載のＥＬ表示装置は、絶縁性基板上に、陰極，発光層及び陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを備えたエレクトロルミネッセンス表示装置であって、前記表示画素領域には前記平坦化膜と前記陰極の両方が設けられており、前記周辺駆動回路領域には前記平坦化膜と前記陰極の両方が設けられていないことを特徴とする。また、本発明の請求項２記載のＥＬ表示装置の製造方法は、絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置の製造方法であって、前記表示画素領域および前記周辺駆動領域のうち、前記表示画素領域にのみ、前記平坦化膜と前記陰極の両方を設けることを特徴とする。本発明によれば、周辺駆動回路上に陰極と平坦化膜の両方を形成しないことで周辺駆動回路上の寄生容量が減り、周辺駆動回路の駆動能力の低下を抑制することできる。
【００１１】
本発明の請求項３記載のＥＬ表示装置は、絶縁性基板上に、陰極，発光層及び陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを備えたエレクトロルミネッセンス表示装置であって、前記表示画素領域及び前記周辺駆動回路領域には前記平坦化膜と前記陰極の両方が設けられ、前記表示画素領域上の平坦化膜と前記周辺駆動回路領域上の平坦化膜は前記表示画素領域と前記周辺駆動回路領域との間で分離されていることを特徴とする。また、本発明の請求項４記載のＥＬ表示装置の製造方法は、絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置の製造方法であって、前記表示画素領域及び前記周辺駆動回路領域には前記平坦化膜と前記陰極の両方を、前記平坦化膜が前記表示画素領域と前記周辺駆動回路領域との間で分離されるように設けることを特徴とする。本発明によれば、周辺駆動回路上に陰極と平坦化膜の両方を形成することで周辺駆動回路上の寄生容量が減り、周辺駆動回路の駆動能力の低下を抑制することできる。
【００１２】
【発明の実施の形態】
以下に、本発明の実施の形態について図１及び図２を用いて説明する。図１及び図２は、それぞれ（実施の形態１）及び（実施の形態２）を説明するための有機ＥＬ表示装置の簡単な構成図であり、全図を通して同一符号は同一対象物を示すものとする。
【００１３】
（実施の形態１）
以下に、本発明の一実施例として請求項１に記載された発明の実施の形態について説明する。
【００１４】
図１は本発明の有機ＥＬ表示装置の簡単な構成図である。なお、本発明の表示画面領域１１の画素トランジスタ４ａ及び４ｂの構成や、周辺駆動回路領域１２のＣＭＯＳトランジスタの構成については、従来の構成と同じであるので、説明は省略する。
【００１５】
有機ＥＬ表示装置は、絶縁性基板上に、画素トランジスタ４ａ及び４ｂからなる表示画面領域１１と、画素トランジスタ４ａ及び４ｂを駆動する、ＣＭＯＳトランジスタで構成されたゲート線駆動回路７及びソース線駆動回路８からなる周辺駆動回路領域１２とで構成されている。画素トランジスタ４ａ及び４ｂは、ゲート線駆動回路７に接続されたゲート信号線１、ソース線駆動回路８に接続されたソース信号線２及び有機ＥＬ素子５を駆動するための駆動電源線３の交差部に配置され、画素トランジスタ４ａ及び４ｂ上には平坦化膜６を介して有機ＥＬ素子５がマトリックス状に配置されている。有機ＥＬ素子５は、平坦化膜６上に設けられたＩＴＯ（Ｉｎｄｉｕｍ Ｔｈｉｎ Ｏｘｉｄｅ）からなる透明電極（有機ＥＬ素子の陽極）５ａ、ホール輸送層，発光層、電子輸送層（図示せず）及び陰極５ｂから構成される。有機ＥＬ素子５の陽極５ａは各画素毎に形成され、陰極５ｂは画素領域全面に形成されている。
【００１６】
次に、平坦化膜６と有機ＥＬ素子５の陰極５ｂの配置について説明する。平坦化膜６は、表示画面領域１１には全面に形成し、周辺駆動回路領域１２には形成しない。具体的には、例えば、平坦化膜を全面に塗布した後、露光・現像することにより、周辺駆動回路領域１２のみ除去する。一方、有機ＥＬ素子の陰極５ｂについても、表示画面領域１１には全面に形成し、周辺駆動回路領域１２には形成しない。陰極５ｂは、周辺駆動回路領域１２をマスキングしたメタルマスク等を用いることにより、表示画面領域１１上にのみ蒸着法等にて形成する。
【００１７】
このように、周辺駆動回路領域１２上に有機ＥＬ素子の陰極と平坦化膜の両方を配置しないようにすることによって、周辺駆動回路上の寄生容量を減らすことができ、周辺駆動回路の駆動能力の低下を抑制できる。
【００１８】
なお、上述に実施の形態において、周辺駆動回路領域１２とは表示画面領域１１の画素トランジスタ４ａ及び４ｂに信号を供給するためのゲート線駆動回路７、ソース線駆動回路８及び外部回路（図示せず）からゲート線駆動回路７及びソース線駆動回路８へ信号を供給するためのバス配線部から構成される領域のことをいう。また、表示画面領域１１とは、ゲート信号線１、ソース信号線２及び駆動電源線３の交差部にマトリックス状に配置された画素トランジスタ４ａ及び４ｂから構成される領域のことをいう。
【００１９】
また、有機ＥＬ素子５の陰極５ｂ及び平坦化膜６の端面は、周辺駆動回路領域１２と表示画面領域１２の間のどの位置に形成されてもよく、周辺駆動回路領域１２にさえ形成されていなければよい。
【００２０】
（実施の形態２）
以下に、本発明の一実施例として請求項２に記載された発明の実施の形態について説明する。
【００２１】
図２は本発明の有機ＥＬ表示装置の簡単な構成図である。なお、本発明の表示画面領域の画素トランジスタの構成や、周辺駆動回路領域の薄膜トランジスタの構成については、従来の構成及び実施の形態１と同じであるので、説明は省略する。
【００２２】
有機ＥＬ表示装置における表示画素領域１１と周辺駆動回路領域１２及びそれらを構成するトランジスタ４ａ，４ｂ，９の配置については、実施の形態１と同様であるが、平坦化膜６と有機ＥＬ素子５の陰極５ｂの配置が異なる。平坦化膜６は、表示画面領域１１に全面に形成し、周辺駆動回路領域１２にも全面に形成する。ただし、表示画面領域１１の平坦化膜６と周辺駆動回路領域１２の平坦化膜６は、表示画面領域１１と周辺駆動回路領域１２の間で分離する。これは、前述のように平坦化膜６が周辺駆動回路領域１２と表示画素領域１１の全面に分離されずに存在すると、平坦化膜６を通して有機ＥＬ素子５に水分が進入し、有機ＥＬ素子５が劣化するためである。本発明のように、平坦化膜６を表示画面領域１１と周辺駆動回路領域１２の間で分離しておけば、周辺駆動回路領域１２上に平坦化膜が存在しても、有機ＥＬ素子５が劣化することはない。一方、有機ＥＬ素子の陰極５ｂについても、表示画面領域１１に全面に形成し、周辺駆動回路領域１２にも全面に形成する。
【００２３】
このように、周辺駆動回路領域上に平坦化膜を配置した上で有機ＥＬ素子の陰極を配置するようにすることによって、周辺駆動回路上に有機ＥＬ素子の陰極を配置しても寄生容量が増加することなく、周辺駆動回路の駆動能力は低下しない。
【００２４】
なお、上述に実施の形態において、周辺駆動回路領域１２とは表示画面領域１１の画素トランジスタ４ａ及び４ｂに信号を供給するためのゲート線駆動回路７、ソース線駆動回路８及び外部回路（図示せず）からゲート線駆動回路７及びソース線駆動回路８へ信号を供給するためのバス配線部から構成される領域のことをいう。また、表示画面領域１１は、ゲート信号線１、ソース信号線２及び駆動電源線３の交差部にマトリックス状に配置された画素トランジスタ４ａ及び４ｂから構成される領域のことをいう。また、有機ＥＬ素子５の陰極５ｂ及び平坦化膜６の端面は、周辺駆動回路領域を完全に覆う形であれば、どの位置に形成されていてもかまわない。
【００２５】
【発明の効果】
以上のように、本発明の有機ＥＬ表示装置によれば、周辺駆動回路領域上に有機ＥＬ素子の陰極と平坦化膜の両方を配置して、周辺駆動回路上の平坦化膜と表示画面領域上の平坦化膜とを分離するか、有機ＥＬ素子の陰極と平坦化膜の両方を配置しないようにすることによって、周辺駆動回路上の寄生容量が減少し、周辺駆動回路の駆動能力の低下を抑制できた。
【図面の簡単な説明】
【図１】本発明の（実施の形態１）を説明する有機ＥＬ表示装置の構成図
【図２】本発明の（実施の形態２）を説明する有機ＥＬ表示装置の構成図
【図３】従来の有機ＥＬ表示装置を説明する構成図
【符号の説明】
１ ゲート信号線
２ ソース信号線
３ 駆動電源線
４ａ、４ｂ 画素トランジスタ
５ 有機ＥＬ素子
５ａ 陽極
５ｂ 陰極
６ 平坦化膜
７ ゲート線駆動回路
８ ソース線駆動回路
９ａ トランスファーゲートトランジスタ
９ｂ シフトレジスタ部
１０ 信号配線
１１ 表示画面領域
１２ 周辺駆動回路領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electroluminescence display device including an electroluminescence element and a thin film transistor, and more particularly to a thin film transistor array having a peripheral driving circuit using a polysilicon thin film transistor and an active matrix electroluminescence display device.
[0002]
[Prior art]
In recent years, an EL display device using an electroluminescence (hereinafter referred to as EL) element has attracted attention as a display device that replaces a CRT or an LCD. In particular, active matrix EL display devices using a thin film transistor (hereinafter referred to as TFT) as a switching element for driving an EL element are being actively developed.
[0003]
FIG. 3 shows an example of a configuration diagram of a general conventional organic EL display device. In the figure, reference numeral 1 is a gate signal line, 2 is a source signal line, 3 is a drive power line, and the display screen region 11 where the gate signal line 1 intersects with the source signal line 2 and the drive power line 3 is arranged in a matrix. Although not shown in the figure, storage capacitors and the like are arranged in the transistors 4a and 4b. A gate line driving circuit 7 and a source line driving circuit 8 are arranged around the display screen area 11.
[0004]
First, the display screen area 11 will be described. One display pixel includes a pixel transistor 4a that is a switching element and a pixel transistor 4b that drives an organic EL element. The pixel transistor 4a, which is a switching element, is connected to the source signal line 2 and a pixel transistor 4b that drives the organic EL element. The pixel transistor 4b that drives the organic EL element includes a drive power supply line 3 that drives the organic EL element, It is connected to the anode 5 a of the EL element 5. Further, in the display pixel region 11 on the pixel transistors 4a and 4b, a flattening film 6 for flattening the surface is provided over the entire surface in order to improve the aperture ratio.
[0005]
Next, the organic EL element will be described. The organic EL element 5 includes a transparent electrode (anode of the organic EL element) 5a made of ITO (Indium Thin Oxide) 5a, a hole transport layer, a light emitting layer, an electron transport layer (not shown) provided on the planarizing film 6. It is comprised from the cathode 5b. In the organic EL element 5, holes injected from the anode 5a and electrons injected from the cathode 5b are recombined inside the light emitting layer to excite organic molecules forming the light emitting layer. Light is emitted from the light emitting layer in the process of emitting this excited energy, and this light is emitted from the anode 5a to the outside through the insulating substrate to emit light. The anode 5a of the organic EL element 5 is formed for each pixel, and the cathode 5b is formed on the entire surface of the organic EL display substrate including the display screen region 11 and a peripheral drive circuit region 12 described later.
[0006]
Next, the peripheral drive circuit region 12 will be described. The peripheral drive circuit region 12 is composed of a gate line drive circuit 7 and a source line drive circuit 8, each composed of a combination of CMOS transistors. Although the gate line driving circuit 7 (only part of the circuit is shown) is connected to the gate signal line 1, the description of the internal configuration of the gate line driving circuit 7 is omitted here. On the other hand, the source line driving circuit 8 is connected to the source signal line 2. The source signal line 2 is connected to a transfer gate transistor 9a which is a source signal writing transistor, the transfer gate transistor 9a is operated by a control signal from the shift register unit 9b, and the source signal from the signal wiring 10 is the source signal line 2 It is configured to be written to. In the monochrome display panel, there is one signal wiring 10 as shown in FIG. 3, but in the color display panel, three signal wirings corresponding to the three colors R, G, and B are required. On the other hand, the above-described planarization film 6 is not disposed in the peripheral drive circuit region 12. This is because if the planarizing film 6 is present on the entire surface of the peripheral drive circuit, moisture enters the organic EL element 5 through the planarizing film 6 and the organic EL element 5 deteriorates.
[0007]
An organic EL display device is configured by adding peripheral members to the above-described thin film transistor circuit substrate.
[0008]
[Problems to be solved by the invention]
However, in the organic EL display device as described above, the cathode of the organic EL element is disposed on the entire surface in the peripheral drive circuit region, but on the other hand, the planarizing film is not disposed. Therefore, the parasitic capacitance on the peripheral drive circuit is increased by the cathode of the organic EL element covering the peripheral drive circuit, and the drive capability of the peripheral drive circuit is significantly reduced.
[0009]
Therefore, in the present invention, both the cathode and the planarization film of the organic EL element are arranged on the peripheral drive circuit region, and the planarization film on the peripheral drive circuit and the display screen region is separated, or the organic EL element It is an object of the present invention to provide an organic EL display device that can reduce parasitic capacitance on the peripheral drive circuit and suppress a decrease in drive capability of the peripheral drive circuit by not arranging both the cathode and the planarizing film.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an EL display device according to claim 1 of the present invention supplies an electroluminescence element having a cathode, a light emitting layer and an anode on an insulating substrate, and supplies a signal to the electroluminescence element. A display pixel region having a first thin film transistor group, a peripheral driver circuit region having a second thin film transistor group for driving the first thin film transistor group around the display pixel region, and the first and second An electroluminescence display device comprising a flattening film for flattening a thin film transistor group, wherein both the flattening film and the cathode are provided in the display pixel region, and the peripheral drive circuit region is provided in the peripheral drive circuit region. Both the planarizing film and the cathode are not provided. According to a second aspect of the present invention, there is provided an EL display device manufacturing method comprising: an electroluminescence element having a cathode, a light emitting layer, and an anode on an insulating substrate; and a first signal for supplying a signal to the electroluminescence element. A display pixel region including a thin film transistor group; a peripheral driver circuit region including a second thin film transistor group for driving the first thin film transistor group around the display pixel region; and the first and second thin film transistor groups. A method of manufacturing an electroluminescence display device comprising a planarizing film for planarizing both of the planarizing film and the cathode only in the display pixel region of the display pixel region and the peripheral drive region. It is characterized by providing. According to the present invention, since both the cathode and the planarizing film are not formed on the peripheral drive circuit, the parasitic capacitance on the peripheral drive circuit is reduced, and a decrease in drive capability of the peripheral drive circuit can be suppressed.
[0011]
The EL display device according to claim 3 of the present invention includes an electroluminescent element including a cathode, a light emitting layer, and an anode on an insulating substrate, and a first thin film transistor group for supplying a signal to the electroluminescent element. A display pixel region, a peripheral driver circuit region having a second thin film transistor group for driving the first thin film transistor group around the display pixel region, and a flat surface for flattening the first and second thin film transistor groups An electroluminescence display device including a planarization film, wherein both the planarization film and the cathode are provided in the display pixel region and the peripheral drive circuit region, and the planarization film on the display pixel region and the The planarization film on the peripheral driver circuit region is separated between the display pixel region and the peripheral driver circuit region. According to a fourth aspect of the present invention, there is provided an EL display device manufacturing method comprising: an electroluminescence element having a cathode, a light emitting layer, and an anode on an insulating substrate; and a first signal for supplying a signal to the electroluminescence element. A display pixel region including a thin film transistor group; a peripheral driver circuit region including a second thin film transistor group for driving the first thin film transistor group around the display pixel region; and the first and second thin film transistor groups. And a planarizing film for planarizing the display, wherein the planarizing film and the cathode are provided in the display pixel region and the peripheral driving circuit region, and the planarizing film is provided with the planarizing film. The display pixel region is provided so as to be separated from the peripheral driver circuit region. According to the present invention, by forming both the cathode and the flattening film on the peripheral drive circuit, the parasitic capacitance on the peripheral drive circuit is reduced, and a decrease in the drive capability of the peripheral drive circuit can be suppressed.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2 are simple configuration diagrams of an organic EL display device for explaining (Embodiment 1) and (Embodiment 2), respectively, and the same reference numerals denote the same objects throughout the drawings. And
[0013]
(Embodiment 1)
An embodiment of the invention described in claim 1 will be described below as an example of the present invention.
[0014]
FIG. 1 is a simple configuration diagram of an organic EL display device of the present invention. The configuration of the pixel transistors 4a and 4b in the display screen region 11 of the present invention and the configuration of the CMOS transistor in the peripheral drive circuit region 12 are the same as those in the conventional configuration, and a description thereof will be omitted.
[0015]
The organic EL display device includes a display screen region 11 including pixel transistors 4a and 4b and a gate line driving circuit 7 and a source line driving circuit configured by CMOS transistors that drive the pixel transistors 4a and 4b on an insulating substrate. The peripheral drive circuit region 12 is composed of eight. The pixel transistors 4 a and 4 b are crossed by a gate signal line 1 connected to the gate line drive circuit 7, a source signal line 2 connected to the source line drive circuit 8, and a drive power supply line 3 for driving the organic EL element 5. The organic EL elements 5 are arranged in a matrix form on the pixel transistors 4a and 4b with a planarizing film 6 interposed therebetween. The organic EL element 5 includes a transparent electrode (anode of the organic EL element) 5a made of ITO (Indium Thin Oxide) 5a, a hole transport layer, a light emitting layer, an electron transport layer (not shown) provided on the planarizing film 6. It is comprised from the cathode 5b. The anode 5a of the organic EL element 5 is formed for each pixel, and the cathode 5b is formed over the entire pixel region.
[0016]
Next, the arrangement of the planarizing film 6 and the cathode 5b of the organic EL element 5 will be described. The planarizing film 6 is formed on the entire surface of the display screen region 11 and is not formed on the peripheral drive circuit region 12. Specifically, for example, after applying a planarizing film to the entire surface, exposure and development are performed, so that only the peripheral drive circuit region 12 is removed. On the other hand, the cathode 5b of the organic EL element is also formed on the entire surface of the display screen region 11 and is not formed in the peripheral drive circuit region 12. The cathode 5b is formed only on the display screen region 11 by vapor deposition or the like by using a metal mask or the like that masks the peripheral drive circuit region 12.
[0017]
Thus, by not arranging both the cathode of the organic EL element and the planarizing film on the peripheral drive circuit region 12, the parasitic capacitance on the peripheral drive circuit can be reduced, and the drive capability of the peripheral drive circuit is reduced. Can be suppressed.
[0018]
In the embodiment described above, the peripheral drive circuit region 12 is the gate line drive circuit 7, the source line drive circuit 8 and an external circuit (not shown) for supplying signals to the pixel transistors 4a and 4b in the display screen region 11. A region composed of a bus wiring portion for supplying a signal to the gate line driving circuit 7 and the source line driving circuit 8. The display screen region 11 is a region composed of pixel transistors 4 a and 4 b arranged in a matrix at the intersection of the gate signal line 1, the source signal line 2, and the drive power supply line 3.
[0019]
Further, the cathode 5b of the organic EL element 5 and the end face of the planarizing film 6 may be formed at any position between the peripheral drive circuit region 12 and the display screen region 12, and even in the peripheral drive circuit region 12. If there is no.
[0020]
(Embodiment 2)
An embodiment of the invention described in claim 2 will be described below as an example of the present invention.
[0021]
FIG. 2 is a simple configuration diagram of the organic EL display device of the present invention. Note that the configuration of the pixel transistor in the display screen region and the configuration of the thin film transistor in the peripheral driver circuit region of the present invention are the same as those in the conventional configuration and the first embodiment, and thus description thereof is omitted.
[0022]
The arrangement of the display pixel region 11 and the peripheral drive circuit region 12 and the transistors 4a, 4b, and 9 constituting them in the organic EL display device is the same as that in the first embodiment, but the planarizing film 6 and the organic EL element 5 are arranged. The arrangement of the cathode 5b is different. The planarizing film 6 is formed on the entire surface of the display screen region 11 and also on the entire surface of the peripheral drive circuit region 12. However, the planarization film 6 in the display screen region 11 and the planarization film 6 in the peripheral drive circuit region 12 are separated between the display screen region 11 and the peripheral drive circuit region 12. As described above, when the planarizing film 6 is present on the entire surface of the peripheral drive circuit region 12 and the display pixel region 11 without being separated, moisture enters the organic EL element 5 through the planarizing film 6 and the organic EL element. This is because 5 deteriorates. If the planarization film 6 is separated between the display screen region 11 and the peripheral drive circuit region 12 as in the present invention, the organic EL element 5 can be used even if the planarization film exists on the peripheral drive circuit region 12. Will not deteriorate. On the other hand, the cathode 5b of the organic EL element is also formed on the entire surface of the display screen region 11 and also on the entire surface of the peripheral drive circuit region 12.
[0023]
As described above, by arranging the planarization film on the peripheral drive circuit region and then arranging the cathode of the organic EL element, the parasitic capacitance can be obtained even if the cathode of the organic EL element is arranged on the peripheral drive circuit. Without increasing, the drive capability of the peripheral drive circuit does not decrease.
[0024]
In the embodiment described above, the peripheral drive circuit region 12 is the gate line drive circuit 7, the source line drive circuit 8 and an external circuit (not shown) for supplying signals to the pixel transistors 4a and 4b in the display screen region 11. A region composed of a bus wiring portion for supplying a signal to the gate line driving circuit 7 and the source line driving circuit 8. The display screen region 11 is a region composed of pixel transistors 4 a and 4 b arranged in a matrix at intersections of the gate signal line 1, the source signal line 2, and the drive power supply line 3. Further, the cathode 5b of the organic EL element 5 and the end face of the planarizing film 6 may be formed at any position as long as they completely cover the peripheral drive circuit region.
[0025]
【The invention's effect】
As described above, according to the organic EL display device of the present invention, both the cathode of the organic EL element and the flattening film are arranged on the peripheral drive circuit region, and the flattening film and the display screen region on the peripheral drive circuit are arranged. By separating the upper planarizing film or not arranging both the cathode and the planarizing film of the organic EL element, the parasitic capacitance on the peripheral driving circuit is reduced and the driving capability of the peripheral driving circuit is lowered. Was able to be suppressed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an organic EL display device illustrating (Embodiment 1) of the present invention. FIG. 2 is a configuration diagram of an organic EL display device illustrating (Embodiment 2) of the present invention. Configuration diagram for explaining a conventional organic EL display device [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Gate signal line 2 Source signal line 3 Drive power supply line 4a, 4b Pixel transistor 5 Organic EL element 5a Anode 5b Cathode 6 Planarization film 7 Gate line drive circuit 8 Source line drive circuit 9a Transfer gate transistor 9b Shift register part 10 Signal wiring 11 Display screen area 12 Peripheral drive circuit area

Claims (4)

絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置であって、
前記表示画素領域には前記平坦化膜と前記陰極の両方が設けられており、前記周辺駆動回路領域には前記平坦化膜が設けられておらず、且つ前記周辺駆動回路領域には前記陰極が設けられていないことを特徴とするエレクトロルミネッセンス表示装置。An electroluminescent element comprising a cathode, a light emitting layer and an anode on an insulating substrate, a display pixel region comprising a first thin film transistor group for supplying a signal to the electroluminescent element, and the display pixel region around the display pixel region An electroluminescence display device comprising: a peripheral driver circuit region including a second thin film transistor group for driving a first thin film transistor group; and a planarizing film for planarizing the first and second thin film transistor groups. ,
Wherein the display pixel region is provided with both of the cathode and the planarization layer, wherein the peripheral driving circuit wherein the planarization layer is not provided in the region, and is in the peripheral drive circuit region and the negative electrode Is not provided. An electroluminescence display device characterized by that. 絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置の製造方法であって、
前記表示画素領域および前記周辺駆動領域のうち、前記表示画素領域にのみ前記平坦化膜を設け、且つ前記表示画素領域にのみ前記陰極を設けることを特徴とするエレクトロルミネッセンス表示装置の製造方法。An electroluminescent element comprising a cathode, a light emitting layer and an anode on an insulating substrate, a display pixel region comprising a first thin film transistor group for supplying a signal to the electroluminescent element, and the display pixel region around the display pixel region A method for manufacturing an electroluminescence display device, comprising: a peripheral driver circuit region including a second thin film transistor group for driving the first thin film transistor group; and a planarizing film for planarizing the first and second thin film transistor groups. Because
Production of the of the display pixel region and the peripheral driving region, the only pre-Symbol planarizing film in the display pixel area is provided, and the display electroluminescent display device, characterized in that only providing the negative electrode in the pixel region Method. 絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジスタ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置であって、
前記表示画素領域及び前記周辺駆動回路領域には前記平坦化膜と前記陰極の両方が設けられ、前記表示画素領域上の平坦化膜と前記周辺駆動回路領域上の平坦化膜は前記表示画素領域と前記周辺駆動回路領域との間で分離されていることを特徴とするエレクトロルミネッセンス表示装置。An electroluminescent element comprising a cathode, a light emitting layer and an anode on an insulating substrate, a display pixel region comprising a first thin film transistor group for supplying a signal to the electroluminescent element, and the display pixel region around the display pixel region An electroluminescence display device comprising: a peripheral driver circuit region including a second thin film transistor group for driving a first thin film transistor group; and a planarizing film for planarizing the first and second thin film transistor groups. ,
The display pixel region and the peripheral drive circuit region are provided with both the planarization film and the cathode, and the planarization film on the display pixel region and the planarization film on the peripheral drive circuit region are the display pixel region. And the peripheral drive circuit region are separated from each other. 絶縁性基板上に、陰極、発光層および陽極を備えたエレクトロルミネッセンス素子と、前記エレクトロルミネッセンス素子に信号を供給する第１の薄膜トランジス
タ群を備えた表示画素領域と、前記表示画素領域の周辺に前記第１の薄膜トランジスタ群を駆動する第２の薄膜トランジスタ群を備えた周辺駆動回路領域と、前記第１及び第２の薄膜トランジスタ群上を平坦化する平坦化膜とを具備するエレクトロルミネッセンス表示装置の製造方法であって、
前記表示画素領域及び前記周辺駆動回路領域には前記平坦化膜と前記陰極の両方を、前記平坦化膜が前記表示画素領域と前記周辺駆動回路領域との間で分離されるように設けることを特徴とするエレクトロルミネッセンス表示装置の製造方法。An electroluminescent element comprising a cathode, a light emitting layer and an anode on an insulating substrate, a display pixel region comprising a first thin film transistor group for supplying a signal to the electroluminescent element, and the display pixel region around the display pixel region A method for manufacturing an electroluminescence display device, comprising: a peripheral driver circuit region including a second thin film transistor group for driving the first thin film transistor group; and a planarizing film for planarizing the first and second thin film transistor groups. Because
In the display pixel region and the peripheral drive circuit region, both the planarization film and the cathode are provided so that the planarization film is separated between the display pixel region and the peripheral drive circuit region. A method for manufacturing an electroluminescent display device.
JP2001342896A 2001-11-08 2001-11-08 Electroluminescence display device and method of manufacturing electroluminescence display device Expired - Lifetime JP4103373B2 (en)

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