JP4100519B2 - Output circuit - Google Patents

Description

  The present invention relates to an output circuit, and more particularly to improvement of a data output circuit used in a semiconductor memory device.

  FIG. 86 is a block diagram schematically showing an overall configuration of a general dynamic semiconductor memory device. Referring to FIG. 86, the dynamic semiconductor memory device includes a memory cell array 900 in which dynamic memory cells MC are arranged in a matrix of rows and columns. In memory cell array 900, a word line WL is provided corresponding to each row of memory cells. Bit line pairs BL and ZBL are arranged corresponding to each column of memory cells MC. Memory cell MC is arranged corresponding to the intersection of one word line WL and a pair of bit lines BL and ZBL. FIG. 86 representatively shows one word line WL and a pair of bit lines BL and ZBL. Complementary data appear on the bit line BL and the complementary bit line ZBL.

  The dynamic semiconductor memory device further decodes the internal row address signal RA from the address buffer 902 and the address buffer 902 for generating the internal row address signal RA and the internal column address signal CA in accordance with the externally applied address signal Ad. Row decoder 904 for selecting a corresponding word line in cell array 900, and column decoder for decoding internal column address signal CA from address buffer 902 and generating a signal for selecting a corresponding column (bit line pair) in memory cell array 900 906 is included.

  Address buffer 902 is activated in response to internal row address strobe signal ZRAS, and latches applied address signal Ad to generate internal row address signal RA, and in response to internal column address strobe signal ZCAS. A column latch 907 for latching the applied address signal Ad and generating an internal column address signal CA is included.

  A row address signal and a column address signal are provided to the address buffer 902 in a time division multiplexed manner. Internal row address strobe signal ZRAS is generated from RAS buffer 910 receiving external row address strobe signal / RAS. Internal column address strobe signal ZCAS is activated in response to activation of internal row address strobe signal ZRAS, and is generated from CAS buffer 912 which takes in external column address strobe signal / CAS.

  The dynamic semiconductor memory device further includes a sense amplifier 914 that detects and amplifies data of a memory cell connected to a selected word line in the memory cell array 900, and a memory cell array in response to a column selection signal from the column decoder 906. IO gate 916 connecting the corresponding column (bit line pair) in 900 to internal data bus 915 is included. The operation of sense amplifier 914 is controlled by a clock control circuit 918 that generates a sense amplifier activation signal (not explicitly shown) at a predetermined timing in response to internal row address strobe signal ZRAS. This clock control circuit 918 also controls activation / deactivation of the row decoder 904.

  The semiconductor memory device further detects the change in the internal column address signal CA from the column latch 907, generates an address change detection signal φATD at the time of detection, and the internal column address strobe signal ZCAS from the CAS buffer 912. An input / output control circuit 922 for generating a timing control signal for determining input / output of data according to an external write / read instruction signal (write enable signal) / WE and an address change detection signal φATD, and an input / output control circuit 922 An input circuit 924 for transmitting internal write data to internal data bus 915 in accordance with external data D in accordance with a data write instruction signal (not explicitly shown), and internal data bus 915 in accordance with a data output permission signal from input / output control circuit 922 External read data from internal read data that appeared above An output circuit 926 that generates and outputs Q is included.

  Write enable signal / WE designates data writing when "L", and designates data reading operation when "H". Next, the operation will be briefly described.

  When external row address strobe signal / RAS attains "L" and internal row address strobe signal ZRAS from RAS buffer 910 attains "L" accordingly, a memory cycle starts. In response to “L” of the internal row address strobe signal ZRAS, the row latch 905 included in the address buffer 902 latches the address signal Ad to generate the internal address signal RA and supplies it to the row decoder 904. Clock control circuit 918 provides an activation signal to row decoder 904 in accordance with internal row address strobe signal ZRAS. Row decoder 904 decodes internal row address signal RA and selects a corresponding word line in memory cell array 900. As a result, the data of the memory cell connected to the selected word line is read to the corresponding bit line BL (or ZBL). Then, memory array 914 is activated in accordance with a sense amplifier activation signal (not shown explicitly) from clock control circuit 918, and the potential appearing on bit line pair BL and ZBL is differentially amplified.

  On the other hand, the external column address strobe signal / CAS becomes “L” after the fall of the external row address strobe signal / RAS and becomes “L” from the CAS buffer 912 enabled by the “L” internal row address strobe signal ZRAS. Internal column address strobe signal ZCAS is generated. In response to internal column address strobe signal ZCAS, column latch 907 latches applied address signal Ad to generate internal column address signal CA. Column decoder 906 decodes internal column address signal CA and generates a signal for selecting a column (bit line pair) in memory cell array 900. After the sense amplifier 914 senses and amplifies the memory cell data in each bit line pair, the IO gate 916 is turned on in response to a column selection signal from the column decoder 906, and the corresponding bit line pair is connected to the internal data bus 915. Connect to. Next, data is written or read via the input circuit 924 or the output circuit 926.

  FIG. 87 is a diagram illustrating a configuration of a 1-bit data output unit in the output circuit 926. When the semiconductor memory device shown in FIG. 86 is configured to input / output multi-bit data such as 4 bits and 8 bits, a plurality of input / output circuits shown in FIG. 87 are provided in accordance with the number of data bits.

  Referring to FIG. 87, output circuit 926 includes an inverter 5 for inverting data ZDD appearing on internal data bus line 915b, a 2-input AND circuit 3 receiving output permission signal OEM and the output of inverter 5, and an output. 2-input AND circuit 4 receiving permission signal OEM and internal read data ZDD, first output drive transistor 1 driving output node 6 to power supply potential Vcc level in response to the output of AND circuit 3, AND circuit 4 The second drive transistor 2 discharges the output node 6 to the ground potential GND level in response to the output of. Drive transistors 1 and 2 are both n-channel MOS transistors. Output permission signal OEM is generated in accordance with internal column address strobe signal ZCAS and address change detection signal φATD from input / output control circuit 922 shown in FIG. Next, the operation of the output circuit shown in FIG. 87 will be described with reference to FIG. 88 which is an operation waveform diagram thereof.

  When the internal column address strobe signal ZCAS becomes “L”, a signal in which the data and logic of the selected memory cell are inverted is transmitted onto the internal data bus line 915b after a predetermined period. Internal data bus line 915b is precharged to an intermediate potential during standby. FIG. 88 shows a state in which an “L” data signal appears on internal data bus line 915b.

  While the output permission signal OEM is “L”, the outputs of the AND circuits 3 and 4 are both “L”, and the drive transistors 1 and 2 are both off. In this state, output node 6 maintains the high impedance state (Hi-Z).

  When the output permission signal OEM becomes “H”, the AND circuits 3 and 4 are enabled. The data signal ZDD on the internal data bus line 915b is “H”, and the output of the inverter 5 is “L”. Therefore, in accordance with the “H” output permission signal OEM, the output of the AND circuit 4, that is, the potential of the node N2, becomes “H”, and the second drive transistor 2 is turned on. Output node 6 is discharged to ground potential level GND level via second drive transistor 2, and output data Q of "L" is output.

  When the data signal ZDD is “L”, in response to the rise of the output permission signal OEM, the output of the AND circuit 3, that is, the potential of the node N1, becomes “H”, and the first drive transistor 1 is turned on. As a result, the output node 6 is charged from the power supply potential Vcc level to a voltage level lower than the threshold voltage of the transistor 1, and the output data Q becomes “H”.

In a data output circuit, configurations that suppress generation of ringing and stably generate an output signal at high speed are disclosed in Patent Document 1 (Japanese Patent Laid-Open No. Sho 62-38617) and Patent Document 2 (Japanese Patent Laid-Open Publication No. Hei 2-). 32616) and Patent Document 3 (Japanese Patent Laid-Open No. 2-12867).
JP-A-62-38617 JP-A-2-32616 JP-A-2-12867

  Drive transistors 1 and 2 have a large current driving capability of, for example, several mA in order to charge / discharge external loads at high speed and output data at high speed. The semiconductor memory device is enclosed in a package. In this case, as shown in FIG. 89, the output node 6 is connected to a frame lead forming an output terminal via a bonding wire. In FIG. 89, these bonding wires and frame leads are shown as output terminals 930. Such bonding wires and frame leads have not only parasitic capacitance C but also parasitic inductance L. When a current change occurs in the parasitic inductance L, a voltage represented by the following equation is generated.

V = −L · di / dt
Here, di / dt represents the time differentiation of the current i flowing through the inductance L.

  When drive transistors 1 and 2 are both off, output node 6 is in a high impedance state. In this high impedance state, the potential level of the previous output data Q is held. Therefore, when the “L” data Q is output after the “H” output data Q is output, the output node 6 is connected to the drive transistor 2 having a large current driving capability, as shown in FIG. Therefore, ringing occurs at the output node 6.

  When the “H” data Q is output after the “L” output data Q is output, the output node 6 is charged via the drive transistor 1 having a large current driving capability. Even in this case, as shown in FIG. 90A, since a large current change occurs in the parasitic inductance L, an overshoot occurs.

  Unlike the configuration in which the output node 6 is maintained in the high impedance state, even when the output node 6 is held at the intermediate potential, the output node precharged to the intermediate potential is charged / discharged according to the logic of the data to be output. Since this charging / discharging is sometimes performed through the drive transistor 1 having a large current driving capability, ringing similarly occurs at the output node.

  When ringing such as overshoot or undershoot occurs, data cannot be read out until the output data is stabilized, resulting in a problem that the access time becomes long. If the amplitude at the time of occurrence of this undershoot is large, a large voltage is applied between the gate and drain of the output drive transistor 1 (node terminal connected to the output node 6). The problem of deterioration arises. The same applies to the drive transistor 2.

  In order to prevent the occurrence of ringing as described above, it is conceivable to drive the output node in two stages as shown in FIG. Here, FIG. 91 shows a configuration of a portion for discharging the output node in two stages.

  91, the output circuit includes drive transistors 2a and 2b provided in parallel between output node 6 and the ground potential node. Drive transistors 2a and 2b are formed of n-channel MOS transistors. The current driving capability of drive transistor 2a is made smaller than the current driving capability of drive transistor 2b. This is realized by adjusting the channel length or channel width of the transistor. The output of AND circuit 4 receiving output permission signal OEM and internal read data signal ZDD is applied to the gate of drive transistor 2a. In order to control on / off of drive transistor 2b, a delay stage 7 for delaying the potential on node N2 for a predetermined time, and an AND circuit 8 for receiving the output of delay stage 7 and the signal potential on node N2 are provided. The output of AND circuit 8 is applied to the gate of drive transistor 2b. The delay stage 7 includes an even number of inverters (four inverters in FIG. 91), and delays a given signal for a predetermined time. Next, the operation of the output circuit shown in FIG. 91 will be described with reference to FIG.

  When internal column address strobe signal ZCAS attains an active state “L”, a column selection operation is started and data of the selected memory cell is transmitted onto internal data bus line 915b. When the output permission signal OEM becomes “H”, the potential of the node N2 becomes “H”, the drive transistor 2a is turned on, and the output node 6 is slowly discharged. At this time, the output of the delay stage 7 is still at the low level, the potential of the node N3 is “L”, and the drive transistor 2b is in the off state.

  When the predetermined time elapses and the output of the delay stage 7 becomes “H”, the output of the AND circuit 8 becomes “H”, and the drive transistor 2b is turned on. Thereby, the output node 6 is discharged at high speed. When drive transistor 2b is turned on, the potential of output node 6 is sufficiently lowered, so that even if output node 6 is discharged at a high speed, ringing hardly occurs. This is because the maximum amplitude when the damped oscillation occurs in the RLC circuit is proportional to the voltage value when the rapid discharge is performed.

  In the dynamic semiconductor memory device, an operation mode called a static column mode is known. In this static column mode, as shown in the operation waveform diagram of FIG. 93, data is input / output randomly by inputting only the address signal to one row of memory cells designated by the row address signal X. Mode.

  That is, as shown in FIG. 93, the row address strobe signal ZRAS is first lowered to "L", the row address signal is taken in, and the word line is selected. Data of the memory cell connected to the selected word line is detected and amplified by a sense amplifier and latched. At this time, if the column address signal Y is input asynchronously and held for a predetermined time, the corresponding column address data is output. In this static column mode, column address strobe signal ZCAS has an output enable function without a column address latch instruction function, and is held at "L". In the static column mode, it is not necessary to toggle the column address strobe signal / CAS to fetch the column address signal, and data can be output at a high speed.

  However, in such a static column mode, as shown in FIG. 93, output permission signal OEM is held in the “H” state. Therefore, one of drive transistors 1 and 2a is in an on state, and output node 6 is held at “H” or “L”. Therefore, in this static column mode operation, when “L” data is output after “H” data is output, if the potential amplitude of the output node 6 increases and the delay time provided by the delay stage 7 is short. The problem of ringing occurs. If the delay time of the delay stage 7 is increased in order to prevent such ringing from occurring, the access time becomes longer, and the characteristics of the static column mode of high-speed access are lost.

  The delay stage is composed of an inverter. In general, a CMOS inverter is often used as such an inverter. The driving force of the MOS transistor is determined by its gate voltage. That is, if the operating power supply voltage of the inverter constituting the delay stage is increased, the operating speed of the inverter is increased and the delay time of the delay stage is shortened. Further, as the operating temperature increases, the operating speed of the MOS transistor decreases (due to an increase in threshold voltage and an increase in channel resistance value due to heat carrier generation). Therefore, if the operating temperature increases, the operating speed of the inverter constituting the delay stage becomes slow, and the delay time of the delay stage becomes long. As described above, when the delay times of the delay stages are different, the on-timing of the drive transistor 2b shown in FIG. 91 is different. In this case, if the delay time is short, the drive transistor 2b is turned on when the potential of the output node is not sufficiently lowered, and the output node 6 is discharged at a high speed, so that ringing occurs. At this time, when the power supply voltage increases or when the temperature is low, the driving capability of the output drive transistor also increases. Therefore, there arises a problem that ringing is more likely to occur.

  In the above-mentioned Patent Documents 1 to 3, although the configuration for adjusting the driving power of the output node according to the potential of the output node is shown, the transistor of the output circuit is controlled according to such power supply voltage and operating temperature. No consideration is given to how the driving force of the output node is adjusted when the operating characteristics change.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an output circuit that can stably output a signal at high speed without causing ringing.

  Another object of the present invention is to provide an output circuit in a semiconductor memory device that can stably output a data signal without increasing the access time.

An output circuit according to a first aspect of the present invention is an output circuit for outputting a logic signal corresponding to the logic of an input signal given to an input node to the output node, and in response to the input signal, A first drive element that drives the output node to a potential level corresponding to the logic of the input signal at a first speed ; and at least one MOS transistor that receives a control voltage at a gate, the gate-source of the MOS transistor and while the voltage decreases and the delay is large na Ru delay means of the input signal, in response to the output of the delay means, the logic to the corresponding potential levels of the input signal an output node at a faster than the first speed second speed And a second drive element that drives the input signal, and an adjustment unit that adjusts the length of the delay time that the delay unit gives to the input signal according to the operating temperature. This adjusting means outputs a control voltage for decreasing the gate-source voltage of the MOS transistor when the operating temperature is lowered.

In the output circuit according to the first aspect, the delay time of the delay means is adjusted such that the gate-source voltage of the MOS transistor decreases as the operation temperature decreases according to the control signal from the adjustment means. Is adjusted to increase as the value decreases . Since the delay time of the delay means is adjusted according to the operating conditions, the second driving element can be activated at an optimal timing regardless of the operating conditions, and an output signal is output at high speed without causing ringing. be able to.

[Embodiment 1]
FIG. 1 is a diagram showing a configuration of an output circuit according to a first embodiment of the present invention. FIG. 1 shows a portion for driving output node 6 to the ground potential level. If a configuration similar to the configuration shown in FIG. 1 is used for the portion where output node 6 is driven to power supply potential Vcc level, overshoot of the output node can be prevented.

  In FIG. 1, an output circuit 926 includes a two-input AND circuit 10 that receives an output permission signal OEM and a read data signal DD on the internal data bus line 915a, and a complementary internal read data on the output permission signal OEM and the internal data bus line 915b. AND circuit 11 receiving signal ZDD, first drive transistor 1 driving output node 6 to power supply potential Vcc level in response to the output of AND circuit 10, and output node 6 in response to the output of AND circuit 11 A drive transistor 2a for driving to the ground potential level and a drive transistor 2b provided in parallel with drive transistor 2a are included. The current driving capability of drive transistor 2a is made smaller than the current driving capability of drive transistor 2b. Drive transistors 1, 2a and 2b are both formed of n-channel MOS transistors. The difference in the current driving capability between the drive transistors 2a and 2b is realized by appropriately setting the size, the gate (channel) width, or the ratio between the gate width and the gate length.

  Output circuit 926 further receives an output of AND circuit 10, that is, an inversion delay circuit 15 that delays the signal potential of node N1 and inverts its logic, and a 2-input NOR that receives the signal on node N1 and the output of delay circuit 15. A circuit 16, an inverting delay circuit 17 that delays the output permission signal OEM for a predetermined time and inverts its logic, a two-input NOR circuit 18 that receives the output of the inverting delay circuit 17 and the output permission signal OEM, and a column address signal An inversion delay circuit 19 that delays the data output instruction signal DOT generated at the time of change and inverts its logic, a NOR circuit 20 that receives the output instruction signal DOT and the output of the inversion delay circuit 19, and NOR circuits 18 and 20 A two-input OR circuit 21 that receives the output of the NOR circuit 16 and a two-input NAND circuit that receives the output of the NOR circuit 16 and the output of the OR circuit Including the 2.

  The 2-input NOR circuit 16 generates a positive one-shot pulse signal having a time width determined by the delay time of the inverting delay circuit 15 when the potential of the node N1 falls from “H” to “L”. To do.

  The 2-input NOR circuit 18 generates a positive one-shot pulse signal having a time width determined by the delay time of the inverting delay circuit 17 when the output permission signal OEM changes from “H” to “L”. .

  The 2-input NOR circuit 20 generates a one-shot positive pulse signal having a time width determined by the delay time of the delay circuit 19 when the output instruction signal DOT changes from “H” to “L”. The output instruction signal DOT is generated in the form of a one-shot pulse that becomes “L” for a predetermined time when the column address signal changes.

  Output circuit 926 further includes a delay circuit 12 that delays an output of AND circuit 11, that is, a signal on node N2, for a predetermined time, a 2-input NAND circuit 13 that receives the signal on node N2 and the output of delay circuit 12, and NAND A two-input NAND circuit 14 that receives the output of the circuit 13 and the output of the NAND circuit 22 is included. When the output of the NAND circuit 14 is “H”, the drive transistor 2b is turned on. Next, the operation of the output circuit shown in FIG. 1 will be described with reference to FIG.

  Now, a data read operation when the selected memory cell stores data “L” will be described. When internal column address strobe signal ZCAS falls to "L" in the active state, internal column address signal Y1 is generated. When internal address signal Y1 is generated from the address buffer, address change detection signal φATD output from the address change detection circuit is generated in the form of a one-shot pulse. In accordance with the address change detection signal, the output instruction signal DOT becomes “L” for a predetermined period. In accordance with output instruction signal DOT, internal data bus lines 915a and 915b are once precharged to "L". In standby, output instruction signal OEM is at "L", nodes N1 and N2 are at "L", and drive transistors 1, 2a and 2b are all in an off state.

  In accordance with the one-shot output instruction signal DOT, a pulse having a time width of the delay time of the inverting delay circuit 19 is generated from the NOR circuit 20 and the output of the OR circuit 21 becomes “H”. At this time, the potential of the node N1 is still “L”, and the potential of the node N4 is still “H”. The output permission signal OEM is at “L”, and the potential of the node N5 is “H”. Therefore, even if the output instruction signal DOT is “L” for a predetermined period, the output of the NAND circuit 22 (the potential of the node N8) is “H” and does not change.

  At this time, the potential of the node N2 is “L”, the output of the NAND circuit 13 is “H”, and the output of the NAND circuit 14 (potential of the node N9) is “L”.

  When the output permission signal OEM becomes “H” in the active state, the potential of the node N1 becomes “L” and the potential of the node N2 becomes “H”. As a result, the drive transistor 1 maintains an off state. On the other hand, drive transistor 2a is turned on, and the potential of output node 6 is gently discharged to the ground potential level. When the delay time of the delay circuit 12 elapses, the output of the delay circuit 12 becomes “H” and the output of the NAND circuit 13 becomes “L”. As a result, the output of the NAND circuit 14 becomes “H”, and the drive transistor 2b is turned on. Drive transistor 2b discharges output node 6 to the ground potential level at high speed.

  When the external column address signal Ad changes, the output instruction signal DOT becomes “L” for a predetermined period accordingly. This operation mode is called a static column mode. When the output instruction signal DOT becomes “L”, it indicates that the data appearing at the output node 6 is invalidated in the next cycle. That is, the output instruction signal DOT can be said to be a signal indicating that the data appearing at the output node 6 at that time should be invalidated. In response to the transition of output instruction signal DOT to “L”, internal data lines 915a and 915b are both precharged to the ground potential level again. As a result, the potentials of nodes N1 and N2 both become "L", and drive transistors 1, 2a and 2b are turned off. After output instruction signal DOT falls to "L", a predetermined time (a time required until a bit line pair is selected in accordance with a column address signal and the selected data is read out to the internal data bus). After the elapse of time, the potentials of internal data bus lines 915a and 915b become “H” and “L”, respectively. As a result, drive transistor 1 is turned on, and output node 6 is charged to the level of power supply potential Vcc.

  When the internal column address strobe signal ZCAS becomes inactive “H”, the output permission signal OEM accordingly becomes “L”. In response to this, a one-shot pulse is generated from the NOR circuit 18. On the other hand, at this time, the potential of the node N1 also falls from "H" to "L", and the drive transistor 1 is turned off. In response to the fall of the potential of the node N1, the NOR circuit 16 generates a one-shot pulse signal on the node N4. The inverting delay circuit 15 is composed of, for example, a five-stage inverter, and the inverting delay circuit 17 is composed of, for example, a three-stage inverter circuit. The delay time of the inverting delay circuit 15 is the delay of the inverting delay circuit 17. Longer than time. Therefore, when the potential of the node N4 is “H”, the potential of the node N7 (the output of the OR circuit 21) becomes “H”, and is determined from the NAND circuit 22 to the node N8 by the delay time of the inverting delay circuit 17. A one-shot pulse signal of “L” having a certain time width is generated. In response, a one-shot pulse of “H” is generated on the node N9 from the NAND circuit 14, and the drive transistor 2b is turned on. Thereby, output node 6 is discharged from power supply potential Vcc level to ground potential level for a predetermined time, and the potential of output node 6 becomes an intermediate potential level between power supply potential Vcc and ground potential GND. The intermediate potential level of output node 6 is determined by the driving capability of drive transistor 2b, the external load, and the delay time of inverting delay circuit 17.

  As described above, since drive transistor 2b that discharges to the ground potential level is turned on for a predetermined time after the completion of data reading of "H", there is no configuration for holding the potential of output node 6 at an intermediate potential. Even in this case, the potential of the output node 6 becomes an intermediate potential level. Therefore, regardless of whether the data read in the next cycle is “H” or “L”, output node 6 is driven from the intermediate potential level, so that the output amplitude is small and ringing may occur. And a stable output signal Q can be obtained at high speed. By obtaining this high-speed and stable output signal Q, for example, ringing occurs at the output node 6 even when “L” data is output after “H” data is output in the static column mode. However, a stable output signal Q can be output.

  Here, by providing the configuration shown in FIG. 1 with respect to drive transistor 1, as shown by the broken line in FIG. 2, output node 6 is pulled up and set to an intermediate potential level after completion of “L” data reading. can do.

  FIG. 3 is a diagram showing a configuration of an output circuit when a control system is provided for reading data of both “H” and “L”. In FIG. 3, each of control blocks 40a and 40b includes NOR circuits 16, 18, and 20, OR circuit 21, NAND circuit 22, and inverting delay circuits 15, 17, and 19 shown in FIG. Delay circuits 12a and 12b correspond to delay circuit 12 shown in FIG. 1, NAND circuits 13a and 13b correspond to NAND circuit 13 shown in FIG. 1, and NAND circuits 14a and 14b correspond to NAND circuit 14 shown in FIG. Corresponding to

  Therefore, when the circuit configuration shown in FIG. 3 is used, as shown in FIG. 4, in the static column mode operation, the output node is driven to the intermediate potential in accordance with the output instruction signal DOT, and when the memory cycle is completed, the output instruction signal Output node 6 is driven to an intermediate potential according to the OEM. Therefore, in any case, since the output node 6 is driven from the intermediate potential to “H” or “L”, a stable output signal can be generated without causing ringing.

  FIG. 5 is a diagram showing a configuration of an output instruction signal and output permission signal generation system. The control signal generation system shown in FIG. 5 is included in the input / output control circuit shown in FIG.

  Referring to FIG. 5, the output control signal generation circuit is activated in response to internal row address strobe signal ZRAS, and generates a one-shot "L" pulse signal in response to address change detection signal φATD. Shot pulse generation circuit 50, delay circuit 51 delaying internal column address strobe signal ZCAS for a predetermined time, and one-shot pulse signal in response to the rise of output instruction signal DOT from one-shot pulse generation circuit 50 A shot pulse generation circuit 52, a gate circuit 57 that receives internal write enable signal ZWE and internal column address strobe signal ZCAS, and outputs an "H" signal when a data read operation is designated, and a one-shot pulse generation circuit 2-input NAN receiving the output of 52 and the output of the gate circuit 57 A circuit 55, an inverter circuit 54 for inverting the delayed column address strobe signal ZCASE from the delay circuit 51, and an “L” signal from the NAND circuit 55, which is set in response to the “L” signal from the inverter circuit 54. Flip-flop 56 that is reset in response to the above and an inverter circuit 58 that inverts the output of flip-flop 56. Output instruction signal OEM is generated from inverter circuit 58.

  One shot pulse generation circuit 52 includes a delay circuit 61 that delays output instruction signal DOT for a predetermined time, and a two-input AND circuit 62 that receives the output of delay circuit 61 and output instruction signal DOT. Delay circuit 61 includes an even number of inverters (two inverter circuits in the configuration shown in FIG. 5).

  The flip-flop 56 includes two cross-coupled NAND circuits NA1 and NA2. NAND circuit NA1 receives the output of inverter circuit 54 at one input and the output of NAND circuit NA2 at the other input. NAND circuit NA2 receives the output of NAND circuit 55 at one input and the output of NAND circuit NA1 at the other input. The output of NAND circuit NA1 is applied to inverter circuit 58.

  The gate circuit 57 outputs a signal “H” when the internal column address strobe signal ZCAS is “L” and the write enable signal ZWE is “H”. When the dynamic semiconductor memory device used uses the output enable signal ZOE, the gate circuit 57 may be replaced with an inverter that inverts the output enable signal ZOE. A configuration that outputs an “H” signal during a data read operation may be used.

  The control signal generation system further inverts the output instruction signal DOT from the one-shot pulse generation circuit 50, and in response to the output of the inverter circuit 59, internal data bus lines 915a and 915b are set to the ground potential level. Precharge transistors 60a and 60b for precharging are included. Precharge transistors 60a and 60b are both n-channel MOS transistors. Next, the operation of the control signal generation system shown in FIG. 5 will be described with reference to FIG.

  When row address strobe signal ZRAS is in an inactive state of “H”, output instruction signal DOT is in “L” and column address strobe signal ZCAS is in an inactive state of “H”. At this time, the potentials of internal nodes N11, N12, and N13 are "L", and the potentials of nodes N10, N14, and N15 are "H".

  When the row address strobe signal ZRAS is activated to “L”, a memory cycle starts. In response to this “L” internal row address strobe signal ZRAS, the one-shot pulse generation circuit 50 is activated, and the output instruction signal DOT, which is its output, is raised to “H”. When a predetermined time elapses after the output instruction signal DOT becomes “H”, the one-shot pulse generation circuit 52 outputs a “H” signal. When the column address signal changes, an address change detection signal φATD is generated in response thereto. It should be noted that in the semiconductor memory device capable of the static column operation mode, the column address strobe signal has only the function of the output enable signal and does not have the function of instructing the address latch. In response to address change detection signal φATD, output instruction signal DOT is set to “L” for a predetermined period. When the output instruction signal DOT becomes “L”, the output of the one-shot pulse generation circuit 52 (output of the node N12) becomes “L”. The one-shot pulse generation circuit 52 outputs an “L” signal having a pulse width longer than the one-shot output instruction signal DOT by the delay time provided by the delay circuit 61.

  When the “L” signal is output on the node 12 from the one-shot pulse generation circuit 52, the NAND circuit 55 outputs the “H” signal on the node N 13.

  Next, when the column address strobe signal ZCAS becomes “L”, a delay column address strobe signal ZCASE that becomes “L” after a predetermined time elapses is generated from the delay circuit 51. In response to the “L” delayed column address strobe signal ZCASE, an “H” signal is output from the inverter circuit 54 onto the node N11.

  On the other hand, the potential of the node N14 is at “H”, and the node N15 becomes “L” in response to the rise of the potential of the node N13. When the potential of the node N15 becomes “L” in response to the rise of the potential of the node N13, the potential of the node N15 becomes “H”, and an “L” signal is output from the NAND circuit NA1 to the node N14. In response to the fall of the potential of the node N14, the output signal from the inverter circuit 58, that is, the output permission signal OEM becomes “H”.

  While the internal column address strobe signal ZCAS (ZCASE) is at “L” and the potential at the node N15 is at “H”, the potential at the node N14 is fixed at “H”. That is, the output permission signal OEM is “H”.

  When the internal delay column address strobe signal ZCASE is “L”, the output instruction signal DOT is “L”, and even if the potential of the node N13 is “H”, the potential of the node N14 is “L”. The potential of N15 does not change. That is, while the delay column address strobe signal ZCASE is “L”, the output permission signal OEM maintains the “H” state even if the output instruction signal DOT is generated.

  On the other hand, when output instruction signal DOT attains "L", the output of inverter circuit 59 attains "H", precharge transistors 60a and 60b are both turned on, and internal data bus lines 915a and 915b are set to the ground potential level for a predetermined time. And discharge. Thus, in the static column mode and the normal mode, when new data is to be read, internal data bus lines 915a and 915b can be once set to a precharge state at a predetermined ground potential level.

  When the precharge operation to the ground potential level of internal data bus lines 915a and 915b is executed only during data reading, inverter circuit 59 is operable when the output of gate circuit 57 is "H". What is necessary is just to be comprised so that. This configuration can be easily realized by receiving the output of the gate circuit 57 and the output instruction signal DOT by the AND circuit and supplying the AND circuit output to the precharge transistors 60a and 60b.

  According to the configuration of the control circuit described above, output node 6 reliably precharges to the intermediate potential level when either “H” or “L” data is read and data is to be read next. be able to.

  The number of stages of the delay circuits 15, 17, 19 and 12 shown in FIG. 1 and the inverter circuit of the delay circuit 61 shown in FIG. 5 is not limited to the number of stages shown in the figure, but can be set to a number that provides an appropriate delay time. Good.

[Modification 1]
FIG. 7 is a diagram showing a modification of the output circuit according to the first embodiment. In the configuration shown in FIG. 7, an n-channel MOS transistor 62 that conducts in response to the output of NAND circuit 22 and drives output node 6 to reference potential VREF for a predetermined period is provided. The output of the NAND circuit 13 is given through the inverter 63 to the drive transistor 2b having a large driving force. In this configuration, when the output node 6 is discharged, first, the drive transistor 2a operates to slowly discharge the output node 6, and then the drive transistor 2b is turned on after a predetermined time has passed, and the output node 6 is rapidly turned on. Discharge to ground potential level. When one read operation is completed or when an “H” output signal is output in the static column mode and then an “L” output signal is output, the transistor 62 becomes the output of the NAND circuit 22. In response, the output node 6 is driven to the reference potential VREF. If, for example, the potential level of Vcc / 2 used in the dynamic semiconductor memory device is used as reference potential VREF, output node 6 can be reliably driven to intermediate potential Vcc / 2. At the time of data reading and “L” data reading, the data determination timing can be made the same without causing any ringing, and high-speed access can be realized (the access time is “H” data and This is because it is determined by the longer data determination time at the time of reading “L” data).

[Modification 2]
FIG. 8 is a diagram illustrating still another modification of the first embodiment. In FIG. 8, a delay circuit 15b and a NOR circuit 16b are provided in order to generate a signal that is "H" for a predetermined period in response to the fall of the potential of node N2. Delay circuit 15b has the same configuration as inversion delay circuit 15a for generating a one-shot pulse in response to the fall of the potential of node N1. The outputs of NOR circuits 16a and 16b are applied to OR circuit 64. The output of the OR circuit 64 is given to the NAND circuit 22.

  According to the configuration shown in FIG. 8, a one-shot pulse signal is generated when the potentials of nodes N1 and N2 fall, and precharge transistor 62 can be turned on for a predetermined period. Therefore, regardless of whether the data signal appearing at output node 6 is “H” or “L”, precharge transistor 62 is turned on when one data read cycle is completed or when new data is to be read. The output node 6 can be precharged to the intermediate potential VREF.

  As described above, according to the first embodiment, the output node is configured to be driven to the intermediate potential when the data signal read operation is completed or when new data is to be read next. Therefore, when a new signal is output, the output node 6 is driven from the intermediate potential to the potential of the corresponding logic level regardless of whether the data signal “H” or “L” is output. The potential amplitude of the node can be reduced, ringing can be prevented, and a data signal can be stably output at high speed. At this time, since the output node is held at the intermediate potential, the time required to determine the potentials of the “H” and “L” levels can be shortened, and high-speed access is possible.

  Furthermore, since the output node is driven from the intermediate potential to the potential level of “H” or “L”, current consumption during data signal output can be reduced.

[Embodiment 2]
FIG. 9 is a diagram showing a configuration of an output circuit according to the second embodiment of the present invention. FIG. 9 shows a circuit configuration for discharging output node 6 to the ground potential level.

  Referring to FIG. 9, the output circuit includes inverter circuit 5 for inverting internal read data signal ZDD, AND circuit 3 receiving output permission signal OEM and the output of inverter circuit 5, output permission signal OEM and internal read data signal. An AND circuit 4 for receiving ZDD is included. Internal read data signal ZDD is a data signal having a logic opposite to that of data DD.

  The output circuit further includes an output of the AND circuit 4, that is, a delay circuit 12 that delays the signal on the node N2 for a predetermined time, a NAND circuit 13 that receives the signal on the node N2 and the output of the delay circuit 12, and an output of the NAND circuit 13 Inverter circuit 64 for receiving and a p-channel MOS transistor 67 for adjusting the “H” driving force of inverter 64 in response to the signal potential on output node 6. Inverter circuit 64 includes a p-channel MOS transistor 66 and an n-channel MOS transistor 65 complementarily connected to each other. Transistor 67 is provided between p channel MOS transistor 66 and a power supply potential node supplying power supply potential Vcc, and receives a signal on output node 6 at its gate.

  The output circuit further responds to the output of AND circuit 3, n channel MOS transistor 1 for charging output node 6 to power supply potential Vcc level, and the potential of output node 6 in response to the output of AND circuit 4. N channel MOS transistor (drive transistor) 2a for discharging relatively slowly, and n channel MOS transistor (drive transistor) for discharging the potential of output node 6 to the ground potential level in response to the output of inverter circuit 64 2b is included. The current driving capability of the transistor 2a is smaller than the current driving capability of the transistor 2b. Next, the operation of the output circuit shown in FIG. 9 will be described with reference to FIG.

  First, an operation when internal read data signal ZDD is set to “H” will be described. When the output permission signal OEM is “L”, the outputs of the AND circuits 3 and 4 are both “L”, and the drive transistors 1, 2a and 2b are all in the off state.

  When the output permission signal OEM rises to “H”, the output of the AND circuit 4 becomes “H”. As a result, drive transistor 2a is turned on, and output node 6 is discharged relatively slowly. The signal potential on output node 6 is applied to the gate of transistor 67. As the gate potential of the transistor 67 decreases, the driving force increases (conductance increases). When a predetermined time elapses, the output of the NAND circuit 13 (signal potential on the node N3) becomes “L”. In response to the fall of the signal potential on the node N3, the output of the inverter circuit 64 becomes "H". The potential level of the “H” signal output from the inverter 64 varies depending on the potential level of the output node 6. The voltage transmitted from transistor 67 to p channel MOS transistor 66 of inverter circuit 64 is Vcc−V (6) −Vth. Here, V (6) represents the potential of output node 6, and Vth represents the absolute value of the threshold voltage of p channel MOS transistor 67. Therefore, as the potential of output node 6 decreases, the potential level of “H” output from inverter circuit 64 rises, drive transistor 2b is turned on more strongly, and the potential of output node 6 is brought to the ground potential level at high speed. And discharge. That is, when the “H” potential level of the output of the inverter circuit 64 increases as the potential of the output node 6 decreases, the drive transistor 2b is turned on in response, and the potential of the output node 6 decreases sufficiently. Drive transistor 2b discharges output node 6 to the ground potential level faster. As a result, when the potential of output node 6 reaches a potential level at which no ringing occurs, drive transistor 2b discharges output node 6 to the ground potential level at a high speed. Can be generated.

  This p-channel MOS transistor 67 is a normally-on transistor, and may be considered as a resistance element whose resistance value (conductance) increases as the potential of output node 6 decreases. In this case, when the output of the inverter 64 becomes “H”, the rise of the output potential is accelerated according to the fall of the potential of the output node 6, and the drive transistor 2 b becomes the fall of the potential of the potential output node 6. In response, it is strongly turned on.

  In the operation waveform diagram shown in FIG. 10, when output node 6 is discharged to the ground potential level and output permission signal OEM is "L", drive transistors 1, 2a and 2b are all turned off. The operation waveforms are shown. However, output node 6 may be used in combination with a configuration in which the output node 6 is held at an intermediate potential level as in the first embodiment. In FIG. 10, the potential change of the output node 6 at this time is shown as Q ′. In the case where the output node 6 is held at the intermediate potential level, the following advantages can be obtained by increasing the discharge power as the potential decreases.

  FIG. 11 shows an operation waveform when valid read data is transmitted after the output permission signal OEM is activated. FIG. 11 shows a state where output node 6 is precharged to an intermediate potential. When output permission signal OEM is “L”, output node 6 is precharged to an intermediate potential. If output permission signal OEM rises to "H" and internal read data signal ZDD is "L" at this time, the potential of node N1 rises to "H", the potential of output node 6 rises, and the output data Q ′ becomes “H”. When the valid data appears after the elapse of a predetermined time and the internal read data signal ZDD becomes “H”, the potential of the node N2 rises to “H”, and the potential of the node N1 falls to “L”. As a result, drive transistor 2a is turned on, and output node 6 is slowly discharged to the ground potential level, and the potential of output signal Q 'gradually decreases.

  Next, when the node N3 (output of the NAND circuit 13) becomes “L” after a predetermined time has elapsed, the output of the inverter circuit 64 rises gently. The rising speed of the output of inverter circuit 64 is determined by the potential of output node 6. Therefore, when the potential of output signal Q ′ is high, the output of inverter circuit 64 rises gently, and when the potential of output signal Q ′ becomes sufficiently low, the output of inverter circuit 60 rapidly rises to power supply potential Vcc level. Go up. The driving capability of drive transistor 2b is increased when the potential of output node 6, that is, the potential of output signal Q 'is sufficiently lowered, and discharges output node 6 to the ground potential level at high speed. As a result, when the invalid data is output and then the valid data is output, even when the logic of the valid data and the invalid data is different, the current driving capability of the drive transistor 2b is set to the potential level of the output node 6. By adjusting accordingly, an output signal can be generated without generating ringing stably.

  The operation mode in which invalid data appears at the output node 6 will be described in detail later.

  FIG. 12 is a diagram showing a configuration of a portion for driving the output node to the “H” level. In FIG. 12, in order to drive (charge) output node 6 to power supply potential Vcc level, a drive transistor 1a composed of an n-channel MOS transistor which is turned on in response to a signal potential on node N1 is provided. A drive transistor 1b is provided in parallel.

  The control unit of the output circuit further delays the signal potential on node N1 for a predetermined time, NAND circuit 13a receiving the signal on node N1 and the output of delay circuit 12a, and the output of NAND circuit 13a as a gate. Receiving p channel MOS transistor 71 and n channel MOS transistor 73, p channel MOS transistor 72 provided between transistors 71 and 73, n channel MOS transistor 75 receiving the signal on output node 6 at its gate, and transistor 75 And a p-channel MOS transistor 74 provided between the power supply potential supply node. The gate of transistor 74 is connected to the connection point of transistors 72 and 73 and the gate of drive transistor 1b. The gate of transistor 72 is connected to the connection point of transistors 74 and 75. Next, the operation of the circuit shown in FIG. 12 will be described with reference to FIG.

  Now, assume that internal read data signal ZDD is "L". When output permission signal OEM is “L”, the potentials of nodes N1 and N2 are both “L”, and drive transistors 1a and 2 are both in the off state. Since the potential of the node N1 is “L”, the output of the NAND circuit 13a is “H”, and the drive transistor 1b is given an “L” signal because the transistor 73 is on. Therefore, drive transistor 1b is also in the off state.

  When the output permission signal OEM rises to “H”, the potential of the node N1 rises to “H”, and the drive transistor 1a is turned on. The current driving capability of drive transistor 1a is relatively small, and the potential of output node 6 is gradually increased. When a predetermined time elapses, the output of the NAND circuit 13a (the output potential of the node N3a) becomes “L”, the transistor 73 is turned off, and the transistor 71 is turned on. The potential of output node 6 is applied to the gate of transistor 75. When the potential level of the output node 6 is the intermediate potential level, the current driving capability of the transistor 75 is small (conductance is small), and the current driving capability of the transistor 74 is larger, so that the gate potential of the transistor 72 is relatively high. The conductance of the transistor 72 is small.

  Therefore, in this state, the potential of drive transistor 1b rises gently, and drive transistor 1b charges output node 6 relatively slowly with its current driving capability being limited. When the potential of output node 6 is sufficiently increased, the current driving capability of drive transistor 75 is increased, and accordingly, the potential of transistor 72 is sufficiently decreased, the current driving capability of transistor 72 is increased, and the potential of transistor 1b is increased at high speed. As the current driving force increases, the output node 6 is charged at high speed. At this time, the current driving capability of the transistor 74 is reduced as the gate potential of the transistor 1b is increased, and the gate potential of the transistor 72 is discharged at a high speed as the potential of the output node 6 is increased. A strong ON state is established, and the current driving capability of the drive transistor 1b is accordingly increased at high speed.

  Thereby, when the potential of the output node 6 rises to a potential level where no ringing occurs, the potential rises at a high speed, and an output signal can be stably generated without ringing. In FIG. 13, the operation waveform when the output node 6 is charged to the intermediate potential is also shown as the output signal Q ′.

  As described above, according to the configuration of the output circuit according to the second embodiment, the driving power of the output node is adjusted in accordance with the potential level of the output node, so that the potential of the output node does not cause ringing. When the level is reached, the potential of the output node is changed at high speed, and a stable output signal without ringing can be generated.

[Embodiment 3]
In a dynamic semiconductor memory device with a static column mode function, a column selection operation is executed in accordance with an address change detection signal φATD generated in response to a change in a column address signal. Column address strobe signal ZCAS is only used to determine the data output timing. Therefore, in this case, the time required for the column address strobe signal ZCAS to be activated after the row address strobe signal ZRAS is activated, that is, the RAS-CAS delay time TRCD and the column address signal Ad after the column address signal Ad is changed. Invalid data may be generated at the output node according to the relationship of time string address-CAS delay time TASC required until the strobe signal ZCAS changes. First, before explaining the third embodiment, the operation when invalid data is output and when invalid data is not output will be described with reference to the control signal generating circuit shown in FIG.

  First, with reference to FIG. 5 and FIG. 14, an operation when invalid data is not output will be described.

  When the row address strobe signal ZRAS is activated and becomes “L”, a memory cycle starts. The address signal Ad applied at that time is taken in as a row address signal X, and a row selection operation is executed. In this state, the control circuit shown in FIG. 5 is in an initial state, and the output permission signal OEM is at “L”.

  When the row address strobe signal ZRAS is activated and becomes “L”, the one-shot pulse generation circuit 50 is enabled and its output becomes “H”. The column address change detection signal φATD is enabled in response to the row address strobe signal ZRAS when the column address buffer 907 is in the static column mode. Since the 907 output does not change, the one-shot address change detection signal φATD is not generated (see FIG. 60). Alternatively, the pulse change detection circuit (ATD circuit) 920 may be configured to be operable when the row address strobe signal ZRAS is “L”.

  When the row address hold time has elapsed, the address signal Ad is then changed and the column address signal Y is generated. In response to the change of the address signal Ad, the address change detection signal φATD is activated, and the output instruction signal DOT generated from the one-shot pulse generation circuit 50 is set to “L” for a predetermined period. In response to the transition of the output instruction signal DOT to “L”, an “L” pulse signal having a longer “L” period than the output instruction signal DOT is applied from the one-shot pulse generation circuit 52 to the node N12. . The pulse width of the “L” one-shot pulse signal applied to the node N12 is longer than the period in which the output instruction signal DOT by the delay circuit 61 is “L”.

  When the potential of the node N 12 becomes “L”, a signal “H” is output from the NAND circuit 55 to the node 13.

At the time of data reading, the output of gate circuit 57 is at “H”.
In the initial state, the potential of the node N14 is “H”. When the potential of the node N13 becomes “H”, the potential of the node N15 becomes “L”. As a result, the potential of the node N14 is reliably set to the “H” level. In this state, the output instruction signal OEM is still inactive at “L”.

  When the address-CAS delay time TASC is sufficiently long, the delayed column address strobe signal ZCASE is still at “H” even if the output instruction signal DOT becomes “H”. In this state, the potential of the node N14 is still “H”. Therefore, when output instruction signal DOT goes to “H”, the potential at node N13 falls to “L”, and the potential at node N15 rises to “H” accordingly.

  Next, when the address-CAS delay time TACD elapses, the column address strobe signal ZCAS is activated and becomes “L”, and accordingly, the delayed column address strobe signal ZCASE becomes “L”. When the delayed column address strobe signal ZCASE becomes “L”, a signal “H” is output from the inverter circuit 54 onto the node N11. Since the potential of the node N15 is “H”, the potential of the node N14 becomes “L” and the output instruction signal OEM becomes “H” in response to the rising of the potential of the node N11.

  When the output permission signal OEM becomes “H”, valid data ZDD has already appeared, and the potential of the node N1 becomes “L” and the potential of the node N2 becomes “H” in accordance with the data signal ZDD. When the potential of the node N2 becomes “H”, the drive transistor 2a is turned on, the output Q is gradually lowered, and then the drive transistor 2b is turned on, and the potential of the output Q is lowered at high speed.

  As described above, if time TASC is sufficiently long, invalid data is not output, and output signal Q can change stably, for example, from the intermediate potential level to the ground potential level or the power supply potential level without causing ringing. .

  FIG. 15 shows an operation waveform when invalid data is output. Hereinafter, the invalid data output operation will be described with reference to FIGS. 15 and 5. FIG.

  The row address strobe signal ZRAS is activated and becomes “L”. In response to the activation of the row address strobe signal ZRAS, the output instruction signal DOT becomes “H”. In response to activation of internal row address strobe signal ZRAS, address Ad given at that time is taken in as a row address signal (X address), and a row corresponding to this X address is selected.

  When the address signal Ad changes, an address change detection signal φATD is generated. In accordance with address change detection signal φATD, output instruction signal DOT, which is an “L” one-shot pulse signal, is generated from one-shot pulse generation circuit 50 after a predetermined time has elapsed.

  Immediately after the column address signal is generated, the column address strobe signal ZCAS falls to "L". That is, consider a state in which the address-CAS delay time TASC is extremely short. At this time, the delay column address strobe signal ZCASE first becomes “L” before the output instruction signal DOT becomes “L”. In response to this, since the potential of the node N11 becomes “H” and the potential of the node N15 is “H”, the output of the NAND circuit NA1 (the potential of the node N14) becomes “L”, and the output permission signal OEM is “H”. After the output instruction signal DOT becomes “L”, valid data is output after a lapse of a predetermined time, and the internal read data ZDD rises to “H”. Therefore, when the output permission signal OEM is “H”, invalid data appears, and the potential of the output signal Q rises according to the “L” invalid data signal ZDD. Next, valid data appears, and output signal Q decreases in accordance with internal read signal ZDD of “H”.

  Therefore, when “L” data is output as valid data after “H” data is output as invalid data, even when the output signal Q is set to an intermediate potential, When the potential amplitude is increased and the drive transistor 2b is turned on, the potential of the output node 6 is not sufficiently lowered, and a state in which ringing occurs in the output signal Q may occur. Therefore, a configuration in which no ringing occurs even when such invalid data is output will be described below. In the following description, the output signal Q is assumed to be precharged to an intermediate potential. Although only the driving unit for outputting the output signal Q to “L” will be described, a similar configuration can be provided for the path when the output signal Q rises to “H”.

  FIG. 16 is a diagram showing the configuration of the output circuit according to the third embodiment of the present invention. FIG. 16 shows a configuration for preventing the occurrence of ringing when an “L” data signal is output to the output node 6. If a similar configuration is provided for the node N1 (output of the AND circuit 3), a configuration for preventing ringing at the time of outputting “H” data can be realized.

  Referring to FIG. 16, the output circuit basically includes an AND circuit 4 that receives output permission signal OEM and internal read data signal ZDD, an inverter circuit 5 that inverts internal read data signal ZDD, and an output of inverter circuit 5. AND circuit 3 receiving output permission signal OEM, drive transistor 1 charging output node 6 to power supply potential Vcc level in response to the output of AND circuit 3, and output node 6 in response to the output of AND circuit 4 Includes a drive transistor 2a having a small current driving capability for slowly discharging to the ground potential level, and a drive transistor 2b provided in parallel with drive transistor 2a for discharging output node 6 with a current driving capability greater than that of drive transistor 2a.

  The control system for controlling the operation of the drive transistor 2b includes an inverter circuit 81 that inverts the output instruction signal DOT, a NAND circuit 82 that receives the signal of the node N2 (output of the AND circuit 4) and the output of the inverter circuit 81, Flip-flop 84 receiving the output of NAND circuit 82 and the signal on node N2 is included. Flip flop 84 includes cross-coupled NAND circuits NA3 and NA4. One input of NAND circuit NA3 receives the output of NAND circuit 82, and the other input receives the output of NAND circuit NA4. NAND circuit NA4 receives the output of NAND circuit NA3 at one input and the signal on node N2 at the other input. The flip-flop 84 has a function of determining whether valid data appears at the node N2.

  The control system further includes an inverter circuit 85 that receives the output of NAND circuit NA3 (signal on node N25) included in flip-flop 84, a NAND circuit 86 that receives the output of inverter circuit 85 and the output of AND circuit 83, and an inverter. Delay circuit 87 that delays the output of circuit 85 for a predetermined time; delay circuit 88 that delays the output of NAND circuit 86; NAND circuit 89 that receives the outputs of delay circuits 87 and 88; and the signal on node N2 and NAND circuit 89 AND circuit 90 that receives the output of The output of AND circuit 90 is applied to the gate of drive transistor 2b.

  The delay time T1 of the delay circuit 87 is set longer than the delay time T2 of the delay circuit 88. Next, the operation of the output circuit shown in FIG. 16 will be described with reference to FIG.

  First, an operation when an invalid data signal is output will be described with reference to FIG. Here, it is assumed that the invalid data signal is an “L” data signal ZDD and the valid data signal is an “H” data signal ZDD.

  When an invalid data signal is output, first, the output instruction signal OEM becomes “H”, and then the output instruction signal DOT becomes “L” in an active state. When the output permission signal OEM rises to “H”, the potential of the node N2 is “L” in accordance with the invalid data signal ZDD. In this state, drive transistor 1 is turned on, drive transistor 2a is turned off, and output node 6 is charged via drive transistor 1 to increase its potential. In this state, when the output instruction signal DOT falls to “L”, a signal “H” is output from the inverter 81 to the node N23. When output instruction signal DOT is "L", valid data appears, and internal read data signal ZDD rises to "H". As a result, the potential of node N2 rises to “H”, drive transistor 2a is turned on, drive transistor 1 is turned off, and output node 6 is slowly discharged.

  When the potential of the node N2 rises to “H”, since the potential of the node N23 is “H”, the “L” signal is output from the NAND circuit 82 to the node N24. When the potential of the node N24 becomes “L”, the flip-flop 84 is set, and the potential of the node N25 becomes “H” (the potential of the node N26 is “H”). When the node N25 rises to “H”, the NAND circuit NA4 included in the flip-flop 84 receives the “H” signal at both inputs thereof, so that the potential of the node N26 becomes “L” and the potential of the node N25 becomes Fixed to “H”.

  When the potential of the node N25 rises to “H”, the potential of the node N27 becomes “L”. When the potential of the node N27 is “H”, the output of the AND circuit 83 is “L” because the output instruction signal DOT is “L”. Therefore, the output of the NAND circuit 86 is fixed to “H”.

  When the delay time T1 included in the delay circuit 87 elapses, the NAND circuit 89 receives the “L” signal from the delay circuit 87 and outputs the “H” signal to the node N30. At this time, the potential of the node N2 is “H”, and the AND circuit 90 outputs a signal of “H” on the node N31 to turn on the drive transistor 2b. As a result, output node 6 is discharged at high speed via drive transistor 2b.

  As described above, when invalid data exists, the output permission signal OEM is activated prior to the change of the output instruction signal DOT. In this case, the ON timing of the output drive transistor 2b is determined by the delay circuit 87 having a long delay time. As a result, the output node 6 is discharged at high speed via the drive transistor 2b after the potential of the output node 6 has sufficiently decreased. Even when invalid data and valid data having different logics are output, occurrence of ringing can be stably and reliably prevented.

  Next, an operation when an invalid data signal is not output will be described with reference to FIG.

  When invalid data is not output, the output permission signal OEM becomes “H” after the output instruction signal DOT is generated. As apparent from the circuit configuration of FIG. 5, when the output instruction signal DOT is “H”, the output permission signal OEM is generated according to the delayed column address strobe signal ZCASE.

  In this state, when the output permission signal OEM rises to “H”, a valid “H” read data signal ZDD has already been output, and the potential of the node N2 rises to the rise of the potential of the output permission signal OEM. In response, it becomes “H”. When the potential of node N2 rises to “H”, output instruction signal DOT has already returned to “H”, and AND circuit 83 outputs a signal of “H” to node N28. On the other hand, in the flip-flop 84, the node N26 is set to “H” in the initial state, and the node N25 is set to “L” in the initial state. Therefore, even when the output instruction signal DOT becomes “L” when the potential of the node N2 is “L”, the latch state of the flip-flop 84 does not change. Similarly, even if the potential of the node N2 rises from “L” to “H”, the output of the NAND circuit 82 is “H” (the output of the inverter circuit 81 has already fallen to “L”). The latch state of the flip-flop 84 does not change. Therefore, the potential of the node N27 is fixed to “H”.

  In this state, when the potential of the node N2 rises to “H” and the potential of the node N28 rises to “H” accordingly, the potential of the node N29 falls to “L” by the NAND circuit 86. After the elapse of the delay time T2 included in the delay circuit 88, the NAND circuit 89 outputs an “H” signal to the node N30. As a result, the AND circuit 90 outputs an “H” signal on the node N31, and the drive transistor 2b is turned on.

  When invalid data is not output, the address access time TASC is relatively long. In this case, since the invalid data signal is not output, when the output permission signal OEM is activated, the output node 6 is gently discharged by the drive transistor 2a, and the potential thereof decreases. At this time, after elapse of delay time T2 provided by delay circuit 88, drive transistor 2b is turned on, and output node 6 is discharged to the ground potential level at high speed. At this time, since invalid data is not output, the drive transistor 2b having a large driving force is activated after the potential of the output node 6 is sufficiently lowered. Therefore, a stable output signal is generated without ringing. can get.

  In the operation waveform diagram shown in FIG. 17, internal read data signal ZDD is set to the “L” state during standby. As in the case of the first embodiment, a configuration is used in which both internal data lines 915a and 915b are precharged to the ground potential level when the output node is held at an intermediate potential.

  The current driving capability of drive transistors 2a and 2b can be realized by making the sizes of drive transistors 2a and 2b, that is, the ratio of gate width W and gate length L different. The drive transistors 2a and 2b may have different β (a constant proportional to W / L).

  Drive transistors 2a and 2b do not need to have different current driving capabilities. When the drive transistor 2b is in the on state, the drive transistor 2a is also in the on state, so that the output node 6 is discharged through the two transistors, so that the discharge capacity of the output node 6 is equivalently increased. The same effect can be obtained even if the drive transistors 2a and 2b have the same current driving capability.

  Further, even when three or more transistors for discharging the output node 6 are provided and discharge of the output node 6 is realized in a plurality of stages, the same effect as in the above embodiment can be obtained. In the configuration shown in FIG. 16, a delay circuit is further provided at the output of the AND circuit 90, and an extra transistor is provided between the output node 6 and the ground potential in response to the output of the delay circuit. It can be easily realized.

  In addition, delay circuits 87 and 88 shown in FIG. 16 can have any number of inverter stages as long as the delay time of delay circuit 87 is shorter than the delay time of delay circuit 87, and delay elements different from the inverter are used. (E.g., RC delay element).

[Modification 1]
FIG. 18 is a diagram showing the configuration and operation of the main part of a modified example of the output circuit shown in FIG. In FIG. 18A, the output control unit is not provided with the delay circuits 87 and 88 shown in FIG. NAND circuit 89 receives signals from NAND circuit 86 and inverter circuit 85 shown in FIG. The output of NAND circuit 89 is applied to AND circuit 90 shown in FIG.

  In FIG. 18A, a NAND circuit 89 is provided between a power supply potential supply node and an output node 894, and receives at its gate a p-channel MOS transistor 890 receiving the output signal A from the NAND circuit 86, and a power supply potential supply. A p-channel MOS transistor 891 provided between the node and output node 894 and receiving output signal B from inverter circuit 85 is included at its gate. The current driving capability of the transistor 890 is larger than the current driving capability of the transistor 891. NAND circuit 89 further includes an n-channel MOS transistor 892 that receives output signal A from NAND circuit 86 at its gate, and an n-channel MOS transistor 893 that receives output signal B from inverter circuit 85 at its gate. Transistors 892 and 893 are connected in series between output node 894 and the ground potential node. The signal on output node 894 is applied to AND circuit 90 at the next stage. The current driving power of the transistors 892 and 893 may be set to be the same. Next, the operation of the NAND circuit shown in FIG. 18A will be described with reference to FIG.

  If output signal A from NAND circuit 86 is at "L", p-channel MOS transistor 890 is turned on. Thus, the potential of output node 894 is charged by transistor 890 with a relatively large driving force, and rises to “H” at a relatively high speed.

  On the other hand, when output signal P from inverter circuit 85 attains “L”, p-channel MOS transistor 891 is turned on, and output node 894 is charged relatively slowly via transistor 891. The signal on output node 894 is applied to AND circuit 90 at the next stage. When the signal potential on the output node 894 exceeds the input logic threshold value of the AND circuit 90 in the next stage, the AND circuit 90 outputs an “H” signal. Therefore, as shown in FIG. 18B, the time required for the output of AND circuit 90 to rise to “H” by setting the current driving power of transistors 890 and 891 to an appropriate value is shown in FIG. The delay time given by the delay circuits 87 and 88 shown in FIG.

[Modification 2]
FIG. 19 is a diagram illustrating the configuration of the control unit of the output circuit according to the second modification of the third embodiment. In FIG. 19, the control unit receives gate circuits 91 and 92 that receive output permission signal DOT and output instruction signal OEM, flip-flop 93 that is set in response to the rise of the output of gate circuit 91, and the output of gate circuit 92. Flip-flop 94 set in response to the rising edge of the signal, delay circuit 95 delaying the signal on node N2 for a predetermined time, AND circuit 96 receiving the output of delay circuit 95 and the output of flip-flop 93, flip-flop 94 receives the Q output of 94 and the output of delay circuit 95, AND circuit 98 receives the signal on node N2 and the output of ADN circuit 96, and receives the signal on node N2 and the output of AND circuit 97. AND circuit 99 and a driver for discharging output node 6 to the ground potential level in response to the output of AND circuit 98. Including a blanking transistor 2ba, the drive transistor 2bb for discharging output node 6 in response to an output of the AND circuit 99 to the ground potential level.

  Gate circuit 91 outputs an “H” signal when both signals DOT and OEM are “L”. When the output instruction signal DOT becomes “L” when the output permission signal OEM is “L”, as shown in FIG. 17B, invalid data is not output. At this time, the gate circuit 91 outputs the “H” signal, sets the flip-flop 93, and outputs the “H” signal from the Q output of the flip-flop 93.

  The gate circuit 92 outputs a signal “H” when the output instruction signal DOT becomes “L” when the output permission signal OEM is “H”. The output instruction signal DOT becomes “L” when the output permission signal OEM is “H” when an invalid data signal is output. At this time, the gate circuit 92 outputs an “H” signal, sets the flip-flop 94, and outputs a signal whose Q output of the flip-flop 94 is “H”.

  Next, the operation will be briefly described. When the potential on output node N2 becomes “H”, drive transistor 2a is turned on, and output node 6 is slowly discharged. When a predetermined time elapses, the output of the delay circuit 95 becomes “H”. When there is a possibility that invalid data is output, the flip-flop 94 is set by the gate circuit 92, and an "H" signal is output from the Q output. When there is no possibility of invalid data being output, the flip-flop 93 is set by the gate circuit 91 and an “H” signal is output from the Q output.

  When the output of the delay circuit 95 becomes “H”, one output of the AND circuits 96 and 97 becomes “H”. Accordingly, one output of AND circuits 98 and 99 becomes “H”.

  The current driving capability of drive transistor 2ba is larger than the current driving capability of drive transistor 2bb. Therefore, when invalid data is not output, drive transistor 2ba is turned on by flip-flop 93 and AND circuits 96 and 98, and the potential of output node 6 is discharged at high speed. When invalid data is not output, the potential amplitude of the output node 6 has already been discharged by the drive transistor 2a. Even if the output node 6 is discharged with a large driving force, no ringing occurs, and the output signal can be output stably. Can be generated.

  When invalid data may be output, drive transistor 2bb is turned on via flip-flop 94 and AND circuits 97 and 99. If there is a possibility that this invalid data signal is output, it is conceivable that the potential of the output node 6 is not sufficiently lowered. Therefore, at this time, output node 6 is gently discharged by drive transistor 2bb having a relatively small driving force. At this time, since drive transistors 2a and 2bb are both turned on, discharging is performed at a higher speed than when output node 6 is driven by one drive transistor. Thereby, an output signal can be stably generated without ringing.

  In the static column operation mode, when the signal OEM is “H”, the output instruction signal DOT is “L”. When there is a possibility that invalid data may be output first, the flip-flop 93 is set, and in the static column operation mode, the set state is continued. Flip-flops 93 and 94 are reset in response to the fall of output permission signal OEM. In static column mode, flip-flops 93 and 94 are both set, and drive transistors 2ba and 2bb are both turned on. However, in the static column mode, output node 6 is once set to the intermediate potential after the completion of the output of the data signal as shown in the first embodiment, and all of drive transistors 2a, 2ba and 2bb are all set. Even in the on state, there is no possibility of ringing.

  At this time, flip-flops 93 and 94 may be configured to be reset by address change detection signal φATD. In this case, the logical sum of the inverted signal of the output signal OEM and the address change detection signal φATD is taken, and the logical sum output is given to the reset inputs of the flip-flops 93 and 94. When flip-flops 93 and 94 are reset in accordance with column address change detection signal φATD as described above, flip-flop 94 is set in the static column mode operation, and output node 6 is discharged by drive transistors 2a and 2bb. .

  Since output node 6 is discharged from the intermediate potential to the ground potential level, even when output node 6 is driven by only two drive transistors 2a and 2bb, output node 6 is discharged to the ground potential level at a sufficiently high speed. Can do.

  In the configuration shown in FIG. 19, AND circuit 96 receives the output signal of delay circuit 95 and the output signal of NAND circuit 86, and AND circuit 97 outputs the output signal of delay circuit 95 and inverter 85 (see FIG. 16). Even if it is configured to receive the output signal, the same effect can be obtained.

[Modification 3]
FIG. 20 is a diagram showing a third modification of the output circuit according to the third embodiment. 20 shows a configuration of NAND circuit 89 and delay circuits 87a and 88 shown in FIG. 20, delay circuit 87a includes a delay circuit 87a for delaying a signal applied from inverter 85 to node N27, and a delay circuit 88 for delaying node N29 (an NAND circuit 86 output) for a predetermined time. Delay circuit 87a includes three stages of cascaded inverter circuits 871-873 and a gate circuit 874 that receives the output of delay circuit 88 at one input and the output of inverter circuit 873 at the other input. The gate circuit 874 outputs an “H” signal when the output of the inverter circuit 873 is “L” and the output of the delay circuit 88 is “H”. Outputs of delay circuits 87a and 88 are applied to NAND circuit 89. The output of NAND circuit 89 is applied to AND circuit 90. The AND circuit 90 turns on the drive transistor 2b when the potential on the node N2 is “H” and the output of the NAND circuit 89 is “H”.

  FIG. 21 shows a configuration of NAND circuit 89 shown in FIG. In FIG. 21, NAND circuit 89 includes p-channel MOS transistors 89a and 89c receiving the signal potential on node N40 at the gate, and p-channel MOS transistor 89b and n-channel MOS transistor 89d receiving the signal potential on node N41 at the gate. Including. Transistors 89a and 89b are provided in parallel between power supply potential node and output node N30. Transistors 89c and 89d are connected in series between output node N30 and the ground potential. The transistors 89a and 89b may be the same size, and the size (channel width) of the transistor 89b may be larger than that of the transistor 89a. Next, the operation of the circuit shown in FIGS. 20 and 21 will be described with reference to FIG.

  When the invalid output exists, the potential level of the node N29 is “H”, and accordingly, the signal potential on the node N41 is also “H”. In this case, the gate circuit 874 included in the delay circuit 87a functions as an inverter circuit. Therefore, when the signal potential on the node N27 becomes “L”, the potential of the node N40 becomes “L” after a predetermined time has elapsed. At this time, as shown in FIG. 21, in NAND circuit 89, only p-channel MOS transistor 89a is turned on, and output node N30 is charged only through transistor 89a. For this reason, the potential rise of the node N30 becomes relatively gradual. When the potential level of the node N30 exceeds the input logic threshold value of the AND circuit 90, since the potential of the node N2 is “H”, the output of the AND circuit 90 becomes “H” (potential of the node N31).

  On the other hand, when there is no invalid output, the potential on the node N27 is “H”. At this time, the gate circuit 874 functions as a buffer circuit. When the potential of the node N29 becomes “L”, the delay circuit 88 causes the potential on the node N41 after the elapse of a predetermined time to become “L”, and the output of the gate circuit 874 becomes “L”. In NAND circuit 89, p channel MOS transistors 89a and 89b are both turned on, and output node N30 is charged by these two transistors 89a and 89b, and the potential thereof rises. When the potential of the node N30 exceeds the input logic threshold value of the AND circuit 90, the AND circuit 90 outputs a signal “H” on the node N31.

  The rise of the signal potential on the node N30 is relatively slow when there is an invalid output, and relatively fast when there is no invalid output. As a result, the rise time of the signal potential on node N31 can be made different, and the on-timing of output drive transistor 2b can be made different when there is an invalid output and when there is no invalid output. At this time, if the input / output response characteristics of the AND circuit 90 are comparatively gentle, the rise of the signal potential on the node N31 is similar to that of the node N30, and the output drive transistor 2b has an invalid output. The driving force gradually increases, and when there is no invalid output, the driving force increases rapidly. As a result, when there is no possibility of ringing occurring, the output node 6 can be discharged at high speed.

[Embodiment 4]
FIG. 23 is a diagram illustrating a configuration of a control unit of the output circuit according to the fourth embodiment. FIG. 23 also shows a circuit configuration for discharging output signal Q to the ground potential level.

  23, the output circuit includes an AND circuit 3 that receives the output permission signal OEM and the output of the inverter circuit 5 that receives the internal read data signal ZDD, an AND circuit 4 that receives the internal read data signal ZDD and the output permission signal OEM, Drive transistor 1 that conducts in response to the output of AND circuit 3 and charges output node 6 to power supply potential Vcc level, and drive that discharges output node 6 to the ground potential level in response to output of AND circuit 4 Transistor 2a is provided in parallel with drive transistor 2a, and includes a drive transistor 2b that discharges output node 6 to the ground potential level in response to a control signal from control circuit 100.

  The control circuit 100 includes an inverter circuit 81 that inverts the logic of a signal on the node N2 (output of the AND circuit 4), an AND circuit 101 that receives the signal potential on the node N2 and the output of the inverter circuit 81, and an output instruction signal DOT. Inverter circuit 102 that inverts the logic of AND circuit 101, NAND circuit 103 that receives the output of AND circuit 101 and the output of inverter circuit 102, NAND circuit 104 that receives the output of AND circuit 101 and output instruction signal DOT, and the output of NAND circuit 103 Latch circuit 105 receiving a signal on node N2 and a latch circuit 106 receiving an output of NAND circuit 104 and a signal on node N2.

  Latch circuit 105 includes a NAND circuit NA5 that receives the output of NAND circuit 103 at one input, and a NAND circuit NA6 that receives a signal on node N2 at one input. The output of NAND circuit NA6 is applied to the other input of NAND circuit NA5. The output of NAND circuit NA5 is applied to the other input of NAND circuit NA6. Latch circuit 106 also includes cross-coupled NAND circuits NA7 and NA8. NAND circuit NA7 receives the output of NAND circuit 104 at one input and the output of NAND circuit NA8 at the other input. NAND circuit NA8 receives the signal on node N2 at one input and the output of NAND circuit NA7 at the other input.

  The output control circuit 100 further delays the output of the NAND circuit NA5 of the flip-flop 105 (the signal on the node N46) for a predetermined time and inverts its logic, and outputs the output of the NAND circuit NA7 of the flip-flop 106 to the predetermined level. Delay circuit 108 that delays the time and inverts its logic, NAND circuit 89 that receives the outputs of delay circuits 107 and 108, and AND circuit 90 that receives the signal on node N2 and the output of NAND circuit 89 are included. The output of AND circuit 90 is applied to the gate of drive transistor 2b.

  The delay time of the delay circuit 107 is set longer than the delay time of the delay circuit 108. Next, the operation of the circuit shown in FIG. 23 will be described with reference to FIG.

  First, an operation when an invalid data signal is output will be described with reference to FIG. Also in this case, the invalid data signal is “L” and the valid data signal is “H”. In the initial state, the output permission signal OEM is at “L”, and the output instruction signal DOT is at “H”. Even if output permission signal OEM rises to "H", internal read data signal ZDD is at "L" at that time, and the potential of node N2 is at "L".

  In this state, when the output instruction signal DOT falls to “L”, the potential of the node N43 becomes “H” by the inverter circuit 102, and the NAND circuit 103 functions as an inverter during this period. The output of the NAND circuit 104 is “L” and maintains the “H” state.

  When valid data signal ZDD is applied to internal data bus line 915b, the potential of node N2 rises to "H" accordingly. As a result, the output of the inverter circuit 81 becomes “L”. Due to the delay time of the inverter circuit 81, the AND circuit 101 gives an “H” pulse signal having a time width of the delay time given by the inverter circuit 81. Is generated.

  In response to the one-shot pulse signal from AND circuit 101, NAND circuit 103 generates a one-shot "L" pulse signal on node N45. Thereby, in the latch circuit 105, the output of the NAND circuit NA5 becomes “H”, and the potential of the node N46 is set to “H”.

  Even if a one-shot “H” pulse signal is generated on node N44, output instruction signal DOT is “L” during this period, and the latch state of latch circuit 106 does not change (the output of NAND circuit 104 is “H”). Maintain). That is, the node N49 (output of the NAND circuit NA7 of the latch circuit 106) is fixed to “L”. The output of the delay circuit 108 is “H”, and the NAND circuit 89 functions as an inverter circuit.

  When the delay time of the delay circuit 107 elapses, an “L” signal is output from the delay circuit 107 and the output of the NAND circuit 89 becomes “H”. Next, since the potential of the node N2 is “H”, the output of the AND circuit 90 (signal potential on the node N31) becomes “H”, and the drive transistor 2b is turned on.

  That is, when an invalid data signal is output, the drive transistor 2b is turned on after the delay time T1 of the delay circuit 107 has elapsed since the drive transistor 2a was turned on. Thus, when the logics of the invalid data signal and the valid data signal are different, the drive transistor 2b is turned on when the potential of the output node 6 is sufficiently lowered to reach a level where no ringing occurs.

  Next, the operation when invalid data is not output will be described with reference to FIG. In this state, first, the output instruction signal DOT is “L” for a predetermined period. In response to the output instruction signal DOT, the output of the inverter circuit 102 is “H” for a predetermined period. However, at this time, the potential of the node N2 is “L”, and the output of the AND circuit 101 is “L”. Therefore, the outputs of NAND circuits 103 and 104 maintain “H”.

  In a period when the output instruction signal DOT is “L”, valid data is transmitted onto the internal data bus line 915b, and the internal data signal ZDD becomes “H”. After the output instruction signal DOT becomes “H”, the output permission signal OEM becomes “H”, and the potential of the node N2 becomes “H”.

  In response to the rise of the potential at node N2, a one-shot "H" pulse signal is generated from AND circuit 101 onto node N44. At this time, the output instruction signal DOT has already returned to “H”, and the output of the inverter circuit 102 is “L”. Therefore, the output of the NAND circuit 103 maintains “H”.

  On the other hand, the NAND circuit 104 generates a pulse signal of “L” in response to the one-shot “H” pulse signal from the AND circuit 101. As a result, the output of the NAND circuit NA7 of the latch circuit 106 rises from "L" to "H". In response to the transition of the output of the NAND circuit NA7 (signal potential on the node N49) to “H”, the output of the NAND circuit NA8 falls to “L”, and the potential of the node N49 is latched to “L”. The

  After the delay time T2 of the delay circuit 108 has elapsed, the output of the delay circuit 108 rises to “H”.

  The potential of the node N46 is “L”, and the output of the delay circuit 107 is “H”. Therefore, the output of NAND circuit 89 rises to "H" in response to the output of delay circuit 108, and then the output of AND circuit 90 rises to "H". Drive transistor 2b conducts in response to the output of AND circuit 90, and discharges output node 6 to the ground potential level.

  As described above, when the invalid data signal is not output, the drive transistor 2b is turned on after the delay time of the delay circuit 108 has elapsed. The delay time that the delay circuit 108 has is shorter than the delay time that the delay circuit 107 has. For this reason, when the invalid data signal is not output, the drive transistor 2b can be turned on at a faster timing.

  As described above, the occurrence of ringing can be reliably prevented by adjusting the on-timing of the drive transistor 2b according to the presence or absence of the generation of the invalid data signal.

  Also in the configuration shown in FIG. 23, various modifications can be performed as in the first embodiment. Also in the modifications described below, a circuit configuration for pulling up the potential of the output node 6 is further used, as in the previous embodiment, and the number of inverter stages in the delay circuit is set appropriately. Can be modified.

[Modification 1]
FIG. 25 is a diagram illustrating a first modification of the fourth embodiment. FIG. 25 also shows a circuit configuration for preventing the occurrence of ringing during discharge of output node 6. In FIG. 25, control circuit 100 includes inverter circuit 110 that inverts the signal potential on node N2, AND circuit 111 that receives the signal on node N2 and the output of inverter circuit 110, and inverter circuit 112 that receives output instruction signal DOT. A NAND circuit 113 that receives the output of the AND circuit 111 and the output of the inverter circuit 112, a delay circuit 114 that delays the output of the NAND circuit 113 for a predetermined time T1, and a NAND that receives the output of the AND circuit 111 and the output instruction signal DOT Circuit 114, delay circuit 118b that delays the output of NAND circuit 118a for a predetermined time T2 (T2 <T1), NAND circuit 115 that receives the outputs of delay circuits 118a and 118b, and inverter circuit 116 that inverts the output of NAND circuit 115 And the output of the inverter circuit 116 A latch circuit 117 for receiving a signal on node N2 and.

  Latch circuit 117 includes NAND circuits NA9 and NA10 that are cross-coupled. A signal for driving the drive transistor 2b is output from the NAND circuit NA10. NAND circuit NA9 receives the signal potential on node N2 at one input, and NAND circuit NA10 receives the output of inverter circuit 116 at one input. Outputs of NAND circuits NA9 and NA10 and the other input are cross-coupled. Next, the operation of the circuit shown in FIG. 25 will be described with reference to FIG.

  First, an operation when an invalid data signal is output will be described with reference to FIG. First, output instruction signal OEM rises to "H". In this state, read data signal ZDD is at "L" and is an invalid data signal. In this state, the potential of the node N2 is “L”, the output of the AND circuit 111 is also “L”, and the outputs of the NAND circuits 113 and 114 are “H”. NAND circuit 115 outputs an “L” signal in accordance with the outputs of delay circuits 118a and 118b, and inverter circuit 116 outputs an “H” signal. The signal potential of the node N2 is “L”. In the latch circuit 117, the output of the NAND circuit NA9 is “H”, and the output of the NAND circuit NA10 is “L”.

  When the output instruction signal DOT becomes “L” for a predetermined period, the output of the inverter circuit 112 becomes “H” accordingly. During the “L” period of output instruction signal DOT, valid data is read, internal read data signal ZDD rises to “H”, and the potential of node N2 rises to “H” accordingly. In response to the rising of the potential at node N2, a one-shot pulse signal generation circuit composed of AND circuit 111 and inverter circuit 110 generates a one-shot “H” pulse signal on node N74. NAND circuit 113 receives an “H” signal at one input via inverter circuit 112, and therefore transmits an “L” signal on node N 75 in response to the rise of the output of AND circuit 111.

  On the other hand, since the output instruction signal DOT is “L”, the NAND circuit 114 does not respond to the one-shot pulse signal from the AND circuit 111 and outputs an “H” signal.

  After the delay time T1 of the delay circuit 118a elapses, the output of the delay circuit 118a becomes “L” and the output of the NAND circuit 115 becomes “H” (the output of the delay circuit 115 is “H”). In accordance with the output of NAND circuit 115, a one-shot “L” signal is output from inverter circuit 116 onto node N77. As a result, the NAND circuit NA10 outputs a “H” signal, and the drive transistor 2b is turned on.

  Even if the output of the inverter circuit 116 returns to “H”, the NAND circuit NA9 responds to the “H” signal generated from the NAND circuit NA10 in response to the previous one-shot pulse signal, and “L”. The signal is output. Therefore, even if the output of the inverter circuit 116 returns to “H”, the output of the NAND circuit NA10 maintains “H”.

  When the potential of the node N2 becomes “L”, the output of the NAND circuit NA9 becomes “H” in the latch circuit 117, and the NAND circuit NA10 receives the “H” signal at both its inputs. receive. As a result, drive transistor 2b is turned off.

  As described above, when an invalid data signal is output, the timing at which the drive transistor 2b is turned on is determined by the delay circuit 114 having a long delay time.

  Next, with reference to FIG. 26B, the discharge operation of output node 6 when invalid data is not output will be described.

  First, the output instruction signal DOT becomes “L”, and the output of the inverter circuit 112 becomes “H”. At this time, the signal potential of the node N2 is still “L”, the output of the AND circuit 111 is “L”, and the output of the NAND circuit 114 maintains “H” regardless of the change of the output instruction signal DOT. To do. In this state, the outputs of delay circuits 118a and 118b are both “H”, the output of NAND circuit 115 is “L”, the output of inverter circuit 116 is “H”, and the output of NAND circuit NA10 is “L”. ".

  A valid data signal is applied to internal data bus line 915b, and internal data signal ZDD rises to "H". Thereafter, the output permission signal OEM becomes “H”, and the potential of the node N2 becomes “H”. In response to the rise of the signal potential of node N2, AND circuit 111 generates a one-shot "H" pulse signal. At this time, the output instruction signal DOT is at “H”, and the output of the inverter circuit 112 is “L”. Accordingly, the output of the NAND circuit 113 does not change and is in the “H” state, while a one-shot “L” signal is output from the NAND circuit 114 onto the node N76. After the delay time T2 of the delay circuit 118b has elapsed, the output of the delay circuit 118b becomes “L” and the output of the NAND circuit 115 becomes “H”. In response, the output of the inverter circuit 116 becomes “L”, and the NAND circuit NA10 outputs a signal “H” on the node N78. In response to the “H” signal on node N78, drive transistor 2b is turned on.

  When the invalid data signal is not output, therefore, the timing at which drive transistor 2b is turned on is determined by the delay time of delay circuit 118b. When the invalid data signal is not output, even when the drive transistor 2b is turned on, the potential of the output node is sufficiently low, ringing does not occur, and an “L” signal can be output stably.

Various modifications can also be made in the modification shown in FIG.
[Modification 2]
FIG. 27 is a diagram showing the configuration of the output circuit control unit of the second modification of the fourth embodiment. In FIG. 27, the output control circuit 100 outputs the internal read data signal ZDD and the output of the inverter circuit 5. NAND circuit 121 that receives output permission signal OEM and latch circuit 122 that receives output permission signal OEM and the output of NAND circuit 121. Latch circuit 122 includes NAND circuits NA11 and NA12. NAND circuit NA11 receives output permission signal OEM at its one input and the output of NAND circuit NA12 at its other input. NAND circuit NA12 receives the output of NAND circuit 121 at one input and the output of NAND circuit NA11 at the other input.

  The output control circuit 100 further includes an inverter circuit 124 that receives the output of the NAND circuit NA12 of the latch circuit 122, a delay circuit 123 that delays a signal on the node N2, and an output of the inverter circuit 124 and an output of the delay circuit 123. Receiving NAND circuit 126, delay circuit 125 delaying the output of inverter circuit 124 for a predetermined time T4, NAND circuit 89 receiving the output of NAND circuit 126 and the output of delay circuit 125, the output of NAND circuit 89 and the node N2 AND90 which receives the signal of. A drive control signal is applied from AND circuit 90 to the gate of drive transistor 2b. Next, the operation of the output control unit shown in FIG. 27 will be described with reference to FIG. In the output control circuit shown in FIG. 27, output instruction signal DOT is not used.

  First, with reference to FIG. 28A, an operation when an invalid output exists will be described. When an invalid data signal is output, output permission signal OEM rises to “H” before the change of internal read data signal ZDD. When internal read data signal ZDD rises to “H” in the state where output permission signal OEMT is “H”, the potential of node N 2 rises to “H” via AND circuit 4.

  On the other hand, even if internal read data signal ZDD rises to “H”, the output of inverter circuit 5 is at “H” level due to the delay time of inverter circuit 5. Therefore, the NAND circuit 121 outputs a signal that has all three inputs thereof set to “H” and is set to “L” during the delay time of the inverter circuit 5.

  When the “L” signal is output from the NAND circuit 121 to the node N82, the output of the NAND circuit NA12 included in the latch circuit 122 becomes “H”. The output of the NAND circuit NA11 becomes “L” by the “H” signal given from the NAND circuit NA12 to the node N84. The “H” state of the output node N84 of the latch circuit 122 is held while the output permission signal OEM is “H”.

  When the potential on the node N84 rises to “H”, the inverter circuit 124 sets the potential of the node N85 to “L”. The output of the delay circuit 123 is at “L” before the output of the inverter circuit 124 falls to “L”. When the output of the delay circuit 123 becomes “H” in response to the rise of the potential of the node N2, the potential of the node N85 is already “H”. Therefore, the output of the NAND circuit 126 is fixed to “H”.

  When “L” on the node N85 is transmitted to one input of the NAND circuit 89 via the delay circuit 125, an “H” signal is output from the NAND circuit 89 to the node N30. In response to this, an “H” signal is output from AND circuit 90 onto node N31, and drive transistor 2b is turned on. That is, when an invalid data signal is output, the drive transistor 2b is turned on at a timing determined by the delay time T4 included in the delay circuit 125. The delay time of the delay circuit 125 is set longer than the delay time T3 of the delay circuit 123. Therefore, drive transistor 2b is turned on after the potential of output node 6 is sufficiently lowered, and the occurrence of ringing can be effectively prevented.

  Next, the operation when an invalid data signal is not output will be described with reference to FIG. When the invalid data signal is not output, the internal read data ZDD rises to “H” and becomes valid, and then the output permission signal OEM becomes “H”. When the output permission signal OEM becomes “H”, the output of the inverter circuit 5 is already “L”, and the output of the NAND circuit 121 is “H”. Even if the internal read data signal ZDD changes from “L” to “H”, the output permission signal OEM is still “L” in that case. Therefore, the NAND circuit 121 always outputs a “H” signal.

  When the output permission signal OEM becomes “H”, the potential of the node N2 rises to “H”. In the latch circuit 122, when the output of the NAND circuit 121 is “H” and the output permission signal OEM is “L”, the NAND circuit NA11 outputs a signal of “L”, and the NAND circuit NA12 outputs “H”. "Signal is output. Therefore, in the NAND circuit NA11, even if the output permission signal OEM rises to “H”, the potential of the node N84 is “L”, and the output of the NAND circuit NA11 is fixed to “H”. That is, the potential of the node N84 is fixed to “L”, and the potential of the node N85 is fixed to “H”.

  After the potential of the node N2 rises from “L” to “H” and the delay time T3 of the delay circuit 123 has elapsed, the output of the delay circuit 123 becomes “H” and the output of the NAND circuit 126 becomes “L”. . Although the output of delay circuit 125 is fixed to “H”, in response to the “L” signal transmitted from NAND circuit 126 to node N86, the output of NAND circuit 89 rises to “H”. As a result, the output of the AND circuit 90 rises to "H". That is, when the invalid data signal is not output, the timing at which the drive transistor 2b is turned on is determined by the delay time T3 of the delay circuit 123. Drive transistor 2b is turned on in a relatively short period after the effective data signal is output. In this case, output node 6 is discharged from, for example, an intermediate potential, and the potential level is sufficiently lowered. Even when the drive transistor 2b is turned on, no ringing occurs and a stable output signal is obtained.

  In the configuration of the output control circuit of the second modified example shown in FIG. 27, the configuration for pulling up the output signal may be used as in the first modified example, and other similar modifications may be made. It may be done.

[Modification 3]
FIG. 29 is a diagram illustrating a configuration of a third modification of the fourth embodiment. FIG. 29 also shows the configuration of the output control circuit for discharging output node 6 to the ground potential level.

  29, output control circuit 100 includes output permission signal OEM, internal read data signal ZDD, NAND circuit 130 that receives the output of inverter circuit 5, and delay circuit 131 that delays the signal potential on node N2 for a predetermined time. In addition, latch circuit 132 that receives output permission signal OEM and the output of NAND circuit 130 is included. Latch circuit 132 includes NAND circuits NA13 and NA14 that are cross-coupled. NAND circuit NA13 receives output permission signal OEM at one input and the output of NAND circuit N14 at the other input. NAND circuit NA14 receives the output of NAND circuit 130 at one input and the output of NAND circuit NA13 at the other input.

  Output control circuit 100 further includes a NAND circuit 134 that receives the output of delay circuit 131 and the output of NAND circuit NA14 included in latch circuit 132, and an inverter circuit 133 that receives a signal output from latch circuit 132 to node N95. A NAND circuit 135 that receives the output of the inverter circuit 133 and the output of the delay circuit 131, a delay circuit 136 that delays the output of the NAND circuit 134 for a predetermined time T1, and a delay circuit 137 that delays the output of the NAND circuit 135 for a predetermined time T2. NAND circuit 139 receiving the outputs of delay circuits 136 and 137, and AND circuit 90 receiving the output of NAND circuit 89 and the signal potential on node N2. A signal is applied from AND circuit 90 to the gate of drive transistor 2b. Next, the operation of the output control circuit shown in FIG. 29 will be described with reference to FIG.

  First, the operation when there is an invalid output will be described with reference to FIG. In this case, first, output permission signal OEM rises to “H” when internal read data signal ZDD is “L”. In this state, the output of NAND circuit 130 (signal potential on node N92) is at "H".

  When valid data signal is transmitted and internal read data signal ZDD rises to "H", the potential of node N2 rises to "H". At this time, the NAND circuit 130 outputs a one-shot “L” signal according to the delay time of the inverter circuit 5. As a result, in the latch circuit 132, the output of the NAND circuit NA14 rises to "H", the signals of both inputs of the NAND circuit NA13 become "H", and the potential of the node N94 falls to "L". The latch state of the latch circuit 132 is maintained while the output permission signal OEM is “H”.

  After the delay time of delay circuit 131 elapses after the potential of node N2 rises to “H”, the potential of node N93 rises to “H”. The potential of the node N95 is “H”, and an “L” signal is output from the NAND circuit 134 to the node N97.

  On the other hand, since the potential of the node N96 is set to “L” by the inverter circuit 133, the NAND circuit 135 maintains the “H” state. Therefore, the output of the delay circuit 137 does not change and maintains the “H” state.

  After the delay time T1 of the delay circuit 136 has elapsed, the output of the delay circuit 136 becomes “L”, and an “H” signal is output from the NAND circuit 89 to the node N30. As a result, the output of the AND circuit 90 becomes “H” (the potential of the node N2 is already “H”). In response to the "H" signal on node N31, drive transistor 2b is turned on, and output node 6 is discharged at high speed.

  Next, an operation when an invalid data signal is not output will be described with reference to FIG. In this case, after the internal read data signal ZDD becomes “H”, the output permission signal OEM becomes “H”. Therefore, the output of the NAND circuit 130 is fixed to “H” and the initial state is maintained by the latch circuit 130. In the initial state, the latch circuit 132 outputs the “L” signal to the node N95 because the output permission signal OEM is “L”. Therefore, the inverter circuit 133 always outputs a “H” signal on the node N96.

  After the delay time of the delay circuit 131 elapses after the potential of the node N92 rises to “H”, the potential of the node N93 rises to “H”. The potential of the node N95 is “L”, and the potential of the node N96 is “H”. Therefore, when the potential of node N93 rises to “H”, an “L” signal is output from NAND circuit 135 to node N98. When the delay time T2 of the delay circuit 137 elapses, the output of the delay circuit 137 rises to “H”. As a result, an "H" signal is output from the NAND circuit 89 to the node N30, and an "H" signal is output from the AND circuit 90 on the node N31, so that the drive transistor 2b is turned on.

  That is, when there is a possibility that an invalid data signal is output, the timing at which the drive transistor 2b is turned on is determined by the delay time of the delay circuits 131 and 136. When the invalid data signal is not output, the timing at which the drive transistor 2b is turned on is determined by the delay times of the delay circuit 131 and the delay circuit 137. Thus, the drive transistor 2b can be turned on at an optimal timing according to whether or not an invalid data signal is output, and an output signal can be stably output without ringing.

  In the output control circuit shown in FIG. 29, various modifications can be made as in the first modification.

[Modification 4]
FIG. 31 is a diagram showing a fourth modification of the output control circuit according to the fourth embodiment. In FIG. 31, output control circuit 100 includes inverter circuit 110 and AND circuit 111 for generating a one-shot “H” pulse signal in response to the rise of the signal potential on node N2, and output instruction signal DOT. NAND circuit 141 receiving the output of AND circuit 111 and a latch circuit 142 receiving the signal on node N2 and the output of NAND circuit 141. Latch circuit 142 includes NAND circuits NA15 and NA16. NAND circuit NA15 receives the output of NAND circuit 141 at one input and the output signal of NAND circuit NA16 at the other input. NAND circuit NA16 receives the signal potential on node N2 at one input and the output of NAND circuit NA15 at the other input.

  Output control circuit 100 further includes a delay circuit 143 that receives the output of NAND circuit NA15 of latch circuit 142, a delay circuit 146 that receives a signal on node N2, and an AND circuit 144 that receives the outputs of delay circuits 146 and 143. Inverter 147 for inverting the signal on node N2, the output of inverter 147, and NOR circuit 145 are included. A drive control signal is applied from NOR circuit 145 to the gate of drive transistor 2b via node N31.

  Delay circuits 143 and 146 delay a given signal for a predetermined time and invert its logic. The inverter circuit 147 also has a function as a delay circuit.

  Next, the operation of the output control circuit shown in FIG. 31 will be described with reference to FIG.

  First, an operation when an invalid data signal is output will be described with reference to FIG.

  First, the output permission signal OEM rises to “H”. In this state, the potential of node N2 is at “L” without changing because internal read data signal ZDD is “L”.

  When output permission signal DOT falls to “L”, a valid data signal of “H” is transmitted onto internal read data line 915b after a predetermined time has elapsed. In accordance with this “H” internal read data signal ZDD, the potential of node N2 rises to “H”. In response to the rising of the potential of the node N2, the AND circuit 111 outputs a one-shot “H” signal. The pulse width of the one-shot pulse signal output from the AND circuit 111 is determined by the delay time of the inverter circuit 110.

  When this one-shot pulse signal is generated from the AND circuit 111, the output instruction signal DOT is still at “L”, and the output of the NAND circuit 141 is fixed at “H”. In the latch circuit 142, in the initial state, the node N2 is at "L", the "H" signal is output from the NAND circuit NA16, and the "L" signal is output from the NAND circuit NA15. ing. Therefore, even when the potential of the node N2 rises to “H”, the signal applied from the NAND circuit NA16 to the node N106 is “H” and does not change. That is, the latch state of the latch circuit 142 does not change at all, and the potential of the node N105 is fixed to “L”.

  When the potential of the node N2 rises to “H”, after the delay time of the inverter 147 has elapsed, an “L” signal is output from the inverter circuit 147 to the node N107. The AND circuit 144 receives the “H” signal from the delay circuit 143. Therefore, after the delay time of the delay circuit 146 elapses after the potential of the node N2 rises to “H”, the potential of the node N108 becomes “L” and the output of the AND circuit 144 becomes “L”. The NOR circuit 145 receives the “L” signal at both its inputs, and raises the potential of the node N31. At this time, as will be described later, the NOR circuit 145 and the AND circuit 144 constitute a composite gate, and only one p-channel MOS transistor is turned on at its output. As a result, the potential of the node N31 rises gradually, and the driving force of the drive transistor 2b is gradually increased. Thereby, the potential drop of the output node 6 is moderated. As a result, even when an invalid signal is output, the drive power of the drive transistor 2b is increased after a sufficient time has elapsed, and a signal of “L” can be stably output without ringing. Can be output.

Next, the operation when invalid data is not output will be described with reference to FIG.
First, an output instruction signal DOT is generated. In response to the output instruction signal DOT, the valid data signal ZDD rises to “H”. In this state, the potential of the node N2 is “L”.

  After output instruction signal DOT rises to “H”, output enable signal OEM rises to “H”, and the potential of node N2 rises to “H”. When the potential of the node N <b> 2 rises to “H”, the AND circuit 111 generates a “H” one-shot pulse signal by the delay function of the inverter circuit 110. In response to the “H” one-shot pulse signal from the AND circuit 111, a one-shot “L” pulse signal is generated from the NAND circuit 141 to the node N104 (the signal DOT is already at “H”). In response to the “L” signal on node N104, the output of NAND circuit NA15 of latch circuit 142 rises to “H”. In response to the “H” signal applied from the NAND circuit NA15 to the node N105, the NAND circuit NA16 outputs an “L” signal to the node N106. This state is maintained while the potential of the node N2 is “H”.

  On the other hand, in response to the rise of the potential of the node N2, the output of the inverter circuit 147 becomes “L”, and the output of the NOR circuit 145 gradually rises. Next, the output of the delay circuit 146 falls to “L” after the delay time has elapsed in response to the rise of the signal on the node N2, and the output of the AND circuit 144 becomes “L”. The output of the delay circuit 143 falls to “L”. As a result, in the composite gate composed of the AND circuit 144 and the NOR circuit 145, at least two p-channel MOS transistors are turned on, and unlike the case where an invalid data signal is output, the potential of the node N31 is increased with a large driving force. The drive transistor 2b is turned on at a relatively fast timing after the valid data signal appears at the node N2, and discharges the output node 6 with a strong driving force. As a result, the potential of the output node 6 falls at a high speed.

  As described above, the gate that controls the potential of the gate of the drive transistor 2b is configured by a composite gate, and the number of charging transistors that are turned on among the transistors of the composite gate is varied according to the presence or absence of invalid data output, Output node 6 can be discharged to the ground potential level at the optimum timing.

  FIG. 33 is a diagram showing a specific configuration of a composite gate of the AND circuit and the NOR circuit shown in FIG. Referring to FIG. 33, AND circuit 144 and NOR circuit 145 are p-channel MOS transistors connected in series between power supply potential supply node and output node N31 and having respective gates connected to nodes N107 and N109. 151 and 152, p-channel MOS transistors 153 and 154 connected in series between power supply potential supply node and node N31, with their gates connected to nodes N107 and N108, output node N31 and ground potential node, N-channel MOS transistor 155 having a gate connected to node N107 and an n-channel MOS transistor connected in series between node N31 and a ground potential node and receiving the potentials of nodes N108 and N109 at its gate MOS transistor 156 Including the preliminary 157.

  In the structure of the composite gate shown in FIG. 33, when the potential of the node N107 is “L”, the NOR circuit 145 functions as an inverter circuit. When the potential of the node N107 is “L”, the transistors 151 and 153 are turned on and the transistor 155 is turned off in FIG. When the potential of the node N108 is “L”, the transistor 154 is turned on. Therefore, output node N31 is charged only through transistors 153 and 154 when an invalid data signal may be output. At this time, the transistor 156 is in an off state, there is no discharge path, and the potential of the node N31 rises gently.

  On the other hand, when both of the potentials of nodes N108 and N109 are “L”, the potential of node N107 is “L”, so that node N31 is charged through transistors 151 and 152 and further connected to nodes via transistors 153 and 154. N31 is charged. At this time, since all the discharging transistors 155, 156 and 157 are in the off state, the node N31 is charged at a relatively high speed and the potential rises at a high speed.

  When the potential of the node N107 becomes “H”, the transistor 155 is turned on, the node N31 is discharged through the transistor 155, and the potential becomes “L”. At this time, the transistors 151 and 153 are off.

  By using the composite gate as shown in FIG. 33 described above, the rising speed of the potential of the gate of the drive transistor 2b, that is, the node N31 can be switched depending on whether or not an invalid data signal is output, and the drive transistor 2b can be switched at an optimum timing. The driving force can be increased.

  In the structure of the composite gate shown in FIG. 33, p channel MOS transistors 151 and 153 may be shared and may be configured by one p channel MOS transistor. In the output control circuit shown in FIG. 31, various modifications can be added as in the previous embodiment.

[Modification 5]
FIG. 34 is a diagram illustrating a configuration of an output circuit which is a fifth modification of the fourth embodiment. 34, the output circuit receives delay circuit 161 that delays output permission signal OEM for a predetermined time T5, inverter circuit 5 that inverts internal read data signal ZDD, the output of delay circuit 161, and the output of inverter circuit 5. AND circuit 3, AND circuit 4 receiving output permission signal OEM and internal read data signal ZDD, n-channel MOS transistor which conducts in response to the output of AND circuit 3 and charges output node 6 to power supply potential Vcc level And drive transistor 2a formed of an n-channel MOS transistor that conducts in response to the output of AND circuit 4 and discharges output node 6 to the ground potential level.

  The output circuit further includes a delay circuit 160 that delays the output of the AND circuit 4 for a predetermined time T6, and an AND circuit 90 that receives the signal of the node N2 (the output of the AND circuit 4) and the output of the delay circuit 160. The output of AND circuit 90 is applied to the gate of drive transistor 2b. The current driving capability of the drive transistor 2b is larger than the current driving capability of the drive transistor 2a. Next, the operation of the output circuit shown in FIG. 34 will be described with reference to FIG. 35 and FIG.

  First, with reference to FIG. 35A, an operation when an invalid data signal is not output will be described. When the invalid data signal is not output, internal read data signal ZDD rises to “H” and then rises to output permission signal “H”. In response to the rise of output permission signal OEM, AND circuit 4 outputs a signal of “H” to node N2. In response to the rise of the potential of node N2, drive transistor 2a is turned on, and the potential of output node 6 is slowly discharged to the ground potential level.

  Next, after the delay time T6 of the delay circuit 160 has elapsed, the output of the delay circuit 160 becomes “H”, and the output of the AND circuit 90 becomes “H”. As a result, drive transistor 2b is turned on, and the potential of output node 6 is discharged to the ground potential level at high speed. When the drive transistor 2b is turned on, the potential of the output node 6 is sufficiently low. Even if the potential of the output node 6 is discharged at high speed by the drive transistor 2b, the output signal can be stably output without ringing. Obtainable.

  Here, even if the output permission signal OEM rises to “H”, the node N1 always maintains the “L” potential because the internal read data signal ZDD is already “H”, and the drive transistor 1 In the off state.

  Next, an operation when an invalid data signal is output will be described with reference to FIG. When the invalid data signal is output, the output permission signal OEM rises to “H”. At this time, the internal read data signal ZDD is still at "L". Therefore, the output of the inverter circuit 5 is at “H”. After the delay time T5 of the delay circuit 161 has elapsed after the output permission signal OEM has risen to “H”, the output of the AND circuit 3 (potential of the node N1) rises to “H” and the drive transistor 1 is turned on. A state is entered and the output node 6 is charged.

  Next, when the valid data signal is transmitted and internal read data signal ZDD rises to "H", the output of inverter circuit 5 becomes "L". As a result, the output of the AND circuit 3 (node N1 potential) becomes “L”, and the drive transistor 1 is turned off. On the other hand, in response to the change of internal read data signal ZDD to "H", the output of AND circuit 4 (potential of node N2) rises to "H", and drive transistor 2a is turned on. As a result, the potential of output node 6 is gently discharged to the ground potential level.

  Next, after the delay time T6 of the delay circuit 160 has elapsed, the output of the delay circuit 160 rises to “H”, and the output of the AND circuit 90 rises to “H”. As a result, drive transistor 2b is turned on, and the potential of output node 6 is discharged to the ground potential level at high speed.

  When this invalid data signal is output, the time that the invalid data signal appears at the output node 6 is shortened by the delay time T5 of the delay circuit 161. Therefore, the time for the invalid data signal to appear at the output node 6 is shortened, and the amount of potential change due to the invalid data signal at the output node 6 can be reduced. As a result, when the drive transistor 2b is turned on after the drive transistor 2a is turned on and the potential of the output node 6 is discharged, the potential of the output node 6 is sufficiently lowered, which is effective in generating ringing. Therefore, a stable output signal can be obtained.

  If the delay time T5 of the delay circuit 161 is set so that the AND circuit 3 does not output the “H” signal to the node N1 until the internal read data signal ZDD becomes “H” in the valid state, an invalid data signal is output. Can be prevented.

  In the case of the configuration shown in FIG. 34, when the invalid data signal is not output (see FIG. 35A), the delay circuit is used until the potential of the node N1 becomes “H” after the output permission signal OEM becomes “H”. 161 is delayed by a delay time T5. Therefore, in this case, only the access time of “H” output is delayed. When the access time is determined by the “L” output time and the “H” access time is shorter than the “L” access time, the access time can be prevented from deteriorating.

  In the configuration shown in FIG. 34, a configuration in which output node 6 is discharged to the ground potential level is shown. However, also in the configuration shown in FIG. 34, a configuration similar to that of delay circuit 151 is provided for AND circuit 4, delay circuit 160 and AND circuit 90 are provided for node N1, and drive transistor 1 is provided. By providing a drive transistor having a larger driving force in parallel with drive transistor 1, it is possible to prevent the occurrence of ringing when the potential of output node 6 rises.

  In the delay circuits 161 and 160 shown in FIG. 34, the number of inverter stages may be set to an appropriate value. Delay circuits 160 and 161 may be realized by a delay element different from the inverter.

[Modification 6]
FIG. 36 is a diagram illustrating a configuration of an output circuit which is a sixth modification of the fourth embodiment. 36, the output circuit receives inverter circuit 5 that inverts internal read data signal ZDD, AND circuit 3 that receives output permission signal OEM and the output of inverter circuit 5, and receives output permission signal OEM and internal read data signal ZDD. The AND circuit 4 includes a delay circuit 160a that delays the output permission signal OEM for a predetermined time Ta, and a delay circuit that delays the output of the AND circuit 4 for a predetermined time Tb. The delay time Ta included in the delay circuit 160a is shorter than the delay time Tb included in the delay circuit 160b. Delay time Ta included in delay circuit 160a is set to a time width for preventing an invalid data signal from appearing at node N2 when "L" data is read. Therefore, delay time Ta of delay circuit 160a is set to, for example, the maximum value of the specification value of the time required from the change of the column address signal to the fall of column address strobe signal ZCAS to "L". As a result, the invalid data signal can be prevented from being transmitted to the node N2. Next, the operation of the circuit shown in FIG. 36 will be described.

  First, the operation when the data signal Q of “H” is output will be described with reference to the operation waveform diagram of FIG.

  In this case, internal read data signal ZDD is "L" (internal read data signal ZDD is once precharged to "L" during standby or before data read operation). In this state, when the output permission signal OEM rises to “H”, the AND gate 3 outputs a signal “H” on the node N1. In response to the rise of the potential on node N1, drive transistor 1a is turned on. The current driving capability of the drive transistor 1a is relatively small. Thereby, output node 6 is slowly charged through drive transistor 1a.

  Next, after the delay time Ta of the delay circuit 160a elapses, the output of the delay circuit 160a rises to "H", and the output of the AND circuit 90a rises to "H". As a result, drive transistor 1a is turned on. The drive transistor 1b has a sufficiently large current driving capability. As a result, output node 6 is charged at high speed by drive transistor 1b, and its potential rises rapidly.

  Next, with reference to FIG. 38, an operation when an invalid data signal is output when “L” data is output will be described. In this case, first, the output permission signal OEM rises to “H”. At this time, internal read data signal ZDD is at "L", and the output of inverter circuit 5 is at "H". Therefore, in response to the rise of output permission signal OEM, AND circuit 3 outputs a signal of “H” to node N1. In response to the rise of the signal potential on node N1, drive transistor 1a having a small current driving capability is turned on, and the potential of output node 6 is gradually increased.

  Next, when the valid data signal is transmitted and internal read data signal ZDD rises to "H", the output of AND circuit 3 becomes "L" and drive transistor 1a is turned off. In response to the internal read data signal ZDD of “H”, the AND circuit 4 outputs an “H” signal to the node N2, and the drive transistor 2a having a small current driving capability is turned on. Thereby, the increased potential of output node 6 is gently discharged to the ground potential level.

  Next, when the delay time Tb of the delay circuit 160b elapses, the output of the delay circuit 160b becomes “H” (node N30b potential), and the AND circuit 90b outputs an “H” signal to the node N31b. As a result, drive transistor 2b having a large current driving capability is turned on, and output node 6 is discharged to the ground potential level at high speed.

  Even when an invalid data signal is output, first, the drive transistor 1a having a small current driving capability is turned on to charge the output node 6. In this case, since the drive transistor 1a has a small current driving capability, the potential rise at the output node 6 is negligible. Therefore, the potential amplitude of output node 6 can be made sufficiently small, and the occurrence of ringing can be effectively prevented.

  Note that the drive transistor 1b having a large current driving capability maintains the OFF state because the potential level of the node N31a is fixed to “L”. This is because when the output of the delay circuit 160a becomes “H”, the potential of the node N1 is already “L”.

  Next, the operation when an invalid data signal is not output will be described with reference to FIG. In this case, first, internal read data signal ZDD rises to "H". As a result, the potential of the node N1 is fixed to “L”.

  Next, when the output permission signal OEM rises to “H”, the potential of the node N 2 rises to “H” via the AND circuit 4. When the predetermined time Ta elapses, the output of the delay circuit 160a rises to “H”. However, since the potential of the node N1 is at “L”, the output of the AND circuit 90a is “L”, and the drive transistor 1b maintains the off state together with the drive transistor 1a.

  On the other hand, in response to the rise of the potential of node N2, drive transistor 2a is turned on, and output node 6 is slowly discharged. Next, when the output of the delay circuit 160b rises to “H”, the potential of the node N31b rises to “H” via the AND circuit 90b, and the drive transistor 2b is turned on. Thereby, output node 6 is discharged to the ground potential level at a high speed. When drive transistor 2b is turned on, the potential of output node 6 has already been sufficiently lowered by drive transistor 2a, and an output signal can be stably generated without ringing.

  In the configuration shown in FIG. 36, the drive transistors 1a and 1b may be realized by appropriately setting the difference in current driving capability between the size, the gate width, or the ratio between the gate width and the gate length. Further, a voltage of the power supply voltage Vcc level may be applied to the drive transistor 1a, and a voltage obtained by boosting the power supply voltage Vcc may be applied to the drive transistor 1b to the gate. The adjustment of the gate voltages of the drive transistors 1a and 1b may be used in combination with the adjustment of the size. The structure in which the gate voltages are made different may be applied to drive transistors 2a and 2b that discharge output node 6 to the ground potential level.

  In the configuration of the output circuit shown in FIG. 36, a configuration in which the output permission signal OEM is supplied to the AND circuit 3 after passing through the delay circuit may be used as in the case of the fifth modification. In this case, the time when the potential of the node N1 rises can be delayed, the time when the invalid data signal is output can be shortened, and the potential amplitude of the output node 6 can be further reduced.

  In the configuration shown in FIG. 36, by providing a circuit configuration similar to that shown in the figure to the drive transistor for raising the potential of output node 6, the invalid data signal is "L". In this case, it is possible to prevent the potential amplitude of the output node 6 from increasing, and to prevent ringing in this case.

[Modification 7]
FIG. 40 is a diagram illustrating a configuration of an output circuit according to a seventh modification example of the fourth embodiment. Referring to FIG. 40, the output circuit includes an inverter circuit 5 that inverts internal read data signal ZDD, an AND circuit 3 that receives output instruction signal DOT, output permission signal OEM, and the output of inverter circuit 5, and AND circuit 3 In response to the output of drive transistor 1, drive transistor 1 charging output node 6 to power supply potential Vcc level, AND circuit 4 receiving output permission signal OEM and internal read data signal ZDD, and responding to the output of AND circuit 4 Drive transistor 2a having a relatively small current driving capability for conducting and discharging output node 6 to the ground potential level.

  The output circuit further includes a delay circuit 160 that delays the output of AND circuit 4 (the potential of node N2) for a predetermined time, and an AND circuit 90 that receives the output of delay circuit 160 and the signal of node N2. The output of the AND circuit 90 is given to the gate of the drive transistor 2b having a large current driving capability. Next, the operation of the output circuit shown in FIG. 40 will be described with reference to FIG.

  First, the operation when the invalid output data signal is “H” and the valid data signal is “L” will be described. In this case, the output permission signal OEM rises to “H” before the output instruction signal DOT falls. Internal read data signal ZDD on internal data bus line 915b is at "L", and the output of inverter circuit 5 is at "H". Therefore, in response to the rise of output permission signal OEM, AND circuit 3 outputs an “H” signal on node N1. As the potential on node N1 rises, drive transistor 1 is turned on. At this time, the output of the AND circuit 4 (the potential of the node N2) is “L”, and the drive transistors 2a and 2b are off. Therefore, the output node 6 is charged via the drive transistor 1, and its potential rises.

  When output instruction signal DOT falls to “L”, the potential of node N1 falls to “L”, and drive transistor 1 is turned off. Next, in response to the fall of output instruction signal DOT, "H" valid data signal ZDD is transmitted to internal data bus line 915b, and "L" signal is output from inverter circuit 5 to node N90. As a result, the output of the AND circuit 3 during the output of the data ZDD, that is, the potential of the node N1 is fixed to “L”.

  When internal read data signal ZDD becomes “H”, AND circuit 4 outputs a signal of “H” on node N2, and drive transistor 2a is turned on. As a result, the output node 6 is slowly discharged, and the potential of the output node gradually decreases.

  Next, when a predetermined time elapses, the output of the delay circuit 150 becomes “H”, and the AND circuit 90 outputs an “H” signal on the node N31. As a result, drive transistor 2b is turned on, and output node 6 is discharged to the ground potential level at a high speed.

  In the case of the configuration shown in FIG. 41, even when an invalid data signal is output, the period during which output node charging drive transistor 1 is on is extremely short, and the potential amplitude of output node 6 can be reduced. It becomes. Further, when the output permission signal OEM becomes “H” after the output instruction signal DOT becomes “L”, it is possible to completely prevent the invalid data from being output. When the valid output data signal is “H”, the internal read data signal ZDD is fixed to “L” as shown by a broken line in FIG. In this case, the output of inverter circuit 5 is at “H”, and the potential at node N1 rises to “H” when output instruction signal DOT rises to “H”. On the other hand, the output of the AND circuit 4 is “L”, and the drive transistors 2a and 2b maintain the off state. Therefore, output node 6 is charged to power supply potential Vcc level via drive transistor 1. That is, when the valid output data signal is “H”, the drive transistor 1 is turned on in response to the rise of the output permission signal OEM, and then once in response to the transition of the output instruction signal DOT to “L”. When the output instruction signal DOT becomes “H” again after being turned off, the drive transistor 1 is turned on again.

  Next, with reference to FIG. 42, an operation when an invalid data signal is not output at the time of reading “L” output data will be described. In this case, first, the output instruction signal DOT falls to “L”. In this state, internal read data signal ZDD is at "L", and the output of inverter circuit 5 (potential of node N90) is at "H". Since the output permission signal OEM is at “L”, the potential of the node N1 is at “L”.

  The valid data signal is transmitted to the internal data bus line 915b after the elapse of a predetermined time after the output instruction signal DOT falls to "L", and the internal read data signal ZDD rises to "H". Thereby, the potential of node N90 falls to "L", and the potential of node N1 is fixed to "L" during the internal read data signal ZDD reading. At this time, the potential of the node N2 is still “L” because the output permission signal OEM is “L”. When the output permission signal OEM rises to “H”, the potential of the node N 2 rises to “H” via the AND circuit 4. As a result, drive transistor 2a is turned on, and output node 6 is gently discharged to the ground potential level. Next, when a predetermined time elapses, the output of the delay circuit 160 becomes “H”, and the output of the AND circuit 90 becomes “H”. As a result, drive transistor 2b is turned on, and output node 6 is discharged to the ground potential level at high speed. When drive transistor 2b is turned on, the potential of output node 6 is sufficiently lowered, and an output signal can be stably output without ringing.

  In the configuration shown in FIG. 40, instead of the output instruction signal DOT, a one-shot pulse signal generated in response to the column address signal change detection signal φATD and becoming “L” at a timing earlier than the output instruction signal DOT is provided. May be used. This can be created by using an appropriate delay circuit in the one-shot pulse generation circuit 50 shown in FIG. If such a signal is used, the pulse width of the one-shot pulse signal generated in response to the rise of the output signal OEM can be further shortened in the operation waveform diagram shown in FIG. The output time of the output data signal can be further shortened, and the potential amplitude of the output node 6 can be further reduced.

  Further, in response to the column address change detection signal φATD, a signal that changes from “H” to “L” at a timing faster than the output permission signal OEM changes from “L” to “H” is supplied to the AND circuit 3. Thus, it is possible to prevent the invalid data signal from appearing at the node N1. As such a signal, in the configuration shown in FIG. 5, a circuit that generates a one-shot pulse signal that becomes “L” for a predetermined period in response to the fall of the potential of the output node N14 of the latch circuit is used. That's fine. The rise of the pulse signal may be determined by the fall of the output instruction signal DOT. As such a signal generation circuit, an AND circuit that receives a signal on node N14 and output instruction signal DOT shown in FIG. 5 can be used. By using such a configuration, it is possible to reliably prevent an invalid data signal from being output to the node N1.

  40, the output permission signal OEM may be provided to the AND circuit 3 through a delay circuit. In this case, the time during which the invalid data signal is output to the node N1 can be shortened, and the potential amplitude of the output node 6 can be reduced. Furthermore, if the delay time of the delay circuit is set to an appropriate value, generation of an invalid data signal at node N1 can be prevented.

[Modification 8]
FIG. 43 is a diagram showing an eighth modification of the output circuit. In the configuration shown in FIG. 43, three drive transistors 2a, 2b and 2c for discharging output node 6 are provided. The drive transistors 2a, 2b and 2c have different gate widths W from small, medium and large in order. That is, the current driving capabilities of the drive transistors 2a, 2b, and 2c are different. The output of AND circuit 90a is applied to the gate of drive transistor 2b. AND circuit 90a receives the potential on node N2 and the output of delay circuit 160a. Delay circuit 160a delays the potential signal at node N2 for a predetermined time. The output of the delay circuit 160a is further delayed by the delay circuit 160b. The output of the AND circuit 90b is applied to the gate of the drive transistor 2c. AND circuit 90b receives the signal on node N2 and the output of delay circuit 160b.

  In the case of the configuration of the output circuit shown in FIG. 43, when the potential of the node N2 becomes “H”, first, the drive transistor 2a is turned on, and the output node 6 is slowly discharged. Then, when a predetermined period elapses, the output of the AND circuit 90a becomes "H", the drive transistor 2b is turned on, and the output node 6 is discharged to the ground potential level.

  When a predetermined time further elapses, the output of the delay circuit 160b becomes “H”, the output of the AND circuit 90b turns on the drive transistor 2c, and the output node 6 is discharged to the ground potential level at a high speed. In this way, three drive transistors for discharging the output node are provided, and the output signal can be stably generated without causing ringing by changing the timing of turning on each of the drive transistors. The configuration of the output circuit shown in FIG. 43 can be used in combination with the first to third embodiments.

[Modification 9]
FIG. 44 is a diagram illustrating a ninth modification example of the fourth embodiment. FIG. 44 shows a configuration of gate circuit 90 for directly driving drive transistor 2b for discharging output node 6 to the ground potential level. This gate circuit 90 can be used in each embodiment and modification. In FIG. 44, a basic circuit configuration is shown as the configuration of the output circuit.

  In FIG. 44, drive transistor 2a is driven by NAND circuit 4a and inverter circuit 4b. NAND circuit 4a receives output permission signal OEM and internal read data signal ZDD. Inverter circuit 4b receives the output of NAND circuit 4a and transmits a logic signal corresponding to the internal read data signal onto node N2.

  The output circuit further includes a delay circuit 171a that delays the output of the NAND circuit 4a for a predetermined time, a delay circuit 171b that further delays the output of the delay circuit 171a, a drive transistor according to the outputs of the NAND circuit 4a and the outputs of the delay circuits 171a and 171b. 2b includes a gate circuit 90 for driving 2b. This gate circuit 90 corresponds to AND circuits 90a and 90b shown in FIG.

  Gate circuit 90 includes p channel MOS transistors 172, 173 and 174 provided in parallel with each other between a power supply potential node and internal node 177. The output of NAND circuit 4a, the output of delay circuit 171a, and the output of delay circuit 171b are applied to the gates of transistors 172, 173, and 174, respectively.

  Gate circuit 90 further includes an inverter circuit provided between internal node 177 and the ground potential. This inverter circuit is provided between output node N31 and internal node 177, and is provided between p channel MOS transistor 175 receiving the output of NAND circuit 4a at its gate, between output node N31 and the ground potential node, and N channel MOS transistor 176 receiving the output of NAND circuit 4a is included at the gate. Next, the operation of the gate circuit 90 will be briefly described.

  When the potential of the node N2 is “L”, the NAND circuit 4a outputs an “H” signal. In this state, transistors 172 through 175 are all off and transistor 176 is on. Therefore, output node N31 is at "L".

  When the output of the NAND circuit 4a becomes “L”, the potential of the node N2 becomes “H”, the drive transistor 2a is turned on, and the output node 6 is slowly discharged by the drive transistor 2a. In this state, when the output of the NAND circuit 4a becomes “H”, the transistors 172 and 175 are turned on and the transistor 176b is turned off. Therefore, output node N31 is slowly charged through transistors 172 and 175, and the potential thereof gradually rises. As a result, the driving force of the drive transistor 2b slightly increases.

  Next, when the output of the delay circuit 171a becomes “L”, the transistor 173 is turned on, the node N31 is charged via the transistors 172, 173 and 175, the potential rises a little faster, and the driving power of the drive transistor 2b also increases. A little bigger.

  When a predetermined time further elapses, the output of the delay circuit 171b becomes “L”, and the transistor 174 is turned on. As a result, a current flows into transistor 175 through transistors 172 to 174, the potential of node N31 rises at high speed, and the driving capability of drive transistor 2b is rapidly increased.

  As described above, by changing the rising speed of the output potential of the gate circuit 90 over time without using a delay circuit, the driving power of the drive transistor 2b also changes over time, and each of the previous embodiments. The same effects as those of the modification can be obtained. As shown in FIG. 44, even if the current driving capability of the drive transistor 2b is increased with time, the time change rate of current that causes ringing at the output node 6, that is, di / dt can be reduced. Occurrence can be prevented.

[Embodiment 5]
In a semiconductor device, an upper limit value Vcmx and a lower limit value Vcmn are set for the power supply voltage Vcc in order to ensure stable operation. For example, when the operating power supply voltage Vcc is 5V, the upper limit value Vcmx is set to 5.5V, and the lower limit value Vcmn is set to 4.5V. Generally, fluctuations in the power supply voltage Vcc within a range of ± 10% of the rated value of the power supply voltage Vcc are allowed.

  Similarly, an upper limit value Tamx and a lower limit value Tamn are set for the operating temperature Ta. As a range of such operating temperature Ta, 0 to 70 ° C. is defined in the specification.

  On the other hand, in a circuit having MOS transistors as its constituent elements, the operation speed increases as the power supply voltage Vcc increases. This is because the current driving capability of the MOS transistor is determined by its gate voltage (gate-source potential difference), and this potential difference is determined by the power supply voltage Vcc.

  The circuit having the MOS transistor as a constituent element has a higher operating speed as the operating temperature Ta is lower. This is because as the operating temperature increases, the resistance of the diffusion region increases, and the threshold voltage increases due to the influence of thermoelectrons and the like, so that the current driving capability decreases.

  A remarkable example of such circuit characteristics appears in a semiconductor memory device in which the access time ta becomes shorter as the power supply voltage Vcc becomes higher and the access time becomes longer as the operating temperature becomes higher.

  A configuration for reliably preventing the occurrence of ringing regardless of fluctuations in power supply voltage Vcc and operating temperature Ta will be described below.

  FIG. 45 is a diagram showing the characteristics of the first control voltage used in the fifth embodiment. As shown in FIG. 45A, the first control voltage VN increases as the ambient temperature T increases. That is, the first control voltage VN has a positive temperature coefficient. As shown in FIG. 45B, the first control voltage VN decreases as the power supply voltage Vcc increases. That is, the first control voltage VN has a negative dependency on the power supply voltage Vcc.

  FIG. 46 is a diagram showing the temperature and power supply voltage dependence characteristics of the second control voltage used in the fifth embodiment. As shown in FIG. 46A, the second control voltage VP decreases as the ambient temperature T increases. That is, the second control voltage VP has a negative temperature coefficient. As shown in FIG. 46 (b), the second control voltage VP increases as the power supply voltage Vcc increases. That is, the second control voltage VP has a positive dependency on the power supply voltage Vcc. The delay time of the delay stage is adjusted using the first and second control voltages VN and VP having mutually opposite voltages and power supply voltage dependency characteristics.

  FIG. 47 is a diagram showing a first configuration of the inverter circuit constituting the delay stage used in the fifth embodiment. 47A, the inverter circuit constituting the delay stage includes p channel MOS transistors 201 and 202 connected in series between power supply voltage Vcc supply node and output node 205, output node 205 and ground potential node. Includes an n-channel MOS transistor 203 provided therebetween. A second control voltage VP is applied to the gate of p-channel MOS transistor 201. The gates of MOS transistors 202 and 203 are both connected to input node 204. Next, operation characteristics of the inverter circuit shown in FIG. 47A will be described with reference to FIG.

  When the power supply voltage Vcc is at the lower limit value Vcmn or the operating temperature T is at the upper limit temperature Tamx, the second control voltage VP is small. Therefore, the current drivability of p-channel MOS transistor 201 is increased as compared with the condition of upper limit value Vcmx of power supply voltage Vcc or lower limit value Tamn of operating temperature T.

  When the input signal IN currently applied to the input node 204 is at a low level, the MOS transistor 202 is turned on and the MOS transistor 203 is turned off. Output node 205 is charged to power supply voltage Vcc level through transistors 201 and 202. Here, the second control voltage VP is set to a value sufficiently lower than the power supply voltage Vcc, and the transistor 201 can pass almost the power supply voltage Vcc. The optimum value of the second control voltage VP is determined according to the operating characteristics of the actual device.

  In this state, when power supply voltage Vcc is close to lower limit value Vcmn or operating temperature T is close to upper limit value Tamx, output node 205 is raised to a high level at high speed (the broken line in FIG. 47B). ).

  When input signal IN is at a high level, MOS transistor 203 is turned on, and output node 205 is discharged to the ground potential level. In this case, the discharge speed of the output node 205 is determined by the current driving capability of the transistor 203. That is, when the delay stage is configured using the inverter circuit shown in FIG. 47A, the time during which a low level signal is transmitted is longer when the upper limit value of power supply voltage Vcc and the ambient temperature are low.

  FIG. 48 is a diagram showing another configuration and operating characteristics of the inverter circuit constituting the delay stage. In FIG. 48A, an inverter circuit 210 includes a p-channel MOS transistor 211 provided between a power supply potential node and an output node 215, and an n-channel MOS provided in series between an output node 215 and a ground potential node. Transistors 212 and 213 are included. Input signal IN is applied to the gates of MOS transistors 211 and 212 via input node 214. The first control voltage VN is applied to the gate of the MOS transistor 213. Next, operation characteristics of the inverter circuit illustrated in FIG. 48A will be described with reference to FIG.

  The first control voltage VN has a negative dependency on the power supply potential Vcc and has a positive temperature coefficient. When the input signal IN is at a high level, the MOS transistor 212 is turned on. When power supply potential Vcc is close to upper limit value Vcmx and when ambient temperature T is close to lower limit value Tamn, first control voltage VN is low. Therefore, in this state, the current driving capability of MOS transistor 213 is reduced. Here, the first control voltage VN is set to a voltage value sufficiently higher than the threshold voltage of the MOS transistor 213. Therefore, when power supply voltage Vcc is high or ambient temperature T is low, output node 215 is discharged relatively slowly as compared to the case where power supply voltage Vcc is low. That is, when a high level signal is transmitted through the delay stage constituted by the inverter circuit shown in FIG. 48A, when the power supply potential Vcc is close to the upper limit value Vcmx or when the ambient temperature T is close to the lower limit value Tamn. Has a longer propagation time than otherwise.

  FIG. 49 is a diagram showing still another configuration and operating characteristics of the inverter circuit constituting the delay stage used in the fifth embodiment. 49A, inverter circuit 220 includes p-channel MOS transistors 221 and 222 connected in series between output node 226 and a power supply potential node, and in series between output node 226 and a ground potential node. N channel MOS transistors 223 and 224 connected are included. MOS transistors 222 and 223 have their gates connected to input node 225 to receive input signal IN. The second control voltage VP is applied to the gate of the MOS transistor 221, and the first control voltage VN is applied to the gate of the MOS transistor 224. Next, the operation of the inverter circuit shown in FIG. 49A will be described with reference to FIG.

  Inverter circuit 220 shown in FIG. 49A has a structure in which inverter circuits 200 and 210 shown in FIGS. 47A and 48A are combined. Therefore, when a high level signal is applied to input node 225, output node 226 is discharged at a higher speed when power supply potential Vcc is low or ambient temperature T is high than when it is not. Similarly, when a low level signal is applied to input node 225, when power supply potential Vcc is low or ambient temperature T is high, output node 226 is charged faster than otherwise. Therefore, when the delay stage is configured using the inverter circuit shown in FIG. 49A, the propagation delay time is close to the upper limit value or the ambient temperature T is high for both high level and low level signals. It becomes longer when is close to the lower limit.

  By configuring the delay stage using the inverter circuit as described above, the output signal Q can be stably output without causing access time fluctuations and ringing even with respect to fluctuations in the power supply voltage Vcc and the ambient temperature T. Can be generated.

  FIG. 50 is a diagram illustrating an example of application of the delay stage according to the fifth embodiment. 50A, a delay stage is provided in a circuit for generating output permission signal OEM shown in FIG. Delay stage 230 includes a delay stage 230 that delays and inverts delay signal ZCASE of the internal column address strobe signal. The output of delay stage 230 is provided to flip-flop 56. When the output of the delay stage 230 becomes high level, the output permission signal OEM output from the inverter circuit 58 becomes high level. This delay stage 230 corresponds to the inverter circuit 54 shown in FIG. Delay stage 230 includes three cascaded inverter circuits 231, 232, and 233. As the inverter circuits 231 to 233 included in the delay stage 230, the inverter circuit 220 shown in FIG. 49 or the inverter circuits 200 and 210 shown in FIGS. 47 and 48 are alternately connected. Generation of output permission signal OEM is triggered by the fall of signal ZCASE. Therefore, inverter circuits 231, 232 and 233 included in delay stage 230 are provided in the order of inverter circuits 200, 210 and 200. When the inverter circuit 220 shown in FIG. 49 is used, all of the inverter circuits 231 to 233 are composed of the inverter circuit 220.

  Next, the operation of the circuit shown in FIG. 50A will be described with reference to FIG.

  When the output instruction signal DOT goes low, the valid data ZDD is output in response. Consider a state where the output permission signal OEM rises to a high level prior to the fall of the output instruction signal DOT. This state corresponds to a state where invalid data is output. At this time, in delay stage 230, when power supply voltage Vcc is close to lower limit value Vcmn or ambient temperature T is high, the delay time is shortened. Therefore, the output permission signal OEM rises to a high level faster than when the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is close to the lower limit value Tamn. Therefore, when the power supply voltage Vcc is high or the ambient temperature T is low, the time during which the invalid data signal is output from the output node is “short”. When the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is close to the lower limit value Tamn, the driving capability of the MOS transistor is large. Therefore, when this invalid data signal is output, the voltage at the output node is reduced by “delaying” the time when the MOS transistor driving power, that is, the MOS transistor driving the output node is large, is turned on. The swing width can be made sufficiently small, and the occurrence of ringing can be reliably prevented.

  Further, even when the output enable signal OEN becomes “H” after the output instruction signal DOT becomes “L” and the effective data ZDD changes thereafter, the occurrence of ringing is similarly prevented to stably output the output data signal. Can be output.

  On the other hand, when the power supply voltage Vcc is close to the lower limit value Vcmn or the ambient temperature T is high, the on-timing of the MOS transistor that drives the output node becomes “fast”. However, in this case, since the driving force of the MOS transistor for driving the output node is small, the swing width of the voltage at the output node is not so large, and the occurrence of ringing can be surely prevented. When the invalid data signal is not output and the valid data signal is output (when the signal OEM rises to the high level after the signal DOT rises to the high level), the driving power of the MOS transistor for driving the output node is small. In such a case, since the timing of turning on is “fast”, an increase in access time is reliably prevented. Since the delay time is adjusted according to the operating conditions, the charge / discharge speed of the output node can be made almost constant regardless of the operating conditions.

  FIG. 51 is a diagram showing another application example of the delay stage according to the fifth embodiment of the present invention. As shown in FIG. 51A, inverter circuits 241 and 242 according to the fourth embodiment of the present invention are provided in delay circuit 161 in the output drive circuit shown in FIG. Other configurations are the same as those shown in FIG. Inverter circuits 241 and 242 utilize inverter circuit 220 shown in FIG. 49A or inverter circuits 200 and 210 shown in FIGS. In this case, in order to delay the rise of the output permission signal OEM to the high level, the inverter circuit 210 shown in FIG. 48 is used for the first-stage inverter circuit 241, and the inverter circuit 200 shown in FIG. Is used. Next, the operation of the output circuit shown in FIG. 51A will be described with reference to FIG.

  Consider an operation mode in which the valid data signal ZDD rises to a high level after the output permission signal OEM rises to a high level. This state is a mode in which an invalid data signal is output. In response to the rising of output enable signal OEM at the high level, the output of delay circuit 161 rises, and the potential of node 243 rises accordingly. At this time, the delay time of the delay circuit 161 is shortened when the power supply voltage Vcc is close to the lower limit value Vcmn or the ambient temperature T is close to the upper limit value Tamx. Therefore, the potential of the node 243 rises quickly when the driving force of the MOS transistor 2 becomes small. At this time, since the driving force of the MOS transistor 1 is reduced, the potential of the output node 6 gradually rises according to the invalid data signal. Thereafter, a valid data signal is transmitted, internal read data signal ZDD rises to a high level, and MOS transistor 1 is turned off. Although the time TB during which the invalid data signal is output is long, the current driving capability of the MOS transistor 1 is a small operating condition. Therefore, the potential amplitude rise of the output node 6 is relatively small, and the drive transistor 2 is turned on. However, the output data signal can be stably generated without causing ringing.

  On the other hand, in an operating condition in which the driving power of MOS transistors 1 and 2 is increased, the delay time of delay circuit 161 is lengthened. That is, when the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is close to the lower limit value Tamx, the delay time of the delay circuit 161 becomes longer, and the MOS transistor 1 is turned on at a later timing. Therefore, even when the current driving capability of the MOS transistor 1 is large, the time for which the MOS transistor 1 is turned on is short, and the potential rise at the output node 6 is small. Therefore, even if MOS transistor 2 is subsequently turned on in accordance with the transmission of the effective data signal, the potential amplitude of output node 6 is sufficiently small, and the occurrence of ringing can be reliably prevented.

  When a valid data signal is output, the potential of the node 243 is always at a low level, and the MOS transistor 1 maintains an off state.

  As described above, the potential amplitude of the output node 6 can be reduced regardless of the operating condition, and the deterioration of the access time can be surely prevented and the occurrence of ringing can be reliably suppressed regardless of the operating condition. it can.

  FIG. 52 is a diagram showing still another application example of the delay circuit according to the fifth embodiment of the present invention. The output control circuit illustrated in FIG. 52A has a structure similar to that of the output control circuit illustrated in FIG. In FIG. 52A, the inverter circuits shown in FIGS. 47 to 49 are applied to the inverter circuits 251 to 254 included in the delay circuit 160a. That is, also in this delay circuit 160a, the delay time is extended under the operating condition where the driving force of the MOS transistor is large. Other configurations are the same as those of the output control circuit shown in FIG. Next, the operation of the output control circuit shown in FIG. 52A will be described with reference to FIG.

  First, the output permission signal OEM rises to a high level. At this time, it is assumed that the internal read data signal ZDD is still at the low level. This state is an operation mode in which an invalid data signal is output. In response to the rise of the output permission signal OEM, the potential of the node N1 rises to a high level, the drive transistor 1a having a small current driving capability is turned on, and the output node 6 is slowly charged.

  Next, the output of the delay circuit 160a rises to a high level. In response to this, the output of AND circuit 90a rises to a high level, and drive transistor 1b is turned on via node N31a. When the output of the delay circuit 160a rises to a high level, if the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is close to the lower limit value Tamn, the delay is made slower than otherwise. Therefore, the timing at which the drive transistor 1b having a large current driving capability is turned on is delayed in an operating environment in which the current driving capability of the MOS transistor is increased. Therefore, the potential increase of the output node 6 can be reliably suppressed, and the potential amplitude of the output node 6 can be reduced to suppress the occurrence of ringing. At this time, if the delay time of the delay circuit 160a is set to an appropriate value, the time when the drive transistor 1b is turned on in the operating environment where the current driving capability of the MOS transistor is increased may be set to almost zero. it can.

  When only the valid data signal is output, the potential of the node N1 is at a low level, and the drive transistors 1a and 1b are not turned on. Therefore, ringing can be reliably prevented regardless of the operating environment.

  FIG. 53 is a diagram showing an example of application of the inverter circuit according to the fifth embodiment of the present invention to still another configuration. In FIG. 53A, inverter circuits 261 to 264 of the fourth embodiment are used for delay circuit 12 for driving drive transistor 2b for driving output node 6 to the ground potential level. . The delay time of the delay circuit 12 is shortened when the power supply voltage Vcc is close to the lower limit value Vcmn or the ambient temperature T is close to the upper limit value Tamx. Other configurations are the same as those of the output control circuit shown in FIGS. Next, operation of the output control circuit illustrated in FIG. 53A is described with reference to FIG.

  First, the output permission signal OEM rises to a high level. Next, internal read data signal ZDD rises to a high level. As a result, the potential of the node N2 rises to a high level, and then the output of the delay circuit 12 rises to a high level. In response to the rise of the output of the delay circuit 12, the drive transistor 2b having a large current driving capability is turned on via the AND circuit 8. At this time, the delay circuit 12 has a long delay time under an operating environment in which the current driving capability of the MOS transistor is large. Accordingly, under an operating environment where the drive current of the drive transistor 2b is large, the time for which the drive transistor 2b is turned on is delayed, and the drive transistor 2b is turned on after the potential of the output node 6 is sufficiently lowered by the drive transistor 2a. Therefore, even if the output node 6 is discharged to the ground potential level with a large current driving force at this time, ringing does not occur, and a stable output data signal Q can be obtained.

  On the other hand, in an operating environment where the current driving capability of the MOS transistor is reduced, the timing at which the drive transistor 2b is turned on is accelerated. In this case, the current driving capability of the drive transistor 2b is relatively small. Therefore, even when the drive transistor 2b is turned on at a relatively fast timing, the potential of the output node 6 is not discharged so rapidly and ringing occurs. A stable output data signal Q is obtained.

  At this time, under the operating environment in which the current driving capability of the MOS transistors 2a and 2b is reduced, the timing at which the drive transistor 2b is turned on is set quickly, so that the low level data signal output from the output node 6 is set. The potential of Q is determined relatively quickly. Therefore, even if the operating environment (operating conditions) deteriorates, the access time does not increase, and a high-speed and stable output data signal can be output.

  When an invalid data signal is not output, internal read data signal ZDD rises to a high level prior to output permission signal OEM. Even in this case, the potential of the node N2 only rises to a high level in response to the rise of the output permission signal OEM to the high level, and the change in the delay time of the delay circuit 12 is the same as that described above. It is. Therefore, even when only this valid data signal is output, the output data signal can be output stably and at high speed.

Next, a configuration for generating the first and second control voltages will be described.
FIG. 54 is a diagram showing a configuration of the control voltage generation unit. 54, the control voltage generator generates a VREF1 generation circuit 250 that generates a constant reference voltage VREF1 that does not depend on the operating temperature and the power supply voltage, and generates a reference voltage VREF2 that depends on the power supply voltage and the ambient temperature (operating temperature). VREF2 generation circuit 251 and differential amplification circuits 252 and 253 for differentially amplifying reference voltage VREF1 from VREF1 generation circuit 251 and second reference voltage VREF2 from VREF2 generation circuit 251 are included. A second control voltage VP is generated from the differential amplifier circuit 252, and a first control voltage VN is generated from the differential amplifier circuit 253. Differential amplifier circuit 252 receives first reference voltage VREF1 at its positive input, and receives second reference voltage VREF2 at its negative input. Differential amplifier circuit 253 receives second reference voltage VREF2 at its positive input and receives first reference voltage VREF1 at its negative input. The differential amplifier circuits 252 and 253 can generate first and second control voltages VP and VN having mutually opposite voltage and temperature dependent characteristics. Next, a specific configuration of each unit will be described.

  FIG. 55 is a diagram showing a characteristic of the first reference voltage VREF1 and a specific configuration of the VREF1 generation circuit. As shown in FIG. 55A, the first reference voltage VREF1 is a constant voltage that does not depend on the power supply voltage and the operating temperature. Referring to FIG. 55B, VREF1 generation circuit 250 has a constant current source 260 provided between power supply potential node and output node 264, and temperature compensation provided between output node 264 and ground potential node. An attached voltage diode 261 is included. Temperature compensated constant voltage diode 261 includes a PN diode 262 connected in the forward direction from output node 264, and a Zener diode 263 provided in the reverse direction between the PN diode and the ground potential node. Zener diode 263 has a positive temperature coefficient, and PN diode 262 has a negative temperature coefficient. The temperature dependence of the Zener diode 263 is compensated for by the mutually opposite temperature coefficients of the diodes 262 and 263, and a constant voltage is generated regardless of the operating temperature.

  The Zener diode 263 causes a Zener breakdown when a voltage higher than the Zener voltage is applied in the reverse direction, and generates a constant Zener voltage. In this case, a sum voltage of the Zener voltage due to the Zener diode and the forward drop voltage due to the PN diode 262 is generated at the output node 264. The forward drop voltage of the PN diode 262 and the Zener diode of the Zener diode 263 have negative and positive temperature coefficients, so that a constant voltage can be generated at the output node 264 regardless of the ambient temperature.

  In the configuration shown in FIG. 55B, as the constant current source 260, various circuit configurations that generate a constant current regardless of the power supply voltage and the operating temperature are known in the analog integrated circuit technical field. Simple circuit can be used. Further, instead of constant current source 260, a resistor having a sufficiently large resistance value (a resistance value large enough to ignore temperature dependence) is connected between output node 264 and the power supply potential node. The constant reference voltage VREF1 provided by the Zener diode 260 with temperature compensation can be generated.

  FIG. 56 is a diagram showing an example of the power supply voltage and ambient temperature dependence characteristics of the second reference voltage VREF2 and the configuration of the second reference voltage generation circuit. As shown in FIGS. 56A and 56B, the second reference voltage VREF2 has a negative dependency characteristic with respect to the power supply voltage and a positive dependency characteristic with respect to the operating temperature (ambient temperature). Have

  56C, a VREF2 generation circuit 251 includes a constant current source 271 provided between the power supply potential node and the output node 275, an n-channel MOS transistor 272 provided between the output node and the node 276, A resistor 273 provided between node 276 and the ground potential node is included. The temperature dependence of the resistance value R of the resistor 273 is sufficiently larger than the temperature dependence characteristic of the constant current source 271 and the temperature dependence characteristic of the on-resistance of the MOS transistor 272. The resistance value R of the resistor 273 is set slightly larger than the on-resistance of the MOS transistor 272. The resistor 273 is formed using, for example, polysilicon or a diffused resistor ion-implanted at a relatively high concentration, and has a positive temperature coefficient. Next, the operation will be described.

  A constant current source 271 supplies a constant power supply voltage Vcc and a current independent of the ambient temperature. Due to the constant current from the constant current source 271, a reference voltage VREF 2 determined by the sum of the on-resistance R (272) provided by the MOS transistor 272 and the resistance R (273) of the resistor 273 is generated at the output node 275. The When the power supply voltage Vcc rises to the upper limit value Vcmx, the conductance of the MOS transistor 272 is increased, that is, the resistance value R (272) is decreased, and the reference voltage VREF2 appearing at the output node 275 is decreased. That is, the second reference voltage VREF2 has a negative power supply voltage dependency characteristic.

  When the ambient temperature T rises, the resistance value R (273) of the resistor 273 increases and the second reference voltage VREF2 from the output node 275 rises. At this time, the on-resistance R (273) of the MOS transistor 272 also changes depending on the ambient temperature T, but the change is negligible compared to the temperature-dependent characteristics of the resistor 273. Therefore, the second reference voltage VREF2 has a positive dependence characteristic with respect to the ambient temperature T.

  For the constant current source 271 shown in FIG. 56C, a constant current source circuit which is not dependent on the power supply voltage and the ambient temperature known in the analog integrated circuit field or the like can be used.

  Instead of the constant current source 271, a configuration in which a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient are provided in parallel between the power supply potential node and the output node 275 may be used. As a resistor having such positive and negative temperature characteristics, a resistor called a thermistor can be used.

  FIG. 57 is a diagram showing a generation form of first control voltage VN and second control voltage VP. As shown in FIG. 54, the differential amplifier circuit 252 receives the first reference voltage VREF1 at its positive input and the second reference voltage VREF2 at its negative input. The first reference voltage VREF1 is constant. When the difference between the first reference voltage VREF1 and the second reference voltage VREF2 increases, the second reference voltage VP is amplified by the differential amplifier circuit 252 and the potential thereof increases (see FIG. 57A). ). That is, when the power supply voltage Vcc increases, the second reference voltage VREF2 decreases. Therefore, the difference (VREF1−VREF2) increases and the second control voltage VP increases. On the other hand, when the operating temperature T increases, the second reference voltage VREF2 increases. In this case, the difference (VREF1-VREF2) becomes smaller as the temperature rises. Therefore, in this case, the second control voltage VP decreases. Therefore, second control voltage VP having the power supply voltage and ambient temperature dependent characteristics shown in FIG. 46 can be generated.

  On the other hand, the differential amplifier circuit 253 shown in FIG. 54 receives the second reference voltage VREF2 at its positive input and the first reference voltage VREF1 at its negative input. Therefore, it is possible to generate the first control voltage VN having a characteristic opposite to that of the second control voltage VP.

  The differential amplifier circuits 252 and 253 are known in the analog integrated circuit field as a configuration in which the amplification characteristics are constant without depending on the power supply voltage and the ambient temperature, and such a configuration can be used. Therefore, since the operational characteristics of differential amplifier circuits 252 and 253 do not depend on the power supply voltage and the ambient temperature, first and second control voltages VN and NP are set to the power supply voltage and the ambient temperature as shown above. It becomes possible to adjust accordingly.

  Note that the voltage levels of the first control voltage VN and the second control voltage VP are not particularly described. However, as shown in FIGS. 47 and 48, the voltage levels in the voltage region for operating the MOS transistor in the region between the three electrodes are shown. Is set to an appropriate value.

  Further, in the structure shown in FIG. 55B, there may be a case where the Zener voltage of Zener diode 263 is higher than the normal operating power supply voltage (for example, 5 volts). In such a case, if the device using this circuit is a semiconductor memory device, a booster circuit is provided for boosting the word line, for example, and the operating power supply voltage Vcc is boosted by such a booster circuit. Thus, the constant reference voltage VREF1 can be sufficiently generated from the Zener diode with temperature compensation.

  When the Zener diode 263 has a low Zener voltage and a negative temperature characteristic, a resistor having a positive temperature coefficient (for example, a diffused resistor having a sufficient impurity concentration) may be used instead of the PN diode 262. .

  FIG. 58 is a diagram showing operating power supply voltage and ambient temperature dependence characteristics of an inverter circuit in a modification of the fifth embodiment. As shown in FIG. 58, in this modification, the operating power supply voltage Vcc (DELAY) of the inverter circuit is generated from the external power supply voltage and becomes lower when the external power supply voltage becomes higher, and the value also becomes higher when the ambient temperature becomes higher. Get higher. The voltage and temperature dependence characteristics shown in FIG. 58 are the same as the voltage and temperature dependence characteristics of first control voltage VN shown in FIG. The difference is that the operating power supply voltage Vcc (DELAY) is generated from the external power supply voltage. A configuration for generating power supply voltage Vcc (DELAY) shown in FIG. 58 is shown in FIG.

  As shown in FIG. 59 (A), the circuit for generating power supply voltage Vcc (DELAY) receives the first reference voltage VREF1 at the negative input and the third reference voltage VREF3 at the positive input. The circuit 290 is configured. Power supply voltage Vcc (DELAY) generated from differential amplifier circuit 290 is applied to the power supply voltage node of inverter circuit 291.

  The third reference voltage VREF3 is created with a circuit configuration similar to the circuit configuration shown in FIG. The difference is that power supply voltage Vcc is external power supply voltage ext. To replace Vcc. In this case, power supply voltage Vcc (DELAY) has the same voltage and ambient temperature dependence characteristics as first control voltage VN shown in FIG. This operating power supply voltage Vcc (DELAY) is equal to external power supply voltage ext. When Vcc approaches the upper limit value, it is lowered, and when ambient temperature rises, it rises as well. Therefore, when the upper limit value or the ambient temperature of the external power supply voltage is close to the lower limit value, this inverter circuit 291 has a lower operating speed (because the operating power supply voltage is lowered, the driving power of the MOS transistor is reduced; the inverter Note that the circuit 291 is used in cascade rather than in one stage).

  Therefore, as shown in FIG. 59 (B), even when such a configuration is used, if external power supply voltage Vcc is high or ambient temperature T is low, the delay time is lengthened. Similar effects can be obtained.

  In the fifth embodiment, the configuration of the output control circuit when the output signal Q is output as a low level is described. However, the present invention can be similarly applied to an output control circuit in the case where the output data signal Q is pulled up to a high level, and is applied to delay circuits of various modifications of the first to fourth embodiments. Is possible.

  Further, in the fifth embodiment, the delay time of the delay circuit may be appropriately changed according to which of the low level output data signal and the high level output data signal determines the access time.

[Embodiment 6]
FIG. 60 schematically shows a structure of an output circuit according to the sixth embodiment of the invention. In FIG. 60, a voltage regulator 301 including dedicated power supply circuits 304a, 304b, 306a, and 306b is provided for output circuit 926 that generates output signal Q in accordance with output permission signal OEM and internal data signal ZDD. The power supply voltage application circuit 304a charges the power supply node 300 at a first speed in response to the output permission signal, and the power supply voltage application circuit 304b is faster than the first speed in response to the output permission signal OEM. The power supply node 300 is charged at the second speed. The ground voltage application circuit 306a discharges the ground node 302 at a third speed (which may be equal to the first speed) in response to the output permission signal OEM, and the ground voltage application circuit 306b receives the output permission signal OEM. In response, power supply node 302 is discharged to the ground voltage level at a fourth rate that is faster than the third rate. Although the configuration will be described in detail later, the power supply voltage application circuit 304b is activated at a later timing than the power supply voltage application circuit 304a, and the ground voltage application circuit 306b is activated at a later timing than the ground voltage application circuit 306a. State. Power supply node 300 and ground node 302 constitute a reference power supply node, and power supply voltage application circuit 304a, power supply voltage application circuit 304b, ground voltage application circuit 306a, and ground voltage application circuit 306b constitute a reference voltage source.

  Output circuit 926 operates using the voltages on power supply node 300 and ground node 302 as both operation power supply voltages when activated (when output permission signal OEM is activated), and outputs output signal Q.

  61 shows a structure of the output circuit shown in FIG. In FIG. 61, output circuit 926 includes inverter 5 for inverting internal data signal ZDD, 2-input AND circuit 3 receiving output permission signal OEM and the output signal of inverter circuit 5, internal data signal ZDD and output permission signal OEM. Receiving 2-input AND circuit 4, turned on in response to the output signal of AND circuit 3, n-channel MOS transistor 1 transmitting voltage VccQ on power supply node 300 to output node 6, and the output signal of AND circuit 4 It includes an n-channel MOS transistor 2 that conducts in response and transmits voltage VssQ on ground node 302 to output node 6. These n-channel MOS transistors 1 and 2 each constitute a drive transistor. The configuration of the output circuit shown in FIG. 61 is the same as that of the conventional configuration except that the voltages applied to power supply node 300 and ground node 302 are adjusted.

  FIG. 62 shows a configuration of the voltage regulator 301 shown in FIG. 60. The voltage regulator 301 includes inverters 310 and 311 that invert the output permission signal OEM, and an even number stage that delays the output permission signal OEM by a predetermined time T5 ( 62. The delay circuit 312 composed of four stages of inverters in FIG. 62, the two-input NAND circuit 313 that receives the output signal of the delay circuit 312 and the output permission signal OEM, the inverter 314 that inverts the output signal of the NAND circuit 313, An n channel MOS transistor 315 that short-circuits power supply node 300 and ground node 302 in response to the output signal of inverter circuit 310, and an n channel MOS transistor that transmits reference voltage VREF to power supply node 300 in response to the output signal of inverter circuit 310 In response to the output signal of the transistor 316 and the inverter circuit 310 And an n channel MOS transistor 317 for transmitting the reference voltage VREF to ground node 302. Reference voltage VREF is an intermediate voltage level between power supply voltage Vcc and ground voltage GND. When output node 6 (see FIG. 60) is precharged to an intermediate voltage level, reference voltage VREF may be set to an intermediate voltage level at which output node 6 is precharged.

  Voltage regulator 301 further includes an n-channel MOS transistor 318 that supplies current from power supply voltage Vcc supply node to power supply node 300 with a first current driving force in response to an output signal of inverter 311, and inverter circuit 314. In response to the output signal, the n-channel MOS transistor 320 supplies current from the power supply voltage Vcc supply node to the power supply node 300 with a current driving power larger than the first current driving power, and responds to the output signal of the inverter circuit 311. In response to the output signal of inverter circuit 314, n-channel MOS transistor 319 discharges current from ground node 302 to the ground voltage supply node with the third current driving force, and ground voltage GND supply node. The current is discharged with a fourth current driving force larger than the third current driving force. Including channel MOS transistor 321. The first current driving force and the third current driving force may be equal, and the second current driving force and the fourth current driving force may be equal. The magnitude of the current driving capability of the MOS transistors 318 to 321 can be realized by appropriately adjusting the W / L (channel width / channel length) ratio of the transistors. The larger the coefficient β (a constant proportional to W / L), the greater the current driving force.

  62, the power supply voltage application circuit 304a includes a MOS transistor 318, the power supply voltage application circuit 304b includes a MOS transistor 320, the ground voltage application circuit 306a includes a MOS transistor 319, and the ground voltage application circuit 306b MOS transistor 321 is included. Delay circuit 312, NAND circuit 313, and inverter 314 constitute a rising delay circuit.

  Now, the operation of the circuit shown in FIGS. 61 and 62 will be described with reference to FIG.

  When output permission signal OEM falls from “H” to “L” level, output circuit 926 is deactivated and the cycle of reading output data Q is completed. FIG. 63 shows, as an example, a configuration in which output signal Q is precharged to an intermediate voltage level when output circuit 926 is inactivated. A configuration in which the output circuit 926 is maintained in the output high impedance state when the output circuit 926 is in an inactive state may be used.

  When the output permission signal OEM becomes “L”, the output signal of the inverter circuit 310 becomes “H”, the MOS transistors 315 to 317 are turned on, and the power supply node 300 and the ground node 302 are set to the reference voltage VREF level of the intermediate voltage level. Precharged. Further, the output signal of the inverter circuit 311 falls to “L”, and the MOS transistors 318 and 319 are turned off. Similarly, the output signal of the NAND circuit 313 also becomes “H”, the output signal of the inverter circuit 314 becomes “L” accordingly, and the MOS transistors 320 and 321 are turned off. By this series of operations, the nodes 300 and 302 are precharged to the reference voltage VREF level.

  When the next data reading is performed, output permission signal OEM first rises to "H" level. The output signal of the inverter circuit 310 falls to “L”, and the MOS transistors 315 to 317 are turned off. Next, the output signal of the inverter circuit 311 becomes “H”, and the MOS transistors 318 and 319 having a small current driving capability are turned on. Thus, the voltage level of power supply node 300 gradually increases from the reference voltage VREF level by MOS transistor 318 having a small current driving capability. Similarly, the ground node 302 is gently discharged to the ground voltage level by the MOS transistor 319 having a small current driving capability, and the voltage level gradually falls from the intermediate level reference voltage VREF. According to the logic level of internal data signal ZDD, one of MOS transistors 1 and 2 shown in FIG. 61 is turned on. MOS transistor 1 or 2 turned on transmits the voltage on its corresponding reference power supply node (power supply node or ground node) to output node 6 (current between the corresponding reference power supply node and output node 6). Flow).

  Therefore, first, MOS transistors 318 and 319 having a small current driving capability are turned on to gradually change the currents of nodes 300 and 302, whereby the voltage on node 300 or 302 is transmitted to output node 6 and output node 6 is output. The voltage of 6 changes slowly from this intermediate voltage level. When the voltage level of the output node 6 reaches a voltage level at which ringing does not occur, the voltage level of the nodes 300 and 302 is suddenly changed at that time, and the ringing even if the voltage level of the output signal Q is suddenly changed accordingly. Will not occur. That is, after the output permission signal OEM rises to “H” and the voltage levels of the nodes 300 and 302 change sufficiently, the output signal of the delay circuit 312 rises to “H”, and in response, the output signal of the NAND circuit 313 changes to “L”. Then, the output signal of the inverter circuit 314 becomes “H”, and the MOS transistors 320 and 321 having a large current driving capability are turned on. As a result, the voltage levels of nodes 300 and 302 change at high speed, and reach power supply Vcc and ground voltage GND levels, respectively. Thereby, the voltage level of output node 6 changes to power supply voltage Vcc or ground voltage GND level via drive transistor 1 or 2, and a stable output signal can be generated at high speed without causing ringing.

[Modification 1]
FIG. 64 is a diagram showing a configuration of a main part of a first modification of the sixth embodiment of the present invention. In the configuration shown in FIG. 64, the boosted voltage from boosting circuit 325 is applied to MOS transistors 318 and 320 shown in FIG. Boost circuit 325 boosts power supply voltage Vcc or external power supply voltage extVcc, and generates high voltage Vp that is equal to or higher than the external power supply voltage. In the configuration shown in FIG. 64, power supply voltage VccQ applied to power supply node 302 can be set to a voltage level sufficiently higher than internal power supply voltage Vcc. In this case, even when the internal power supply voltage Vcc is lowered due to low power consumption or the like, an “H” signal having a sufficient voltage level can be output with a margin. In such a low power supply voltage, even when the difference between VOH (the high level voltage of the output signal) and VOL (the low level voltage of the output signal) becomes small, the booster circuit 325 as shown in FIG. 64 is used. As a result, it is possible to compensate for the loss in the output drive transistor 1 and generate a high level output signal having a sufficiently high voltage level. Also in this case, since the power supply node 302 is charged in two stages, an output signal having a sufficient voltage level can be stably output at high speed without any ringing.

  FIG. 65 is a diagram showing a configuration of an output circuit when the booster circuit shown in FIG. 64 is used. In FIG. 65, an output circuit 926 is provided between the AND circuit 3 and the output drive transistor 1 and operates using the high voltage Vp from the booster circuit 325 as one operating power supply voltage, and the output signal of the AND circuit 3 is at “H” level. Includes a level conversion circuit 327 for converting the voltage to a high voltage Vp level. AND circuits 3 and 4 operate using internal power supply voltage Vcc as one operating power supply voltage. The level conversion circuit 327 can be configured such that a p-channel MOS transistor receives a high voltage Vp at its source and is cross-coupled. An n channel MOS transistor is connected between the drain of the p channel MOS transistor and the ground voltage node. By using level conversion circuit 327, power supply voltage VccQ at high voltage Vp level applied to power supply node 302 can be transmitted to output node 6.

  Voltage regulator 301 also receives high voltage Vp. This is because, in the configuration shown in FIG. 62, it is necessary to boost the output signals of inverters 311 and 314 to high voltage Vp level, and this high voltage Vp is applied to inverters 311 and 314. These inverters 311 and 314 output a high voltage Vp level signal. In this case, a level conversion circuit may be provided at the output part of the inverters 311 and 314, or the inverters 311 and 314 themselves may be configured to have a level conversion function.

  In this case, the voltage applied to power supply node 300 may be different from the voltage level applied to level conversion circuit 327. That is, two types of high voltage Vp output from the booster circuit 325 are prepared, and the level conversion circuit 327 sets the high level of the output signal of the NAND circuit 3 to the higher one of the two types of high voltages. The level is converted, and the high level voltages of the inverters 311 and 314 (see FIG. 52) are also level-converted to the higher high voltage level. In this case, the lower high voltage level can be transmitted to power supply node 300 without loss of the threshold voltage of the MOS transistor.

  In the configuration shown in FIG. 65, no level conversion circuit is provided in the output section of the AND circuit 4. When discharging output node 6, even if the gate potential of drive transistor 2 is at internal power supply voltage Vcc level, drive transistor is turned on, and the voltage to output node 6 is discharged to the voltage level on ground node 302. At this time, if the gate potential of drive transistor 2 is at internal power supply voltage Vcc level, the conductance is reduced and the discharge speed of output node 6 is made slower than when high voltage Vp is applied. Therefore, a rapid current change at the start of discharge of the output node 6 can be suppressed, which is more effective for suppressing ringing. Even if the gate voltage level of drive transistor 2 is sufficiently higher than the voltage level of ground node 302 and voltage VssQ on ground node 302 is discharged at high speed to ground voltage GND level, the voltage level of output node 6 according to the high speed discharge. Can be discharged to the ground voltage GND level at high speed.

  Even in this case, by providing a level conversion circuit between the gate of the drive transistor 2 and the AND circuit 4, the gate potential of the drive transistor 2 is made sufficiently high, and the discharge speed adjustment of the output node 6 is performed only by the voltage regulator 301. The configuration performed in may be used. In the above configuration, the voltages on power supply node 300 and ground node 302 (collectively referred to as the reference power supply node) are changed in two stages. However, a configuration in which the voltage on the reference power supply node is changed over three or more stages may be used.

  In the output circuit, a configuration using a plurality of drive transistors connected in parallel whose delay time is variable depending on whether or not an invalid signal is output may be used. The configuration of the output circuit 926 can apply all of the first to fifth embodiments.

  As described above, according to the sixth embodiment of the present invention, the voltage on the reference power supply node of the output stage transistor that drives the output node according to the internal signal is configured to change its changing speed over a plurality of stages. The voltage change on the output node 6 can be gradually and gradually increased at the beginning, and a stable output signal can be output at high speed without causing ringing.

[Embodiment 7]
FIG. 66 shows a structure of a main portion of the output circuit according to the seventh embodiment of the present invention. FIG. 66 shows a configuration of a voltage adjusting unit that supplies both operating power supply voltages of the output circuit. The configuration of the output circuit is the same as that shown in FIG.

  66, the voltage adjustment unit is different from the configuration of the voltage regulator 301 shown in FIG. 60 in the following points. That is, in the configuration shown in FIG. 66, n channel MOS transistor 328 responding to the output signal of inverter circuit 311 transmits voltage Vccp between reference voltage VREF and power supply voltage Vcc to power supply node 300 to power supply node 300. To do. N channel MOS transistor 330 provided in parallel with MOS transistor 328 transmits power supply voltage Vcc to power supply node 300 in response to the output signal of inverter circuit 314. In addition, n channel MOS transistor 329 coupled to ground node 302 transmits voltage Vbsg closer to intermediate voltage VREF to ground node 302 than ground voltage GND in response to the output signal of inverter circuit 311. N channel MOS transistor 331 transmits ground voltage GND to ground node 302 in response to the output signal of inverter circuit 314. Other configurations are the same as those shown in FIG.

  The channel width and channel length ratio W / L of MOS transistors 328 and 330 may be the same, and as shown in FIG. 62, the ratio (or coefficient β) of the channel width and channel length of MOS transistor 328 is MOS. It may be made smaller than that of the transistor 330. Further, the W / L of the MOS transistor 329 may be equal to that of the MOS transistor 331 or may be made smaller than that. Next, the operation will be briefly described.

  The operation of the output circuit is the same as that shown in FIG. In standby, the output signal of inverter circuit 310 is “H”, MOS transistors 315, 316 and 317 are in an on state, and nodes 300 and 302 are precharged to the voltage level of reference voltage VREF. At this time, the output signals of inverter circuits 311 and 314 are both “L” (output permission signal OEM is at “L” level), and MOS transistors 328, 330, 321 and 331 are all in the off state.

  When the data signal is read, output permission signal OEM rises from "L" to "H". Thereby, first, all the MOS transistors 315 to 317 are turned off. First, the output signal of inverter circuit 311 rises to “H” level, and MOS transistors 328 and 329 are turned on. Power supply node 300 is charged by MOS transistor 328 to a Vccp level, which is a voltage level at which ringing does not occur relatively slowly. On the other hand, MOS transistor 329 gently discharges ground node 302 to the voltage Vbsg level where no ringing occurs. Thereafter, MOS transistors 330 and 331 are turned on by the output signal of inverter circuit 314, and power supply node 300 is charged to power supply voltage Vcc level at a high speed, while ground node 302 is discharged to the ground voltage GND level at a high speed. The When a high level output signal is output from the output circuit, the voltage on power supply node 300 is transmitted to output node 6 via drive transistor 1 (see FIG. 61). On the other hand, when the output circuit outputs a low level signal, the voltage on the ground node 302 is transmitted to the output node 6 via the drive transistor 2. Therefore, the voltage change at output node 6 is substantially the same as the voltage change at power supply node 300 or ground node 302. As a result, the output signal Q on the output node 6 gradually changes to a voltage level where no ringing occurs, and is then driven at a high speed to the power supply voltage or the ground voltage level. With this configuration, it is possible to output a stable output signal at high speed without causing ringing.

  MOS transistor 329 may have the same channel width to channel length ratio W / L (or coefficient β) as MOS transistor 331. Since the source voltage Vbsg of the MOS transistor 329 is higher than the source voltage GND of the MOS transistor 331, the gate voltage of the MOS transistor 329 is effectively lower than the gate voltage of the MOS transistor 331. Accordingly, the conductance of the MOS transistor 329 is This is because the conductance of the MOS transistor 331 becomes smaller, and as a result, the current driving capability of the MOS transistor 329 is made smaller than the current driving capability of the MOS transistor 331.

  A p-channel MOS transistor may be used as MOS transistors 318, 320, 328 and 330 for charging power supply node 300 shown in FIGS. Power supply voltage Vcc can be transmitted to power supply node 300 without any loss of threshold voltage. In the configuration shown in FIG. 66, when p-channel MOS transistors are used instead of n-channel MOS transistors 328 and 330, the channel width channel length ratio (or coefficient β) of these p-channel MOS transistors is the same. May be. This is because the current drivability of a p-channel MOS transistor receiving voltage Vccp at its source is made smaller than that of a p-channel MOS transistor receiving voltage Vcc at its source.

  FIG. 67 shows an example of a configuration for generating voltages Vccp and Vbsg shown in FIG. FIG. 67A shows a configuration for generating voltage Vccp, and FIG. 67B shows a configuration for generating voltage Vbsg.

  67A, the voltage generation circuit includes diode-connected p-channel MOS transistors PM1 to PMn connected in series between power supply voltage Vcc supply node and node 332, node 332 and ground voltage GND supply node. And a resistor Rp connected between the two. The resistor Rp has a resistance value sufficiently larger than the channel resistance of the MOS transistors PM1 to PMn. Each of MOS transistors PM1 to PMn operates in a diode mode, and the voltage is lowered by an absolute value Vthp of the threshold voltage. Therefore, in the structure shown in FIG. 67A, a voltage of Vcc−n · Vthp is output as voltage Vccp. The number of MOS transistors PM1 to PMn is adjusted to an appropriate value according to the level of voltage Vccp.

  In FIG. 67B, the voltage generators are connected in series between a resistor Rn connected between the power supply voltage Vcc supply node and the node 333, and between the node 333 and the ground voltage GND supply node. It includes diode-connected n-channel MOS transistors NM1 to NMn. The resistor Rn has a resistance value sufficiently larger than the channel resistance of each of the MOS transistors NM1 to NMn. In this case, MOS transistors NM1 to NMn operate in a diode mode, and the voltage is reduced by the threshold voltage Vthn. Therefore, in the configuration shown in FIG. 67B, voltage Vbsg appearing at node 33 is n · Vthn (ground voltage GND is set to 0 V).

  The voltage Vccp has a larger value than the reference voltage VREF, and the voltage Vbsg has a smaller value than the reference voltage VREF.

  Various reference voltage generating circuits can be used instead of the voltage generating circuit shown in FIGS. 67 (A) and 67 (B).

  As described above, according to the configuration of the seventh embodiment of the present invention, the power supply node for supplying the voltage for determining the voltage level of the output signal of the output circuit and the ground voltage are driven in two stages, and the first stage Is configured to supply a current from a power supply node and a ground node to a power supply node and a ground node, respectively, because the voltage Vccp is lower than the power supply voltage Vcc and the voltage Vbsg is higher than the ground voltage GND. By doing so, the output node of the output circuit can be reliably driven to a voltage level at which ringing does not occur, and thereafter, it can be driven at high speed to the power supply voltage Vcc level or the ground voltage GND level. A stable output signal can be output at high speed.

  Further, according to the configuration of the seventh embodiment, the voltage level at which no ringing occurs can be set by the voltages Vccp and Vbsg, so that the output level can be increased at a high speed before the voltage level of the output node sufficiently changes. It is possible to prevent the node from being charged / discharged and to reliably suppress the occurrence of ringing.

[Embodiment 8]
FIG. 68 shows a structure of a main portion of the output circuit according to the eighth embodiment of the present invention. 68, output circuit 926 includes inverter circuit 5 that inverts internal data signal ZDD, AND circuit 3 that receives output permission signal OEM and the output signal of inverter circuit 5, and output permission signal, as in the previous embodiment. AND circuit 4 receiving OEM and internal data signal ZDD, drive transistor 1 driving output node 6 to voltage VccQ level on power supply node 300 in response to the output signal of AND circuit 3, and AND circuit 4 An output drive transistor is included that discharges output node 6 to voltage VssQ level on ground node 302 in response to the output signal.

  The output circuit further includes a voltage regulator 340 that adjusts the voltage level on ground node 302 in response to a signal applied from AND circuit 4 to node N2. In FIG. 68, only voltage regulator 340 that adjusts voltage VssQ on ground node 302 is shown to simplify the drawing, but voltage VccQ on power supply node 300 is adjusted according to the voltage level on node N1. A voltage regulator is also provided. A circuit for adjusting voltage VccQ on power supply node 300 according to the signal on node N1 has the same configuration as voltage regulator 340.

  Voltage regulator 340 determines whether there is an invalid output in response to output instruction signal DOT and an external signal on node N2, adjusts the delay time according to the determination result, and activates after a predetermined delay time has elapsed. Drive circuit 350 for outputting the enable signal, 2-input NAND circuit 351 for receiving the output signal of drive circuit 350 and the internal signal on node N2, inverter circuit 352 for inverting the output signal of NAND circuit 351, and node N2 An inverter circuit 353 for inverting the signal, an inverter circuit 354 for inverting the output signal of the inverter circuit 353, and conducting in response to the output signal of the inverter circuit 354, and discharging the ground node 302 to the ground voltage GND level. Responds to output signal of n-channel MOS transistor 360 and inverter circuit 352 having a small current driving capability Conductive Te, and an n-channel MOS transistor 365 having a relatively large current driving force for discharging the ground node 302 to the ground voltage GND level. Inverter circuits 353 and 354 constitute a buffer circuit.

  Voltage regulator 340 further includes an inverter circuit 370 that inverts output permission signal OEM, and an n-channel MOS transistor 375 that transmits reference voltage VREF to ground node 302 in response to the output signal of inverter circuit 370. MOS transistor 375 conducts when output circuit 926 is inactive when output permission signal OEM is at “L”, and precharges ground node 302 to reference voltage VREF.

  Drive circuit 350 includes an inverter circuit 381 that inverts output instruction signal DOT, a two-input NAND circuit 382 that receives an internal signal on node N2 and an output signal of inverter circuit 381, and an internal signal on node N2 and an output instruction signal DOT. And a flip-flop including cross-coupled NAND circuits NA13 and NA14 set in response to an output signal of NAND circuit 382 and reset in response to an internal signal on internal node N2. 384, an inverter circuit 385 that receives the output signal of the NAND circuit NA13 included in the flip-flop 384, a delay circuit 387 that delays the output signal of the inverter circuit 385 for a predetermined time T1, an output signal of the inverter circuit 385, and the AND circuit 383 2-input NAND receiving output signal It includes a road 386, a delay circuit 388 for a predetermined time T2 delays the output signal of the NAND circuit 386, a 2-input NAND circuit 389 receiving the output signal of the delay circuit 387 and 388.

  The flip-flop 384 has a function of determining whether or not a valid signal (“H” signal) is output on the internal node N2 when the output instruction signal DOT becomes “H” in the active state. . The delay time T1 of the delay circuit 387 is set longer than the delay time T2 of the delay circuit 388.

  The configuration of drive circuit 350 is substantially the same as that of the control circuit for adjusting the conduction timing of the drive transistor shown in FIG. Next, the operation will be briefly described.

  First, the operation when there is no invalid output will be described with reference to the operation waveform diagram shown in FIG. When the internal signal on internal node N2 rises to “L” or “H”, the output signals of inverter circuits 353 and 354 become “H” in response, MOS transistor 360 is turned on, and its small current driving capability Thus, voltage VssQ on ground node 302 is discharged from intermediate voltage VREF to ground voltage GND. At this time, the output permission signal OEM rises to “H”, and accordingly, the MOS transistor 345 is in the off state, and the ground node 302 is separated from the intermediate voltage VREF supply source. On the other hand, drive transistor 2 for output discharge is turned on in response to the internal signal on internal node N 2, and discharges output node 6 to voltage VssQ level on ground node 302. At this time, since the output instruction signal DOT has not risen to “H”, this signal is an invalid signal. Therefore, the output signal until the node N 2 becomes “H” is an invalid signal, and the output node 6 is charged from the power supply node 300 via the drive transistor 1. The flip-flop 384 is reset, and its output signal is “L”. When the output instruction signal DOT rises from “L” to “H”, the output signal of the NAND circuit 382 becomes “L”, the flip-flop 384 is set, and the output signal of the inverter circuit 385 rises to “L” accordingly. Go down. On the other hand, the output signal of the AND circuit 383 simultaneously rises to “H”. At this time, the output signal of the inverter circuit 385 is “L”, and the output signal of the NAND circuit 386 maintains “H”. Therefore, the output signal of the delay circuit 388 maintains “H”.

  When a predetermined time T1 elapses after the output signal of the inverter circuit 385 falls to “L”, the output signal of the delay circuit 387 falls to “L” and the output signal of the NAND circuit 389 rises to “H”. At this time, the internal signal on the node N2 has already risen to “H”, the input signals of the NAND circuit 351 both become “H”, and the output signal of the NAND circuit 351 changes from “H” to “L”. In response to the fall, the output signal of the inverter circuit 352 rises from “L” to “H”. As a result, MOS transistor 365 having a large current driving capability that has been in an off state until then is turned on, and ground node 302 is rapidly lowered to the level of ground voltage GND. As a result, the output signal Q on the output node 6 also drops to the ground voltage GND level via the drive transistor 2 at a high speed. The MOS transistor 355 is turned on after the elapse of the delay time T1 after the output instruction signal DOT rises to “H”. By increasing the delay time T1, the output signal Q that has risen due to the invalid output can be gradually lowered to a voltage level that does not cause ringing, and then lowered to the ground voltage GND level at a high speed. A stable output signal can be output.

  Next, the operation when no signal is output as an invalid output will be described with reference to FIG. In this state, after the output instruction signal DOT becomes “H”, the internal signal on the internal node N2 rises to “H”. When the internal signal on node N2 and output instruction signal DOT both become “H”, the output signal of NAND circuit 383 becomes “H”. On the other hand, while the internal signal on internal node N2 is “L”, the output signal of NAND circuit 382 is “H” regardless of the state of output instruction signal DOT, and flip-flop 384 maintains the reset state. The output signal is maintained at “L”. Accordingly, the output signal of inverter circuit 385 maintains the “H” state. Therefore, when the output signal of the NAND circuit 383 rises to “H”, the output signal of the NAND circuit 386 falls to “L”, and after the elapse of the predetermined time T2, the output signal of the delay circuit 388 becomes “L”. Fall. As a result, the output signal of the NAND circuit 389 rises from “L” to “H”.

  When the internal signal on internal node N2 rises to "H", MOS circuits 360 are turned on by inverter circuits 353 and 354. On the other hand, MOS transistor 375 is in an off state at this time, and voltage VssQ on ground node 302 is discharged at the level of ground voltage GND through MOS transistor 360, and the potential thereof gradually decreases. Thereby, drive transistor 2 discharges output signal Q on output node 6 in accordance with voltage VssQ on ground node 302. For this reason, the potential change of the output signal Q on the output node 6 is gentle, and no ringing occurs in the output node 6. After the delay time T2 has elapsed since the internal signal on the internal node N2 rises to “H”, the output signal of the NAND circuit 351 becomes “L”, the output signal of the inverter circuit 352 becomes “H”, The MOS transistor 365 having a large current driving capability is turned on. As a result, voltage VssQ on ground node 302 that has been lowered to a voltage level at which ringing does not occur is discharged to ground voltage GND level by MOS transistor 365 having a high current driving capability at high speed. Drive transistor 2 discharges the voltage on output node 6 to the voltage level on ground node 302. Therefore, in this case, although the output signal Q on the output node 6 rapidly decreases, it has already decreased to a voltage level at which ringing does not occur, so that a stable output signal without ringing is output to the output node 6. .

  Thus, by adjusting the timing at which the transistor 365 that drives the ground node 302 is turned on according to the presence or absence of the invalid signal output, the voltage level on the output node 6 is reliably lowered to a voltage level that does not cause ringing. Later, the voltage on output node 6 can be discharged to the ground voltage level at high speed, and a stable output signal free from ringing can be generated regardless of the presence or absence of an invalid signal.

  In the configuration shown in FIG. 68, MOS transistor 360 may be connected to receive voltage Vbsg higher than ground voltage GND level as shown in FIG. Further, as shown in FIGS. 23, 25, 27, 29, and 31, for the output circuit 926, the timing at which the transistor having a large current driving capability is turned on varies depending on the presence or absence of invalid output. A configuration may be provided.

  The drive circuit 350 included in the voltage regulator shown in FIG. 68 may be configured to vary the timing at which the MOS transistor 365 is turned on in accordance with the presence or absence of an invalid signal output. FIG. 23, FIG. 25, FIG. 27, 29 and 31 can be applied to this control circuit.

  As described above, according to the configuration of the eighth embodiment of the present invention, a plurality of transistors having different current driving capabilities are provided for the reference power supply node of the output circuit, and the current driving capability is large according to the presence or absence of invalid output. Since the transistor is turned on at different timings, an output signal that does not cause ringing can be output at high speed regardless of the presence or absence of invalid output.

[Embodiment 9]
FIG. 71 is a diagram showing the configuration of the output circuit according to the ninth embodiment of the present invention. 71, an output circuit 926 includes a delay circuit 401 that delays a signal on internal node N2 for a predetermined time, a delay circuit 402 that further delays an output signal of delay circuit 401 for a predetermined time, and a signal and delay on internal node N2. NAND circuit 404 receiving the output signal of circuit 401, 2-input AND circuit 706 receiving the internal signal on internal node N2 and the output signal of delay circuit 402, and conducting in response to the internal signal on internal node N2, Drive transistor 2e formed of an n-channel MOS transistor discharging node 6 to ground voltage GND level, and n-channel MOS conducting in response to an output signal of AND circuit 404 and discharging output node 6 to ground voltage GND level Responds to the output signal of the drive transistor 2f composed of transistors and the AND circuit 406 Conductive Te, including the drive transistor 2g formed of an n-channel MOS transistor for discharging the output node 6 to the ground voltage GND level.

  Similarly to the previous embodiment, output circuit 926 also includes inverter circuit 5 that inverts internal data signal ZDD, AND circuit 3 that receives output permission signal OEM and the output signal of inverter circuit 5, and the output signal of AND circuit 3. Drive transistor 1 formed of an n-channel MOS transistor which is rendered conductive in response to output node 6 to charge power supply voltage Vcc level, and drive transistor 2e is turned on in response to output permission signal OEM and internal data signal ZDD. An AND circuit 4 is included. Drive transistors 2e, 2f and 2g have other threshold voltages Vth1, Vth2 and Vth3, and bias voltages VBB1, VBB2 and VBB3 are applied to the respective well regions (or substrate regions).

The threshold voltages Vth1, Vth2, and Vth3 are:
Vth1>Vth2>Vth3> 0
The substrate bias voltages VBB1, VBB2, and VBB3 are as follows:
VBB1 <VBB2 <VBB3 <0
Satisfy the relationship. When the threshold voltage of the n-channel MOS transistor increases, when the same gate voltage is applied, the gate potential is effectively lowered and the conductance is reduced. Therefore, when the same “H” level voltage is applied to drive transistors 2e, 2f, and 2g, the conductance increases in the order of drive transistors 2e, 2f, and 2g. Similarly, the substrate bias voltage generally increases as the absolute value of the substrate bias voltage increases. Therefore, similarly, due to the influence of the substrate bias voltage, the substrate bias effect is reduced and the conductance is increased in the order of drive transistors 2e, 2f, and 2g. However, it is assumed here that drive transistors 2e, 2f and 2g have the same size.

  In operation, first, when an internal signal on internal node N2 rises to "H", drive transistor 2e is turned on and output node 6 is discharged to the level of ground voltage GND. The threshold voltage Vth1 of the drive transistor 2e is the largest and the substrate bias voltage is also the smallest, and the substrate bias effect is increased. Therefore, output node 6 is discharged to the level of ground voltage GND with a relatively small current driving force. Next, when the output signal of the delay circuit 401 rises to “H”, the drive transistor 2 f is turned on. Drive transistor 2f has an intermediate threshold voltage Vth2 and substrate bias voltage VBB2, and discharges output node 6 to the level of ground voltage GND with a relatively large current driving capability. Next, the output signal of the delay circuit 402 rises to “H”, and accordingly, the output signal of the AND circuit 406 becomes “H”, and the drive transistor 2g is turned on. Drive transistor 2g has the shallowest substrate bias and the smallest threshold voltage Vth3. Therefore, output node 6 is discharged to the level of ground voltage GND with a large current driving capability. As a result, the voltage on output node 6 that has been lowered to the voltage level at which ringing does not occur by drive transistors 2e and 2f is discharged to ground voltage GND level at a high speed via drive transistor 2g.

  As described above, the substrate bias voltage VBB (VBB1 to VBB3) and the threshold voltage Vth (Vth1 to Vth3) are different in magnitude, and the current driving capability of the drive transistor is made different according to the comparison in the initial stage. The output node 6 can be discharged slowly to a voltage level at which ringing does not occur, and the output node 6 can be discharged to the ground voltage GND level at a high speed using a drive transistor having a large current driving capability when the voltage level is reduced to a level where no ringing occurs. A stable output signal that does not cause ringing can be output at high speed.

[Modification 1]
FIG. 72 shows a modification of the output circuit according to the ninth embodiment of the present invention. In FIG. 71, voltage VssQ from voltage regulator 301b is applied to ground node 302 constituting the sources of drive transistors 2e, 2f and 2g for discharging output node 6. Drive transistors 2e, 2f and 2g and delay circuits 401 and 402 are the same as those shown in FIG. 71, and corresponding portions bear the same reference numerals. The voltage regulator 301b changes the output voltage VssQ from the reference voltage VREF to the ground voltage GND level in response to the output permission signal OEM. The configuration of this voltage regulator is the same as that shown in FIGS. 62 and 66.

  In FIG. 72, the output circuit further includes drive transistors 1e, 1f and 1g formed of n-channel MOS transistors in parallel between power supply node 300 and output node 6. Drive transistor 1e conducts in response to a signal on internal node N1. Drive transistor 1f conducts in response to an output signal of delay circuit 403 that delays the signal on internal node N1 for a predetermined time. Drive transistor 1g conducts in response to the output signal of delay circuit 404 that further delays the output signal of delay circuit 403. These drive transistors 1e, 1f and 1g have different threshold voltages and different substrate bias voltages. In FIG. 72, as an example, drive transistors 1e, 1f, and 1g have the same magnitude as the threshold voltage and bias voltage of drive transistors 2e, 2f, and 2g for discharging output node 6, respectively. It is shown having a threshold voltage and a bias voltage. These may be set to different values. In output charging drive transistors 1e to 1g, the drive transistor that is turned on first may have a large threshold voltage and a deep substrate bias. Delay circuits 403 and 404 have the same delay time as delay circuits 401 and 402, respectively.

  Power supply node 300 is supplied with voltage VccQ from voltage regulator 301a. The voltage regulator 301a is activated in response to the output permission signal OEM, and regulates the output voltage VccQ from the level of the reference voltage VRF. Similar to the voltage regulator 301b, the voltage regulator 301a only needs to have the configuration shown in FIG. 62 or FIG.

  In general, the current (drain current) Ids flowing from the drain to the source of the MOS transistor is given by the following equation.

Saturation region: | Vds | ≧ | Vgs−Vth |;
Ids = (Vgs−Vth) 2
Unsaturated region: | Vds | <| Vgs−Vth |:
Ids = A {(Vgs−Vth) Vds− (Vgs / 2)}
Here, Vds indicates a drain-source voltage, and Vgs indicates a gate-source voltage. Vth represents a threshold voltage. In both the saturated region and the non-saturated region, when the gate-source voltage Vgs decreases, the drain current Ids is greatly affected by the threshold voltage Vth. That is, in other words, when power supply voltage Vcc is lowered and the amplitude of the output signal at output node 6 is reduced, the change rate of the signal on output node 6 is set to this threshold voltage by threshold voltage Vth. It is possible to adjust sufficiently. Similarly, the threshold voltage Vth is
Vth = A + B (C + | VBB |) 1/2
With the relationship. That is, the absolute value of threshold voltage Vth increases in accordance with the absolute value of substrate bias voltage VBB. Therefore, similarly, even when the power supply voltage is lowered, the influence of the substrate voltage bias VBB is superimposed on the threshold voltage, and the change in the voltage level of the output node 6 can be adjusted. In particular, when the voltages of power supply node 300 and ground node 302 are adjusted using voltage regulators 301a and 301b as shown in FIG. 72, the following advantages are obtained.

  In other words, in the initial stage where output permission signal OEM is activated, voltage VssQ applied to ground node 302 is at a voltage level higher than ground voltage GND. In this case, the source potentials of the discharge drive transistors 2e, 2f and 2g rise, and the gate voltage is effectively lowered accordingly. That is, the gate voltage Vgs is reduced. In this case, as apparent from the above formula, the influence of the threshold voltage Vth is increased, and accordingly, the influence of the substrate bias voltage is also increased. On the other hand, when the voltage level of output node 6 decreases to a voltage level at which ringing does not occur, the voltage level on ground node 302 is also set to the ground voltage GND level, and the gate-source voltage Vgs of drive transistors 2e-2g is sufficiently large. It becomes. In this case, the influence of threshold voltage Vth is made relatively small, and output node 6 can be discharged to the level of ground voltage GND at high speed. Therefore, by changing the voltage on ground node 302 in stages, the current driving capability of the drive transistor can be adjusted effectively using the influence of the substrate bias voltage and the ground threshold voltage.

  The same applies to drive transistors 1e, 1f, and 1g for charging output node 6. In this case, when the voltage on power supply node 300 is relatively low, only drive transistor 1e is turned on. At this time, in drive transistor 1e, in the drain (conduction region connected to power supply node 300), the impurity region and the substrate region are in a relatively weak reverse bias state, and the spread of the depletion layer is made relatively large. The Therefore, in this case, the drain electric field is small, the drain current is suppressed from flowing, and the drain current depends on the substrate bias. Therefore, the drain current can be effectively suppressed, and a current is slowly supplied from power supply node 300 to output node 6. When voltage VccQ on power supply node 300 becomes sufficiently large, in drive transistors 1e-1g, the drain region and the substrate region are sufficiently reverse-biased, the depletion layer becomes sufficiently narrow, and the drain current Becomes easier to flow. Therefore, in this case, the bias voltage dependency is not impaired, and a relatively large drain current can be supplied. In this state, drive transistor 1e is turned on. Therefore, also in drive transistors 1e-1g for charging the output node, the current driving capability can be adjusted by adjusting the threshold voltage and the bias voltage to appropriate values. In this manner, ringing is effectively generated by using a plurality of drive transistors that vary the substrate bias voltage and the threshold voltage in combination with circuits for adjusting voltages VssQ and VccQ on ground node 302 and power supply node 300. Can be obtained.

  71 and 72 can also more effectively suppress the ringing of the output signal by combining the timing at which drive transistors 1e and 2e are turned on in accordance with the presence / absence of an invalid output. Can do.

  As described above, according to the configuration of the ninth embodiment of the present invention, a plurality of transistors having different substrate bias voltages and threshold voltages are provided in parallel between the output node and the reference power supply node. Since the drive transistors are configured to be turned on at different timings, these drive transistors have different current driving capabilities. Therefore, an output circuit that outputs a stable output signal at high speed while effectively suppressing ringing is provided. Obtainable.

[Embodiment 10]
FIG. 73 shows a structure and operation of an output circuit according to the tenth embodiment of the present invention. In FIG. 73A, n is rendered conductive in response to the output signal A of the rising delay circuit 410 that delays the signal on the internal node N2 for a predetermined time between the output node 6 and the drive transistor 2 for discharging the output node. A channel MOS transistor 412 and a resistance element 414 are provided in parallel with the MOS transistor 412. The resistor 414 has a current limiting function. Other configurations are the same as those of the previous embodiment, inverter circuit 5 that inverts internal data signal ZDD, AND circuit 3 that receives output permission signal OEM and the output signal of inverter circuit 5, and the output of AND circuit 3 Drive transistor 1 conducting in response to signal NOH, transmitting power supply voltage Vcc to output node 6, AND circuit 4 receiving output permission signal OEM and internal data signal ZDD, and responding to output signal NOL of AND circuit 4 Drive transistor 2 is provided. Next, the operation of the output circuit shown in FIG. 73A will be described with reference to FIG.

  When the output permission signal OEM is “L”, the output signal NOL of the AND circuit 4 is “L”, and the drive transistor 2 is in the off state. In this state, the output signal A of the rising delay circuit 410 is “L”, and the MOS transistor 412 is in the off state.

  When output permission signal OEM and internal data signal ZDD both attain “H”, output signal NOL from AND circuit 4 rises to “H”, and drive transistor 2 is turned on. At this time, the output signal A of the rising delay circuit 410 is still at the “L” level, and the MOS transistor 412 is in the off state. Therefore, in this state, output node 6 is discharged to the level of ground voltage GND through resistance element 414 and drive transistor 2. In this case, the output node 6 is discharged relatively slowly by the current limiting function of the resistance element 414.

  After a predetermined time T6 elapses after the output signal NOL of the AND circuit 4 rises to “H”, the output signal A of the rise delay circuit 410 rises to “H”. As a result, the MOS transistor 412 is turned on and the resistance element 414 is short-circuited. The on resistance (channel resistance) of the MOS transistor 412 is set to a value sufficiently smaller than the resistance value of the resistance element 414. Therefore, output node 6 is discharged to the level of ground voltage GND at high speed via MOS transistor 412 and drive transistor 2. When MOS transistor 412 is turned on, the voltage level of output node 6 is lowered to a voltage level at which ringing does not occur. Even if the voltage level of output node 6 is discharged to the ground voltage GND level at high speed. No ringing occurs at the output node.

  Delay circuit 410, MOS transistor 412 and resistance element 414 shown in FIG. 73A may also be provided for drive transistor 1 for charging the output node.

[Modification 1]
FIG. 74 shows a structure and operation of a first modification of the output circuit according to the tenth embodiment of the invention. 74A, output circuit 926 includes inverter circuit 5 that inverts internal data signal ZDD, AND circuit 3 that receives the output signal of inverter circuit 5 and output permission signal OEM, and Drive transistor 1 that conducts in response to output signal NOH and charges output node 6 to power supply voltage Vcc level, AND circuit 4 that receives output permission signal OEM and internal data signal ZDD, and output signal NOL1 of AND circuit 4 Drive transistor 2h which conducts in response and discharges output node 6 to the level of ground voltage GND is included.

  The output circuit 926 further includes a rising delay circuit 420 that delays the rising of the output signal NOL1 of the AND circuit 4 for a predetermined time, a rising delay circuit 422 that further delays the rising of the output signal NOL2 of the rising delay circuit 420, and One end of the output node 6 is connected to the MOS transistor 424 which is turned on in response to the output signal A of the rising delay circuit 422, the resistance element 426 connected in parallel with the MOS transistor 424, and the output of the rising delay circuit 420. A drive transistor 2i that conducts in response to signal NOL2 and couples resistance element 426 to ground voltage GND is included. The channel width of drive transistor 2h is smaller than the channel width of drive transistor 2i, and the current driving capability of drive transistor 2h is smaller than the current driving capability of drive transistor 2i. Further, the channel resistance (ON resistance) of the MOS transistor 424 is made sufficiently smaller than the ON resistance value of the resistance element 426. Next, the operation of the output circuit shown in FIG. 74 (A) will be described with reference to FIG. 74 (B) which is an operation waveform diagram thereof.

  When at least one of the output permission signal OEM and the internal data signal ZDD is “L”, the output signal NOL1 of the AND circuit 4 is maintained in the “L” state. In this state, drive transistors 2h and 2i are both off, and output node 6 is not discharged.

  When output permission signal OEM and internal data signal ZDD both attain "H", output signal NOL1 of AND circuit 4 rises to "H". Thereby, drive transistor 2h is first turned on, and output node 6 is discharged to ground voltage GND level relatively slowly by drive transistor 2h having a small current driving capability. After the delay time T7 of the rising delay circuit 420 elapses after the signal NOL1 rises to "H", the output signal NOL2 of the rising delay circuit 420 becomes "H" and the drive transistor 2i is turned on. . Thus, output node 6 is discharged to the level of ground voltage GND through resistance element 426 and drive transistor 2i. Due to the current limiting function of resistance element 426, output node 6 is discharged to the ground voltage level more slowly.

  Further, after the delay time T8 of the rising delay circuit 422 has elapsed since the rise of the signal NOL2 to "H", the output signal A of the rising delay circuit 422 rises to "H" and the MOS transistor 424 is turned on. State. The channel resistance (ON resistance) of MOS transistor 424 is made sufficiently smaller than the resistance value of resistance element 426. Therefore, output node 6 is discharged to the level of ground voltage GND at high speed by drive transistor 2i due to its large current driving capability. The Thereby, when the voltage level is lowered to a level at which no ringing occurs, the voltage level of output node 6 is discharged to the ground voltage level at a high speed, so that an output signal can be generated at a high speed without causing ringing. At this time, since the voltage level decreasing speed of the output node 6 is increased sequentially over three stages, the discharge speed of the output node 6 is increased when the possibility of ringing is reduced. In addition, an output signal can be generated without causing ringing.

  The configuration shown in FIG. 74A can also be applied to a configuration in which output node 6 is charged to the level of power supply voltage Vcc.

  Further, in the output circuit configuration shown in FIGS. 73A and 74A, voltages VccQ and VssQ may be applied using a voltage regulator instead of voltage power supply Vcc and ground voltage GND. Further, for drive transistors 1 and 2h, a configuration may be used in which the timing of turning on varies depending on the presence or absence of invalid output.

  As described above, according to the tenth embodiment of the present invention, the output node is first driven to the voltage level of the reference power supply node using the resistance element, and then the resistance element is short-circuited to connect the output node to the reference power supply. Since the node voltage level is driven at a high speed, when there is a possibility of ringing, the output node is driven slowly by a current limiting function using a resistance element. Since it is driven, it is possible to obtain an output circuit that outputs an output signal stably and at high speed without causing ringing.

[Embodiment 11]
FIG. 75 shows a structure and operation of an output circuit according to the eleventh embodiment of the present invention. 75A, output circuit 926 includes inverter circuit 5 that inverts internal data signal ZDD, AND circuit 3 that receives the output signal of inverter circuit 5 and output permission signal OEM, and the output of AND circuit 3 as in the prior art. Drive transistor 1 that conducts in response to signal NOH and charges output node 6 to power supply voltage Vcc level, and AND circuit 4 that receives output permission signal OEM and internal data signal ZDD are included.

  Output circuit 926 further connects resistance elements 430, 432, and 434 having different resistance values coupled in parallel to output node 6 and grounds the other end of resistance element 430 in response to output signal NOL1 of AND circuit 4. Drive transistor 2j coupled to voltage GND level, rising delay circuit 440 delaying the rising of output signal NOL1 of AND circuit 4 for a predetermined time T9, and conducting in response to output signal NOL2 of rising delay circuit 440, resistance element 432 In response to drive transistor 2k that couples the other end to ground voltage GND level, rising delay circuit 442 that further delays the rising of output signal NOL2 of rising delay circuit 440 for a predetermined time T10, and output signal NOL3 of rising delay circuit 442 Do not couple the other end of resistance element 434 to the ground voltage GND level. Including the drive transistor 2l. Resistance elements 430, 432, and 434 have large resistance values in this order. Next, the operation of the circuit shown in FIG. 75A will be described with reference to FIG. 75B which is a signal waveform diagram thereof.

  When output permission signal OEM and internal data signal ZDD both become “H”, output signal NOL1 of AND circuit 4 becomes “H”. As a result, drive transistor 2j is turned on. In this state, output node 6 is discharged to the level of ground voltage GND through resistance element 430 having a large resistance value. Resistance element 430 has the largest current limiting function (has the largest resistance value), and the voltage drop at output node 6 is relatively gradual. Next, when a predetermined time T9 elapses, the signal NOL2 from the rising delay circuit 440 becomes “H”, the drive transistor 2k is turned on, and the output node 6 is discharged to the ground voltage level via the resistance element 432. Resistance element 432 has a resistance value smaller than that of resistance element 430. Therefore, the potential of output node 6 is discharged slightly more slowly.

  Next, after the time T10 has elapsed since the signal NOL2 rises, the output signal NOL3 of the rise delay circuit 442 becomes "H", and the drive transistor 21 is turned on. Resistive element 434 has the smallest resistance value, and therefore output node 6 is discharged to the level of ground voltage GND at high speed. When drive transistor 21 is turned on, the voltage level of output node 6 has already dropped to a voltage level at which ringing does not occur. Even if output node 6 is discharged through drive transistor 21 at a high speed, ringing occurs. Is generated at the output node, and a stable output signal can be generated.

  In the configuration shown in FIG. 75A, resistance elements 430, 432, and 434 have resistance values different from each other, and are configured to discharge output nodes in order from the largest resistance element. This configuration provides the following advantages over a configuration in which resistance elements having the same resistance value are provided in parallel at the output node 6. When resistance elements having the same resistance value are provided in parallel, the combined resistance connected to the output node 6 is sequentially reduced. Therefore, in this case as well, output node 6 can be discharged sequentially at a high speed. However, even when a voltage level at which ringing does not occur is reached, the discharge speed is determined by the combined resistance value determined by the number of resistance elements, and the output node 6 cannot be discharged at high speed. Therefore, by using a configuration with different resistance values, when the voltage at the output node 6 is lowered to a voltage level that does not cause ringing, the voltage at the output node 6 can be discharged at high speed. An output signal can be generated.

  The configuration shown in FIG. 75A can also be applied to a configuration for charging output node 6.

  Further, in the configuration shown in FIG. 75A, a configuration in which the timing at which the drive transistor is turned on may vary depending on the presence or absence of the invalid output signal may be used. Further, a voltage regulator that applies voltages VccQ and VssQ to the power supply node and the ground node may be used.

  As described above, according to the tenth embodiment of the present invention, a plurality of resistance elements having different resistance values are connected in parallel to the output node, and the output nodes are charged / discharged in order from the resistance element having the largest resistance value. Therefore, when ringing occurs at the output node, the output node is charged relatively slowly, and when the output node changes to a voltage level at which no ringing occurs, the output node is driven to the minimum voltage level at high speed. Therefore, an output circuit that can generate an output signal at high speed without causing ringing can be obtained.

[Embodiment 12]
FIG. 76 schematically shows a structure of an output circuit according to the eleventh embodiment of the present invention. In FIG. 76, an output circuit 926 generates a drive circuit 450 that generates an internal data signal, an output permission signal and, if necessary, a data signal output in accordance with an output instruction signal DOT, and an output node 6 in accordance with the output signal of drive circuit 450. Drive transistors 1 and 2 for outputting an output signal Q to the output. The configuration of the output circuit 926 is the same as that of the previous embodiment or the conventional configuration.

  In FIG. 76, the output circuit is further supplied with a current from external power supply voltage extVcc supply node 455, and generates a reference voltage VREF3 depending on temperature and external power supply voltage extVcc. Temperature T and external power supply A constant reference voltage VREF1 independent of the voltage extVcc and a differential amplifier 460 for differentially amplifying the reference voltage VREF3 are included. One operating power supply voltage VccQ for output circuit 926 is applied from differential amplifier 460 to power supply node 300. Differential amplifier 460 operates using external power supply voltage extVcc applied to external power supply voltage extVcc supply node 455 as one operation power supply voltage. Reference voltage VREF1 is generated using the circuit configuration shown in FIG. 55B (however, reference voltage VREF1 is generated from external power supply voltage extVcc).

  Reference voltage generation circuit 470 includes a constant current source 471 for supplying a constant current from external power supply voltage extVcc supply node 455 to node 475, a MOS transistor 472 connected in series between node 475 and ground voltage GND supply node, and A resistance element 473 is included. External power supply voltage extVcc is applied to the gate of MOS transistor 472. The configuration of reference voltage generating circuit 470 is substantially the same as that shown in FIG. The reference voltage VREF3 is simply generated from the external power supply voltage extVcc. In other words, resistance element 473 is formed using, for example, polysilicon or a diffused resistor ion-implanted at a relatively high concentration, and has a positive temperature coefficient. The resistance value R of the resistance element 473 is made slightly larger than the ON resistance of the MOS transistor 472. Further, the temperature dependence of the resistance value R of the resistor 473 is made sufficiently larger than the temperature dependence characteristic of the constant current source 271 and the temperature dependence characteristic of the on-resistance of the MOS transistor 472. MOS transistor 472 functions as a variable resistance element that provides conductance that varies according to external power supply voltage extVcc. The operation of this reference voltage generation circuit 470 is the same as that of the reference voltage generation circuit shown in FIG. The reference voltage generation circuit 470 has a negative dependence characteristic with respect to the external power supply voltage extVcc as shown in FIG. 77A, and also with respect to the ambient temperature (operating temperature) as shown in FIG. 77B. Thus, the reference voltage VREF3 having a positive dependency characteristic is generated.

  The differential amplifier 460 amplifies the difference between the reference voltage VREF3 and the reference voltage VREF1. When the operating temperature (ambient temperature) T rises, the reference voltage VREF3 rises, and the voltage VccQ output from the differential amplifier 460 increases accordingly. On the other hand, when the ambient temperature (operating temperature) T is constant and the external power supply voltage extVcc increases, the reference voltage VREF3 decreases, and the voltage VccQ output from the differential amplifier 460 decreases accordingly. That is, differential amplifier 460 has a positive dependence characteristic on operating temperature (ambient temperature) T as shown in FIG. 78 (A), and FIG. 78 (B) with respect to external power supply voltage extVcc. As shown, a voltage VccQ having a negative dependence characteristic is applied onto power supply node 300. Next, the effect of the voltage VccQ having such characteristics will be described.

  As described with reference to FIGS. 56 and 59, generally, when the operating temperature rises, the operating speed of the MOS transistor decreases due to generation of thermoelectrons in the channel region, while the gate potential or the drain potential is reduced. When it becomes higher, the drain current increases and the operation speed becomes faster (in the case of an n-channel MOS transistor). When external power supply voltage extVcc rises, operating voltage of drive transistor 1 increases when power supply node 300 is supplied with a voltage that changes in proportion to external power supply voltage extVcc. In this case, when the potential of the output node 6 is precharged to the intermediate potential, the operation speeds of the drive transistor 2 and the drive transistor 1 are different, and the time required for outputting the “H” level signal. As a result, a difference occurs in the time required for outputting the “L” level signal, and the operating characteristics of the output circuit deteriorate. In this case, by using differential amplifier 460 to reduce voltage VccQ applied to power supply node 300, an increase in the operating speed of drive transistor 1 can be suppressed, and the access time when the “H” level signal is output. Can be suppressed, and the operating characteristics can be kept constant. Similarly, when the ambient temperature (operating temperature) T increases, the operating speed of drive transistors 1 and 2 decreases. In this case, the operation of drive transistor 1 is increased by increasing power supply voltage VccQ on power supply node 300. The decrease in speed can be compensated, and the fixed timing of the output signal can be kept constant.

  In the configuration shown in FIG. 76, the gate of drive transistors 1 and 2 is configured to apply a voltage VccQ level voltage changing similarly to voltage VccQ using a level conversion circuit, so that external power supply voltage extVcc and It is possible to obtain a stable output circuit that can make the output signal determination timing constant regardless of the ambient temperature (operating temperature) T.

  FIG. 79 is a diagram schematically showing an overall configuration of a semiconductor device to which the present invention is applied. In FIG. 79, the semiconductor device is applied to internal power supply line 303 from step-down circuit 480 that generates a constant internal voltage Vcc that does not depend on external power supply voltage extVcc within a predetermined range of external power supply voltage extVcc. Internal power supply use circuit 482 that operates using internal power supply voltage Vcc and ground voltage GND applied on ground line 302 as both operation power supply voltages, external power supply voltage extVcc applied to power supply node 300, and ground node 302 It includes an input / output circuit 484 that operates with the ground voltage GND as both operating power supply voltages and provides an interface with the outside of the apparatus. In the configuration shown in FIG. 79, the components included in the system outside the apparatus operate using external power supply voltage extVcc as the operating power supply voltage. Therefore, in this case, in order to interface with an external device, input / output circuit 484 uses external power supply voltage extVcc as its operating power supply voltage. By applying the configuration shown in FIG. 76 to the output circuit included in input / output circuit 484, a stable output signal independent of external power supply voltage extVcc and ambient temperature (operating temperature) can be generated. The signal output timing can also be made constant.

  In the configuration shown in FIG. 76, power supply voltage VccQ applied to power supply node 300 may be applied not only to drive transistor 1 but also to drive circuit 450. In output circuit 926, drive circuit 450 may be provided with a circuit for converting the level of internal power supply voltage Vcc to the level of external power supply voltage extVcc and applying the level to the gates of drive transistors 1 and 2.

  As described above, according to the eleventh embodiment of the present invention, a voltage having a positive dependence characteristic on the ambient temperature and a negative dependence characteristic on the external power supply voltage is applied to the power supply node of the output circuit. Since it is configured to transmit, it is possible to generate an output circuit that stably compensates for changes in the operating characteristics of the drive transistor due to variations in ambient temperature and external power supply voltage, and generates an output signal that does not cause ringing stably at a constant timing. .

  Needless to say, in the output circuit according to the eleventh embodiment, a configuration in which the output node drive timing in the first to sixth embodiments is different may be used in combination.

[Embodiment 13]
FIG. 80 shows a structure of a main portion of the output circuit according to the twelfth embodiment of the present invention. In the configuration shown in FIG. 80, in order to apply voltage VccQ to power supply node 300 of output circuit 926, it is activated in response to clock signal φCK, and voltage VccQ on power supply node 300 and reference voltage VREFa are differentially applied. Amplifying differential amplifier 490 is coupled between power supply node (internal power supply voltage supply node or external power supply voltage supply node) and power supply node 300, and in response to output signal C1 of differential amplifier 490, this power supply voltage supply node A p-channel MOS transistor 492 that supplies current from 491 to power supply node 300 and a switching transistor 494 that includes an n-channel MOS transistor that discharges power supply node 300 to the level of ground voltage GND in response to clock signal / φCK are provided. It is done.

  Clock signal φCK is activated, for example, when output permission signal OEM is activated. This clock signal φCK may be activated in response to a signal for giving an operation timing of output circuit 926. Next, the operation of the circuit shown in FIG. 80A will be described with reference to FIG.

  When clock signal φCK is inactive “L”, differential amplifier 490 is inactive, its output signal C1 is at the voltage Vcc level applied to power supply voltage supply node 491, and drive transistor 492 is off. Is in a state. On the other hand, clock signal / φCK is at “H”, switching transistor 494 is on, and voltage VccQ on power supply node 300 is at the level of ground voltage GND. In this state, drive transistors 1 and 2 included in output circuit 926 are both off, and output node 6 is precharged to the intermediate voltage level or maintained in the state of the output signal read in the previous cycle. (Set to output high impedance state).

  When a new data signal is read, clock signal φCK becomes active “H” level at the same time or earlier than output permission signal OEM, and differential amplifier 490 is activated. On the other hand, the clock signal / φCK becomes “L”, and the switching transistor 494 is turned off. When voltage VccQ on power supply node 300 is lower than reference voltage VREFa, output signal C1 from differential amplifier 490 falls from its "H" level (voltage Vcc level), and drive transistor 492 is turned on. Then, a current is supplied from power supply voltage supply node 491 to power supply node 300 to raise voltage VccQ. At this time, if the current driving capability of drive transistor 492 is adjusted to an appropriate value, voltage VccQ on power supply node 300 rises gently. When voltage VccQ on power supply node 300 becomes higher than reference voltage VREFa, the output signal of differential amplifier 490 becomes “H” level, and drive transistor 492 is turned off. Thereby, voltage VccQ on power supply node 300 is maintained at the voltage level of reference voltage VREFa.

  In the output circuit 926, when “H” signal is output, the drive transistor 1 is turned on, and current is supplied from the power supply node 300 to the output node 6. At this time, the change in the voltage level on output node 6 is substantially the same as the change in voltage VccQ at power supply node 300. The rate of change of voltage VccQ on power supply node 300 is determined by the current driving capability of drive transistor 492 and the parasitic capacitance associated with power supply node 300. The parasitic capacitance in the power supply node 300 is a circuit-specific value and is almost constant. Therefore, by adjusting the current driving capability of drive transistor 492 to an appropriate value, the rate of change of voltage VccQ can be adjusted to an appropriate value, and the occurrence of ringing of output signal Q at output node 6 accordingly. Can be suppressed.

  At this time, if the change speed of the output signal C1 of the differential amplifier 490 is adjusted, the current driving force of the drive transistor 492 can be changed at an appropriate speed, and the change speed of the output signal Q of the output node 6 accordingly. Can be made gentle so that ringing does not occur.

  If reference voltage VREFa is set to a voltage level at which ringing does not occur when output node 6 is driven at high speed, output node 6 can reach the voltage level of reference voltage VREFa at a relatively high speed. At this time, if a configuration in which the voltage on power supply node 300 is raised to the level of power supply voltage Vcc by another circuit is used, output signal Q can be output at high speed without causing ringing stably.

  The reference voltage VREFa may be a voltage level higher than the high level voltage VOH of the output signal determined by the specification.

  As described above, according to the twelfth embodiment of the present invention, the voltage VccQ applied to the power supply node of output circuit 926 is activated in response to the signal giving the operation timing of the output circuit. Since the amplifier and the drive transistor supplying current from the power supply voltage supply node to the power supply node in response to the output signal of the differential amplifier are provided, the output signal appearing at the output node is supplied to the voltage VccQ on the power supply node 300. The output signal can be generated stably and at high speed without causing ringing.

[Embodiment 14]
FIG. 81 schematically shows a structure of a portion related to data signal output of the semiconductor device according to the thirteenth embodiment of the present invention. In FIG. 81, semiconductor device 500 amplifies the data of memory cell arrays 501 and 502 each having a plurality of memory cells arranged in a matrix, and the data of the memory cells selected in memory cell arrays 501 and 502, and an internal data bus 506 includes a data bus amplifier 504 for transmission on 506. A configuration may be used in which memory cell arrays 501 and 502 are activated at the same time, a memory cell is selected from each, and data in the selected memory cell is read out. Even if only one memory cell array of memory cell arrays 501 and 502 is activated, a memory cell is selected in the activated memory cell array, and the selected memory cell data is read out. Good.

  In this semiconductor memory device 500, a plurality of bits of data signals are output, so that a plurality of pads 510a to 510c and 510d to 510f are arranged. Between internal data bus 506 and pads 510a-501f, output circuits 926a-926c and 926d-926f are arranged corresponding to pads 510a-510f, respectively. As shown in FIG. 81, the length of the internal data bus 506 from the data bus amplifier 504 to the output circuits 926a to 926f is different. 81, in the semiconductor device 500, the output circuits 926a to 926c and the output circuits 926d to 926f are shown to be symmetrically arranged. In that case, the length of the internal data bus 506 between the data bus amplifier 504 and the output circuits 926a and 926d is the shortest, and the length of the internal data bus 506 between the output circuits 926c and 926f and the data bus amplifier 504 is the longest. Become.

  As the output circuits 926a to 926c move away from the data bus amplifier 504 (as the length of the internal data bus 506 increases), the time constant for generating the output signal Q is reduced, and the change rate of the output signal Q is Increased. Similarly, in the output circuits 926d to 926f, the time constant of the output signal Q is reduced as the distance from the data bus amplifier 504 is increased.

  In addition, when drive transistors for driving a plurality of output nodes are provided in parallel, and the on-timings of the plurality of drive transistors are different, the time difference between the on-timings of the drive transistors in the output circuit 926a is the output circuit 926c. Be bigger than that in Similarly, the time difference between the ON timings of the plurality of drive transistors in the output circuit 926d is made larger than that of the output circuit 926f. Next, the operation will be described.

  First, an operation when the time constant of the output signal is reduced as the distance from the data bus amplifier 504 is increased will be described with reference to FIG. In FIG. 82A, output signals Qa and Qc change from “L” to “H” in accordance with internal data signal IQa applied to output circuit 926a and internal data signal IQc applied to output circuit 926c. Operation is shown. The data bus amplifier 504 is activated in response to, for example, a preamplifier enable signal (not shown), amplifies data of a plurality of memory cells selected in the memory cell arrays 501 and / or 502, and the amplified plurality of bits of memory cell data On the internal data bus 506. Thereby, internal signals IQa and IQc on internal data bus 506 change according to the amplified signal from time ta. The longer the internal data bus 506 is, the greater its parasitic capacitance and wiring resistance. Therefore, the internal data signal IQa changes relatively faster than the internal data signal IQc. FIG. 82A shows a state where internal data signal IQa reaches “H” level of a predetermined voltage level at time tb.

  Output circuits 926a to 926c and 926d to 926f are activated at the same timing according to output permission signal OEM (not shown). The output circuit 926a has a small current driving force, a time constant of the output signal Qa is increased, and the rate of change of the output signal Qa is relatively slow. On the other hand, the time constant of the output signal Qc of the output circuit 926c is made small, that is, the current driving power of the output circuit 926c is made relatively large, and the output signal Qc changes at a relatively high speed according to the internal data signal IQc. To do. Since internal data signal IQa changes at high speed and the current driving capability of output circuit 926a is reduced, output signal Qa from output circuit 926a changes relatively slowly. On the other hand, in the output circuit 926c, although the internal data signal IQc changes relatively slowly, the current driving force of the output circuit 926c is increased, and therefore, the output is compensated for the moderate change speed of the internal data signal IQc. The signal Qc changes relatively quickly. As a result, the change speeds of the output signals Qc and Qa of the output circuits 926c and 926a can be made the same, and a definite state can be established at substantially the same timing.

  FIG. 82 (A) shows an example in which data output signals Qa and Qc are set to a definite state at time tc. At this time, the current driving capability of the output circuit 926a that receives the internal data signal IQa that changes at high speed is reduced, and even if the internal data signal IQa changes at high speed, the occurrence of ringing is suppressed in the output signal Qa. The On the other hand, in the output circuit 926c that receives the internal data signal IQc that changes relatively slowly, the current drivability is increased, but the rate of change of the internal data signal IQc is moderate, and the signal Qc has a large current drivability. By generating the output signal Qc, the gradual change of the internal data signal IQc can be compensated for and the output signal Qc can be generated at high speed. At this time, even if the current driving capability of the output circuit 926c is increased, for example, if the output signal level change of the AND circuit included therein follows the change speed of the internal data signal IQc, this output signal Qc can generate the output signal Qc at high speed without causing ringing. As a result of this series of operations, output signals that are stably determined at substantially the same timing are generated on the pads 510a to 510c and 510d to 510f.

  Next, with reference to FIG. 82B, an operation in the case where the output circuit includes two drive transistors and these two drive transistors are turned on at different timings will be described. FIG. 82B also shows the data input / output relationship of the output circuits 926a and 926c. Also in FIG. 82B, there is an example in which internal data signals IQa and IQc both change to “H” and output signals Qa and Qc from output circuits 926a and 926c both change to “H” level. As shown.

  When data bus amplifier 504 is activated and internal data signals IQa and IQc on internal data bus 506 change, output circuits 926a to 926c and 926d to 926f are activated after a predetermined time has elapsed. Internal data signal IQa for output circuit 926a is set to a stable state at time tb. At this time, the output circuit 926a outputs the output signal Qa with a relatively small driving force. Therefore, the data signal Qa changes relatively slowly (charged by a transistor having a small driving force). Next, at time te, the drive transistor having a large driving force included in the output circuit 926a is turned on, and the output signal Qa is charged to a predetermined voltage level at high speed. At this time, the voltage level of the output signal Qa has sufficiently changed to a voltage level at which ringing does not occur. Therefore, even if the internal signal Qa is driven to a predetermined voltage level at high speed, ringing does not occur and stable output is achieved. A signal can be obtained. On the other hand, internal data signal IQc changes relatively slowly. In this case, the output circuit 926c first turns on the drive transistor having a small driving force to charge the output signal Qc. At time td, the drive transistor having a large current driving capability is turned on in the output circuit 926c, and the output signal Qc is charged at high speed. At this time, the internal data signal IQc changes relatively slowly. Therefore, even when the output circuit 926c changes the output signal Qc with a large driving force, the signal voltage level applied to the drive transistor 1 remains at the internal data. Due to the gradual change of the signal IQc, a sufficiently high voltage level (predetermined final voltage level) has not been reached, so that the output node is driven relatively slowly, and the output signal Qc is generated at high speed without causing ringing. Are driven to a predetermined voltage level. When internal data signal IQc reaches a predetermined voltage level, output signal Qc finally reaches the predetermined voltage level at high speed according to internal data signal IQc.

  As shown in FIGS. 82A and 82B, by adjusting the magnitude of the current driving capability of the output circuit and the time difference between the ON timings of the plurality of drive transistors in accordance with the distance from the data bus amplifier 504. Without causing ringing, the timing at which the output signals from all the output circuits are determined can be made substantially the same, and a semiconductor memory device with a short access time can be realized.

  In the signal waveform diagrams shown in FIGS. 82A and 82B, when the data bus amplifier 504 is activated, the output circuit is also activated at the same time. However, in the configuration in which output circuits 926a to 926f are activated (output permission signal OEM is activated) after data bus amplifier 504 is activated and internal data of data bus 506 is substantially determined. However, the time difference between the activation timing of the data bus amplifier 504 and the activation timing of the output circuits 926a to 926f can be shortened, so that a semiconductor memory device with a short access time can be realized.

[Modification 1]
FIG. 83 shows a structure of a modified example of the thirteenth embodiment of the present invention. In FIG. 83, the semiconductor device 500 is housed in a package 550. In this package 550, external lead terminals 515a to 515c and 515d to 515f are arranged. These external lead terminals 515a to 515f are connected to pads 510a to 510c and 510d to 510f of the semiconductor device 500 through lead frames and bonding wires. In FIG. 83, pads 510a to 510f and external lead terminals 515a to 515f are shown by a single straight line including these bonding wires and lead frames. In the semiconductor device, the length of the lead frame varies depending on the shape of the package. 83, the distance lf between the pad 510 (510a to 510f) and the external lead terminal 515 (515a to 515f) and the distance ld between the data bus amplifier 504 and the pad 510 (the output circuit is shown in FIG. 83). The time difference between the current driving power of the drive transistor and the on timing of the plurality of drive transistors in the output circuit is adjusted according to the distance (not shown). That is, for example, the smaller the sum of the distance ld of the internal data bus 506 and the total distance lf of the bonding wire and the lead frame, the larger the time constant of the output signal Q output from the output circuit and the slower the change speed (drive transistor) To reduce the current driving force). Alternatively, the time difference between the ON timings of the plurality of drive transistors is increased as the sum of the distances ld and lf is smaller. If the length lf of the lead frame and the bonding wire is long, the load to be driven by the output circuit increases and the change rate of the output signal decreases. Therefore, by increasing the driving force of the output circuit as the distance if increases, this large load is compensated to change the output signal at high speed. With this configuration, regardless of the internal data bus distance and the length of the sum of the distance between the wire bonding and the lead frame, all output signals from all the output circuits are achieved in a stable state at the same timing without causing ringing. A semiconductor memory device that can be used can be obtained.

  If the signal delay in the internal data bus is not as great as the effect of the length of the bonding wire and lead frame on the input / output characteristics of the output circuit, the driving force of the output circuit is the length of the bonding wire and lead frame. The time constant of the output signal Q may be determined according to the length of the length lf.

  As described above, according to the thirteenth embodiment of the present invention, the magnitude of the current driving capability of the drive transistor according to the input and output loads (the length of the internal data bus and the output signal line) of each output circuit is large. Alternatively, since the time difference between the timings at which the plurality of drive transistors are turned on is adjusted, it is possible to obtain a semiconductor device that operates at high speed and is in a definite state at almost the same timing in all output circuits without causing ringing.

[Embodiment 15]
FIG. 84 shows a structure of a main portion of the output circuit according to the fourteenth embodiment of the present invention. FIG. 84 shows a configuration of a portion for discharging the output node to the ground voltage level. A similar configuration may be provided for a portion that charges output node 6 to a voltage level on power supply node 561. In FIG. 84, the output circuit includes a drive element 562 having a small current driving capability that discharges output node 6 to the level of ground voltage GND in response to internal signal NOL1, and a drive that becomes active at a timing later than internal signal NOL1. Drive element 564 having a large current driving capability for discharging output node 6 to the ground voltage level in response to signal NOL2 is included. Output node 6 is connected to pad 560. Drive element 564 having a large current driving force is arranged at a position close to pad 560. In FIG. 84, drive elements 562 and 564 may include resistance elements therein, and various configurations described in the previous embodiments can be applied. Therefore, drive transistors 2a and 2b are representatively shown. .

  The drive transistor 2b having a large current driving capability has a larger channel width than the drive transistor 2a having a small current driving capability. That is, the junction area between the impurity region connected to output node 6 and the substrate region is larger in drive transistor 2b than in drive transistor 2a. Similarly, the area of the gate insulating film is larger in the drive transistor 2b than in the drive transistor 2a. Therefore, even when the same voltage is applied between the drain gate and the drain source of drive transistors 2a and 2b, the drain electric field is smaller in drive transistor 2b, and the junction breakdown voltage is accordingly increased. Similarly, in the drive transistor 2b having a wider gate insulating film, the electric field between electrodes of the capacitor, which is larger than the withstand voltage of the drive transistor 2a, is inversely proportional to the capacitor area). When the resistance element is used, the voltage drop of the resistance element having a large resistance value becomes large.

  Therefore, with the configuration shown in FIG. 84, when a large noise such as a surge voltage is generated in output pad 560, the excessive noise is absorbed by drive transistor 2b having a large junction withstand voltage or withstand voltage, and the junction withstand voltage is small. Alternatively, it is possible to prevent excessive noise from being applied to the drive transistor 2a having a small withstand voltage. Thereby, an output circuit excellent in resistance to excessive noise can be obtained without providing any special protective device.

  In the configuration shown in FIG. 84, power supply voltage Vcc may be applied to power supply node 561, or voltage VccQ output from another power supply circuit as described in the previous embodiment is applied. May be.

  Further, the number of drive elements connected in parallel to the output node may be larger than two. In this case, the drive element having the largest electrode driving force may be disposed at the position closest to the output pad 560.

  As described above, according to the fourteenth embodiment of the present invention, a plurality of drive elements are provided, and when the current drive powers of the plurality of drive elements are different, they have the largest current drive power. By arranging the drive element in the position closest to the output pad, excessive noise such as surge voltage generated in the output pad is absorbed by the drive element having a large current driving capability, so a special protective device must be provided. In addition, a highly reliable output circuit having excellent noise resistance can be obtained.

[Embodiment 16]
FIG. 85 shows a structure of a main portion of the output circuit according to the fifteenth embodiment of the present invention. FIG. 85 shows a configuration of a portion for discharging output node 6 to the ground voltage level. A similar structure can be provided for a portion that charges output node 6 to a voltage level on power supply node 561 (transistor 1 is representatively shown). Transistor 1 is shown protected by protection circuit 570.

  In FIG. 85, the output circuit includes a plurality of drive elements having different current driving capabilities connected in parallel to output node 6. In FIG. 85, only the drive element 562 having the smallest current driving force is shown. The drive element 562 can be applied in various configurations as in the previous embodiment, and only the drive transistor 2a is representatively shown. Output node 6 is connected to output pad 560. A protection circuit 570 is provided at the position of the output node between the drive element 562 having a small current driving capability and the power supply pad 560. For example, protection circuit 570 is connected to receive a ground voltage GND, a diode 571 having a cathode connected to power supply node 561 and an anode connected to output node 6, and a cathode connected to output node 6. A diode 574 having an anode. A drive element having a large current driving force may be provided at any of positions F and G indicated by arrows in FIG. The protection circuit 570 may be disposed between the drive element and the output pad 560 that may be destroyed by excessive noise such as a surge voltage having a small current driving force. In the configuration shown in FIG. 85, when positive excessive noise occurs in output pad 560, diode 572 conducts, discharges this positive excessive noise to power supply node 561, and absorbs excessive noise. On the other hand, when negative excessive noise occurs, the diode 574 conducts and charges this negative excessive voltage to the ground voltage level. Thus, excessive noise such as positive and negative surge voltages can be absorbed by the protection circuit 570, and the drive transistor 2a having a small junction withstand voltage and withstand voltage can be prevented from being destroyed by the excessive noise. The same applies when a resistive element is used.

  In the configuration shown in FIG. 85, power supply node 561 may be combined with a configuration in which voltage VccQ is applied. Note that although the protection circuit 570 includes a diode, any configuration can be used as long as the circuit has a protection function for absorbing excessive noise such as a surge voltage.

  Further, the output charging transistor 1 is provided in the subsequent stage of the protection circuit 570. However, when the transistor 1 has a relatively large current driving capability, it is provided between the protection circuit 570 and the pad 560. Also good.

  As described above, according to the fifteenth embodiment of the present invention, since the protection circuit for absorbing excessive noise is arranged between the drive element having a small current driving capability and the output pad, the output is output via the output pad. Even when excessive noise occurs in a node, such excessive noise is absorbed by the protection circuit, preventing excessive noise from being transmitted to a drive element with a small current driving capability, and an excessive amount of drive elements with a small current driving capability. It is possible to obtain an output circuit that is prevented from being destroyed by noise and has excellent resistance to excessive noise.

  As described above, the first to fifteenth embodiments of the present invention have been described in detail, but these embodiments may be used in combination as appropriate in the application to which they are applied.

  In the above-described embodiment, as an example of the data output configuration, a case where inverted data of data in a memory cell is transmitted to the data output system is shown. However, the present invention is not limited to this, and the configuration of the present invention is also applied to the case where non-inverted data is transmitted or when both the inverted data and the complementary data pair of non-inverted data are transmitted to the data output system through a pair of data lines. Can be applied.

  Furthermore, in the above-described embodiment, the configuration in which “L” level output data is mainly output has been described. However, the present invention can also be applied to a path for outputting “H” data. it can.

  In the above embodiment, one output circuit is mainly described. However, the configuration of the present invention can be applied to the output system of each bit even in a multi-bit parallel output configuration. The data output node and the data input node may be shared, or may be provided separately.

  Furthermore, in the above-described embodiment, the output circuit is composed of only an n-channel MOS transistor, but the output circuit is composed of a CMOS circuit using both an n-channel MOS transistor and a p-channel MOS transistor. The same applies to the case.

  The output circuit according to the present invention can be applied to a portion that drives an external bus through a pad in a general semiconductor integrated circuit device, and in particular, by being applied to a portion that interfaces with the outside of a semiconductor memory device. A storage device that can stably generate data can be realized.

It is a figure which shows the structure of the output control circuit which is 1st Embodiment of this invention. FIG. 2 is a signal waveform diagram showing an operation of the output control circuit shown in FIG. 1. It is a figure which shows the 1st example of a change of 1st Embodiment of this invention. FIG. 4 is a diagram for explaining the operation of the output control circuit shown in FIG. 3. FIG. 2 is a diagram showing a configuration of an output permission signal generation circuit shown in FIG. 1. FIG. 6 is a signal waveform diagram showing an operation of the output permission signal generation circuit shown in FIG. 5. It is a figure which shows the 2nd modification of 1st Embodiment of this invention. It is a figure which shows the 3rd modification of 1st Embodiment of this invention. It is a figure which shows the structure of the output control circuit which is 2nd Embodiment of this invention. FIG. 10 is a signal waveform diagram showing an operation of the output control circuit shown in FIG. 9. FIG. 10 is a signal waveform diagram showing an operation of the output control circuit shown in FIG. 9. It is a figure which shows the example of a change of 2nd Embodiment of this invention. FIG. 13 is a signal waveform diagram illustrating an operation of the output control circuit illustrated in FIG. 12. It is a figure for showing the timing relationship of an output instruction | indication signal and an output permission signal, and the relationship of the output signal which appears at that time. It is a figure for demonstrating the timing relationship of an output instruction | indication signal and an output permission signal, and the relationship of an output data signal. It is a figure which shows the structure of the output control circuit which is the 3rd Embodiment of this invention. FIG. 17 is a signal waveform diagram showing an operation of the output control circuit shown in FIG. 16. It is a signal waveform diagram which shows the structure and the operation | movement of the 1st modification of the 3rd Embodiment of this invention. It is a figure which shows the structure of the 2nd modification of the 3rd Embodiment of this invention. It is a figure which shows the structure of the 3rd modification of the 3rd Embodiment of this invention. FIG. 21 is a diagram illustrating a modification example of the NAND circuit illustrated in FIG. 20. FIG. 22 is a signal waveform diagram showing an operation of the circuit shown in FIG. 21. It is a figure which shows the structure of the output control circuit which is the 4th Embodiment of this invention. FIG. 24 is a signal waveform diagram illustrating an operation of the output control circuit illustrated in FIG. 23. It is a figure which shows the 1st modification of the output control circuit of 4th Embodiment of this invention. FIG. 26 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 25. It is a figure which shows the 2nd modification of the output control circuit which is 4th Embodiment of this invention. FIG. 28 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 27. It is a figure which shows the 3rd modification of the output control circuit which is 4th Embodiment of this invention. FIG. 30 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 29. It is a figure which shows the 4th modification of the output control circuit which is 4th Embodiment of this invention. FIG. 32 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 31. It is a figure which shows the 5th modification of the output control circuit which is 4th Embodiment of this invention. It is a figure which shows the 6th modification of the output control circuit which is 4th Embodiment of this invention. FIG. 35 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 34. It is a figure which shows the 7th modification of the output control circuit which is 4th Embodiment of this invention. FIG. 37 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 36. FIG. 37 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 36. FIG. 37 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 36. It is a figure which shows the 8th modification of the output control circuit which is 4th Embodiment of this invention. FIG. 41 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 40. FIG. 41 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 40. It is a figure which shows the 9th modification of the output control circuit which is 4th Embodiment of this invention. It is a figure which shows the 10th modification of the output control circuit which is 4th Embodiment of this invention. It is a figure which shows the temperature and voltage dependence characteristic of the 1st control voltage used in 5th Embodiment of this invention. It is a figure which shows the temperature and voltage dependence characteristic of the 2nd control voltage used in 5th Embodiment of this invention. It is a figure which shows the structure of the component of the delay circuit used in the 5th Embodiment of this invention, and its operating characteristic. It is a figure which shows the other structural example of the component of the delay circuit used in the 5th Embodiment of this invention, and its operating characteristic. It is a figure which shows the further another structure of the component of the delay circuit used in the 5th Embodiment of this invention, and its operating characteristic. It is a figure which shows the 1st example of application of 5th Embodiment of this invention, and its operation | movement waveform. It is a figure which shows the 2nd application example of the 5th Embodiment of this invention, and its operation | movement waveform. It is a figure which shows the 3rd application example of the 5th Embodiment of this invention, and its operation | movement waveform. It is a figure which shows the 4th example of application of 5th Embodiment of this invention, and its operation | movement waveform. It is a figure which shows schematically the circuit structure for generating the 1st and 2nd control voltage. FIG. 55 is a diagram showing a specific configuration of the VREF1 generation circuit shown in FIG. 54 and a voltage / temperature dependency characteristic of a first reference voltage. FIG. 55 is a diagram showing a specific configuration of the VREF2 generation circuit shown in FIG. 54 and a voltage / temperature dependency characteristic of a second reference voltage. FIG. 55 is a diagram showing input / output voltages of the differential amplifier circuit shown in FIG. 54. It is a figure which shows the voltage / temperature dependence characteristic of the operating power supply voltage used in the modification of the 5th Embodiment of this invention. It is a figure which shows the example of a change of 5th Embodiment of this invention, and its operating characteristic. It is a figure which shows schematically the structure of the output circuit which is the 6th Embodiment of this invention. FIG. 61 is a diagram schematically showing a configuration of an output circuit shown in FIG. 60. FIG. 61 is a diagram showing a configuration of a voltage regulator shown in FIG. 60. FIG. 63 is a signal waveform diagram representing an operation of the voltage regulator shown in FIG. 62. It is a figure which shows the 1st modification of 6th Embodiment of this invention. It is a figure which shows roughly the structure of the output circuit in the 1st modification of the 6th Embodiment of this invention. It is a figure which shows the structure of the voltage regulator in the output circuit of 7th Embodiment of this invention. FIG. 67 shows a configuration of adjustment voltage Vccp and Vbsg generation circuits shown in FIG. 66. It is a figure which shows the structure of the output circuit which is 8th Embodiment of this invention. FIG. 69 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 68. FIG. 69 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 68. It is a figure which shows the structure of the output circuit which is the 9th Embodiment of this invention. It is a figure which shows the example of a change of 9th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an output circuit which are the 10th Embodiment of this invention. It is a figure which shows the structure and operation | movement of the example of a change of 10th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an output circuit which are 11th Embodiment of this invention. It is a figure which shows the structure of the output circuit which is 12th Embodiment of this invention. FIG. 77 is a diagram showing an external power supply voltage and temperature dependence characteristic of reference voltage VRF3 output from the reference voltage generation circuit shown in FIG. 76. FIG. 77 is a diagram showing a temperature and external power supply voltage dependence characteristic of power supply voltage VccQ appearing on the reference power supply node shown in FIG. 76. It is a figure which shows the example of application of 12th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an output circuit which are 13th Embodiment of this invention. It is a figure which shows the structure of the semiconductor device which is 13th Embodiment of this invention. FIG. 82 is a waveform diagram showing a signal output operation in the semiconductor device shown in FIG. 81. It is a figure which shows the example of a change of 13th Embodiment of this invention. It is a figure which shows the structure of the output circuit which is 14th Embodiment of this invention. It is a figure which shows the structure of the output circuit which is 15th Embodiment of this invention. 1 is a diagram schematically showing an overall configuration of a conventional dynamic semiconductor memory device. It is a figure which shows the structure of the conventional output circuit. FIG. 88 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 87. It is a figure which shows the parasitic capacitance and parasitic inductance which accompany an output node. FIG. 90 is a diagram for explaining ringing caused by the parasitic inductance shown in FIG. 89; It is a figure which shows the example of a possible correction | amendment of an output control circuit. FIG. 92 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 91. FIG. 92 is a diagram showing a relationship between an output permission signal and a column address strobe signal shown in FIG. 91.

Explanation of symbols

  1, 1a, 1b Output drive transistor, 2, 2a, 2b Output drive transistor, 6 output node, 12 delay circuit, 13 NAND circuit, 14 NAND circuit, 15 delay circuit, 16 NOR circuit, 17 inverting delay circuit, 18 NOR circuit , 19 Inversion delay circuit, 20 NOR circuit, 21 OR circuit, 22 NAND circuit, 40a, 40b control block, 50 one-shot pulse generation circuit, 51 delay circuit, 52 one-shot pulse generation circuit, 56 flip-flop, 60a, 60b Data line precharge transistor, 67 p-channel MOS transistor, 84 flip-flop, 87 delay circuit, 87a delay circuit, 88 delay circuit, 89 NAND circuit, 90 AND circuit, 91 NOR circuit, 92 gate circuit, 93 Lip flop, 94 flip-flop, 95 delay circuit, 100 output control circuit, 105 latch circuit, 106 latch circuit, 107 delay circuit, 108 delay circuit, 111 AND circuit, 113 NAND circuit, 114 delay circuit, 115 delay circuit, 116 NAND Circuit, 117 latch circuit, 121 NAND circuit, 122 latch circuit, 123 delay circuit, 125 delay circuit, 126 NAND circuit, 130 NAND circuit, 131 delay circuit, 132 latch circuit, 134 NAND circuit, 135 NAND circuit, 136 delay circuit, 137 delay circuit, 142 latch circuit, 143 delay circuit, 144 AND circuit, 145 NOR circuit, 146 delay circuit, 160, 160a, 160b delay circuit, 161 delay circuit, 230 delay circuit, 2 1, 232, 233 Inverter circuit, 241, 242 Inverter circuit, 251-254 Inverter circuit, 261-264 Inverter circuit, 250 VREF1 generator circuit, 251 VREF2 generator circuit, 252 Differential amplifier circuit, 253 Differential amplifier circuit, 261 Temperature Zener diode with compensation, 271 constant current source, 272 n-channel MOS transistor, 273 resistance element, 290 differential dynamic amplifier circuit, 291 inverter circuit, 922 input / output control circuit, 926 output circuit, 300 power supply node, 301 voltage regulator, 302 ground node, 304a, 304b power supply voltage application circuit, 306a, 306b ground voltage application circuit, 318, 319, 320, 321 drive transistor, 325 boost circuit, 327 level conversion circuit, 328, 329 Eve transistor, 330, 331 drive transistor, 340 voltage regulator, 350 drive circuit, 360, 365 drive transistor, 384 flip-flop, 387, 388 delay circuit, 2e, 2f, 2g drive transistor, 401, 402 delay circuit, 404, 406 AND circuit, 1e, 1f, 1g drive transistor, 403, 404 delay circuit, 301a, 301b voltage regulator, 410 rise delay circuit, 412 switching transistor, 414 resistance element, 420, 422 rise delay circuit, 2h, 2i drive transistor 424 switching transistor, 426 resistance element, 2j, 2k, 2l drive transistor, 430, 432, 434 resistance element, 440, 442 rise delay circuit, 46 0 differential amplifier (comparison circuit), 470 reference voltage generation circuit, 490 differential amplifier, 492 drive element, 494 switching transistor, 504 data bus amplifier, 506 internal data bus, 510a-510f output pad, 515a-515f external lead terminal 560 output pad, 562, 564 drive element, 570 protection circuit, 926a to 926f output circuit.

Claims (1)

An output circuit for outputting to the output node a logic signal corresponding to the logic of the input signal applied to the input node,
In response to the input signal, a first drive element that drives the output node to a potential level corresponding to the logic of the input signal at a first speed;
Has a M OS transistor Ru receiving a control voltage to the gate at least one, the gate of the MOS transistor - delay means for delaying the input signal and the source voltage is decreased is increased,
A second drive element for driving the output node to a potential level corresponding to the logic of the input signal at a second speed higher than the first speed in response to the output of the delay means;
Adjusting means for adjusting the length of a delay time given to the input signal by the delay means according to an operating temperature, and the adjusting means is configured to adjust a control voltage for reducing a gate-source voltage of the MOS transistor when the operating temperature is lowered. Output circuit to output.

Images