JP4096028B2 - Gain stabilization circuit for digital-to-analog converter - Google Patents

Description

【数２】

【数３】

ここで、Ｃ_dは、デジタルデータであり、０〜１の範囲の値を取る。例えば、８ビットの場合には、１/２⁸＝１/２５６きざみで０〜１の範囲の値を取りうる。
また、同様にして、電圧値Ｖ１およびＶ２は、以下の（数４）および（数５）のように表される。
【数４】

【数５】

【００１９】
また、電圧加算器の出力をＶ_Aとすると、このＶ_Aは、以下の（数６）のように表される。
【数６】

ここで、Ｒ_A＝Ｒ_Bの場合には、Ｖ_Aは、以下の（数７）で表される。
【数７】

つまり、ＤＡＣ１０に入力されるデジタルデータＣ_dには依存しないことになる。
【００２０】
ところで、ＤＡＣ１０の基準入力電圧（Ｖ_DAC）とフルスケール電流（Ｉ_FS）との間に比例関係がある場合には、以下の（数８）のように表現することができる。
【数８】

ここで、ａは変換係数であり、ｂはオフセットである。
次に、差動積分器１６からＤＡＣ１０の基準入力へとフィードバックを行うと、Ｖ_A＝Ｖ_REFになったところで平衡状態となるので、（数７）を用いて
【数９】

となるため、
【数１０】

が得られる。ここで、Ｖ_REFとＲ_Aとはともに定数なので、ＤＡＣ１０内部のａおよびｂが温度等によって変動しても、ＤＡＣ１０のフルスケール電流Ｉ_FSは常に一定値となる。従って、安定することになる。
【００２１】
実際には、差動積分器１６のフィードバックによって、ＤＡＣ１０の基準入力とフルスケール出力電圧（Ｖ_out）との関係が厳密な比例関係でなくても単調に増加する関係にある場合には、安定に動作させることができる。つまり、（数１１）に示すように、出力電圧Ｖ_outは、ＤＡＣ１０の内部ドリフトに左右されないことがわかる。
【数１１】

ここで、（数１）を用いて、
【数１２】

さらに、（数１０）を用いてＩ_FSを消去すると、（数１３）が得られる。
【数１３】

ここで、（数１３）のＲ_fとＶ_REFとＲ_Aとは定数であり、Ｃ_dは０〜１の範囲のデジタルデータに対応する変数である。従って、出力電圧Ｖ_outは、ＤＡＣ１０の内部ドリフトに左右されないことがわかる。また、このＶ_REFの値を変更することにより、Ｖ_REFに比例する出力電圧Ｖ_outの利得を正確に調整することができる。
【００２２】
次に、図２を参照して、図１のフィードバック回路を備えたＤＡＣ１０の利得安定化回路についてさらに詳細に説明する。図において抵抗Ｒ_1Aと抵抗Ｒ_1BはＤＡＣ１０の内部ラダー抵抗であり、抵抗Ｒ_2Aと抵抗Ｒ_2Bは外部シャント抵抗であり、抵抗Ｒ_3Aと抵抗Ｒ_3Bは相補出力Ａ、Ｂの加算値を検出するセンシング抵抗である。ここで、Ｒ_3A、Ｒ_3Bは、Ｒ_2AとＲ_2Bに比して十分大きい。相補出力Ａ、Ｂを有するＤＡＣ１０からの一方の出力Ａは、抵抗Ｒ_1Aと抵抗Ｒ_2Aと抵抗Ｒ_3Aとに分岐し、抵抗Ｒ_1Aは接地されており、抵抗Ｒ_2Aは増幅器１２の入力に接続され、抵抗Ｒ_3Aは抵抗Ｒ_3Bと加算器１４の入力とにそれぞれ接続されている。また、ＤＡＣ１０からの相補出力の他方の出力Ｂは、抵抗Ｒ_1Bと抵抗Ｒ_2Bと抵抗Ｒ_3Bとに分岐しており、抵抗Ｒ_1Bと抵抗Ｒ_2Bとはともに接地されており、抵抗Ｒ_3Bは抵抗Ｒ_3Aと増幅器１４の入力とにそれぞれ接続されている。加算器１４の出力は、差動積分器１６の入力に接続されている。また、差動積分器１６の別の入力は、基準電圧であるＶ_REFに接続されている。そして、加算器１４からの出力電圧と基準電圧Ｖ_REFとの差に応じた電圧が、（図２にＲＥＦで示す）ＤＡＣ１０の基準入力へとフィードバックされる。また、加算器１４から出力される電圧をＶ_FBとする。
【００２３】
ここで、図２の抵抗Ｒ_3Aを流れる電流をi₁とし、抵抗Ｒ_3Bを流れる電流をi₂とする。上記の図２の回路において、Ｒ_1AとＲ_2Aとの並列回路の合成抵抗値をＲ_CAとし、Ｒ_1BとＲ_2Bとの並列回路の合成抵抗値をＲ_CBとすると、電流i₁およびi₂は以下の（数１４）のように表される。
【数１４】

となる。従って、電流i₁とi₂との和は、（数１５）のように表される。
【数１５】

ここで、Ｒ_3Bを調整することにより、（数１５）の交流成分をゼロ、つまり、[（Ｒ_CB＋Ｒ_3B）・Ｒ_CA−（Ｒ_CA＋Ｒ_3A）・Ｒ_CB]＝０とすると、（数１６）が得られる。
【数１６】

従って、差動積分器１６からＤＡＣ１０へとフィードバックされる電圧Ｖ_FSは、（数１７）で表される。
【数１７】

つまり、Ｖ_FSとＶ_REFとを比較して、差動積分器等を用いてＤＡＣのリファレンスへとフィードバックすることにより、Ｉ_FSを安定化できる。つまり、Ｖ_REF＝Ｖ_FBとすることにより、Ｉ_FSは、（数１８）となる。
【数１８】

【００２４】
ここで、Ｉ_A＝Ｉ_FSの場合には、図２のα点での電圧は、（数１９）となる。
【数１９】

つまり、α点の電圧は、利得フィードバックによって、Ｒ_3A、Ｒ₄、Ｖ_REFのみにより求まることがわかる。
【００２５】
また、（数１９）から、図２のβ点のフルスケール電圧（Ｖ_OUTFS）は、（数２０）により表される。
【数２０】

ここで、（数２０）にはＲ_1Aの項が含まれていないため、このフィードバックにはシャント抵抗、つまりＤＡＣ１０の内部ラダー抵抗や外付シャント抵抗等の利得に全く影響しないということがわかる。例えば、ＤＡＣの内部ラダー抵抗の特性が不明であるような場合には、高精度で高安定度のＤＡＣを実現することが困難な場合があるが、本発明によればこのような問題は発生しない。同様に、図３に示すようにローパスフィルタ（ＬＰＦ）３０、３２を含む態様において、このようなＬＰＦの直列抵抗Ｒ_LPF等によって、出力フルスケール電圧Ｖ_OUTFS は影響を受けないことがわかる。
【００２６】
次に、本発明のフィードバック回路図を備えた具体的なＤＡＣを図４に示す。図４では、リニアテクノロジー社製のＬＴＣ１６６８をＤＡＣとして用いている。また、（図１の抵抗Ｒ_AおよびＲ_Bにも対応する）図４の抵抗Ｒ_AおよびＲ_Bは、０．１％マッチングのものを使用している。ここで、図４の抵抗Ｒ_AとＲ_BとＲ_Cとの温度係数についても、できる限りマッチングするものを選択して使用することが好ましい。このとき、ＤＡＣに入力されるデジタルコードに関連して、ＤＡＣから出力される、１組の相補出力であるノーマル出力電流Ｉ_Aとコンプリメンタリ出力電流Ｉ_Bとの関係について図５に示す。ノーマル出力電流Ｉ_Aとコンプリメンタリ出力電流Ｉ_Bとの和がフルスケール電流Ｉ_FSに等しく一定になっている。
【００２７】
次に、上記の図４の回路構成において、フィードバック回路を用いなかった場合（従来技術の場合）とフィードバック回路を用いた場合（本発明の場合）とのＤＡＣの出力電圧の安定性を図６に示す。図６Ａは、本発明のフィードバック回路を用いない従来技術の場合に対応し、図６Ｂはフィードバック回路を用いた本発明の場合に対応する。本発明のフィードバック回路を用いることによって、図６Ａの従来技術の場合と比較して、約６０分間における出力電圧の変動幅が、半分程度（１０μＶ）に低減しており、利得安定度が向上していることがわかる。
【００２８】
このように、高速だが利得安定度が劣るために利用することができなかったＤＡＣに対して本発明のフィードバック回路を適用することによって、高い利得安定性を有するＤＡＣを安価に得ることができる。また、本発明のフィードバック回路は、ＤＡＣのゲインドリフト等によって影響を受けず、ＤＡＣの内部基準等も不要である。また外部基準入力を調整することによって、正確な利得制御を行うこともできる。さらに、ＤＡＣ内部のラダー抵抗のばらつきやローパスフィルタ（ＬＰＦ）の直流損失分についても本発明のフィードバック回路によって自動的にキャンセルされる。また、本発明は利得フィードバック方式を採用しているので、これらの発熱による温度ドリフトも抑制することができ、熱設計が非常に楽になる。
【００２９】
なお、上記実施態様では電流の場合について説明してきたが、本発明はこれに限らず電圧出力のＤＡＣにも適用することができる。また、外部基準信号は、外部基準電圧であっても外部基準電流であってもよい。さらに、上記の加算器は、増幅器を含まない、例えば抵抗加算であってもよい。
【００３０】
【発明の効果】
以上説明したように、本発明によって、少なくとも１組の相補出力と外部基準入力とを有するＤＡＣの利得安定度の改善が可能となる。また、外部直流電圧に比例してＤＡＣの利得を精密に安定に制御することができる。
また、本発明によれば、利得安定度が１２ビット程度のＤＡＣについても１６ビット以上に改善することができる。もちろん、この場合においても、１６ビット以上の安定度を実現するためには、温度係数が低く、温度係数がマッチングした抵抗や低ドリフトのオペアンプの選択が必要である。しかし、その場合であっても、最初から高い安定性を有するＤＡＣを設計して作成することに比べると、本発明による回路をＤＡＣに適用する方がはるかに容易で低コストに実現することができる。
また、従来よりドリフトが大きくて実用回路への適用が困難な回路構成に対しても、本発明を適用することができる。さらに、従来は、スピード、安定度、分解能に応じて、必要なＤＡＣを選択していたが、本発明によれば、ＤＡＣの安定度はほぼ不問となるため、設計の自由度や選択の自由度が大幅に向上する。
【図面の簡単な説明】
【図１】本発明のフィードバック回路の動作原理を説明するための回路構成を示す概略図である
【図２】本発明のフィーバック回路のより詳細な回路構成を示す概略図である。
【図３】本発明のフィードバック回路にローパスフィルタ（ＬＰＦ）をさらに適用した場合の回路構成を示す概略図である。
【図４】本発明のフィードバック回路を適用した具体的な実施態様を示す概略図である。
【図５】デジタルコードに対応してＤＡＣから出力される、ノーマル出力電流Ｉ_Aと相補出力（コンプリメンタリ出力）Ｉ_Bとの関係を示す概略図である。
【図６】図４のフィードバック回路を用いた場合のＤＣドリフト特性を示すグラフである。Ａは、フィードバック回路が無い場合である。Ｂは、フィードバック回路が有る場合である。
【符号の説明】
１０ デジタル・アナログ変換器
１２ 増幅器
１４ 加算器
１６ 差動積分器
３０、３２ ローパスフィルタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for gain stabilization of a digital-to-analog converter (hereinafter referred to as “DAC”) having a complementary output, and more particularly to an external feedback circuit for improving the gain stability of a DAC.
[0002]
[Prior art]
Conventionally, a low-speed DAC can be created with good gain stability. However, when a high-speed DAC is created, elements such as transistors are mainly required to be miniaturized, and the drive voltage is required to be low because of the breakdown voltage of such elements. Accordingly, gain stability generally tends to deteriorate as the DAC becomes faster.
[0003]
For this reason, in order to realize a high-speed and stable DAC, a standard that is as stable as possible is given. If necessary, selection of elements by a temperature test, use of a thermostatic chamber that maintains the ambient temperature at a certain temperature, A method of performing calibration after elapse of a certain time has been performed.
[0004]
In addition, even when a stable reference voltage is applied from the outside, the output of the DAC changes due to temperature changes or changes with time of the resistors and transistors in the DAC. Patent Document 1 discloses a method of changing a value of an error correction register so as to compensate for a DC offset by detecting a voltage difference of a differential output pair of a DAC during a specific period (testing mode). . In order to compensate for this temperature change and change over time, the following Patent Document 1 discloses a method of changing a compensation value stored in a storage unit in accordance with an error signal indicating a difference between an ideal output and an actual output. Is disclosed.
[0005]
[Patent Document 1]
JP-A-7-202893 (page 3-6, FIG. 1)
[0006]
However, if a storage means, a thermostat, etc. are used, the cost will increase. In addition, if calibration is performed after a certain time has elapsed, extra time is required. Furthermore, there is concern about whether sufficient effects can be obtained for long-term stability.
[0007]
Furthermore, in recent years, with the development of monolithic IC technology, high-speed and high-resolution DACs have been supplied at a relatively low cost. However, it is difficult to obtain the stability suitable for the resolution of the DAC. In addition, if the DAC itself is improved to obtain a DAC having high speed and high stability, its manufacturing cost becomes very high. Further, in a high-speed DAC, even when a stable reference voltage is applied from the outside, the stability of the output current is only about 50 to 100 ppm / ° C. Further, since the power consumption is relatively large, the DAC is at a higher temperature than the surroundings and is easily affected by outside air such as wind. In general, the DAC internal fluctuation (drift) factors may include various factors such as temperature matching mismatch caused by temperature changes of the internal reference operational amplifier, resistors, transistors, and the like. For this reason, it is difficult to obtain a low drift in a high-speed DAC. On the other hand, there is a fact that DACs that are high speed but relatively low in stability have been provided at low cost.
[0008]
As means for realizing high stability (or low drift) using a DAC having poor stability, (1) temperature correction method, (2) temperature stabilization method, and (3) time division A calibration method, (4) a composite DAC method, and (5) a gain feedback method have been proposed. Here, the gain feedback system is to take out an output having some correspondence with the DAC gain and stabilize the gain by feedback. Among these, (1) the temperature correction method and (2) the temperature stabilization method have a problem in long-term stability because there is no feedback. In addition, (3) continuous output is not possible with the time division calibration method. And (4) circuit configuration is generally difficult in the composite DAC system. For this reason, (5) there is a fact that the gain feedback method has been adopted.
[0009]
[Problems to be solved by the invention]
Therefore, there is a need for a method for improving the gain stability of a DAC having a complementary output and an external reference input at a relatively low cost.
[0010]
[Means for Solving the Problems]
The present invention provides a circuit applicable to a digital-to-analog converter (DAC) having a set of complementary outputs capable of obtaining high gain stability without using a special technique or apparatus as in the prior art. . Specifically, a gain stabilization circuit for a digital-to-analog converter that includes a reference input and a complementary output pair, and outputs a complementary output signal pair to the complementary output pair according to an input signal to the reference input. First and second inputs coupled to the complementary output pair; a third input for inputting an external reference signal; a signal related to a sum of signals received by the first and second inputs; A circuit is provided that includes an output for providing a signal related to a difference from an external reference signal to the reference input.
A gain stabilization circuit for a digital-to-analog converter having at least one set of complementary outputs and at least one reference input, each coupled to the at least one set of complementary outputs of the digital-to-analog converter. An adder for detecting and outputting an output signal of the digital-analog converter; a signal output from the adder and an external reference voltage are input; and a signal output from the adder and the external reference voltage And an error detector that outputs a signal corresponding to the difference between the signals, and outputs the signal corresponding to the difference output from the error detector to the digital-analog converter. A circuit is provided that feeds back to a reference input.
Here, the external reference voltage is set to a polarity according to the circuit configuration of the adder and the error detector, or the reference input of the digital-analog converter is a current input type. In some cases, the voltage corresponding to the difference output from the error detector is fed back to the reference input of the digital-analog converter via a voltage-current conversion means, or the adder, An embodiment realized by a combination of an inverting amplifier and a differential amplifier is preferable.
[0011]
The present invention also provides a digital-to-analog converter having a set of complementary outputs that can achieve high gain stability.
Specifically, the digital-to-analog converter circuit having at least one set of complementary outputs and the at least one set of complementary outputs of the digital-to-analog converter circuit are respectively coupled to detect an output signal of the digital-to-analog converter circuit The signal output from the adder and the external reference voltage are input, and the signal output from the adder is compared with the external reference voltage to correspond to the difference between the signals. And a digital-to-analog converter that feeds back a voltage corresponding to the difference output from the error detector to a reference input of the digital-to-analog conversion circuit. .
Here, the external reference voltage is set to a polarity according to the circuit configuration of the adder and the error detector, or the reference input of the digital-analog converter is a current input type. In some cases, it is preferable that the voltage corresponding to the difference output from the error detector is fed back to the reference input of the digital / analog converter via a voltage-current conversion means.
[0012]
Here, the adder may include a combination with a fixed gain differential amplifier, for example. In addition, the adder here may include a mode in which, for example, an inverting amplifier and a differential amplifier or a subtracter are combined to substantially execute the operation of the adder. In addition, the voltage / current converting means may include, for example, a resistor for the connection between the adder and the differential amplifier.
[0013]
Therefore, by applying the present invention to a DAC that has been used at a high speed but is inferior in gain stability, a DAC having high speed and high stability can be provided at low cost.
[0014]
Further, by stabilizing the gain of the DAC, for example, the stability (or offset drift) at the zero point (that is, half of full scale) at the time of bipolar output is also improved.
[0015]
Furthermore, a DAC having a complementary output and an external reference input can be applied to most DACs except for a CMOS multiplying DAC that cannot obtain accuracy unless the output voltage is 0V. Further, in order to obtain a high resolution, for example, the present invention can be similarly applied to a plurality of DACs composed of combinations of upper bits and lower bits (also called upper and lower combined DACs).
[0016]
In this way, by providing a circuit that detects and feeds back a signal proportional to the full-scale output current of the DAC, the full-scale output voltage of the DAC (that is, the gain of the DAC) is made as stable as the external reference. be able to.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
The operation principle of the DAC using the feedback circuit of the present invention will be described with reference to the circuit configuration of FIG. An amplifier 12 that outputs a voltage corresponding to the digital data value C _d input to the DAC 10 via a resistor R _A to one output A of the DAC 10 having a reference input and a pair of complementary outputs A and B. Is connected. A voltage adder 14 is connected to a pair of complementary outputs A and B of the DAC 10 and takes the sum of the voltages output from the DAC 10. A differential integrator 16 is connected to the output of the voltage adder 14 via a resistor R. Here, in the differential integrator 16, the difference between the reference voltage _VREF input to the differential integrator 16 via the resistor R and the voltage input from the voltage adder 14 via the resistor R is determined. The voltage V _DAC is configured to be fed back to the reference input of the DAC 10.
[0018]
Next, the operation principle of the circuit of the present invention will be described. Here, the values of the current and voltage that are output from one of the complementary outputs A of the DAC 10 and flow through the resistor _RA are I ₁ and V _1, and the resistor R that is output from one of the complementary outputs B of the DAC ₁₀ and branches in the middle thereof The values of current and voltage flowing through _B are I ₂ and V ₂ . However, the input resistance of each input terminal of the voltage adder 14 is sufficiently high. Further, the total current (full scale current) output from the DAC 10 is I _FS . Then, the current values I ₁ and I ₂ are expressed as the following (Equation 1), (Equation 2), and (Equation 3).
[Expression 1]

[Expression 2]

[Equation 3]

Here, C _d is digital data and takes a value in the range of 0-1. For example, in the case of 8 bits, a value in the range of 0 to 1 can be taken in increments of 1/2 ⁸ = 1/256.
Similarly, the voltage values V1 and V2 are expressed as the following (Equation 4) and (Equation 5).
[Expression 4]

[Equation 5]

[0019]
If the output of the voltage adder is V _A , this V _A is expressed as in the following (Equation 6).
[Formula 6]

Here, when R _A = R _B , V _A is expressed by the following (Equation 7).
[Expression 7]

That is, it does not depend on the digital data C _d input to the DAC 10.
[0020]
By the way, when there is a proportional relationship between the reference input voltage (V _DAC ) and the full-scale current (I _FS ) of the _{DAC 10,} it can be expressed as the following (Equation 8).
[Equation 8]

Here, a is a conversion coefficient and b is an offset.
Next, when feedback is performed from the differential integrator 16 to the reference input of the DAC 10, an equilibrium state is reached when V _A = V _REF , so that

So that
[Expression 10]

Is obtained. Here, since V _REF and R _A are both constants, the full-scale current I _FS of the DAC 10 is always a constant value even if a and b inside the DAC 10 fluctuate due to temperature or the like. Therefore, it becomes stable.
[0021]
Actually, when the relationship between the reference input of the DAC 10 and the full-scale output voltage (V _out ) is not strictly proportional but is monotonically increased by the feedback of the differential integrator 16, the stability is stable. Can be operated. That is, as shown in (Equation 11), it can be seen that the output voltage V _out is not influenced by the internal drift of the DAC 10.
[Expression 11]

Here, using (Equation 1),
[Expression 12]

Further, when _IFS is erased using (Equation 10), (Equation 13) is obtained.
[Formula 13]

Here, R _f , V _REF, and R _A in (Equation 13) are constants, and C _d is a variable corresponding to digital data in the range of 0-1. Therefore, it can be seen that the output voltage V _out is not influenced by the internal drift of the DAC 10. Further, by changing the value of this V _REF, it is possible to accurately adjust the gain of the output voltage V _out proportional to V _REF.
[0022]
Next, the gain stabilization circuit of the DAC 10 including the feedback circuit of FIG. 1 will be described in more detail with reference to FIG. In the figure, the resistors R _1A and R _1B are internal ladder resistors of the DAC 10, the resistors R _2A and R _2B are external shunt resistors, and the resistors R _3A and R _3B detect the added values of the complementary outputs A and B. Sensing resistance. Here, R _3A and R _3B are sufficiently larger than R _2A and R _2B . Complementary output A, one of the output A from DAC10 with B, is branched into the resistor R _1A and the resistor R _2A and resistor R _3A, resistor R _1A is grounded, the resistor R _2A is the input of the amplifier 12 The resistor R _3A is connected to the resistor R _3B and the input of the adder 14. Further, other output B of the complementary output from DAC10, the resistance R _1B and branches into the resistor R _2B and resistor R _3B, and both are grounded and the resistor R _1B and the resistor R _2B, the resistor R _{3B Are} connected to the resistor R _3A and the input of the amplifier 14, respectively. The output of the adder 14 is connected to the input of the differential integrator 16. Further, another input of the differential integrator 16 is connected to V _REF which is a reference voltage. A voltage corresponding to the difference between the output voltage from the adder 14 and the reference voltage V _REF is fed back to the reference input of the DAC 10 (indicated by REF in FIG. 2). The voltage output from the adder 14 is V _FB .
[0023]
Here, the current flowing through the resistor R _{3A in} FIG. 2 is i _1, and the current flowing through the resistor R _3B is i ₂ . In the circuit shown in FIG. 2, if the combined resistance value of the parallel circuit of R _1A and R _2A is R _CA and the combined resistance value of the parallel circuit of R _1B and R _2B is R _CB , currents i ₁ and i ₂ is expressed as (Equation 14) below.
[Expression 14]

It becomes. Therefore, the sum of the currents i ₁ and i ₂ is expressed as (Equation 15).
[Expression 15]

Here, by adjusting R _3B , if the AC component of (Equation 15) is zero, that is, [(R _CB + R _3B ) · R _CA − ( _{RC A} + R _3A ) · R _CB ] = 0, Equation 16) is obtained.
[Expression 16]

Therefore, the voltage V _FS fed back from the differential integrator 16 to the DAC 10 is expressed by (Equation 17).
[Expression 17]

That is, I _FS can be stabilized by comparing V _FS and V _REF and feeding back to the DAC reference using a differential integrator or the like. That is, by setting V _REF = V _FB , I _FS becomes (Expression 18).
[Formula 18]

[0024]
Here, when I _A = I _FS , the voltage at the point α in FIG. 2 is (Equation 19).
[Equation 19]

That is, it can be seen that the voltage at the point α is obtained only by R _3A , R ₄ , and V _REF by gain feedback.
[0025]
Further, from ( _Equation 19), the full-scale voltage (V _OUTFS ) at the point β in FIG. 2 is expressed by ( _Equation 20).
[Expression 20]

Here, since the R _1A term is not included in (Equation 20), it can be seen that this feedback has no influence on the gain of the shunt resistance, that is, the internal ladder resistance or the external shunt resistance of the DAC 10. For example, when the characteristics of the internal ladder resistance of the DAC are unknown, it may be difficult to realize a highly accurate and highly stable DAC. However, according to the present invention, such a problem occurs. do not do. Similarly, as shown in FIG. 3, in the embodiment including the low-pass filters (LPF) 30 and 32, it can be seen that the output full-scale voltage V _OUTFS is not affected by the series resistance R _{LPF of the LPF} .
[0026]
Next, a specific DAC provided with the feedback circuit diagram of the present invention is shown in FIG. In FIG. 4, LTC1668 manufactured by Linear Technology is used as the DAC. Further, (corresponding to resistor R _A and R _B in Fig. 1) resistors R _A and R _B in FIG. 4 with the existing 0.1% matching. Here, it is preferable to select and use temperature coefficients of the resistors R _A , R _B, and R _C in FIG. 4 as much as possible. FIG. 5 shows the relationship between a normal output current I _A and a complementary output current I _B , which are a set of complementary outputs, output from the DAC in relation to the digital code input to the DAC. The sum of the normal output current I _A and the complementary output current I _B is equal to the full-scale current I _FS and is constant.
[0027]
Next, in the circuit configuration of FIG. 4, the stability of the output voltage of the DAC when the feedback circuit is not used (in the case of the prior art) and when the feedback circuit is used (in the case of the present invention) is shown in FIG. Shown in 6A corresponds to the case of the prior art not using the feedback circuit of the present invention, and FIG. 6B corresponds to the case of the present invention using the feedback circuit. By using the feedback circuit of the present invention, the fluctuation range of the output voltage in about 60 minutes is reduced to about half (10 μV) as compared with the case of the prior art of FIG. 6A, and the gain stability is improved. You can see that
[0028]
In this way, by applying the feedback circuit of the present invention to a DAC that has been used at a high speed but has been inferior in gain stability, a DAC having high gain stability can be obtained at low cost. Further, the feedback circuit of the present invention is not affected by the gain drift of the DAC and does not require an internal reference of the DAC. Also, accurate gain control can be performed by adjusting the external reference input. Further, variations in ladder resistance inside the DAC and DC loss of the low-pass filter (LPF) are also automatically canceled by the feedback circuit of the present invention. In addition, since the present invention employs a gain feedback system, temperature drift due to these heat generations can be suppressed, and the thermal design becomes very easy.
[0029]
In the above embodiment, the case of current has been described. However, the present invention is not limited to this and can be applied to a voltage output DAC. The external reference signal may be an external reference voltage or an external reference current. Further, the adder may not include an amplifier, for example, a resistance addition.
[0030]
【The invention's effect】
As described above, the present invention can improve the gain stability of a DAC having at least one set of complementary outputs and an external reference input. Further, the gain of the DAC can be precisely and stably controlled in proportion to the external DC voltage.
Further, according to the present invention, a DAC having a gain stability of about 12 bits can be improved to 16 bits or more. Of course, even in this case, in order to realize stability of 16 bits or more, it is necessary to select a low-drift operational amplifier or a resistor having a low temperature coefficient and matching the temperature coefficient. However, even in that case, it is much easier and less expensive to apply the circuit according to the present invention to the DAC than to design and create a DAC having high stability from the beginning. it can.
Further, the present invention can be applied to a circuit configuration that has a greater drift than before and is difficult to apply to a practical circuit. Further, conventionally, the necessary DAC is selected according to the speed, stability, and resolution. However, according to the present invention, the stability of the DAC is almost unquestioned, and thus the degree of freedom in design and freedom of selection are selected. The degree is greatly improved.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a circuit configuration for explaining an operation principle of a feedback circuit of the present invention. FIG. 2 is a schematic diagram showing a more detailed circuit configuration of a feedback circuit of the present invention.
FIG. 3 is a schematic diagram showing a circuit configuration when a low-pass filter (LPF) is further applied to the feedback circuit of the present invention.
FIG. 4 is a schematic diagram showing a specific embodiment to which the feedback circuit of the present invention is applied.
FIG. 5 is a schematic diagram showing a relationship between a normal output current I _A and a complementary output (complementary output) I _B output from a DAC in correspondence with a digital code.
6 is a graph showing DC drift characteristics when the feedback circuit of FIG. 4 is used. A is a case where there is no feedback circuit. B is a case where a feedback circuit is provided.
[Explanation of symbols]
10 Digital-analog converter 12 Amplifier 14 Adder 16 Differential integrator 30, 32 Low-pass filter

Claims (9)

A gain stabilization circuit for a digital-to-analog converter, comprising a reference input and a complementary output pair, and outputting a complementary output signal pair to the complementary output pair in response to an input signal to the reference input,
A first input coupled to the complementary output pair; a third input coupled to an external reference signal; a signal associated with a sum of signals received by the first and second inputs; A circuit comprising: an output for supplying a signal related to a difference from a reference signal to the reference input; A gain stabilization circuit for a digital-to-analog converter with at least one set of complementary outputs and at least one reference input,
An adder coupled to each of the at least one set of complementary outputs of the digital-to-analog converter for detecting and outputting an output signal of the digital-to-analog converter;
An error detector that inputs a signal output from the adder and an external reference voltage, compares the signal output from the adder with the external reference voltage, and outputs a signal corresponding to the difference between the signals And feeding back a signal corresponding to the difference output from the error detector to the reference input of the digital-to-analog converter. 3. The circuit according to claim 2, wherein the external reference voltage is set to a polarity corresponding to a circuit configuration of the adder and the error detector. When the reference input of the digital-analog converter is a current input type, a voltage corresponding to the difference output from the error detector is transferred to the reference input of the digital-analog converter. The circuit according to any one of claims 2 to 3, which feeds back through the conversion means. 5. The circuit according to claim 2, wherein the adder is realized by a combination of an inverting amplifier and a differential amplifier. A digital-to-analog converter circuit having at least one set of complementary outputs;
An adder coupled to at least one set of complementary outputs of the digital-to-analog converter circuit for detecting and outputting an output signal of the digital-to-analog converter circuit;
An error detector that inputs a signal output from the adder and an external reference voltage, compares the signal output from the adder with the external reference voltage, and outputs a signal corresponding to the difference between the signals And a digital-to-analog converter that feeds back a voltage corresponding to the difference output from the error detector to a reference input of the digital-to-analog conversion circuit. The digital-to-analog converter according to claim 6, wherein the external reference voltage is set to a polarity according to a circuit configuration of the adder and the error detector. When the reference input of the digital-analog converter is a current input type, a voltage corresponding to the difference output from the error detector is transferred to the reference input of the digital-analog converter. 8. The digital-to-analog converter according to claim 6, wherein the digital-to-analog converter feeds back through the converting means. 9. The digital / analog converter according to claim 6, wherein the adder is realized by a combination of an inverting amplifier and a differential amplifier.

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