JP4093765B2 - Semiconductor device mounting circuit - Google Patents

Semiconductor device mounting circuit Download PDF

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Publication number
JP4093765B2
JP4093765B2 JP2002033048A JP2002033048A JP4093765B2 JP 4093765 B2 JP4093765 B2 JP 4093765B2 JP 2002033048 A JP2002033048 A JP 2002033048A JP 2002033048 A JP2002033048 A JP 2002033048A JP 4093765 B2 JP4093765 B2 JP 4093765B2
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semiconductor element
side electrode
stress relaxation
layer
conductive
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JP2003234447A (en
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幸夫 宮地
雅人 橋本
伸二 小池
政彦 山中
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子が実装された回路および半導体素子の実装方法に関し、特に電力用半導体素子の実装回路に関する。
【０００２】
【従来の技術】
半導体素子に設けられた電極（素子側電極）と、この半導体素子が実装される回路側に設けられた電極（回路側電極）とをワイヤボンディングにより電気的に接続した半導体素子実装回路が知られている。このようなワイヤボンディングでは素子側電極と回路側電極とが細径のボンディングワイヤを介して接続されている。このため、例えば電力用半導体素子のエミッタ電極やコレクタ電極と回路側電極との接続のように大電流が流れる箇所では、ワイヤボンディングによって素子側電極と回路側電極との十分な導通性を確保することは困難である。
【０００３】
一方、図１１に示すように、半導体素子１１０上に形成された半田層１５０を介して、この半導体素子１１０に備えられた素子側電極（図示せず）と回路側電極１６０とを直接（ボンディングワイヤ等を介することなく）接続する実装構造も提案されている。かかる実装構造では、ワイヤボンディング等に比べて、素子側電極と回路側電極とが広範囲に亘って接続（半田付）されている。このように素子側電極と回路側電極との接続面積が広いことから、素子側電極と回路側電極との十分な導通性を確保しやすい。また、半田層は半導体素子および回路側電極と広範囲で接触（面接触）しているので、この半田層を介して半導体素子の作動により生じた熱を外部へと効率よく放出することができる。このような実装構造は、例えば特開平８−８３９５号公報に開示されている。
【０００４】
【発明が解決しようとする課題】
しかし、素子側電極と回路側電極とを面的に半田付（ベタ付）する上述の実装方法では、半田層の一面側は半導体素子（素子側電極）に、他面側は回路側電極にそれぞれ接合されているので自由な熱膨張あるいは収縮が抑制されている。このため、半導体素子と回路側電極との熱膨張係数の違いによって半田層に過剰な応力がかかる場合があった。
この熱膨張係数の違いによって半田層にかかる応力につき、図１１および図１２を用いて説明する。
【０００５】
図１１に示す構造において、回路側電極１６０（リードフレーム等）は一般に金属材料からなり熱膨張係数が大きい。これに対して、半導体素子１１０を構成する半導体基板（Ｓｉ等）の熱膨張係数は小さく、このため半導体素子に備えられた薄膜状の素子側電極も熱膨張が抑えられている。これにより、例えば昇温時には、図１２に示すように、半田層１５０の他面側１５０ｂ（回路側電極に接合された側）では回路側電極１６０の熱膨張に伴って引っ張り応力Ｆ1が生じ、半田層１５０の各部が中央部から外側に向かって変位（引っ張り変位）しようとする。一方、半田層１５０の一面側１５０ａ（図示しない素子側電極を有する半導体素子１１０に接合された側）では、半導体素子１１０があまり熱膨張しないことから、半田層１５０各部の外側への変位（熱膨張）を抑制しようとする圧縮応力Ｆ0が生じる。このように、半田層１５０の一面側１５０ａが拘束された状態で他面側１５０ｂが外方に変位することによって半田層１５０の内部に応力が発生する。この応力により、半田層１５０を構成する半田に微細な傷や転移が発生して組織が粗大化し（応力による半田の疲労）、さらには半田層１５０にクラックが発生して接続信頼性を損なう場合があった。
【０００６】
面的に広がる半田層では、中央部から離れるにつれて変位が蓄積されるため、半田層の端部付近には特に大きな応力がかかる。また、半田層の面積が大きくなるほど半田層の端部における変位量は大きくなる。したがって、電気導通性や熱伝導性を向上させるために半田層と電極（素子側電極および／または回路側電極）との接合長さ（面積）を大きくすると、半田が応力によって疲労するという上述の問題がさらに顕在化する。
【０００７】
本発明は、半導体素子の素子側電極と回路側電極とが半田層を介して電気的に接続された構成であって、その接続信頼性が改善された半導体素子実装回路を提供することを目的とする。
【０００８】
【課題を解決するための手段、作用および効果】
本発明では、素子側電極と半田層との間に応力緩和層を設けることによって、素子側電極と回路側電極が実質的に広い範囲にわたって接続されることによって良好な電気導通性を確保し、しかも、素子側電極と回路側電極の熱膨張係数の相違にもかかわらずに両者ともに過大な応力が作用しないようにすることに成功した。
【０００９】
本発明により提供される半導体素子実装回路は、素子側電極が形成された半導体素子と、その素子側電極の形成領域を含む半導体素子上に形成された応力緩和層と、その応力緩和層上に形成された半田層と、その半田層上において少なくとも半導体素子の一端を越えて半導体素子の周辺にまで延びているとともに、半田層上に位置する範囲で半田層に固定されている回路側電極を備えている。その応力緩和層は、複数個の導電部と緩衝部とを備えている。各々の導電部は、素子側電極と半田層の間を伸びているとともに素子側電極と半田層とを電気的に接続している。緩衝部は、隣接する導電部間に介在して導電部同士を相互に隔てている。
【００１０】
本発明の半導体素子実装回路では、半導体素子と半田層との間に応力緩和層が設けられている。この応力緩和層は、面内の少なくとも一方向に加えられた応力に対して半田層よりも変形しやすい（例えばヤング率がより低い）性質を有する。したがって、半導体素子と回路側電極との熱膨張係数の違い等によって両者の間に応力が生じた場合、この応力を応力緩和層の変形により吸収し、半田層にかかる応力を緩和することができる。これにより半田層を構成する半田の疲労が軽減され、素子側電極と回路側電極との接続信頼性を長期に亘って維持することができる。
【００１１】
この応力緩和層に用いられる緩衝部は、前記導電部よりもヤング率の低い材料を主体として形成されていることが好ましい。このような構成によると、応力緩和層にかかる応力を主として緩衝部の変形により吸収することができるので、導電部にかかる応力が低減される。
【００１２】
前記緩衝部の主体をなす「導電部よりもヤング率の低い材料」の代表例としては、各種の有機高分子が挙げられる。有機高分子のうち感光性樹脂が特に好ましい。緩衝部が感光性樹脂を主体として構成されている場合には、応力緩和層の形成時において、フォトリソグラフィ等により緩衝部の平面形状を容易に加工する（例えば貫通部を形成する加工を行う）ことができるので好都合である。
【００１３】
前記導電部は素子側電極と半田層の間を実質的に直線状に伸びていることが好ましい。このような直線状の導電部によると、例えば応力緩和層の表面と平行に延びる部分を有する折れ線状の導電部に比べて、素子側電極と回路側電極とをより導通性良く（低電気抵抗で）接続することができる。また、半導体素子のもつ熱を導電部から半田層（さらには外部）へとより効率よく放出することができる。
【００１４】
前記半導体素子の表面には前記素子側電極を露出させる絶縁保護層が設けられていることが好ましい。この絶縁保護層は酸化シリコン、窒化シリコン等の絶縁性材料から構成することができる。絶縁保護層には素子側電極を露出させる開口部が設けられており、この開口部を通じて素子側電極と導電部とが接続される。かかる絶縁保護層が設けられた半導体素子は動作の安定性および耐久性に優れる。
また、応力緩和層に形成されている緩衝部に、絶縁性を保持したまま熱伝導性を高める絶縁性充填材が分散して配置されていてもよい。絶縁性充填財として、セラミックスの微粒子を用いることが好ましい。これによると、緩衝部の絶縁性を保持したまま熱伝導性を高めることができる。
一方、応力緩和層に形成されている緩衝部に、導電性を高める導電性充填材が分散して配置されていてもよい。有機高分子等からなる緩衝部中に、導電性繊維や導電性微粒子等の導電性充填材を分散して配置することにより、緩衝部の導電性を高めることができる。
このように、緩衝部は、絶縁性であってもよいし、導電性であってもよい。
【００１５】
本発明により提供される半導体素子の実装方法は、素子側電極が形成された半導体素子を準備する工程と、その電極形成領域を含む半導体素子上に応力緩和層を形成する工程とを含む。その応力緩和層を形成する工程は、半導体素子上に樹脂層を形成する工程と、樹脂層をパターニングして素子側電極を露出させる工程と、樹脂層に形成された間隙に金属を充填する工程とを包含する。
このように、パターニングされた樹脂層を金属充填の型枠として利用することにより、この樹脂層（緩衝部）によって隔てられた金属部（導電部）を容易に作製することができる。
【００１６】
前記樹脂層は感光性樹脂により形成され、前記パターニングはフォトリソグラフィにより行われることが好ましい。この場合には、貫通部を形成する位置やその形状を容易に制御することができる。この貫通部に金属を充填する方法としては無電解メッキ法が好ましく用いられる。
これら本発明の実装方法は、本発明のいずれかの半導体素子実装回路を作製するにあたって半導体素子を実装する方法として好適である。
【００１７】
【発明の実施の形態】
次に、後述する実施例の主要な特徴を列記する。
（形態１）
応力緩和層は、貫通導電部および／または緩衝部が少なくとも一方向に規則的に繰り返された構造を有する。
（形態２）
応力緩和層は、貫通導電部および／または緩衝部が直交する二方向に規則的に繰り返された構造を有する。あるいは、互いに６０°の角度をなす三方向に規則的に繰り返された構造を有する。
（形態３）
応力緩和層の全体にわたって貫通導電部および／または緩衝部が概ね均等な密度で分布している。
（形態４）
応力緩和層は、この応力緩和層を貫通する複数の貫通導電部が緩衝部によって互いに隔てられた構造を有する。
（形態５）
貫通導電部の表面には半田濡れ性のよい金属からなるメッキが施されている。
【００１８】
【実施例】
以下、本発明の好適な実施例について詳細に説明する。
本発明の回路に備えられる半導体素子または本発明の方法により実装される半導体素子としては、各種の半導体素子（ＩＧＢＴ（Insulated Gate Bipolar Transistor）等のバイポーラトランジスタや、ＭＯＳ等の電界効果型トランジスタ等）を用いることができる。この半導体素子が電力用半導体素子（ＩＧＢＴ、パワーＭＯＳ等）である場合には、本発明を適用することによる効果が特によく発揮される。
【００１９】
この半導体素子に設けられており応力緩和層および半田層を介して回路側電極と接続される素子側電極の種類は特に問わない。本発明を適用することによる効果は、この素子側電極が半導体素子の比較的広い（例えば１mm×１mm以上）面積に亘って設けられている場合によく発揮される。本発明における素子側電極の好適例としては、電力用半導体素子のエミッタ電極および／またはコレクタ電極（特に好ましくはエミッタ電極）が挙げられる。
【００２０】
応力緩和層（貫通導電部）および半田層を介してこの素子側電極と電気的に接続される回路側電極の代表例としては、リードフレーム、二以上の半導体素子を連結する導電バー、半導体素子が実装される回路基板上に形成された導体膜（膜状電極）、この回路基板上に配置された板状電極等が挙げられる。本発明は、回路側電極がリードフレームまたは導電バーである場合に特に好ましく適用される。このような場合には回路側電極が大きく熱変形しやすいからである。
【００２１】
次に、素子側電極と半田層との間に設けられる応力緩和層につき説明する。
この応力緩和層は、半導体素子のうち素子側電極の形成された領域（電極形成領域）の少なくとも一部を含む範囲上に形成される。素子側電極と回路側電極との電気導通性の観点からは、電極形成領域の全体上に応力緩和層が形成されていることが好ましい。また、半導体素子から外部への熱伝導性（熱放出性）の観点からは、半導体素子の実質的に全面に応力緩和層が形成されていることが好ましい。このように全面に形成された応力緩和層は製造容易性の点でも有利である。なお、半導体素子の両面に電極（例えばエミッタ電極およびコレクタ電極）が形成されている場合、応力緩和層は半導体素子の一面上にのみ形成されていてもよく、両面上に形成されていてもよい。少なくとも、回路基板に取り付けられる側（基板取付側）とは反対側の面（半導体素子の上面）上に応力緩和層が形成されていることが好ましい。基板取付側の素子側電極に接続される回路側電極よりも、半導体素子の上面側の素子側電極に接続される回路側電極のほうが熱変形しやすいからである。半導体素子の一面上に形成される応力緩和層は一続きになっていることが好ましいが、複数に分割されていてもよい。
【００２２】
応力緩和層のうち貫通導電部を構成する材質としては、導電性および熱伝導性の高い金属が好ましい。例えば、銅、銀、金、白金、ニッケル、コバルト、亜鉛等の純金属およびそれらを含む合金が好ましく使用される。また、これらの材料の表面に半田濡れ性のよい金属（ニッケル、金等）がメッキされた貫通導電部であってもよい。このようなメッキ層を形成することにより、半田付性の向上、材料費の低減、耐酸化性の向上等を実現し得る。
【００２３】
応力緩和層のうち緩衝部は、貫通導電部と比較してより変形しやすい性質を有することが好ましい。このため、貫通導電部よりもヤング率の低い材料（各種の有機高分子等）を主体として形成されていることが好ましい。このような材料としては、ベンゾオキサゾール、ポリイミド、ポリメチルアクリルアミドその他、フォトリソグラフィに用いられる公知のポジ型またはネガ型の感光性樹脂等を用いることができる。この緩衝部は導電性でもよく絶縁性でもよい。緩衝部の導電性を高めるために、有機高分子等からなるマトリックス中に導電性充填材を分散させた構成等とすることができる。このような導電性充填材としては、導電性繊維（金属繊維等）、導電性微粒子（金属微粒子等）等を用いることができる。絶縁性を保持したまま熱伝導性を高めるために、マトリックス中に絶縁性充填材を分散させた構成とすることもできる。このような絶縁性充填材としては、セラミックス（典型的にはＳｉＮ，ＡｌＮ等）の微粒子等を用いることができる。
【００２４】
本発明の応力緩和層では、応力緩和層を貫通する貫通導電部が緩衝部によって隔てられている。このような応力緩和層の構造としては、面的に形成された（連続した）緩衝部に貫通導電部が分散した構造、板状（壁状）の貫通導電部および緩衝部が交互に積層された構造、これらが混在した構造等が例示される。
【００２５】
好ましい応力緩和層の例としては、線状（柱状）の貫通導電部が膜状（層状）の緩衝部を貫通した構造が挙げられる。この構造において、貫通導電部の形状は円柱状、角柱状、円錐台状、角錐台状等とすることができる。円柱状の貫通導電部を有する応力緩和層の一例を図５に、四角柱状の貫通導電部を有する応力緩和層の一例を図６に、六角柱状の貫通導電部を有する応力緩和層の一例を図７に示す。これら図５〜図７において、符号４０は応力緩和層を、符号４５は貫通導電部を、符号４１は緩衝部を示している。
このような構成において、柱状の貫通導電部は一方向に規則的に繰り返し配置されていることが好ましい。図５および図７では直交する二方向に、図６では互いに６０°の角度をなす三方向に貫通導電部４５が繰り返し配置されている。
【００２６】
また、好ましい応力緩和層の他の例として、板状（壁状）の貫通導電部および緩衝部が、応力緩和層の厚み方向と非平行に交互に積層された構造が挙げられる。図８に示すように、貫通導電部４５および緩衝部４１が半導体素子上にほぼ直立するように（積層方向が半導体素子表面とほぼ平行になるように）積層されていることが好ましい。この積層方向に貫通導電部４５および緩衝部４１が繰り返し配置されている。このような構成の応力緩和層によると、この積層方向に近い方向（特に積層方向に沿った方向）にかかる応力をよく緩和（吸収）することができる。また、線状の貫通導電部に比べて素子側電極と貫通導電部との合計接続面積を広くとり得るので良好な導通性および熱伝導性を実現し得る。
【００２７】
以下、線状の貫通導電部が膜状の緩衝部を貫通した構造または板状の貫通導電部および緩衝部が交互に積層された構造の応力緩和層を中心に説明する。
貫通導電部は応力緩和層をほぼ直線状に貫通して設けられていることが好ましい。貫通する方向は応力緩和層の厚み方向とほぼ平行であることが好ましい。すなわち、貫通導電部が素子側電極上にほぼ直立していることが好ましい。このような応力緩和層によると、貫通導電部が応力緩和層を斜めに（厚み方向と非平行に）貫通している場合に比べて貫通導電部の長さを短くすることができるので導通性および伝熱性が良好である。
【００２８】
貫通導電部の下端（半導体素子側端面）は素子側電極に接続されている。この下端の形状は素子側電極の表面形状に沿った形状（基本的には平面状）であることが好ましい。一方、貫通導電部の上端は半田層に接続されている。この上端は、緩衝部の表面（半田層側表面）とほぼ同じ高さであってもよく、図２に示すように、貫通導電部４５の上端が緩衝部４１の表面より幾分盛り上がっていてもよい。あるいは、応力緩和層上に半田層を形成する際に半田が進入可能な程度であれば、貫通導電部の上端が緩衝部の表面より幾分凹んでいてもよい。
【００２９】
貫通導電部は、応力緩和層のうち少なくとも電極形成領域上に形成される部分では、概ね均等な間隔で設けられていることが好ましい。貫通導電部が応力緩和層の全体に亘って概ね等間隔で設けられていることがより好ましい。これにより、応力緩和層にかかる応力が著しく偏ることを抑制して、この応力を効率よく吸収することができる。
【００３０】
応力緩和層の好ましい厚さは１μm以上であり、より好ましくは５μm以上である。応力緩和層の厚さが１μmよりも小さすぎると応力緩和効果が少なくなる。一方、応力緩和層の厚さが大きすぎると、この応力緩和層を貫通する貫通導電部が長くなることから導電性および熱伝導性が低下しやすくなる。このため、通常は応力緩和層の厚さを１０００μm以下とすることが好ましい。なお、貫通導電部の好ましい長さ（応力緩和層を貫通する方向に沿った長さをいう。）は１〜１０００μmであり、より好ましくは５〜６００μmである。
【００３１】
複数の貫通導電部を備える構成において、各貫通導電部と半田層および／または素子側電極との接合部が大きすぎると、このような貫通導電部を備える応力緩和層の応力緩和効果が少なくなったり、各接合部に過剰な応力がかかったりすることがある。このため、各接合部の最小幅（例えば、接合部が円状である場合には直径、長方形状である場合には短辺の長さをいう。）は１mm以下であることが好ましく、より好ましくは０．６mm以下である。また、この最小幅が貫通導電部の長さよりも小さい場合には良好な応力緩和効果が得られるので好ましい。一方、各貫通導電部と半田層および／または素子側電極との接合部が小さすぎると導電性および熱伝導性が小さくなる。このため、通常は貫通導電部の最小幅を５μm以上とすることが好ましい。
【００３２】
複数の貫通導電部を備える構成において、応力緩和層の単位面積当たりに備えられる貫通導電部の数（形成密度）は、少なすぎると導電性および熱伝導性が小さくなり、多すぎると応力緩和効果が小さくなる。貫通導電部の好ましい形成密度は１〜４０，０００個／mm2の範囲であり、より好ましくは３〜２０，０００個／mm2の範囲である。
一または二以上の貫通導電部を備える構成において、応力緩和層の横断面に占める貫通導電部の面積割合は１０〜９０％であることが好ましく、より好ましくは２０〜８０％である。この面積割合が大きすぎると応力緩和効果が少なくなり、小さすぎると導電性および熱伝導性が低下する。
【００３３】
このような応力緩和層は、半導体素子上に樹脂層を形成する工程と、樹脂層をパターニングして素子側電極を露出させる工程と、樹脂層に形成された間隙に金属を充填する工程とを包含する方法により好適に形成することができる。
樹脂層を形成する工程は、半導体素子上に樹脂組成物（感光性樹脂を主体とするものが好ましい）を塗布することにより行うことができる。塗布方法としては回転塗布、コーター塗布、キャスティング等の従来公知の各種塗布方法を適宜採用することができる。応力緩和層の好ましい形成方法では、ここで形成された樹脂層の硬化物を緩衝部として用いる。この緩衝部の厚さは樹脂層の最終硬化膜厚によって調節することができる。例えば、スピンナーを用いた回転塗布では、塗布される樹脂組成物の粘度およびスピンナーの回転数等により塗布厚を制御し得る。樹脂組成物の粘度が１０００ｃＰ（１Ｐａ）である場合、スピンナーの回転数が２６００のときに形成され得る緩衝部の厚さは例えば約５μmであり、スピンナーの回転数が１６００のときに形成され得る緩衝部の厚さは例えば約７μmである。
【００３４】
樹脂層をパターニングする工程はフォトリソグラフィにより行われることが好ましい。このフォトリソグラフィは常法に従って実施することができる。
樹脂層の間隙（素子側電極を露出させる貫通部）に金属を充填する方法としては、無電解メッキ法、電解メッキ法、スパッタリング等の各種方法を用いることができる。これらのうち無電解メッキ法を用いることが好ましい。無電解メッキ法により充填される金属の好ましい例としては、ニッケル、銅、金、クロム、コバルト、銀等が挙げられる。無電解メッキ法を用いる場合において、貫通部に充填する金属の量（メッキ厚さ）は、メッキ液に含まれる各成分の濃度、メッキ液のｐＨ、浴温度等を調整して析出速度を一定に保つとき、メッキ時間を管理すること等により制御することができる。このメッキ厚さは１μm以上であることが好ましい。メッキ厚さが１μmよりも小さすぎるとピンホールが生じやすくなる場合がある。メッキは少なくとも貫通部がほぼ満たされるまで行うことが好ましい。メッキの上端が樹脂層よりも高く盛り上がるまでメッキを進めてもよい。さらにメッキを進めて、各貫通部に充填された金属（貫通導電部）の頂部（上端）同士が連結してもよい。
【００３５】
かかる応力緩和層形成工程は、ウエハに形成された（通常は複数の）半導体素子に対して行ってもよく、個々のチップに分割した後の半導体素子に対して行ってもよい。製造効率の点からは、ウエハに形成された複数の半導体素子上にまとめて応力緩和層を形成した後、これら応力緩和層を備える半導体素子を個々のチップに分割することが好ましい。
【００３６】
応力緩和層の機能につき図９および図１０を用いて説明する。
図９に示すように、本発明の典型的な構成では、半導体素子１０と回路側電極６０との間に、半導体素子側から順に応力緩和層４０および半田層５０が設けられている。応力緩和層４０は、半導体素子１０の素子側電極（図示せず）と半田層５０とを接続する複数の貫通導電部４５と、これら貫通導電部４５を互いに隔てる緩衝部４１とを備える。半田層５０の一面側５０ａは応力緩和層４０に接続され、他面側５０ｂは回路側電極６０に接続されている。このような構成を有することにより、例えば昇温により回路側電極６０が半導体素子１０に比べて大きく熱膨張した場合、図１０に示すように、この熱膨張程度の差を応力緩和層４０の変形によって吸収することができる。したがって、応力緩和層４０が形成されていない図１２に示す構成に比べて、図１０に示す構成によると、半田層５０の一面側５０ａと他面側５０ｂとの間に生じる応力が低減される。
【００３７】
素子側電極と半田層５０との電気的接続は複数の貫通導電部４５によりなされる。このように、半導体素子１０と半田層５０との接合部を複数に分割しているので、図１１に示すように半導体素子１１０を面的に半田付（ベタ付）する場合に比べ、各貫通導電部４５と半導体素子電極１０（素子側電極）との接合面積（接合長さ）は小さくなる。また、各貫通導電部４５は緩衝部４１を隔ててほぼ独立しており、貫通導電部間４５の干渉がない。このため、半導体素子の個々の場所で素子の横（面内）方向に働く圧縮変位あるいは引っ張り変位が生じた場合にも、各貫通導電部４５において発生するのは主として純粋な剪断応力であって、貫通導電部４５相互の間に生じる応力は比較的小さく抑えられる。
このように、本発明の応力緩和層を設けることにより、半田にかかる応力が低減されることから半田の寿命が延び、素子側電極と回路側電極との接続信頼性が向上する。
【００３８】
また、本発明の典型的な構成では、素子側電極上に分散された複数の貫通導電部を介して素子側電極と回路側電極とを接続するので、従来のワイヤボンディングによる接続に比べて良好な導通性および熱伝導性を実現し得る。また、素子側電極と回路側電極とが素子側電極の複数箇所で接続されるので、ワイヤボンディングによる接続に比べて素子側電極内における電流経路を短縮し得る。これにより電気抵抗を低減することができる。
【００３９】
この貫通導電部は緩衝部によって隔てられている。この緩衝部は、応力緩和層に加えられた応力を吸収するとともに、貫通導電部を保護（形状維持、応力緩和等）する役割を果たすことができる。また、上述のように貫通導電部を形成する際の型枠（マスク）としても利用することができる。さらに、貫通導電部上と回路側電極とを半田付する際に、貫通導電部の間に半田が回りこむことを防ぐ役割を果たすことができる。
【００４０】
以下、本発明に関する実験例を説明するが、本発明をかかる実施例に示すものに限定することを意図したものではない。
【００４１】
（１）半導体素子の作製
以下に示す方法により、図１に示す半導体素子（トレンチ型ＩＧＢＴ）を作製した。
図示するように、ｐ型シリコン基板２上にｎ型層４，６，８をエピタキシャル成長させたウエハ１１に、イオン注入や熱拡散を順次行うことによりｐベース層１３、ｎエミッタ層１５を形成した。
【００４２】
このウエハ１１の表面に、ＲＩＥ（Reactive Ion Etching）によって複数のストライプ状の溝を形成した。この溝内およびウエハの表面を拡散炉等により酸化させてゲート酸化膜２１を形成した。ＣＶＤ（Chemical Vapor Deposition）等によりポリシリコンを堆積させて、溝内にポリシリコン２３を埋め込んだ。必要箇所（溝内および接続部）のポリシリコンを保護するレジストパターン（フォトリソグラフィにより作製した。以下同じ。）を形成し、このレジストパターンから露出したポリシリコン２３をＲＩＥ，ＣＤＥ（Chemical Dry Etching）等の方法により除去（エッチバック）した。このようにしてスイッチング制御用のゲート２５を作製した。
【００４３】
ゲート２５の作製されたウエハ表面に、ゲート２５を覆うとともにエミッタ層１５の一部を露出させる層間絶縁膜２７を形成した後、スパッタリング法によりアルミニウム（Ａｌ）を成膜した。必要箇所のＡｌ膜を覆うレジストパターンを作製し、レジストパターンから露出したＡｌ膜をウェットエッチングにより除去してＡｌ配線を作製した。このＡｌ配線によりエミッタ電極３１とゲート電極（図示せず）が形成される。また、このＡｌ配線と同様にしてウエハの裏面にコレクタ電極３３を作製した。
【００４４】
（２）絶縁保護層の形成
図２に示すように、上記（１）により半導体素子が形成されたウエハ１１の表面に、プラズマＣＶＤによりシリコン酸化膜３５を成膜した。このシリコン酸化膜３５は、半導体素子を外界から保護するための絶縁保護層（パッシベーション膜）である。レジストパターンを利用して、Ａｌ配線上に形成されたシリコン酸化膜（絶縁保護層）３５の一部をＲＩＥにより除去して窓３７を開け、この窓３７からＡｌ配線（エミッタ電極３１等）を露出させた。これにより、Ａｌ配線と外部とを接続するためのパッドを形成した。
【００４５】
（３）応力緩和層の形成
上記（２）で得られたウエハ１１上に応力緩和層４０を形成した。
図２に示すように、シリコン酸化膜３５の形成されたウエハ１１の表面に、感光性樹脂を主成分とする樹脂組成物をスピンナーにより塗布して樹脂層４１を形成した。感光性樹脂としてはポリベンゾオキサゾールを用いた。この樹脂層４１をフォトリソグラフィによりパターニングして、エミッタ電極（素子側電極）３１の一部を露出させる複数の円柱状貫通孔（間隙）４３を形成した。これら貫通孔４３は、樹脂層４１の厚み方向に穿たれている。このパターニングされた樹脂層４１を有するウエハ１１を硝酸でエッチングし、貫通孔４３から露出されたエミッタ電極３１の表面に形成されたＡｌ酸化膜を除去した。さらに亜鉛を含む強アルカリ溶液に浸漬し、エミッタ電極３１の露出表面を亜鉛で置換するジンケート処理を行った。硝酸ニッケル、乳酸および次亜リン酸ナトリウムを含有するメッキ浴にウエハ１１を浸漬して無電解ニッケルメッキを行った。これにより、貫通孔４３から露出されたエミッタ電極３１上にニッケルを析出させて、エミッタ電極３１上に直立した円柱状の貫通導電部４５を形成した。この無電解ニッケルメッキは、図２に示すように、析出したニッケル（貫通導電部４５）が貫通孔４３を満たし、さらにその上端が樹脂層４１よりも高くマッシュルーム状に盛り上がるまで行った。なお、貫通導電部の酸化を抑制するため、無電解ニッケルメッキにより析出したニッケルの露出表面にさらに金メッキを施してもよい。例えば、シアン化金カリウム主成分とするメッキ浴を用いた置換金メッキ法、または亜硫酸ナトリウムを添加成分とするメッキ浴を用いた無電解メッキ法により金メッキ層を形成することができる。
【００４６】
（４）回路側電極との接続
上記（３）により得られたウエハをダイシングして個々のチップに分割した。各チップの応力緩和層形成側に板状の半田を載せ、さらにその半田の上にリードフレームを載せたものを還元雰囲気の炉に通した。このことによって、応力緩和層とリードフレームとを接続する半田層を形成した。その後、半導体素子の下面（応力緩和層の形成されていない側；コレクタ電極側）およびリードフレームを回路基板（窒化アルミナ製等）に接合した。
このようにして、図３に示すように、半導体素子１０のエミッタ電極側（図３の上側）が応力緩和層４０および半田層５０を介してリードフレーム６０に接続され、半導体素子１０のコレクタ電極側（図３の下側）が回路基板７０に半田付されたＩＧＢＴ実装回路を得た。回路基板７０の表面には回路パターン７２が形成されている。半導体素子１０の他面はこの回路パターン７２により形成された回路側電極に半田層５５を介して接続されている。リードフレーム６０の一端は半田層５７を介して回路パターン７２に接続されている。
【００４７】
（５）応用例
上記実験例では樹脂層４１を形成する感光性樹脂としてポリベンゾオキサゾールを用いたが、ポリベンゾオキサゾールに代えてポリメチルアクリルアミド等を用いてもよい。フォトリソグラフィによる樹脂層４１のパターニングに用いるマスクとしては、窒化シリコン膜上に厚さ１〜５μmのチタン箔および厚さ１〜１５μmの金を蒸着したもの等を使用することができる。ポリメチルアクリルアミドを主成分とする厚さ１００〜６００μmの樹脂層をキャスティング法により形成し、その上に上述のマスクを置き、シンクロトロン放射で得られるＸ線（Ｘ線ピーク；０．２nm、Ｘ線強度；１０kj/cm2）を照射してパターニングした場合、樹脂層の厚さが６００μm程度以下であればパターニング（解像）が可能であった。
【００４８】
上記実験例では無電解ニッケルメッキより貫通導電部を形成したが、この貫通導電部を無電解銅メッキにより形成してもよい。この無電解銅メッキは、例えば、硫酸銅、ロシェル塩およびホルムアルデヒド等を含有するメッキ浴にパターニングされたウエハを浸漬して行うことができる。その後、銅の酸化防止や半田付性向上等の目的で、無電解ニッケルメッキおよび／または無電解金メッキを施してもよい。
【００４９】
上記実験例では半導体素子の上面側（基板取付側とは反対側）のみに応力緩和層を設けたが、半導体素子の下面側（基板取付側）に応力緩和層を設けてもよく、半導体素子の上下に応力緩和層を設けてもよい。
半導体素子の上下に応力緩和層を設けた半導体素子実装回路の一例を図４に示す。図示するように、複数（ここでは二つが示されている）の半導体素子１０が導電バー６２（回路側電極）によって連結されている。導電バー６２と各半導体素子１０の上面に形成された電極との接続は、上記実施例と同様に、応力緩和層４０および半田層５０を介して行われている。半導体素子１０の下面に形成された電極もまた、この下面に設けられた応力緩和層４８および半田層５５を介して、回路基板７０表面に回路パターン（図示せず）により形成された回路側電極に接続されている。このような構成では、半導体素子１０と導電バー６２との熱膨張係数の違いにより導電バー６２と個々の半導体素子１０との間に生じる応力Ｆ1に加え、回路基板７０と導電バー６２との熱膨張係数の違いによって各半導体素子１０の全体を回路基板７０に対して変位させようとする応力Ｆ2が発生し得る。図４に示す構成によると、半導体素子１０の上下に設けられた応力緩和層４０，４８によってこの応力Ｆ2を吸収することができる。これにより、半導体素子１０と半田層５０，５５との間に生じる応力を低減することができる。なお、この応力Ｆ2は、上側応力緩和層４０および下側応力緩和層４８のいずれか一方によっても緩和し得る。
【００５０】
以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
【図面の簡単な説明】
【図１】 本発明の一実験例に係る半導体素子を示す断面図である。
【図２】 図１に示す半導体素子上に応力緩和層を形成した断面図である。
【図３】 本発明の一実験例に係る半導体素子実装回路を示す断面図である。
【図４】 本発明の一応用例に係る半導体素子実装回路を示す断面図である。
【図５】 円柱状の貫通導電部を備える応力緩和層の一例を模式的に示す斜視図である。
【図６】 四角柱状の貫通導電部を備える応力緩和層の一例を模式的に示す斜視図である。
【図７】 六角柱状の貫通導電部を備える応力緩和層の一例を模式的に示す斜視図である。
【図８】 板状の貫通導電部および緩衝部が積層された構造の応力緩和層の一例を模式的に示す斜視図である。
【図９】 半導体素子と回路側電極とが応力緩和層を用いて接続された構造を示す模式的断面図である。
【図１０】 図９に示す接続構造の昇温時の状態を示す模式的断面図である。
【図１１】 半導体素子と回路側電極との従来の接続構造を示す模式的断面図である。
【図１２】 図１１に示す接続構造の昇温時の状態を示す模式的断面図である。
【符号の説明】
１０ 半導体素子
１１ ウエハ（半導体素子）
３１ エミッタ電極（素子側電極）
３３ コレクタ電極（素子側電極）
３５ シリコン酸化膜（絶縁保護層）
４０，４８ 応力緩和層
４１ 樹脂層（緩衝部）
４３ 貫通孔（貫通部、間隙）
４５ 貫通導電部
５０，５５，５７ 半田層
６０ リードフレーム（回路側電極）
６２ 導電バー（回路側電極）
７０ 回路基板
７２ 回路パターン（回路側電極）[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a circuit on which a semiconductor element is mounted and a method for mounting the semiconductor element, and in particular, to a mounting circuit for a power semiconductor element.On the roadRelated.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor element mounting circuit is known in which an electrode (element side electrode) provided on a semiconductor element and an electrode (circuit side electrode) provided on a circuit side on which the semiconductor element is mounted are electrically connected by wire bonding. ing. In such wire bonding, the element side electrode and the circuit side electrode are connected to each other through a thin bonding wire. For this reason, sufficient electrical conductivity between the element side electrode and the circuit side electrode is ensured by wire bonding at a location where a large current flows, such as connection between the emitter electrode or collector electrode of the power semiconductor element and the circuit side electrode. It is difficult.
[0003]
On the other hand, as shown in FIG. 11, an element side electrode (not shown) and a circuit side electrode 160 provided in the semiconductor element 110 are directly (bonded) via a solder layer 150 formed on the semiconductor element 110. There has also been proposed a mounting structure for connection (without a wire or the like). In such a mounting structure, compared to wire bonding or the like, the element side electrode and the circuit side electrode are connected (soldered) over a wide range. As described above, since the connection area between the element side electrode and the circuit side electrode is large, it is easy to ensure sufficient conductivity between the element side electrode and the circuit side electrode. Further, since the solder layer is in contact with the semiconductor element and the circuit side electrode in a wide range (surface contact), heat generated by the operation of the semiconductor element can be efficiently released to the outside through the solder layer. Such a mounting structure is disclosed, for example, in JP-A-8-8395.
[0004]
[Problems to be solved by the invention]
However, in the above-described mounting method in which the element side electrode and the circuit side electrode are soldered (solid) on the surface, one side of the solder layer is the semiconductor element (element side electrode), and the other side is the circuit side electrode. Since each is joined, free thermal expansion or contraction is suppressed. For this reason, excessive stress may be applied to the solder layer due to the difference in thermal expansion coefficient between the semiconductor element and the circuit side electrode.
The stress applied to the solder layer due to the difference in thermal expansion coefficient will be described with reference to FIGS.
[0005]
In the structure shown in FIG. 11, the circuit side electrode 160 (lead frame or the like) is generally made of a metal material and has a large coefficient of thermal expansion. On the other hand, the thermal expansion coefficient of the semiconductor substrate (Si or the like) constituting the semiconductor element 110 is small, and thus the thermal expansion of the thin-film element side electrode provided in the semiconductor element is also suppressed. Thus, for example, when the temperature rises, as shown in FIG. 12, the tensile stress F on the other surface side 150 b (side joined to the circuit side electrode) of the solder layer 150 is accompanied by the thermal expansion of the circuit side electrode 160.1As a result, each part of the solder layer 150 tends to be displaced (tensile displacement) from the central part toward the outside. On the other hand, on one side 150a of the solder layer 150 (the side bonded to the semiconductor element 110 having an element-side electrode not shown), the semiconductor element 110 does not thermally expand so much, so that each part of the solder layer 150 is displaced outward (heat). Compressive stress F to suppress expansion)0Occurs. Thus, stress is generated inside the solder layer 150 when the other surface side 150b is displaced outward while the one surface side 150a of the solder layer 150 is constrained. Due to this stress, fine scratches or transitions occur in the solder constituting the solder layer 150 to coarsen the structure (solder fatigue due to stress), and further cracks occur in the solder layer 150 to impair connection reliability. was there.
[0006]
In the solder layer that spreads across the surface, displacement accumulates as the distance from the center portion increases, so that particularly large stress is applied near the end of the solder layer. Further, the displacement amount at the end of the solder layer increases as the area of the solder layer increases. Therefore, when the bonding length (area) between the solder layer and the electrode (element-side electrode and / or circuit-side electrode) is increased in order to improve electrical conductivity and thermal conductivity, the solder is fatigued due to stress. The problem becomes even more apparent.
[0007]
  An object of the present invention is to provide a semiconductor element mounting circuit in which an element side electrode and a circuit side electrode of a semiconductor element are electrically connected via a solder layer, and the connection reliability is improved. TossThe
[0008]
[Means, actions and effects for solving the problems]
In the present invention, by providing a stress relaxation layer between the element side electrode and the solder layer, the element side electrode and the circuit side electrode are connected over a substantially wide range to ensure good electrical conductivity, In addition, despite the difference in thermal expansion coefficient between the element side electrode and the circuit side electrode, both have succeeded in preventing excessive stress from acting.
[0009]
  A semiconductor element mounting circuit provided by the present invention includes a semiconductor element in which an element side electrode is formed, a stress relaxation layer formed on a semiconductor element including a region where the element side electrode is formed, and the stress relaxation layer. A formed solder layer and a circuit-side electrode extending to the periphery of the semiconductor element over at least one end of the semiconductor element on the solder layer and fixed to the solder layer in a range located on the solder layer I have. There are multiple stress relaxation layers.GuidanceAn electric part and a buffer part are provided. EachGuidanceThe electric part extends between the element side electrode and the solder layer and electrically connects the element side electrode and the solder layer. The buffer is adjacent toLeadInterposed between electrical partsLeadThe electrical parts are separated from each other.
[0010]
In the semiconductor element mounting circuit of the present invention, a stress relaxation layer is provided between the semiconductor element and the solder layer. This stress relaxation layer has the property of being more easily deformed (for example, having a lower Young's modulus) than the solder layer with respect to stress applied in at least one direction in the plane. Therefore, when a stress is generated between the semiconductor element and the circuit side electrode due to a difference in thermal expansion coefficient, the stress applied to the solder layer can be absorbed by the deformation of the stress relaxation layer. . Thereby, fatigue of the solder constituting the solder layer is reduced, and the connection reliability between the element-side electrode and the circuit-side electrode can be maintained for a long period of time.
[0011]
  The buffer used for this stress relaxation layer isGuidanceIt is preferably formed mainly of a material having a Young's modulus lower than that of the electrical part. According to such a configuration, the stress applied to the stress relaxation layer can be absorbed mainly by the deformation of the buffer portion., GuidanceStress applied to the electric part is reduced.
[0012]
  The main part of the buffer part"InductionRepresentative examples of the “material having a Young's modulus lower than that of the electrical part” include various organic polymers. Of the organic polymers, a photosensitive resin is particularly preferable. When the buffer portion is mainly composed of a photosensitive resin, the planar shape of the buffer portion is easily processed by photolithography or the like when forming the stress relaxation layer (for example, processing for forming a through portion is performed). This is convenient.
[0013]
  in frontGuidanceElectric DepartmentBetween element side electrode and solder layerIn a substantially straight lineGrowingIt is preferable. Like this straight lineGuidanceAccording to the electrical part, for example, a polygonal line having a part extending parallel to the surface of the stress relaxation layerGuidanceCompared with the electric part, the element side electrode and the circuit side electrode can be connected with better conductivity (with low electrical resistance). Also, the heat of semiconductor elementsLeadIt is possible to discharge more efficiently from the electrical part to the solder layer (and also to the outside).
[0014]
  It is preferable that an insulating protective layer for exposing the element side electrode is provided on the surface of the semiconductor element. This insulating protective layer can be made of an insulating material such as silicon oxide or silicon nitride. The insulating protective layer is provided with an opening for exposing the element side electrode, and the element side electrode is exposed through the opening.And leadElectrical unit is connected. A semiconductor element provided with such an insulating protective layer is excellent in operational stability and durability.
  Moreover, the insulating filler which improves thermal conductivity may be disperse | distributed and arrange | positioned in the buffer part currently formed in the stress relaxation layer, maintaining insulation. It is preferable to use ceramic fine particles as the insulating filler. According to this, it is possible to increase the thermal conductivity while maintaining the insulation of the buffer portion.
  On the other hand, conductive fillers that enhance conductivity may be dispersed and arranged in the buffer portion formed in the stress relaxation layer. By disperse | distributing and arrange | positioning electroconductive fillers, such as a conductive fiber and electroconductive fine particles, in the buffer part which consists of organic polymers etc., the electroconductivity of a buffer part can be improved.
  As described above, the buffer portion may be insulative or conductive.
[0015]
  Semiconductor device provided by the present inventionofThe mounting method includes a step of preparing a semiconductor element in which an element-side electrode is formed, and a step of forming a stress relaxation layer on the semiconductor element including the electrode formation region. The step of forming the stress relaxation layer includes a step of forming a resin layer on the semiconductor element, a step of patterning the resin layer to expose the element side electrode, and a step of filling the gap formed in the resin layer with metal. Including.
  Thus, by using the patterned resin layer as a metal-filled mold, the metal parts separated by this resin layer (buffer part)(GuideThe electric part) can be easily manufactured.
[0016]
The resin layer is preferably formed of a photosensitive resin, and the patterning is preferably performed by photolithography. In this case, the position where the penetrating portion is formed and its shape can be easily controlled. An electroless plating method is preferably used as a method of filling the through portion with metal.
These mounting methods of the present invention are suitable as a method of mounting a semiconductor element in producing any one of the semiconductor element mounting circuits of the present invention.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, main features of embodiments described later are listed.
(Form 1)
The stress relaxation layer has a structure in which penetrating conductive portions and / or buffer portions are regularly repeated in at least one direction.
(Form 2)
The stress relaxation layer has a structure in which the through conductive portion and / or the buffer portion are regularly repeated in two directions orthogonal to each other. Or it has the structure repeated regularly in three directions which make an angle of 60 degrees mutually.
(Form 3)
Through-conductive portions and / or buffer portions are distributed at a substantially uniform density throughout the stress relaxation layer.
(Form 4)
The stress relaxation layer has a structure in which a plurality of through conductive portions that penetrate the stress relaxation layer are separated from each other by a buffer portion.
(Form 5)
The surface of the through conductive portion is plated with a metal with good solder wettability.
[0018]
【Example】
Hereinafter, preferred embodiments of the present invention will be described in detail.
The semiconductor element provided in the circuit of the present invention or the semiconductor element mounted by the method of the present invention includes various semiconductor elements (bipolar transistors such as IGBT (Insulated Gate Bipolar Transistor), field effect transistors such as MOS, etc.) Can be used. When this semiconductor element is a power semiconductor element (IGBT, power MOS, etc.), the effect of applying the present invention is particularly well demonstrated.
[0019]
The type of the element side electrode provided in this semiconductor element and connected to the circuit side electrode via the stress relaxation layer and the solder layer is not particularly limited. The effect obtained by applying the present invention is often exhibited when the element-side electrode is provided over a relatively wide area (for example, 1 mm × 1 mm or more) of the semiconductor element. Preferable examples of the element side electrode in the present invention include an emitter electrode and / or a collector electrode (particularly preferably an emitter electrode) of a power semiconductor element.
[0020]
Typical examples of the circuit side electrode electrically connected to the element side electrode through the stress relaxation layer (penetrating conductive portion) and the solder layer include a lead frame, a conductive bar connecting two or more semiconductor elements, and a semiconductor element. And a conductive film (film-like electrode) formed on a circuit board on which is mounted, and a plate-like electrode arranged on the circuit board. The present invention is particularly preferably applied when the circuit side electrode is a lead frame or a conductive bar. This is because in such a case, the circuit side electrode is large and easily deformed by heat.
[0021]
Next, the stress relaxation layer provided between the element side electrode and the solder layer will be described.
The stress relaxation layer is formed on a range including at least a part of a region (electrode formation region) where the element side electrode is formed in the semiconductor element. From the viewpoint of electrical conductivity between the element-side electrode and the circuit-side electrode, it is preferable that a stress relaxation layer is formed over the entire electrode formation region. Further, from the viewpoint of thermal conductivity (heat release) from the semiconductor element to the outside, it is preferable that a stress relaxation layer is formed on substantially the entire surface of the semiconductor element. The stress relaxation layer formed on the entire surface in this way is advantageous also in terms of manufacturability. When electrodes (for example, an emitter electrode and a collector electrode) are formed on both surfaces of the semiconductor element, the stress relaxation layer may be formed only on one surface of the semiconductor element, or may be formed on both surfaces. . It is preferable that a stress relaxation layer is formed at least on the surface (upper surface of the semiconductor element) opposite to the side attached to the circuit board (substrate mounting side). This is because the circuit side electrode connected to the element side electrode on the upper surface side of the semiconductor element is more easily thermally deformed than the circuit side electrode connected to the element side electrode on the substrate mounting side. The stress relaxation layer formed on one surface of the semiconductor element is preferably continuous, but may be divided into a plurality of layers.
[0022]
As a material constituting the through conductive portion in the stress relaxation layer, a metal having high conductivity and thermal conductivity is preferable. For example, pure metals such as copper, silver, gold, platinum, nickel, cobalt, and zinc and alloys containing them are preferably used. Moreover, the through-conductive part by which the metal (nickel, gold | metal | money etc.) with good solder wettability was plated on the surface of these materials may be sufficient. By forming such a plating layer, improvement in solderability, reduction in material cost, improvement in oxidation resistance, and the like can be realized.
[0023]
It is preferable that the buffer portion of the stress relaxation layer has a property of being more easily deformed than the through conductive portion. For this reason, it is preferable that it is mainly formed of a material (such as various organic polymers) having a Young's modulus lower than that of the through conductive portion. As such a material, benzoxazole, polyimide, polymethylacrylamide, and other known positive or negative photosensitive resins used for photolithography can be used. This buffer may be conductive or insulating. In order to increase the conductivity of the buffer portion, the conductive filler may be dispersed in a matrix made of an organic polymer or the like. As such a conductive filler, conductive fibers (such as metal fibers), conductive fine particles (such as metal particles), and the like can be used. In order to increase thermal conductivity while maintaining insulation, an insulating filler may be dispersed in the matrix. As such an insulating filler, fine particles of ceramics (typically SiN, AlN, etc.) can be used.
[0024]
  In the stress relaxation layer of the present invention, the through conductive portion that penetrates the stress relaxation layer is separated by the buffer portion. Such a stress relaxation layer has a structure in which penetrating conductive parts are dispersed in a surface-formed (continuous) buffer part.Structure, boardStructure with wall-like through-wall conductive parts and buffer parts stacked alternatelyRagaA mixed structure is exemplified.
[0025]
  As an example of a preferable stress relaxation layer, there is a structure in which a linear (columnar) penetrating conductive portion penetrates a film-shaped (layered) buffer portion. In this structure, the shape of the through conductive portion can be a columnar shape, a prism shape, a truncated cone shape, a truncated pyramid shape, or the like. FIG. 5 shows an example of a stress relaxation layer having a cylindrical penetrating conductive portion, FIG. 6 shows an example of a stress relaxation layer having a square columnar penetrating conductive portion, and FIG. 6 shows an example of a stress relaxation layer having a hexagonal column penetrating conductive portion. As shown in FIG. 5 to 7, reference numeral 40 indicates a stress relaxation layer, reference numeral 45 indicates a through conductive portion, and reference numeral 41 indicates a buffer portion.
  In such a configuration, it is preferable that the columnar through conductive portions are regularly and repeatedly arranged in one direction. 5 and 7, the through-conductive portions 45 are repeatedly arranged in two directions orthogonal to each other and in FIG. 6 in three directions forming an angle of 60 ° with each other.The
[0026]
Another example of a preferable stress relaxation layer is a structure in which plate-like (wall-like) through-conductive portions and buffer portions are alternately stacked in a non-parallel manner with respect to the thickness direction of the stress relaxation layer. As shown in FIG. 8, it is preferable that the through conductive portion 45 and the buffer portion 41 are stacked on the semiconductor element so as to be substantially upright (so that the stacking direction is substantially parallel to the surface of the semiconductor element). The through conductive portion 45 and the buffer portion 41 are repeatedly arranged in the stacking direction. According to the stress relaxation layer having such a configuration, the stress applied in the direction close to the stacking direction (particularly the direction along the stacking direction) can be relaxed (absorbed) well. In addition, since the total connection area of the element side electrode and the through conductive portion can be increased as compared with the linear through conductive portion, good electrical conductivity and thermal conductivity can be realized.
[0027]
Hereinafter, a stress relaxation layer having a structure in which a linear penetrating conductive portion penetrates a film-like buffer portion or a structure in which plate-like penetrating conductive portions and buffer portions are alternately stacked will be mainly described.
The through conductive portion is preferably provided so as to penetrate the stress relaxation layer substantially linearly. The penetrating direction is preferably substantially parallel to the thickness direction of the stress relaxation layer. That is, it is preferable that the through conductive portion is substantially upright on the element side electrode. According to such a stress relaxation layer, the length of the through conductive portion can be shortened as compared with the case where the through conductive portion penetrates the stress relaxation layer obliquely (non-parallel to the thickness direction). And heat conductivity is good.
[0028]
The lower end (end surface on the semiconductor element side) of the through conductive portion is connected to the element side electrode. The shape of the lower end is preferably a shape (basically a planar shape) along the surface shape of the element-side electrode. On the other hand, the upper end of the through-conductive portion is connected to the solder layer. The upper end may be almost the same height as the surface of the buffer portion (solder layer side surface), and the upper end of the through-conductive portion 45 is somewhat raised from the surface of the buffer portion 41 as shown in FIG. Also good. Alternatively, the upper end of the through conductive portion may be somewhat recessed from the surface of the buffer portion as long as the solder can enter when forming the solder layer on the stress relaxation layer.
[0029]
The through conductive portions are preferably provided at substantially equal intervals in at least a portion of the stress relaxation layer formed on the electrode formation region. It is more preferable that the through conductive portions are provided at substantially equal intervals throughout the stress relaxation layer. Thereby, it can suppress that the stress concerning a stress relaxation layer remarkably deviates, and can absorb this stress efficiently.
[0030]
The preferred thickness of the stress relaxation layer is 1 μm or more, more preferably 5 μm or more. If the thickness of the stress relaxation layer is too smaller than 1 μm, the stress relaxation effect is reduced. On the other hand, if the thickness of the stress relaxation layer is too large, the through-conductive portion that penetrates the stress relaxation layer becomes long, so that the conductivity and thermal conductivity are likely to decrease. For this reason, it is usually preferable to set the thickness of the stress relaxation layer to 1000 μm or less. In addition, the preferable length (referring the length along the direction which penetrates a stress relaxation layer) of a penetration conductive part is 1-1000 micrometers, More preferably, it is 5-600 micrometers.
[0031]
In a configuration including a plurality of through-conductive portions, if the joint portion between each through-conductive portion and the solder layer and / or the element side electrode is too large, the stress relaxation effect of the stress relaxation layer including such a through-conductive portion is reduced. Or excessive stress may be applied to each joint. For this reason, it is preferable that the minimum width of each joint part (for example, the diameter when the joint part is circular, and the length of the short side when the joint part is rectangular) is 1 mm or less. Preferably it is 0.6 mm or less. In addition, it is preferable that the minimum width is smaller than the length of the through conductive portion because a good stress relaxation effect can be obtained. On the other hand, if the joint portion between each penetrating conductive portion and the solder layer and / or the element side electrode is too small, the conductivity and thermal conductivity are reduced. For this reason, it is usually preferable that the minimum width of the through conductive portion is 5 μm or more.
[0032]
  In a configuration including a plurality of through-conductive portions, if the number of through-conductive portions provided per unit area of the stress relaxation layer (formation density) is too small, the conductivity and thermal conductivity are reduced, and if too large, the stress relaxation effect is achieved. Becomes smaller. A preferable formation density of the through-conductive portion is in the range of 1 to 40,000 pieces / mm 2, and more preferably in the range of 3 to 20,000 pieces / mm 2.
  In the configuration including one or more through conductive portions, the area ratio of the through conductive portions in the cross section of the stress relaxation layer is preferably 10 to 90%, more preferably 20 to 80%. If this area ratio is too large, the stress relaxation effect is reduced, and if it is too small, the conductivity and thermal conductivity are reduced.The
[0033]
Such a stress relaxation layer includes a step of forming a resin layer on the semiconductor element, a step of patterning the resin layer to expose the element-side electrode, and a step of filling the gap formed in the resin layer with a metal. It can form suitably by the method to include.
The step of forming the resin layer can be performed by applying a resin composition (preferably mainly composed of a photosensitive resin) on the semiconductor element. As a coating method, various conventionally known coating methods such as spin coating, coater coating, and casting can be appropriately employed. In a preferred method of forming the stress relaxation layer, a cured product of the resin layer formed here is used as a buffer portion. The thickness of the buffer portion can be adjusted by the final cured film thickness of the resin layer. For example, in spin coating using a spinner, the coating thickness can be controlled by the viscosity of the applied resin composition, the spinner rotation speed, and the like. When the viscosity of the resin composition is 1000 cP (1 Pa), the thickness of the buffer portion that can be formed when the rotation speed of the spinner is 2600 is, for example, about 5 μm, and can be formed when the rotation speed of the spinner is 1600. The buffer portion has a thickness of about 7 μm, for example.
[0034]
The step of patterning the resin layer is preferably performed by photolithography. This photolithography can be performed according to a conventional method.
Various methods such as electroless plating, electrolytic plating, and sputtering can be used as a method of filling the gap in the resin layer (the through portion that exposes the element-side electrode) with metal. Of these, the electroless plating method is preferably used. Preferable examples of the metal filled by the electroless plating method include nickel, copper, gold, chromium, cobalt, silver and the like. When using an electroless plating method, the amount of metal (plating thickness) filled in the through-hole is adjusted by adjusting the concentration of each component contained in the plating solution, the pH of the plating solution, the bath temperature, etc. It is possible to control the plating time by managing the plating time. The plating thickness is preferably 1 μm or more. If the plating thickness is less than 1 μm, pinholes are likely to occur. Plating is preferably performed until at least the through portion is substantially filled. The plating may proceed until the upper end of the plating rises higher than the resin layer. Further, the top (upper end) of the metal (penetrating conductive portion) filled in each penetrating portion may be connected by further plating.
[0035]
Such a stress relaxation layer forming step may be performed on (usually a plurality of) semiconductor elements formed on the wafer, or may be performed on the semiconductor elements after being divided into individual chips. From the viewpoint of manufacturing efficiency, it is preferable to form a stress relaxation layer on a plurality of semiconductor elements formed on a wafer and then divide the semiconductor elements including the stress relaxation layer into individual chips.
[0036]
The function of the stress relaxation layer will be described with reference to FIGS.
As shown in FIG. 9, in the typical configuration of the present invention, the stress relaxation layer 40 and the solder layer 50 are provided between the semiconductor element 10 and the circuit side electrode 60 in order from the semiconductor element side. The stress relaxation layer 40 includes a plurality of through-conductive portions 45 that connect element-side electrodes (not shown) of the semiconductor element 10 and the solder layer 50, and a buffer portion 41 that separates the through-conductive portions 45 from each other. One surface side 50 a of the solder layer 50 is connected to the stress relaxation layer 40, and the other surface side 50 b is connected to the circuit side electrode 60. By having such a configuration, for example, when the circuit-side electrode 60 is largely thermally expanded as compared with the semiconductor element 10 due to a temperature rise, as shown in FIG. Can be absorbed by. Therefore, compared with the configuration shown in FIG. 12 in which the stress relaxation layer 40 is not formed, according to the configuration shown in FIG. 10, the stress generated between the one side 50a and the other side 50b of the solder layer 50 is reduced. .
[0037]
Electrical connection between the element-side electrode and the solder layer 50 is made by a plurality of through-conductive portions 45. As described above, since the joint portion between the semiconductor element 10 and the solder layer 50 is divided into a plurality of parts, as shown in FIG. The junction area (junction length) between the conductive portion 45 and the semiconductor element electrode 10 (element side electrode) is reduced. Further, each through conductive portion 45 is substantially independent across the buffer portion 41, and there is no interference between the through conductive portions 45. For this reason, even when a compressive displacement or tensile displacement acting in the lateral (in-plane) direction of the device occurs at each location of the semiconductor device, it is mainly pure shear stress that occurs in each through-conductive portion 45. The stress generated between the through-conductive portions 45 is kept relatively small.
Thus, by providing the stress relaxation layer of the present invention, the stress applied to the solder is reduced, so that the life of the solder is extended and the connection reliability between the element side electrode and the circuit side electrode is improved.
[0038]
In addition, in the typical configuration of the present invention, the element side electrode and the circuit side electrode are connected through a plurality of through-conductive portions dispersed on the element side electrode, which is better than the conventional wire bonding connection. High conductivity and thermal conductivity can be realized. Further, since the element side electrode and the circuit side electrode are connected at a plurality of positions of the element side electrode, the current path in the element side electrode can be shortened as compared with the connection by wire bonding. Thereby, electrical resistance can be reduced.
[0039]
The through conductive portions are separated by a buffer portion. This buffer portion can play a role of absorbing the stress applied to the stress relaxation layer and protecting the penetrating conductive portion (shape maintenance, stress relaxation, etc.). Further, as described above, it can also be used as a mold (mask) for forming the through conductive portion. Further, when soldering the through conductive portion and the circuit side electrode, it is possible to prevent the solder from flowing between the through conductive portions.
[0040]
Hereinafter, although the experiment example regarding this invention is demonstrated, it is not intending to limit this invention to what is shown to this Example.
[0041]
(1) Fabrication of semiconductor elements
The semiconductor element (trench IGBT) shown in FIG. 1 was produced by the method described below.
As shown in the figure, a p base layer 13 and an n emitter layer 15 are formed by sequentially performing ion implantation and thermal diffusion on a wafer 11 obtained by epitaxially growing n type layers 4, 6 and 8 on a p type silicon substrate 2. .
[0042]
A plurality of stripe-shaped grooves were formed on the surface of the wafer 11 by RIE (Reactive Ion Etching). The gate oxide film 21 was formed by oxidizing the inside of the groove and the surface of the wafer by a diffusion furnace or the like. Polysilicon was deposited by CVD (Chemical Vapor Deposition) or the like, and polysilicon 23 was buried in the groove. A resist pattern (manufactured by photolithography, the same applies hereinafter) is formed to protect the polysilicon at the necessary locations (in the groove and at the connection portion), and the polysilicon 23 exposed from this resist pattern is formed by RIE, CDE (Chemical Dry Etching). Etc. (etchback). In this way, a gate 25 for switching control was produced.
[0043]
An interlayer insulating film 27 that covers the gate 25 and exposes part of the emitter layer 15 is formed on the wafer surface on which the gate 25 is formed, and then aluminum (Al) is formed by sputtering. A resist pattern covering the Al film at a required location was prepared, and the Al film exposed from the resist pattern was removed by wet etching to prepare an Al wiring. An emitter electrode 31 and a gate electrode (not shown) are formed by the Al wiring. Further, a collector electrode 33 was formed on the back surface of the wafer in the same manner as this Al wiring.
[0044]
(2) Formation of insulating protective layer
As shown in FIG. 2, a silicon oxide film 35 was formed by plasma CVD on the surface of the wafer 11 on which the semiconductor elements were formed by the above (1). This silicon oxide film 35 is an insulating protective layer (passivation film) for protecting the semiconductor element from the outside. Using the resist pattern, a part of the silicon oxide film (insulating protective layer) 35 formed on the Al wiring is removed by RIE to open a window 37, and the Al wiring (emitter electrode 31 and the like) is opened from the window 37. Exposed. Thus, a pad for connecting the Al wiring and the outside was formed.
[0045]
(3) Formation of stress relaxation layer
The stress relaxation layer 40 was formed on the wafer 11 obtained in the above (2).
As shown in FIG. 2, the resin layer 41 was formed on the surface of the wafer 11 on which the silicon oxide film 35 was formed by applying a resin composition containing a photosensitive resin as a main component with a spinner. Polybenzoxazole was used as the photosensitive resin. The resin layer 41 was patterned by photolithography to form a plurality of columnar through holes (gap) 43 exposing a part of the emitter electrode (element side electrode) 31. These through holes 43 are formed in the thickness direction of the resin layer 41. The wafer 11 having the patterned resin layer 41 was etched with nitric acid, and the Al oxide film formed on the surface of the emitter electrode 31 exposed from the through hole 43 was removed. Furthermore, it was immersed in a strong alkali solution containing zinc, and a zincate treatment was performed in which the exposed surface of the emitter electrode 31 was replaced with zinc. The wafer 11 was immersed in a plating bath containing nickel nitrate, lactic acid and sodium hypophosphite to perform electroless nickel plating. As a result, nickel was deposited on the emitter electrode 31 exposed from the through hole 43 to form a cylindrical penetrating conductive portion 45 upright on the emitter electrode 31. As shown in FIG. 2, this electroless nickel plating was performed until the deposited nickel (penetrating conductive portion 45) filled the through-hole 43 and the upper end thereof was higher than the resin layer 41 and raised in a mushroom shape. In addition, in order to suppress the oxidation of the through conductive portion, the exposed surface of nickel deposited by electroless nickel plating may be further plated with gold. For example, the gold plating layer can be formed by a displacement gold plating method using a plating bath mainly composed of potassium gold cyanide or an electroless plating method using a plating bath containing sodium sulfite as an additive component.
[0046]
(4) Connection with circuit side electrode
The wafer obtained by the above (3) was diced and divided into individual chips. A plate-like solder was placed on the stress relaxation layer forming side of each chip, and a lead frame placed on the solder was passed through a furnace in a reducing atmosphere. As a result, a solder layer for connecting the stress relaxation layer and the lead frame was formed. Thereafter, the lower surface of the semiconductor element (the side where the stress relaxation layer is not formed; the collector electrode side) and the lead frame were joined to a circuit board (made of alumina nitride or the like).
In this way, as shown in FIG. 3, the emitter electrode side (the upper side in FIG. 3) of the semiconductor element 10 is connected to the lead frame 60 via the stress relaxation layer 40 and the solder layer 50, and the collector electrode of the semiconductor element 10. An IGBT mounting circuit in which the side (the lower side in FIG. 3) was soldered to the circuit board 70 was obtained. A circuit pattern 72 is formed on the surface of the circuit board 70. The other surface of the semiconductor element 10 is connected to a circuit side electrode formed by the circuit pattern 72 via a solder layer 55. One end of the lead frame 60 is connected to the circuit pattern 72 via the solder layer 57.
[0047]
(5) Application examples
In the above experimental example, polybenzoxazole was used as the photosensitive resin for forming the resin layer 41, but polymethylacrylamide or the like may be used instead of polybenzoxazole. As a mask used for patterning the resin layer 41 by photolithography, a mask obtained by depositing a titanium foil having a thickness of 1 to 5 μm and a gold having a thickness of 1 to 15 μm on a silicon nitride film can be used. A resin layer having a thickness of 100 to 600 μm containing polymethylacrylamide as a main component is formed by a casting method, and the above-described mask is placed thereon, and X-rays (X-ray peaks; 0.2 nm, X Line strength: 10 kj / cm2), Patterning (resolution) was possible if the thickness of the resin layer was about 600 μm or less.
[0048]
In the above experimental example, the through conductive portion is formed by electroless nickel plating, but the through conductive portion may be formed by electroless copper plating. This electroless copper plating can be performed, for example, by immersing a patterned wafer in a plating bath containing copper sulfate, Rochelle salt, formaldehyde and the like. Thereafter, electroless nickel plating and / or electroless gold plating may be performed for the purpose of preventing copper oxidation and improving solderability.
[0049]
In the above experimental example, the stress relaxation layer is provided only on the upper surface side (the side opposite to the substrate mounting side) of the semiconductor element, but the stress relaxation layer may be provided on the lower surface side (substrate mounting side) of the semiconductor element. A stress relaxation layer may be provided above and below.
FIG. 4 shows an example of a semiconductor element mounting circuit in which stress relaxation layers are provided above and below the semiconductor element. As shown in the figure, a plurality (two are shown here) of semiconductor elements 10 are connected by a conductive bar 62 (circuit side electrode). The connection between the conductive bar 62 and the electrode formed on the upper surface of each semiconductor element 10 is made through the stress relaxation layer 40 and the solder layer 50 as in the above embodiment. The electrode formed on the lower surface of the semiconductor element 10 is also a circuit side electrode formed on the surface of the circuit board 70 by a circuit pattern (not shown) via the stress relaxation layer 48 and the solder layer 55 provided on the lower surface. It is connected to the. In such a configuration, the stress F generated between the conductive bar 62 and each semiconductor element 10 due to the difference in thermal expansion coefficient between the semiconductor element 10 and the conductive bar 62.1In addition to the stress F that tends to displace each of the semiconductor elements 10 relative to the circuit board 70 due to the difference in thermal expansion coefficient between the circuit board 70 and the conductive bar 62.2Can occur. According to the configuration shown in FIG. 4, the stress F is reduced by the stress relaxation layers 40 and 48 provided above and below the semiconductor element 10.2Can be absorbed. Thereby, the stress produced between the semiconductor element 10 and the solder layers 50 and 55 can be reduced. This stress F2Can be relaxed by either the upper stress relaxation layer 40 or the lower stress relaxation layer 48.
[0050]
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to an experimental example of the present invention.
2 is a cross-sectional view in which a stress relaxation layer is formed on the semiconductor element shown in FIG.
FIG. 3 is a cross-sectional view showing a semiconductor element mounting circuit according to an experimental example of the present invention.
FIG. 4 is a cross-sectional view showing a semiconductor element mounting circuit according to an application example of the present invention.
FIG. 5 is a perspective view schematically showing an example of a stress relaxation layer including a columnar through-conductive portion.
FIG. 6 is a perspective view schematically showing an example of a stress relaxation layer including a quadrangular columnar through-conductive portion.
FIG. 7 is a perspective view schematically showing an example of a stress relaxation layer including a hexagonal columnar through-conductive portion.
FIG. 8 is a perspective view schematically showing an example of a stress relaxation layer having a structure in which a plate-like penetrating conductive portion and a buffer portion are laminated.
FIG. 9 is a schematic cross-sectional view showing a structure in which a semiconductor element and a circuit side electrode are connected using a stress relaxation layer.
10 is a schematic cross-sectional view showing a state of the connection structure shown in FIG.
FIG. 11 is a schematic cross-sectional view showing a conventional connection structure between a semiconductor element and a circuit side electrode.
12 is a schematic cross-sectional view showing a state of the connection structure shown in FIG.
[Explanation of symbols]
10 Semiconductor elements
11 Wafer (semiconductor element)
31 Emitter electrode (element side electrode)
33 Collector electrode (element side electrode)
35 Silicon oxide film (insulating protective layer)
40, 48 Stress relaxation layer
41 Resin layer (buffer part)
43 Through hole (penetrating part, gap)
45 Penetration conductive part
50, 55, 57 Solder layer
60 Lead frame (circuit side electrode)
62 Conductive bar (circuit side electrode)
70 Circuit board
72 Circuit pattern (circuit side electrode)

Claims (8)

素子側電極が形成された半導体素子と、
その素子側電極の形成領域を含む半導体素子上に形成された応力緩和層と、
その応力緩和層上に形成された半田層と、
その半田層上において少なくとも半導体素子の一端を越えて半導体素子の周辺にまで延びているとともに、半田層上に位置する範囲で半田層に固定されている回路側電極とを備えており、
その応力緩和層は、複数個の導電部と緩衝部とを備えており、
各々の導電部が、素子側電極と半田層の間を伸びているとともに素子側電極と半田層とを電気的に接続しており、
緩衝部が、隣接する導電部間に介在して導電部同士を相互に隔てていることを特徴とする半導体素子実装回路。A semiconductor element having an element-side electrode formed thereon;
A stress relaxation layer formed on the semiconductor element including the element-side electrode formation region;
A solder layer formed on the stress relaxation layer;
On the solder layer, it extends to at least the periphery of the semiconductor element beyond one end of the semiconductor element, and includes a circuit side electrode fixed to the solder layer in a range located on the solder layer,
The stress relaxation layer includes a plurality of conductive portions and buffer portions,
Each conductive part extends between the element side electrode and the solder layer and electrically connects the element side electrode and the solder layer,
Buffer portion, the semiconductor element mounting circuit, characterized by separating the conductive portions from one another interposed between the conductive parts you neighbor. 前記緩衝部は前記導電部よりもヤング率の低い材料を主体として形成されている請求項１に記載の半導体素子実装回路。The buffers have a semiconductor element mounting circuit according to claim 1 which is formed a material having a lower Young's modulus than prior Kishirube collector portion mainly. 前記緩衝部は感光性樹脂により形成されている請求項１または２に記載の半導体素子実装回路。  The semiconductor element mounting circuit according to claim 1, wherein the buffer portion is formed of a photosensitive resin. 前記導電部は素子側電極と半田層の間を直線状に伸びている請求項１，２または３に記載の半導体素子実装回路。The semiconductor element mounting circuit of the front Kishirube conductive part according to claim 1, 2 or 3 extending between the element-side electrode and the solder layer in a straight line. 前記半導体素子の表面には前記素子側電極を露出させる絶縁保護層が設けられている請求項１から４のいずれか一項に記載に半導体素子実装回路。  5. The semiconductor element mounting circuit according to claim 1, wherein an insulating protective layer that exposes the element-side electrode is provided on a surface of the semiconductor element. 6. 前記緩衝部に、絶縁性を保持したまま熱伝導性を高める絶縁性充填材が分散して配置されていることを特徴とする請求項１から５のいずれか一項に記載の半導体素子実装回路。  6. The semiconductor element mounting circuit according to claim 1, wherein an insulating filler that increases thermal conductivity is dispersed and disposed in the buffer portion while maintaining insulation. 6. . 前記絶縁性充填材がセラミックスの微粒子であることを特徴とする請求項６に記載の半導体素子実装回路。  The semiconductor element mounting circuit according to claim 6, wherein the insulating filler is ceramic fine particles. 前記緩衝部に、導電性を高める導電性充填材が分散して配置されていることを特徴とする請求項１から５のいずれか一項に記載の半導体素子実装回路。  6. The semiconductor element mounting circuit according to claim 1, wherein a conductive filler for increasing conductivity is dispersedly disposed in the buffer portion.
JP2002033048A 2002-02-08 2002-02-08 Semiconductor device mounting circuit Expired - Fee Related JP4093765B2 (en)

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