JP4090660B2

JP4090660B2 - Current-voltage conversion circuit

Info

Publication number: JP4090660B2
Application number: JP2000056399A
Authority: JP
Inventors: 弘道原川; 匡市川
Original assignee: Hoya Corp
Current assignee: Hoya Corp
Priority date: 1999-12-24
Filing date: 2000-03-01
Publication date: 2008-05-28
Anticipated expiration: 2020-03-01
Also published as: JP2001245469A

Description

【０００１】
【発明の属する技術分野】
本発明は、電流を抵抗による電圧降下から検出して電圧として出力する電流―電圧変換回路およびそれを利用した電流モードＤＣ−ＤＣコンバータに関する。
【０００２】
【従来の技術】
パーソナルコンピュータの電源回路などとして使用される従来の降圧型電流モードＤＣ−ＤＣコンバータの代表的な回路図を図８に示す。この図において、１１は電源電圧Ｖｃｃをオンオフするスイッチング素子としてのＰＭＯＳトランジスタであり、ダイオード１２、インダクタ１３およびキャパシタ１４とともに電圧発生部１６を構成する。ダイオード１２は、アノードが接地され、カソードが前記ＰＭＯＳトランジスタ１１のドレインに接続される。インダクタ１３は一端が前記ＰＭＯＳトランジスタ１１のドレインに接続され、他端は出力端子１５に接続される。キャパシタ１４は出力端子１５と接地間に接続される。
【０００３】
ＰＭＯＳトランジスタ１１のソースと電源電圧Ｖｃｃ間には、ＰＭＯＳトランジスタ１１を介して流れる出力電流を電圧降下で検出する抵抗１７が接続され、この抵抗１７の前記ソース側の一端と反対側の他端（電源電圧Ｖｃｃ）は増幅器１８のプラス入力、マイナス入力にそれぞれ接続される。そして、この増幅器１８の出力は加算器１９の第１入力に接続されており、この加算器１９の第２入力には鋸歯状波電圧発生回路２０から鋸歯状波電圧が供給される。このように接続された抵抗１７、増幅器１８、加算器１９および鋸歯状波電圧発生回路２０は、ＤＣ−ＤＣコンバータの出力電流を抵抗による電圧降下から検出して電圧として出力し、かつその電圧に鋸歯状波電圧を加算する電流―電圧変換回路２１を構成する。
【０００４】
出力端子１５の出力電圧は抵抗２２，２３で分圧されており、分圧点の電圧は誤差増幅器２４のマイナス入力に供給される。この誤差増幅器２４のプラス入力には基準電圧２５が供給される。誤差増幅器２４の出力はＰＷＭ（パルス幅変調）用の比較器２６のマイナス入力に供給され、この比較器２６のプラス入力には前記加算器１９の出力が供給される。さらに、比較器２６の出力はフリップフロップ回路２７のリセット入力に供給されており、このフリップフロップ回路２７のＱ出力は前記ＰＭＯＳトランジスタ１１のゲートに接続される。フリップフロップ回路２７のセット入力には発振器２８の出力が供給されている。
【０００５】
このように構成されたＤＣ−ＤＣコンバータにおいては、抵抗１７の両端の電圧差（抵抗１７による電圧降下）をオペアンプ型の増幅器１８で検知・増幅することにより、出力電流を検出して電圧として出力しており、その出力電圧に加算器１９で鋸歯状波電圧発生回路２０からの鋸歯状波電圧が加算される。この加算器１９の出力電圧は、前記出力電流に応じて変化する。また、ＤＣ−ＤＣコンバータの出力端子１５の出力電圧が抵抗２２，２３で分圧されており、その分圧電圧と基準電圧２５が誤差増幅器２４で比較されることにより、出力端子１５の出力電圧の誤差に応じた電圧が誤差増幅器２４の出力に得られる。そして、この誤差増幅器２４の出力電圧と加算器１９の出力電圧が比較器２６で比較されることにより、ＤＣ−ＤＣコンバータの出力電圧と出力電流により制御されたＰＷＭ信号が比較器２６の出力に得られ、このＰＷＭ信号でフリップフロップ回路２７を介してＰＭＯＳトランジスタ１１をスイッチング制御することにより、電源電圧Ｖｃｃより低い一定の出力直流電圧を電圧発生部１６で発生させて出力端子１５に得ることができる。
【０００６】
【発明が解決しようとする課題】
しかしながら、上記のような従来のＤＣ−ＤＣコンバータでは、出力電流を検出し電圧として出力する方法として、抵抗１７の両端の電圧差をオペアンプ型の増幅器１８で検知・増幅しているので、回路構成が複雑になり、ＩＣ化において種々の弊害が発生するという問題点があった。すなわち、従来の図８の回路では、増幅器１８のマイナス入力は電源電圧Ｖｃｃ固定、プラス入力は、抵抗１７による電圧降下が生じているときでも電源電圧からその電圧降下分の高々数１００ｍＶ程度下がった電圧であるため、両入力とも入力電圧はほぼ回路の電源電圧Ｖｃｃである。したがって、この増幅器１８に求められる機能として、同相入力電圧範囲が電源電圧を含んでいることが挙げられる。しかしながら、増幅器１８として使用される通常のオペアンプはこの機能を有しておらず、この機能を持たせるには複雑な回路構成が必要となる。そして、これは、このＤＣ−ＤＣコンバータをＩＣ化する場合にチップ内の素子数の増加を招き、これは、チップサイズの増加あるいは消費電流の増加につながる。
【０００７】
本発明は上記の点に鑑みなされたもので、回路構成が簡単になり、ＣＭＯＳプロセスでのＩＣ化に好適し、しかも電源電圧付近（降圧型ＤＣ−ＤＣコンバータの場合）あるいは接地電圧付近（昇圧型ＤＣ−ＤＣコンバータの場合）の電圧でも問題なく動作し、微小な電圧差でも精度よく検知することができる電流―電圧変換回路およびそれを利用したＤＣ−ＤＣコンバータを提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明の電流―電圧変換回路は、電流を抵抗による電圧降下から検出して電圧として出力する電流―電圧変換回路であって、前記電流経路に挿入された検出用抵抗と、この検出用抵抗両端間の電圧差を電流に変換する電圧―電流変換部と、この電圧―電流変換部の出力電流を電圧に変換する電流―電圧変換部とを具備することを特徴とする。
【０００９】
本発明のＤＣ−ＤＣコンバータは、出力電流を抵抗による電圧降下から検出して電圧として出力し、かつその電圧に鋸歯状波電圧を加算する電流―電圧変換回路を有し、この電流―電圧変換回路出力と出力電圧誤差電圧からＰＷＭ信号を発生させ、このＰＷＭ信号でスイッチング素子をスイッチング制御するようにしたＤＣ−ＤＣコンバータであって、前記電流―電圧変換回路は、前記スイッチング素子と直列に接続された出力電流検出用抵抗と、この検出用抵抗両端間の電圧差を電流に変換する電圧―電流変換部と、この電圧―電流変換部の出力電流を電圧に変換し、同時に鋸歯状波電圧を加算する電流―電圧変換部とを具備することを特徴とする。
【００１０】
上記の記載から明らかなように本発明では、従来の抵抗両端の電圧差をオペアンプ型の増幅器で検知・増幅する代わりに、この電圧差を一度電流に変換し、その後電圧に再変換する手法をとる。この手法において、電圧―電流変換部は、検知する電圧が電源電圧付近（降圧型ＤＣ−ＤＣコンバータの場合）あるいは接地電圧付近（昇圧型ＤＣ−ＤＣコンバータの場合）でも特に問題はなく、微小な電圧差でも精度よく検知することができる。さらに、回路構成は、特殊な機能が不要であるからごく簡単な構成とし得る。また、再度電圧に戻す電流―電圧変換部には一般的なオペアンプ（増幅器）を使用することができ、このオペアンプのバイアス電圧として鋸歯状波電圧を供給することにより、鋸歯状波電圧の加算も同時に実現できる。
【００１１】
【発明の実施の形態】
次に添付図面を参照して本発明の実施の形態を詳細に説明する。図１は本発明の実施の形態としての降圧型電流モードＤＣ−ＤＣコンバータを示す回路図である。このＤＣ−ＤＣコンバータは、電流―電圧変換回路３１の構成が図８の従来例と相違する。そこで、以下の説明では電流―電圧変換回路３１部分についてのみ詳述することとし、その他の同一部分は図８の各部と同一符号を付すことによりその説明を省略する。
【００１２】
電流―電圧変換回路３１は、検出用抵抗３２と、電圧―電流変換部３３と、電流―電圧変換部としての増幅器（オペアンプ）３４と、鋸歯状波電圧発生回路３５からなる。検出用抵抗３２は、スイッチング素子としてのＰＭＯＳトランジスタ１１のソースと電源電圧Ｖｃｃ間に接続される。この検出用抵抗３２の前記ソース側の一端、および反対側の他端（電源電圧Ｖｃｃ）は、電圧―電流変換部３３の第１、第２入力にそれぞれ接続される。この電圧―電流変換部３３の出力は増幅器３４のマイナス入力に接続され、この増幅器３４のプラス入力には鋸歯状波電圧発生回路３５の出力が接続される。増幅器３４の出力とマイナス入力間には帰還用の抵抗３６が接続されており、増幅器３４の出力が比較器２６のプラス入力に接続される。
【００１３】
このように構成された電流―電圧変換回路３１においては、抵抗３２両端の電圧差が電圧―電流変換部３３で電流に変換され、さらにその電流が増幅器３４で電圧に再変換されるもので、これにより従来の電流―電圧変換回路と同様に、出力電流を抵抗による電圧降下から検出して電圧として出力することができる。しかも、増幅器３４で電流を電圧に再変換する際、増幅器３４のプラス入力に鋸歯状波電圧発生回路３５から鋸歯状波電圧がバイアス電圧として供給されることにより、増幅器３４の出力電圧に鋸歯状波電圧を加算することができる。したがって、増幅器３４の出力電圧を誤差増幅器２４の出力電圧と比較することにより、ＰＷＭ信号を発生させることができる。
【００１４】
図２は、上記電流―電圧変換回路３１（特に電圧―電流変換部３３）の第１の具体的回路図を示す。電圧―電流変換部３３は、定電流源４１、抵抗４２，４３およびＭＯＳトランジスタ４４〜５４で構成される。ＭＯＳトランジスタ４４〜５４のうち、ＭＯＳトランジスタ４４，４５はＰＭＯＳトランジスタ、ＭＯＳトランジスタ４６〜５４はＮＭＯＳトランジスタである。電源電圧Ｖｃｃと接地間には、定電流源４１、ＮＭＯＳトランジスタ４６およびＮＭＯＳトランジスタ４７がこれらの順で直列接続される。ＮＭＯＳトランジスタ４６およびＮＭＯＳトランジスタ４７は、それぞれドレインとゲートが共通接続される。この直列回路には、定電流源４１によって定電流Ｉｒが流れる。検出用抵抗３２の一端（ＰＭＯＳトランジスタ１１のソース側）には抵抗４２を介してＰＭＯＳトランジスタ４４のソースが接続される。このＰＭＯＳトランジスタ４４はゲートがドレインに共通接続される。このＰＭＯＳトランジスタ４４のドレインと接地間にはＮＭＯＳトランジスタ４８およびＮＭＯＳトランジスタ４９がこれらの順で直列接続される。検出用抵抗３２の他端（電源電圧Ｖｃｃ）には抵抗４３を介してＰＭＯＳトランジスタ４５のソースが接続される。このＰＭＯＳトランジスタ４５のドレインと接地間には、ＮＭＯＳトランジスタ５０およびＮＭＯＳトランジスタ５１がこれらの順で直列接続される。ＮＭＯＳトランジスタ５０のゲートおよび前記ＮＭＯＳトランジスタ４８のゲートは前記ＮＭＯＳトランジスタ４６のゲートに共通接続される。ＮＭＯＳトランジスタ５１のゲートおよび前記ＮＭＯＳトランジスタ４９のゲートは前記ＮＭＯＳトランジスタ４７のゲートに共通接続される。前記ＰＭＯＳトランジスタ４５のソースにはＮＭＯＳトランジスタ５２のドレインが接続され、このＮＭＯＳトランジスタ５２のゲートはＰＭＯＳトランジスタ４５のドレインに接続される。ＮＭＯＳトランジスタ５２のソースにはＮＭＯＳトランジスタ５３のドレインが接続される。このＮＭＯＳトランジスタ５３は、ドレインとゲートが共通接続され、かつソースが接地される。ＮＭＯＳトランジスタ５３のゲートにはＮＭＯＳトランジスタ５４のゲートが接続される。このＮＭＯＳトランジスタ５４はソースが接地され、ドレインが電流―電圧変換部としての増幅器（オペアンプ）３４のマイナス入力に接続される。この増幅器３４のプラス入力には図１と同様に鋸歯状波電圧発生回路３５の出力が接続される。さらに、増幅器３４の出力とマイナス入力間には抵抗３６が接続される。なお、ＭＯＳトランジスタ４４〜５４のバックゲート端子は、ＰＭＯＳトランジスタ４４，４５についてはすべてソース端子に、ＮＭＯＳトランジスタ４６〜５４についてはすべて接地に接続される。
【００１５】
上記回路構成においてＮＭＯＳトランジスタ４７，４９，５１はカレントミラー回路を構成し、これらの素子のチャネル長、チャネル幅比（Ｗ／Ｌ）を等しく設定すれば、ＮＭＯＳトランジスタ４９，５１のドレイン電流はほぼ定電流Ｉｒに等しい。ＮＭＯＳトランジスタ４６，４８，５０はＮＭＯＳトランジスタ４９，５１のドレイン電圧を等しく固定し、チャネル長変調効果によるドレイン電流のバラツキを防ぐ。スイッチング素子としてのＰＭＯＳトランジスタ１１のソースの電圧をＶｓとすると、検出用抵抗３２（抵抗値Ｒｓ）を流れる全電流のうちＰＭＯＳトランジスタ１１を流れる電流分Ｉｏは、抵抗４２（抵抗値Ｒ₁）へ流れる電流Ｉｒに比べて極めて大きいので、
【数１】

となる。
【００１６】
また、ＰＭＯＳトランジスタ４４，４５のソースの電圧は、これらＰＭＯＳトランジスタ４４，４５のＷ／Ｌを等しく設定することで等しくなり、これをＶｓ₇とすると、
【数２】

となる。したがって、ＮＭＯＳトランジスタ５２のドレインへ流れる電流Ｉ₉は、抵抗４２，４３の抵抗値Ｒ₁，Ｒ₂を等しく設定すれば、
【数３】

となり、出力電流Ｉｏ（抵抗３２の端子間電圧）に比例する電流が取出せる。ＮＭＯＳトランジスタ５２は負帰還ループ（動作は後述する）を構成しており、電流Ｉ₉を精度よく取出すことができる。したがって、ＮＭＯＳトランジスタ５３とＮＭＯＳトランジスタ５４のＷ／Ｌを等しく設定すれば、ＮＭＯＳトランジスタ５４のドレイン電流も電流Ｉ₉と等しくなり、出力電流Ｉｏに比例した電流となる。そして、このＮＭＯＳトランジスタ５４のドレイン電流（電流Ｉ₉）が増幅器３４のマイナス入力から引き出され、かつ増幅器３４のプラス入力に鋸歯状波電圧（Ｖｒｇ）が印加されることにより、増幅器３４の出力電圧Ｖａｏは
【数４】

（ただし、Ｒ₃は抵抗３６の抵抗値）となる。すなわち、出力電圧Ｖａｏとして、出力電流Ｉｏに比例し、かつ鋸歯状波電圧Ｖｒｇが加算された電圧を得ることができる。ここで、ＲｓＩｏの増幅率はＲ₃／Ｒ₂の抵抗比で決まる。
【００１７】
電流―電圧変換回路３１の具体的回路は以上であるが、この具体例において、電圧―電流変換部３３の動作を端的に述べれば次の通りである。すなわち、ＰＭＯＳトランジスタ４４，４５のソース電圧を同一、ＰＭＯＳトランジスタ４４，４５のドレイン電流を一定としておけば、抵抗３２の端子間電圧が変化し、ＰＭＯＳトランジスタ４４，４５のソース電圧が変化したとき、ＰＭＯＳトランジスタ４４，４５のドレイン電流は一定であるから、前記変化に比例した電流が電流Ｉ₉として取出せるというものである。
【００１８】
また、この電圧―電流変換部３３においてＮＭＯＳトランジスタ５２は負帰還ループを構成しているが、この負帰還ループの動作は次の通りである。すなわち、何らかの原因でＰＭＯＳトランジスタ４５のドレイン電流が増加し、その結果として電流Ｉ₉が減少し、電流Ｉ₉と抵抗３２の端子間電圧（出力電流Ｉｏ）との比例関係が崩れるようになると、前記ＰＭＯＳトランジスタ４５のドレイン電流が増大することにより、ＮＭＯＳトランジスタ５２のゲート電圧が上昇し、その結果としてＮＭＯＳトランジスタ５２の導通度が増して電流Ｉ₉が増大するようになるので、電流Ｉ₉と抵抗３２の端子間電圧との比例関係が回復し維持される。これとは逆に、ＰＭＯＳトランジスタ４５のドレイン電流が減少し、電流Ｉ₉が増大した場合は、上記とは逆の作用で電流Ｉ₉が減少し、やはり電流Ｉ₉と抵抗３２の端子間電圧との比例関係が維持される。
【００１９】
そして、以上のようにして上記電圧―電流変換部３３によれば、電源電圧付近の電圧でも問題なく、かつ微小な抵抗３２両端の電圧差でも精度よく検知して電流に変換できる。さらに、回路構成は上記のように簡単であり、ＣＭＯＳプロセスでのＩＣ化に好適する。さらに、増幅器３４は、電圧―電流変換部３３からの電流を電圧に変換すると同時に、その電圧に鋸歯状波電圧を加算できる。
【００２０】
図３は電流―電圧変換回路３１の第２の具体的回路図で、図２の電圧―電流変換部３３を簡略化した回路例である。この回路では、図２のＮＭＯＳトランジスタ４６，４８，５０，５３が省略されている。したがって、電源電圧Ｖｃｃと接地間には定電流源４１とＮＭＯＳトランジスタ４７が直列接続される。さらに、ＰＭＯＳトランジスタ４４のドレインと接地間にはＮＭＯＳトランジスタ４９のみが、またＰＭＯＳトランジスタ４５のドレインと接地間にはＮＭＯＳトランジスタ５１のみが接続される。さらにＰＭＯＳトランジスタ４５のソースと接地間にＮＭＯＳトランジスタ５２が接続され、このＮＭＯＳトランジスタ５２のゲートにＮＭＯＳトランジスタ５４のゲートが接続される。
【００２１】
この図３の回路は、カレントミラーを構成するＮＭＯＳトランジスタ４９，５１のドレイン電流に若干の差が生じるため精度的には図２の回路より劣るが、ＭＯＳトランジスタを４つ削減でき、チップ占有面積の点からは有利である。
【００２２】
図４は、電流―電圧変換回路３１（特に電圧―電流変換部３３）の第３の具体的回路図を示す。この回路は、図２の回路を昇圧型ＤＣ−ＤＣコンバータに適用した場合である。昇圧型の場合は、ＭＯＳトランジスタ４４〜５４のうち、ＭＯＳトランジスタ４４，４５がＮＭＯＳトランジスタ、ＭＯＳトランジスタ４６〜５４がＰＭＯＳトランジスタである。また、電源電圧Ｖｃｃと接地電圧が図２の場合と逆になっている。したがって、検出用抵抗３２の他端、定電流源４１の一端（ＰＭＯＳトランジスタ４６，４７と反対側）、抵抗４３の一端（ＮＭＯＳトランジスタ４５と反対側）は接地電圧に接続され、ＰＭＯＳトランジスタ４７、４９、５１、５３、５４のソースは電源電圧Ｖｃｃに接続される。さらに、昇圧型の場合は、ＰＭＯＳトランジスタ５４のドレイン電流と同一電流を増幅器３４のマイナス入力から接地に引き出すためにＮＭＯＳトランジスタ５５，５６が追加される。ＮＭＯＳトランジスタ５５は、ソースが接地され、ドレインとゲートは共通接続され、ドレインはＮＭＯＳトランジスタ５４のドレインに接続される。ＮＭＯＳトランジスタ５６は、ソースが接地され、ゲートがＮＭＯＳトランジスタ５５のゲートに接続され、ドレインが増幅器３４のマイナス入力に接続される。また、昇圧型の場合は、電圧発生部１６のスイッチング素子としてのＭＯＳトランジスタ１１にＮＭＯＳトランジスタが使用されるとともに、電圧発生部１６中のインダクタ１３とダイオード１２の接続のし方が図２と異なる。インダクタ１３は、ＮＭＯＳトランジスタ１１のドレインと電源電圧Ｖｃｃ間に接続され、ダイオード１２はＮＭＯＳトランジスタ１１のドレインと出力端子１５間に接続される。
【００２３】
図５は電流―電圧変換回路３１の第４の具体的回路図で、図４の昇圧型で、図３と同様に電圧―電流変換部３３の回路を簡略化した場合である。この回路では、図４のＰＭＯＳトランジスタ４６，４８，５０，５３が省略されている。したがって、電源電圧Ｖｃｃと接地間にはＰＭＯＳトランジスタ４７と定電流源４１がこの順で直列接続される。さらに、ＮＭＯＳトランジスタ４４のドレインと電源電圧Ｖｃｃ間にはＰＭＯＳトランジスタ４９のみが、またＮＭＯＳトランジスタ４５のドレインと接地間にはＰＭＯＳトランジスタ５１のみが接続される。さらにＮＭＯＳトランジスタ４５のソースと電源電圧Ｖｃｃ間にＰＭＯＳトランジスタ５２が接続され、このＰＭＯＳトランジスタ５２のゲートにＰＭＯＳトランジスタ５４のゲートが接続される。
【００２４】
図４および図５の昇圧型の場合も、電流―電圧変換回路３１は図２および図３の降圧型の場合と同様に動作し、同様な効果を得ることができる。
【００２５】
図６は、電流―電圧変換回路３１の第５の具体的回路図で、図２の降圧型で、電圧―電流変換部３３の回路を一部変更した場合である。この回路では、ＭＯＳトランジスタ５２としてＰＭＯＳトランジスタが使用されており、このＰＭＯＳトランジスタ５２のソースがＮＭＯＳトランジスタ４５のソースに接続される。また、このＰＭＯＳトランジスタ５２のドレインにＮＭＯＳトランジスタ５３のドレインとゲートが接続される。また、ＰＭＯＳトランジスタ５２のゲートが、ＰＭＯＳトランジスタ４５のドレインからＰＭＯＳトランジスタ４４のドレインに接続変更されるとともに、ＰＭＯＳトランジスタ４４、４５のゲートが、ＰＭＯＳトランジスタ４４のドレインからＰＭＯＳトランジスタ４５のドレインに接続変更される。さらに、図２で示されるＮＭＯＳトランジスタ４６，４８，５０が省略される。したがって、電源電圧Ｖｃｃと接地間には定電流源４１とＮＭＯＳトランジスタ４７が直列接続される。さらに、ＰＭＯＳトランジスタ４４のドレインと接地間にはＮＭＯＳトランジスタ４９のみが、またＰＭＯＳトランジスタ４５のドレインと接地間にはＮＭＯＳトランジスタ５１のみが接続される。
【００２６】
このような図６の構成でも図２と同様に動作し、ＰＭＯＳトランジスタ５２による負帰還も作用する。すなわち、ＰＭＯＳトランジスタ４５のドレイン電流が増加して電流Ｉ₉が減少すると、ＰＭＯＳトランジスタ４４のドレイン電流が減少し、その結果、ＰＭＯＳトランジスタ５２のゲート電圧が低下し、ＰＭＯＳトランジスタ５２の導通度が増して電流Ｉ₉が増大するので、電流Ｉ₉と抵抗３２の端子間電圧との比例関係が維持される。これとは逆に、ＰＭＯＳトランジスタ４５のドレイン電流が減少して電流Ｉ₉が増大する場合は、上記とは逆の作用で電流Ｉ₉が減少し、やはり電流Ｉ₉と抵抗３２の端子間電圧との比例関係が維持される。ただし、図６の負帰還ではループ利得が図２に比較して低いため、精度的には図２より若干劣る。
【００２７】
しかし、図６の回路は、図２に比較すると電源電圧Ｖｃｃを低くすることができるという効果がある。すなわち、図２の回路では、ＭＯＳトランジスタ５２のゲート電圧は、ＭＯＳトランジスタ５３のゲート・ソース間電圧にＭＯＳトランジスタ５２のゲート・ソース間電圧を加えた電圧（以下第１電圧という）になる。これに対して、図６の回路では、ＭＯＳトランジスタ５２のゲート電圧は、抵抗４３の電圧降下にＭＯＳトランジスタ５２のゲート・ソース間電圧を加えた電圧（以下第2電圧という）になる。電源電圧Ｖｃｃは、これら第１、第2電圧より高くする必要があるが、図６の第2電圧は図２の第１電圧より低くなるので、対応して電源電圧Ｖｃｃも図６の方が図２より低くすることができる。
【００２８】
図７は、電流―電圧変換回路３１の第６の具体的回路図で、図４の昇圧型で、電圧―電流変換部３３の回路を図６と同様に一部変更した場合である。すなわち、この回路では、ＭＯＳトランジスタ５２としてＮＭＯＳトランジスタが使用され、このＮＭＯＳトランジスタ５２のソースがＮＭＯＳトランジスタ４５のソースに接続され、ＮＭＯＳトランジスタ５２のドレインにＰＭＯＳトランジスタ５３のドレインとゲートが接続される。また、前記ＮＭＯＳトランジスタ５２のゲートが、ＮＭＯＳトランジスタ４５のドレインからＮＭＯＳトランジスタ４４のドレインに接続変更されるとともに、ＮＭＯＳトランジスタ４４、４５のゲートが、ＮＭＯＳトランジスタ４４のドレインからＮＭＯＳトランジスタ４５のドレインに接続変更される。さらに、図４で示されるＰＭＯＳトランジスタ４６，４８，５０が省略される。したがって、電源電圧Ｖｃｃと接地間にはＰＭＯＳトランジスタ４７と定電流源４１がこの順で直列接続される。さらに、ＮＭＯＳトランジスタ４４のドレインと電源電圧Ｖｃｃ間にはＰＭＯＳトランジスタ４９のみが、またＮＭＯＳトランジスタ４５のドレインと接地間にはＰＭＯＳトランジスタ５１のみが接続される。このような図７の回路も図６と同様に動作し、同様な効果を得ることができる。
【００２９】
【発明の効果】
以上詳細に説明したように本発明の電流―電圧変換回路およびそれを利用したＤＣ−ＤＣコンバータによれば、抵抗による電圧降下から、電源電圧付近または接地電圧付近の電圧でも問題なく、かつ微小な電圧差でも精度よく検知して、電流（出力電流）を電圧として出力することができ、回路構成も簡単でＣＭＯＳプロセスでのＩＣ化に好適する。
【図面の簡単な説明】
【図１】本発明の実施の形態としての降圧型電流モードＤＣ−ＤＣコンバータを示す回路図。
【図２】上記ＤＣ−ＤＣコンバータにおける電流―電圧変換回路の第１の具体的回路を示す回路図。
【図３】上記ＤＣ−ＤＣコンバータにおける電流―電圧変換回路の第２の具体的回路を示す回路図。
【図４】本発明に係る電流―電圧変換回路の第３の具体的回路を示す回路図。
【図５】本発明に係る電流―電圧変換回路の第４の具体的回路を示す回路図。
【図６】本発明に係る電流―電圧変換回路の第５の具体的回路を示す回路図。
【図７】本発明に係る電流―電圧変換回路の第６の具体的回路を示す回路図。
【図８】従来の降圧型電流モードＤＣ−ＤＣコンバータを示す回路図。
【符号の説明】
３１電流―電圧変換回路
３２検出用抵抗
３３電圧―電流変換部
３４増幅器（電流―電圧変換部）
３５鋸歯状波電圧発生回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a current-voltage conversion circuit that detects a current from a voltage drop caused by a resistor and outputs the current as a voltage, and a current mode DC-DC converter using the same.
[0002]
[Prior art]
FIG. 8 shows a typical circuit diagram of a conventional step-down current mode DC-DC converter used as a power supply circuit for a personal computer. In this figure, 11 is a PMOS transistor as a switching element for turning on and off the power supply voltage Vcc, and constitutes a voltage generator 16 together with a diode 12, an inductor 13 and a capacitor. The diode 12 has an anode grounded and a cathode connected to the drain of the PMOS transistor 11. The inductor 13 has one end connected to the drain of the PMOS transistor 11 and the other end connected to the output terminal 15. The capacitor 14 is connected between the output terminal 15 and the ground.
[0003]
A resistor 17 is connected between the source of the PMOS transistor 11 and the power supply voltage Vcc to detect an output current flowing through the PMOS transistor 11 by a voltage drop. The other end of the resistor 17 opposite to the one end on the source side ( The power supply voltage Vcc) is connected to the plus input and minus input of the amplifier 18, respectively. The output of the amplifier 18 is connected to the first input of the adder 19, and the sawtooth wave voltage is supplied from the sawtooth wave voltage generation circuit 20 to the second input of the adder 19. The resistor 17, the amplifier 18, the adder 19 and the sawtooth voltage generation circuit 20 connected in this way detect the output current of the DC-DC converter from the voltage drop due to the resistor and output it as a voltage. A current-voltage conversion circuit 21 for adding the sawtooth voltage is configured.
[0004]
The output voltage at the output terminal 15 is divided by

resistors

22 and 23, and the voltage at the voltage dividing point is supplied to the negative input of the error amplifier 24. A reference voltage 25 is supplied to the plus input of the error amplifier 24. The output of the error amplifier 24 is supplied to the minus input of a comparator 26 for PWM (pulse width modulation), and the output of the adder 19 is supplied to the plus input of the comparator 26. Further, the output of the comparator 26 is supplied to the reset input of the flip-flop circuit 27, and the Q output of the flip-flop circuit 27 is connected to the gate of the PMOS transistor 11. The output of the oscillator 28 is supplied to the set input of the flip-flop circuit 27.
[0005]
In the DC-DC converter configured as described above, a voltage difference between both ends of the resistor 17 (voltage drop due to the resistor 17) is detected and amplified by an operational amplifier type amplifier 18, thereby detecting an output current and outputting it as a voltage. The adder 19 adds the sawtooth wave voltage from the sawtooth wave voltage generation circuit 20 to the output voltage. The output voltage of the adder 19 changes according to the output current. Further, the output voltage of the output terminal 15 of the DC-DC converter is divided by the

resistors

22 and 23, and the divided voltage and the reference voltage 25 are compared by the error amplifier 24, whereby the output voltage of the output terminal 15 is output. A voltage corresponding to the error is obtained at the output of the error amplifier 24. The output voltage of the error amplifier 24 and the output voltage of the adder 19 are compared by the comparator 26, so that the PWM signal controlled by the output voltage and output current of the DC-DC converter is output to the output of the comparator 26. As a result, by switching control of the PMOS transistor 11 through the flip-flop circuit 27 with this PWM signal, a constant output DC voltage lower than the power supply voltage Vcc can be generated by the voltage generator 16 and obtained at the output terminal 15. it can.
[0006]
[Problems to be solved by the invention]
However, in the conventional DC-DC converter as described above, the voltage difference between both ends of the resistor 17 is detected and amplified by the operational amplifier type amplifier 18 as a method of detecting the output current and outputting it as a voltage. However, there is a problem that various adverse effects occur in the implementation of IC. That is, in the conventional circuit of FIG. 8, the negative input of the amplifier 18 is fixed at the power supply voltage Vcc, and the positive input is lowered from the power supply voltage by several hundred mV at most even when a voltage drop due to the resistor 17 occurs. Since this is a voltage, the input voltage for both inputs is approximately the power supply voltage Vcc of the circuit. Therefore, a function required for the amplifier 18 is that the common-mode input voltage range includes the power supply voltage. However, a normal operational amplifier used as the amplifier 18 does not have this function, and a complicated circuit configuration is required to provide this function. This leads to an increase in the number of elements in the chip when the DC-DC converter is integrated into an IC, which leads to an increase in chip size or an increase in current consumption.
[0007]
The present invention has been made in view of the above points. The circuit configuration is simplified, and it is suitable for an IC in a CMOS process. Further, the power supply voltage is near (in the case of a step-down DC-DC converter) or near the ground voltage (step-up). It is an object of the present invention to provide a current-voltage conversion circuit that can operate even with a small voltage difference and can accurately detect even a small voltage difference and a DC-DC converter using the same. .
[0008]
[Means for Solving the Problems]
The current-voltage conversion circuit according to the present invention is a current-voltage conversion circuit that detects a current from a voltage drop caused by a resistor and outputs the voltage as a voltage, and a detection resistor inserted in the current path and both ends of the detection resistor. And a voltage-current conversion unit that converts a voltage difference between them into a current, and a current-voltage conversion unit that converts an output current of the voltage-current conversion unit into a voltage.
[0009]
The DC-DC converter of the present invention has a current-voltage conversion circuit that detects an output current from a voltage drop caused by a resistor and outputs the detected voltage as a voltage, and adds a sawtooth voltage to the voltage. A DC-DC converter that generates a PWM signal from a circuit output and an output voltage error voltage and controls switching of the switching element with the PWM signal, wherein the current-voltage conversion circuit is connected in series with the switching element. Output current detection resistor, the voltage-current conversion unit that converts the voltage difference between both ends of this detection resistor into current, and the output current of this voltage-current conversion unit is converted into voltage, and at the same time the sawtooth voltage And a current-voltage conversion unit for adding.
[0010]
As is apparent from the above description, in the present invention, instead of detecting and amplifying the voltage difference between both ends of the conventional resistor with an operational amplifier type amplifier, a method of converting this voltage difference into current once and then reconverting it into voltage is employed. Take. In this method, the voltage-current converter has no particular problem even if the detected voltage is near the power supply voltage (in the case of a step-down DC-DC converter) or near the ground voltage (in the case of a step-up DC-DC converter). Even voltage differences can be detected accurately. Furthermore, the circuit configuration can be a very simple configuration because no special function is required. In addition, a general operational amplifier (amplifier) can be used for the current-voltage conversion section for returning the voltage again. By supplying a sawtooth voltage as a bias voltage of the operational amplifier, the sawtooth voltage can be added. It can be realized at the same time.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a step-down current mode DC-DC converter as an embodiment of the present invention. In this DC-DC converter, the configuration of the current-voltage conversion circuit 31 is different from the conventional example of FIG. Therefore, in the following description, only the current-voltage conversion circuit 31 portion will be described in detail, and the other same portions are denoted by the same reference numerals as the respective portions in FIG.
[0012]
The current-voltage conversion circuit 31 includes a detection resistor 32, a voltage-current conversion unit 33, an amplifier (op-amp) 34 as a current-voltage conversion unit, and a sawtooth voltage generation circuit 35. The detection resistor 32 is connected between the source of the PMOS transistor 11 serving as a switching element and the power supply voltage Vcc. One end of the detection resistor 32 on the source side and the other end on the opposite side (power supply voltage Vcc) are connected to the first and second inputs of the voltage-current converter 33, respectively. The output of the voltage-current converter 33 is connected to the negative input of the amplifier 34, and the output of the sawtooth voltage generating circuit 35 is connected to the positive input of the amplifier 34. A feedback resistor 36 is connected between the output of the amplifier 34 and the negative input, and the output of the amplifier 34 is connected to the positive input of the comparator 26.
[0013]
In the current-voltage conversion circuit 31 configured as described above, the voltage difference between both ends of the resistor 32 is converted into a current by the voltage-current conversion unit 33, and the current is converted back to a voltage by the amplifier 34. As a result, like the conventional current-voltage conversion circuit, the output current can be detected from the voltage drop due to the resistor and output as a voltage. In addition, when the amplifier 34 reconverts the current into a voltage, the sawtooth wave voltage is supplied as a bias voltage from the sawtooth voltage generation circuit 35 to the positive input of the amplifier 34, so that the output voltage of the amplifier 34 is sawtooth. Wave voltage can be added. Therefore, the PWM signal can be generated by comparing the output voltage of the amplifier 34 with the output voltage of the error amplifier 24.
[0014]
FIG. 2 shows a first specific circuit diagram of the current-voltage conversion circuit 31 (particularly the voltage-current conversion unit 33). The voltage-current converter 33 includes a constant current source 41,

resistors

42 and 43, and MOS transistors 44 to 54. Of the MOS transistors 44 to 54, the

MOS transistors

44 and 45 are PMOS transistors, and the MOS transistors 46 to 54 are NMOS transistors. A constant current source 41, an NMOS transistor 46, and an NMOS transistor 47 are connected in series in this order between the power supply voltage Vcc and the ground. The drains and gates of the NMOS transistor 46 and the NMOS transistor 47 are commonly connected to each other. In this series circuit, the constant current Ir flows by the constant current source 41. The source of the PMOS transistor 44 is connected to one end (the source side of the PMOS transistor 11) of the detection resistor 32 via the resistor 42. The gates of the PMOS transistors 44 are commonly connected to the drains. An NMOS transistor 48 and an NMOS transistor 49 are connected in series in this order between the drain of the PMOS transistor 44 and the ground. The other end of the detection resistor 32 (power supply voltage Vcc) is connected to the source of the PMOS transistor 45 via the resistor 43. Between the drain of the PMOS transistor 45 and the ground, an NMOS transistor 50 and an NMOS transistor 51 are connected in series in this order. The gate of the NMOS transistor 50 and the gate of the NMOS transistor 48 are commonly connected to the gate of the NMOS transistor 46. The gate of the NMOS transistor 51 and the gate of the NMOS transistor 49 are commonly connected to the gate of the NMOS transistor 47. The source of the PMOS transistor 45 is connected to the drain of the NMOS transistor 52, and the gate of the NMOS transistor 52 is connected to the drain of the PMOS transistor 45. The drain of the NMOS transistor 53 is connected to the source of the NMOS transistor 52. The NMOS transistor 53 has a drain and a gate connected in common and a source grounded. The gate of the NMOS transistor 53 is connected to the gate of the NMOS transistor 54. The NMOS transistor 54 has a source grounded and a drain connected to the negative input of an amplifier (op-amp) 34 as a current-voltage converter. The positive input of the amplifier 34 is connected to the output of the sawtooth voltage generator 35 as in FIG. Further, a resistor 36 is connected between the output of the amplifier 34 and the negative input. The back gate terminals of the MOS transistors 44 to 54 are all connected to the source terminal for the

PMOS transistors

44 and 45, and all the NMOS transistors 46 to 54 are connected to the ground.
[0015]
In the above circuit configuration, the

NMOS transistors

47, 49, 51 constitute a current mirror circuit, and if the channel length and channel width ratio (W / L) of these elements are set equal, the drain currents of the

NMOS transistors

49, 51 are almost equal. It is equal to the constant current Ir. The

NMOS transistors

46, 48, 50 fix the drain voltages of the

NMOS transistors

49, 51 equally, and prevent variations in drain current due to the channel length modulation effect. Assuming that the source voltage of the PMOS transistor 11 as a switching element is Vs, the current Io flowing through the PMOS transistor 11 out of the total current flowing through the detection resistor 32 (resistance value Rs) is transferred to the resistor 42 (resistance value R ₁ ). Since it is extremely large compared to the flowing current Ir,
[Expression 1]

It becomes.
[0016]
The source voltage of the

PMOS transistor

44 and 45 is equal by setting the W / L of the

PMOS transistors

44 and 45 equal, when this is the Vs _7,
[Expression 2]

It becomes. Therefore, the current I ₉ flowing to the drain of the NMOS transistor 52 can be obtained by setting the resistance values R ₁ and R ₂ of the

resistors

42 and 43 equal to
[Equation 3]

Thus, a current proportional to the output current Io (voltage between the terminals of the resistor 32) can be taken out. The NMOS transistor 52 forms a negative feedback loop (the operation will be described later), and the current I ₉ can be taken out with high accuracy. Therefore, if the W / L of the NMOS transistor 53 and the NMOS transistor 54 are set to be equal, the drain current of the NMOS transistor 54 is also equal to the current I ₉ and becomes a current proportional to the output current Io. The drain current (current I ₉ ) of the NMOS transistor 54 is drawn from the negative input of the amplifier 34, and the sawtooth wave voltage (Vrg) is applied to the positive input of the amplifier 34, whereby the output voltage of the amplifier 34 is output. Vao is [Expression 4]

(Where R ₃ is the resistance value of the resistor 36). That is, as the output voltage Vao, a voltage proportional to the output current Io and added with the sawtooth voltage Vrg can be obtained. Here, the amplification factor of RsIo is determined by the resistance ratio of R ₃ / R ₂ .
[0017]
The specific circuit of the current-voltage conversion circuit 31 is as described above. In this specific example, the operation of the voltage-current conversion unit 33 will be briefly described as follows. That is, if the source voltages of the

PMOS transistors

44 and 45 are the same and the drain currents of the

PMOS transistors

44 and 45 are constant, the voltage between the terminals of the resistor 32 changes and the source voltage of the

PMOS transistors

44 and 45 changes. Since the drain currents of the

PMOS transistors

44 and 45 are constant, a current proportional to the change can be taken out as the current I ₉ .
[0018]
In the voltage-current converter 33, the NMOS transistor 52 forms a negative feedback loop. The operation of this negative feedback loop is as follows. That is, for some reason, the drain current of the PMOS transistor 45 increases, and as a result, the current I ₉ decreases, and the proportional relationship between the current I ₉ and the voltage across the resistor 32 (output current Io) is lost. by drain current of the PMOS transistor 45 increases, the gate voltage increases the NMOS transistor 52, because as a result becomes the current I ₉ is increased increasing the conductivity of the NMOS transistor 52, the current I ₉ The proportional relationship with the voltage between the terminals of the resistor 32 is recovered and maintained. Conversely, the drain current decreases the PMOS transistor 45, a current if I ₉ is increased, the current I ₉ decreases in reverse action and, also the terminal voltage of the current I ₉ and the resistor 32 The proportional relationship is maintained.
[0019]
As described above, according to the voltage-current conversion unit 33, there is no problem even with a voltage near the power supply voltage, and even a minute voltage difference between both ends of the resistor 32 can be accurately detected and converted into a current. In addition, the circuit configuration is simple as described above, and is suitable for IC implementation in a CMOS process. Further, the amplifier 34 can convert the current from the voltage-current converter 33 into a voltage, and simultaneously add a sawtooth voltage to the voltage.
[0020]
FIG. 3 is a second specific circuit diagram of the current-voltage conversion circuit 31 and is a circuit example in which the voltage-current conversion unit 33 of FIG. 2 is simplified. In this circuit, the

NMOS transistors

46, 48, 50, 53 of FIG. 2 are omitted. Therefore, the constant current source 41 and the NMOS transistor 47 are connected in series between the power supply voltage Vcc and the ground. Further, only the NMOS transistor 49 is connected between the drain of the PMOS transistor 44 and the ground, and only the NMOS transistor 51 is connected between the drain of the PMOS transistor 45 and the ground. Further, an NMOS transistor 52 is connected between the source of the PMOS transistor 45 and the ground, and the gate of the NMOS transistor 54 is connected to the gate of the NMOS transistor 52.
[0021]
The circuit of FIG. 3 is inferior to the circuit of FIG. 2 in accuracy because there is a slight difference in the drain currents of the

NMOS transistors

49 and 51 constituting the current mirror, but the number of MOS transistors can be reduced and the area occupied by the chip can be reduced. This is advantageous.
[0022]
FIG. 4 shows a third specific circuit diagram of the current-voltage conversion circuit 31 (particularly, the voltage-current conversion unit 33). This circuit is a case where the circuit of FIG. 2 is applied to a step-up DC-DC converter. In the step-up type, of the MOS transistors 44 to 54, the

MOS transistors

44 and 45 are NMOS transistors, and the MOS transistors 46 to 54 are PMOS transistors. Further, the power supply voltage Vcc and the ground voltage are opposite to those in FIG. Therefore, the other end of the detection resistor 32, one end of the constant current source 41 (on the opposite side to the PMOS transistors 46 and 47), and one end of the resistor 43 (on the opposite side to the NMOS transistor 45) are connected to the ground voltage. The sources of 49, 51, 53 and 54 are connected to the power supply voltage Vcc. Further, in the case of the boost type,

NMOS transistors

55 and 56 are added to draw the same current as the drain current of the PMOS transistor 54 from the negative input of the amplifier 34 to the ground. The NMOS transistor 55 has a source grounded, a drain and a gate connected in common, and a drain connected to the drain of the NMOS transistor 54. The NMOS transistor 56 has a source grounded, a gate connected to the gate of the NMOS transistor 55, and a drain connected to the negative input of the amplifier 34. In the case of the step-up type, an NMOS transistor is used as the MOS transistor 11 serving as a switching element of the voltage generator 16 and the way of connecting the inductor 13 and the diode 12 in the voltage generator 16 is different from that in FIG. . The inductor 13 is connected between the drain of the NMOS transistor 11 and the power supply voltage Vcc, and the diode 12 is connected between the drain of the NMOS transistor 11 and the output terminal 15.
[0023]
FIG. 5 is a fourth specific circuit diagram of the current-voltage conversion circuit 31, which is the boost type of FIG. 4 and the circuit of the voltage-current conversion unit 33 is simplified as in FIG. In this circuit, the

PMOS transistors

46, 48, 50, 53 of FIG. 4 are omitted. Therefore, the PMOS transistor 47 and the constant current source 41 are connected in series in this order between the power supply voltage Vcc and the ground. Further, only the PMOS transistor 49 is connected between the drain of the NMOS transistor 44 and the power supply voltage Vcc, and only the PMOS transistor 51 is connected between the drain of the NMOS transistor 45 and the ground. Further, a PMOS transistor 52 is connected between the source of the NMOS transistor 45 and the power supply voltage Vcc, and the gate of the PMOS transistor 54 is connected to the gate of the PMOS transistor 52.
[0024]
Also in the boost type of FIGS. 4 and 5, the current-voltage conversion circuit 31 operates in the same manner as the step-down type of FIGS. 2 and 3, and the same effect can be obtained.
[0025]
FIG. 6 is a fifth specific circuit diagram of the current-voltage conversion circuit 31, and is a case where the voltage-current conversion unit 33 is partly changed in the step-down type of FIG. In this circuit, a PMOS transistor is used as the MOS transistor 52, and the source of the PMOS transistor 52 is connected to the source of the NMOS transistor 45. The drain and gate of the NMOS transistor 53 are connected to the drain of the PMOS transistor 52. The gate of the PMOS transistor 52 is changed from the drain of the PMOS transistor 45 to the drain of the PMOS transistor 44, and the gates of the

PMOS transistors

44 and 45 are changed from the drain of the PMOS transistor 44 to the drain of the PMOS transistor 45. Is done. Further, the

NMOS transistors

46, 48 and 50 shown in FIG. 2 are omitted. Therefore, the constant current source 41 and the NMOS transistor 47 are connected in series between the power supply voltage Vcc and the ground. Further, only the NMOS transistor 49 is connected between the drain of the PMOS transistor 44 and the ground, and only the NMOS transistor 51 is connected between the drain of the PMOS transistor 45 and the ground.
[0026]
6 operates in the same manner as in FIG. 2, and negative feedback by the PMOS transistor 52 also acts. That is, when the drain current of the PMOS transistor 45 increases and the current I ₉ decreases, the drain current of the PMOS transistor 44 decreases. As a result, the gate voltage of the PMOS transistor 52 decreases and the conductivity of the PMOS transistor 52 increases. Since the current I ₉ increases, the proportional relationship between the current I ₉ and the voltage across the resistor 32 is maintained. On the other hand, when the drain current of the PMOS transistor 45 decreases and the current I ₉ increases, the current I ₉ decreases due to the reverse action to the above, and the voltage between the current I ₉ and the terminal of the resistor 32 is also decreased. The proportional relationship is maintained. However, in the negative feedback of FIG. 6, since the loop gain is lower than that of FIG. 2, the accuracy is slightly inferior to that of FIG.
[0027]
However, the circuit of FIG. 6 has an effect that the power supply voltage Vcc can be lowered as compared with FIG. That is, in the circuit of FIG. 2, the gate voltage of the MOS transistor 52 is a voltage obtained by adding the gate-source voltage of the MOS transistor 52 to the gate-source voltage of the MOS transistor 53 (hereinafter referred to as the first voltage). On the other hand, in the circuit of FIG. 6, the gate voltage of the MOS transistor 52 is a voltage obtained by adding the voltage between the gate and source of the MOS transistor 52 to the voltage drop of the resistor 43 (hereinafter referred to as the second voltage). The power supply voltage Vcc needs to be higher than these first and second voltages. However, since the second voltage in FIG. 6 is lower than the first voltage in FIG. 2, the power supply voltage Vcc is correspondingly higher in FIG. It can be made lower than in FIG.
[0028]
FIG. 7 is a sixth specific circuit diagram of the current-voltage conversion circuit 31, and is a case where the circuit of the voltage-current conversion unit 33 is partially changed as in FIG. That is, in this circuit, an NMOS transistor is used as the MOS transistor 52, the source of the NMOS transistor 52 is connected to the source of the NMOS transistor 45, and the drain and gate of the PMOS transistor 53 are connected to the drain of the NMOS transistor 52. The gate of the NMOS transistor 52 is changed from the drain of the NMOS transistor 45 to the drain of the NMOS transistor 44, and the gates of the

NMOS transistors

44 and 45 are connected from the drain of the NMOS transistor 44 to the drain of the NMOS transistor 45. Be changed. Further, the

PMOS transistors

46, 48 and 50 shown in FIG. 4 are omitted. Therefore, the PMOS transistor 47 and the constant current source 41 are connected in series in this order between the power supply voltage Vcc and the ground. Further, only the PMOS transistor 49 is connected between the drain of the NMOS transistor 44 and the power supply voltage Vcc, and only the PMOS transistor 51 is connected between the drain of the NMOS transistor 45 and the ground. Such a circuit of FIG. 7 also operates in the same manner as in FIG. 6, and the same effect can be obtained.
[0029]
【The invention's effect】
As described above in detail, according to the current-voltage conversion circuit and the DC-DC converter using the current-voltage conversion circuit of the present invention, there is no problem even with a voltage near the power supply voltage or the ground voltage due to a voltage drop due to the resistance. Even a voltage difference can be detected with high accuracy, and a current (output current) can be output as a voltage. The circuit configuration is simple, and it is suitable for integration in a CMOS process.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a step-down current mode DC-DC converter as an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a first specific circuit of a current-voltage conversion circuit in the DC-DC converter.
FIG. 3 is a circuit diagram showing a second specific circuit of a current-voltage conversion circuit in the DC-DC converter.
FIG. 4 is a circuit diagram showing a third specific circuit of the current-voltage conversion circuit according to the present invention.
FIG. 5 is a circuit diagram showing a fourth specific circuit of the current-voltage conversion circuit according to the present invention.
FIG. 6 is a circuit diagram showing a fifth specific circuit of the current-voltage conversion circuit according to the present invention.
FIG. 7 is a circuit diagram showing a sixth specific circuit of the current-voltage conversion circuit according to the present invention.
FIG. 8 is a circuit diagram showing a conventional step-down current mode DC-DC converter.
[Explanation of symbols]
31 Current-Voltage Conversion Circuit 32 Detection Resistance 33 Voltage-Current Conversion Unit 34 Amplifier (Current-Voltage Conversion Unit)
35 Sawtooth voltage generator

Claims

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A first PMOS transistor having a source connected to one end of the detection resistor via a resistor and a gate and a drain connected in common, a source connected to the power supply voltage of the other end of the detection resistor via a resistor, consists of a first 2PMOS transistor connected to the gate of the first 1PMOS transistor, and the circuit first, source voltage of the 2PMO S transistor are the same, first, the drain current of the 2PMO S transistor is constant,
A pair of constant current NMOS transistor inserted between ground and the drain of the second 2PMOS transistor and the second 1PMOS transistor,
A pair of NMOS transistors connected in series with each of the constant current NMOS transistors and fixing the drain voltage of the pair of constant current NMOS transistors equally;
A first NMOS which has a drain connected to the source of the second PMOS transistor and a gate connected to the drain of the second PMOS transistor, takes out a current proportional to a change in voltage between the terminals of the detection resistor, and constitutes a negative feedback loop A transistor,
A second NMOS transistor connected between the source of the first NMOS transistor and the ground and having a drain and a gate connected in common;
A third NMOS transistor having a gate connected to the gate of the second NMOS transistor and a source grounded;
The first 3NMOS transistor characteristic and to that current drain that is formed of an amplifier connected to the input of the - voltage converting circuit.

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A first PMOS transistor having a source connected to one end of the detection resistor via a resistor and a gate and a drain connected in common, a source connected to the power supply voltage of the other end of the detection resistor via a resistor, consists of a first 2PMOS transistor connected to the gate of the first 1PMOS transistor, and the circuit first, source voltage of the 2PMO S transistor are the same, first, the drain current of the 2PMO S transistor is constant,
A pair of constant current NMOS transistor inserted between ground and the drain of the second 2PMOS transistor and the second 1PMOS transistor,
A first NMOS connected between the source of the second PMOS transistor and the ground, a gate connected to the drain of the second PMOS transistor, taking out a current proportional to a change in voltage between the terminals of the detection resistor, and constituting a negative feedback loop A transistor,
A third NMOS transistor having a gate connected to the gate of the first NMOS transistor and a source grounded;
The first 3NMOS transistor characteristic and to that current drain that is formed of an amplifier connected to the input of the - voltage converting circuit.

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A first PMOS transistor having a source connected to one end of the detection resistor via a resistor, a source connected to the power supply voltage of the other end of the detection resistor via a resistor, and a gate and a drain together with the gate of the first PMOS transistor consists of a commonly connected second 2PMOS transistor, and the circuit first, source voltage of the 2PMO S transistor are the same, first, the drain current of the 2PMO S transistor is constant,
A pair of constant current NMOS transistor inserted between ground and the drain of the second 2PMOS transistor and the second 1PMOS transistor,
A third PMOS which has a source connected to the source of the second PMOS transistor and a gate connected to the drain of the first PMOS transistor, takes out a current proportional to a change in voltage between the terminals of the detection resistor, and constitutes a negative feedback loop A transistor,
A second NMOS transistor connected between the drain and the ground of the third PMOS transistor, the drain and the gate of which are connected in common;
A third NMOS transistor having a gate connected to the gate of the second NMOS transistor and a source grounded;
The first 3NMOS transistor characteristic and to that current drain that is formed of an amplifier connected to the input of the - voltage converting circuit.

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A source is connected to one end of the detection resistor via a resistor, a first NMOS transistor having a gate and a drain connected in common, a source connected to the ground voltage at the other end of the detection resistor, and a gate connected to the ground consists of a first 2NMOS transistor connected to the gate of the first 1NMOS transistor, and the circuit first, source voltage of the 2NMO S transistor are the same, first, the drain current of the 2NMO S transistor is constant,
A pair of constant current PMOS transistor interposed between each drain and source voltage of the first 2NMOS transistor and the second 1NMOS transistor,
A pair of PMOS transistors connected in series with each of the constant current PMOS transistors and equally fixing the drain voltage of the pair of constant current PMOS transistors;
A first PMOS having a drain connected to the source of the second NMOS transistor and a gate connected to the drain of the second NMOS transistor, taking out a current proportional to a change in voltage between the terminals of the detection resistor, and constituting a negative feedback loop A transistor,
A second PMOS transistor connected between the source of the first PMOS transistor and a power supply voltage and having a drain and a gate connected in common;
A third PMOS transistor having a gate connected to the gate of the second PMOS transistor and a source connected to the power supply voltage;
A third NMOS transistor connected between the drain of the third PMOS transistor and the ground voltage and having a drain and a gate connected in common;
A fourth NMOS transistor having a gate connected to the gate of the third NMOS transistor and a source connected to the ground voltage;
This feature and to that current drain that is formed of an amplifier connected to an input of a 4NMOS transistor - voltage converter circuit.

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A source is connected to one end of the detection resistor via a resistor, a first NMOS transistor having a gate and a drain connected in common, a source connected to the ground voltage at the other end of the detection resistor, and a gate connected to the ground consists of a first 2NMOS transistor connected to the gate of the first 1NMOS transistor, and the circuit first, source voltage of the 2NMO S transistor are the same, first, the drain current of the 2NMO S transistor is constant,
A pair of constant current PMOS transistor interposed between each drain and source voltage of the first 2NMOS transistor and the second 1NMOS transistor,
A second NMOS transistor is connected between the source and the power supply voltage, a gate is connected to the drain of the second NMOS transistor, a current proportional to a change in voltage between the terminals of the detection resistor is taken out, and a negative feedback loop is formed . 1 PMOS transistor,
A third PMOS transistor having a gate connected to the gate of the first PMOS transistor and a source connected to the power supply voltage;
A third NMOS transistor connected between the drain of the third PMOS transistor and the ground voltage and having a drain and a gate connected in common;
A fourth NMOS transistor having a gate connected to the gate of the third NMOS transistor and a source connected to the ground voltage;
This feature and to that current drain that is formed of an amplifier connected to an input of a 4NMOS transistor - voltage converter circuit.

A current-voltage conversion circuit that detects current from a voltage drop due to resistance and outputs a voltage proportional to the change in current.
A detection resistor inserted in the current path;
A voltage-current converter that converts the voltage difference between both ends of the detection resistor into a current;
A current-voltage converter that converts the output current of the voltage-current converter into a voltage ;
The voltage-current converter and the current-voltage converter are
A first NMOS transistor having a source connected to one end of the detection resistor via a resistor, a source connected to the ground voltage of the other end of the detection resistor via a resistor, and a gate and a drain together with the gate of the first NMOS transistor consists of a commonly connected second 2NMOS transistor, and the circuit first, source voltage of the 2NMO S transistor are the same, first, the drain current of the 2NMO S transistor is constant,
A pair of constant current PMOS transistor interposed between each drain and source voltage of the first 2NMOS transistor and the second 1NMOS transistor,
A fifth NMOS which has a source connected to the source of the second NMOS transistor and a gate connected to the drain of the first NMOS transistor, takes out a current proportional to a change in voltage between the terminals of the detection resistor, and constitutes a negative feedback loop A transistor,
A second PMOS transistor connected between the drain of the fifth NMOS transistor and the power supply voltage and having the drain and gate connected in common;
A third PMOS transistor having a gate connected to the gate of the second PMOS transistor and a source connected to the power supply voltage;
A third NMOS transistor connected between the drain of the third PMOS transistor and the ground voltage and having a drain and a gate connected in common;
A fourth NMOS transistor having a gate connected to the gate of the third NMOS transistor and a source connected to the ground voltage;
This feature and to that current drain that is formed of an amplifier connected to an input of a 4NMOS transistor - voltage converter circuit.