JP2006262103A - Volt-ampere converting circuit and error amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a volt-ampere converting circuit which has a low input offset voltage and a wide output current range and to provide a current output type error amplifying circuit which uses the volt-ampere converting circuit and makes the low input offset voltage and a high speed transient response compatible. <P>SOLUTION: An output step has a circuit constituted of the output current I0 which is a difference between the current I1 output from a power source (VDD) side by a first current mirror circuit and the current I2 input to a ground (GND) side by a second current mirror circuit. A gate of a transistor to constitute the first and the second current mirrors is controlled by an operational amplifier to be operated by a voltage mode. A capacitive element is connected to an output terminal of the volt-ampere converting circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a voltage / current conversion circuit and an error amplification circuit of a switching power supply using the voltage / current conversion circuit.

First, a configuration example of the switching power supply will be described with reference to FIG. FIG. 6 shows a PWM (pulse width modulation) step-down DC / DC converter that generates an output voltage Vo from an input voltage VDD and supplies the output voltage Vo to a load Z. This DC / DC converter includes an error amplifier 1, an oscillator 2 that generates a triangular wave Vosc 2, a PWM comparator 3, a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a switching element 4, and an N-channel as a commutation element of a synchronous rectification system MOSFET 5, the drive circuit 6 for driving the P-channel MOSFET4 and N-channel MOSFET 5 according to the output of the PWM comparator 3, the inductor 7, a capacitor C0, resistors R1 and R2 becomes a feedback means for voltage setting, the reference voltage for generating a reference voltage _{V REF} A source 8 and an output terminal 9 are provided. Reference numeral 10 denotes a power supply line to which a power supply voltage VDD is supplied. A reference voltage _VREF is input to the non-inverting input terminal of the error amplifier 1, and a resistor Rc and a capacitor Cc are connected as a phase compensation element between the output terminal and the inverting input terminal. The output signal Verr of the error amplifier 1 is input to the non-inverting input terminal of the PWM comparator 3, and the triangular wave Vosc is input to the inverting input terminal. The PWM comparator 3 compares the output signal Verr of the error amplifier 1 with the triangular wave Vosc. If the signal level of the triangular wave Vosc is smaller, it is H (high level), and if the signal level of the triangular wave Vosc is larger, it is L (low level). Is output to the drive circuit 6 as a PWM signal. The drains of the P-channel MOSFET 4 and the N-channel MOSFET 5 are connected to each other and to one end of the inductor 7. The sources of the P channel MOSFET 4 and the N channel MOSFET 5 are connected to the power supply line 10 and the ground potential (GND), respectively. The other end of the inductor 7 is connected to the output terminal 9. A series circuit of a capacitor C0 and resistors R1 and R2 is connected in parallel between the output terminal 9 and GND. The potential at the connection point between the resistors R1 and R2 is input to the inverting input terminal of the error amplifier 1 as a feedback signal _VFB . A load 11 is connected to the output terminal 9 as a load of the DC / DC converter.

The operation of this DC / DC converter will be briefly described below. The error amplifier 1 inputs a signal Verr obtained by amplifying the difference between the reference voltage V _REF and the feedback signal V _FB to the PWM comparator 3. The PWM comparator 3 compares the Verr and the triangular wave Vosc to generate a square wave pulse (PWM signal) whose period is constant but whose ratio of H and L in one period changes according to the output of the error amplifier 1 through the drive circuit 6. To the gate of the P-channel MOSFET 4. That is, as (V _REF −V _FB ) is larger (smaller), a square wave pulse is generated so that the period during which the P-channel MOSFET 4 is turned on (conducted) in one cycle becomes longer (shorter), and the energy accumulated in the inductor 7 is increased. keep the output voltage V _O constant by a larger (smaller). Similarly, a square wave pulse is output to the gate of the N-channel MOSFET 5. Basically, the square wave pulses output to the gates of the P-channel MOSFET 4 and the N-channel MOSFET 5 are in phase, but both are turned off so that the P-channel MOSFET 4 and the N-channel MOSFET 5 are turned on simultaneously and no through current flows. A dead time that is a period of

Resistors R1, R2, Rc, capacitor Cc, error amplifier 1 and reference voltage source 8 constitute an error amplifier circuit. This part is extracted and shown in FIG. The error amplifier circuit illustrated in FIG. 7 is a kind of amplifier circuit that receives an input signal _VIN and outputs an output signal _VOUT . Signals V _IN and V _OUT correspond to Vo and Verr in FIG. 6, respectively. The error amplifying circuit of FIG. 7 is DC stable when the following equation is satisfied.

上の（１）式を満たす安定点からのＶ_ＩＮ，Ｖ_ＯＵＴの変動分をそれぞれｖ_ｉｎ，ｖ_ｏｕｔとし、ｖ_ｉｎに応じて抵抗Ｒ１に流れる電流（すなわち安定点からの変動分）をｉとすると、抵抗Ｒ１とＲ２の接続点の電位は基準電位Ｖ_ＲＥＦにイマジナリショートされて固定されているからｉ＝ｖ／Ｒ_１となる。ここでＲ_１は抵抗Ｒ１の抵抗値である。以下、同様に抵抗Ｒｉの抵抗値をＲ_ｉ（ｉ＝０，１，２）で表す。抵抗Ｒ２の両端の電圧は上述のようにＶ_ＲＥＦに固定されていて抵抗Ｒ２に流れる電流も変化できないため、電流ｉは抵抗Ｒ２には流れず抵抗Ｒｃに流れる。これより、ｖ_ｉｎ，ｖ_ｏｕｔおよびｉの関係式は次式となる。

The fluctuations of V _IN and V _OUT from the stable point satisfying the above equation (1) are defined as v _in and v _out , respectively, and the current flowing through the resistor R1 according to v _in (that is, the fluctuation from the stable point) is i. When, the potential of the connection point of the resistors R1 and R2 is from being fixed by imaginary short to the reference potential V _REF and i = v / R _1. Wherein _{R 1} is the resistance value of the resistor R1. Hereinafter, similarly, the resistance value of the resistor Ri is represented by R _i (i = 0, 1, 2). Since the voltage across the resistor R2 is fixed at _VREF as described above and the current flowing through the resistor R2 cannot change, the current i does not flow through the resistor R2 but flows through the resistor Rc. Accordingly, the relational expression of v _in , v _out and i is as follows.

これより、図７に示す回路の（安定点からの変動分に関する）伝達関数Ｔ（ｓ）は次式となる。

Accordingly, the transfer function T (s) (related to the fluctuation from the stable point) of the circuit shown in FIG.

図７に示す誤差増幅回路を図６に示すような電圧モードのＤＣ／ＤＣコンバータに用いる場合、制御ループを安定に動作させるために比較的大きな時定数τ＝Ｒ_１・Ｃ_Ｃが要求される。なお、Ｃ_ＣはコンデンサＣｃの容量値である。例えばτ＝１００μｓを実現するためには、Ｒ_１＝１ＭΩとしてもコンデンサＣｃの容量値Ｃ_Ｃとして１００ｐＦが必要となり、これは集積回路に内蔵する容量値としては大きな値である。このように、図７に示す回路を集積回路で実現する場合、要求される時定数τがある程度大きいとコンデンサＣｃを外付け素子とせざるを得ず、当該集積回路に外付け端子を２つ設ける必要がある。集積回路における端子数増加はコストアップや実装面積の増大などを引き起こすため、コンデンサＣｃのためだけに端子が２つ増えてしまうのは問題となる。

When the error amplifying circuit shown in FIG. 7 is used in a voltage mode DC / DC converter as shown in FIG. 6, a relatively large time constant τ = R ₁ · C _C is required to stably operate the control loop. . Incidentally, _{C C} is the capacitance of the capacitor Cc. For example, in order to realize τ = 100 μs, even if R ₁ = 1 MΩ, 100 pF is required as the capacitance value C _C of the capacitor Cc, which is a large value as a capacitance value built in the integrated circuit. Thus, when the circuit shown in FIG. 7 is realized by an integrated circuit, if the required time constant τ is large to some extent, the capacitor Cc must be an external element, and two external terminals are provided in the integrated circuit. There is a need. An increase in the number of terminals in the integrated circuit causes an increase in cost, an increase in mounting area, and the like. Therefore, it is a problem that the number of terminals increases only for the capacitor Cc.

To solve the problem of the increase in the number of terminals, it is possible to take a measure of configuring the error circuit of FIGS. 8 and 9 using a current output type amplifier. That is, the error circuit of FIGS. 8 and 9 requires only one external terminal.
The circuits of FIGS. 8 and 9 will be briefly described. The same parts as those in FIGS. 6 and 7 are denoted by the same reference numerals, and description thereof is omitted. In the circuit of FIG. 8, OTA is a transconductance amplifier. As described in the figure, the input voltages Vx and Vy applied to the input terminals x and y and the output current Io output from the output terminal o are Io = g _It functions to satisfy the relationship _m (Vx−Vy). G _m is a positive constant representing conductance. The circuit of FIG. 8 is also stabilized in a direct current when the following equation is satisfied.

図７の回路と同様に、上の（４）式を満たす安定点からのＶ_ＩＮ，Ｖ_ＯＵＴの変動分をそれぞれｖ_ｉｎ，ｖ_ｏｕｔとし、ｖ_ｉｎに応じて抵抗Ｒｃに流れる電流をｉ_ｏとすると、ｉ_ｏ＝−ｇ_ｍ・ｖ_ｉｎ・Ｒ_２／（Ｒ_１＋Ｒ_２）となる。これより、図８に示す回路のｖ_ｉｎとｖ_ｏｕｔの間の関係式は次式となる。

Similar to the circuit of FIG. 7, the fluctuations of V _IN and V _OUT from the stable point satisfying the above equation (4) are defined as v _in and v _out , respectively, and the current flowing through the resistor Rc according to v _in is represented by i _o. Then, i _o = −g _m · v _in · R ₂ / (R ₁ + R ₂ ). Than this, relation between _{v in} and _{v out} of the circuit shown in FIG. 8 becomes the following equation.

また、上式より、図８に示す回路の（安定点からの変動分に関する）伝達関数Ｔ（ｓ）は次式となる。

From the above equation, the transfer function T (s) of the circuit shown in FIG.

また、図９の回路のおいてＣＣＩＩはカレント（電流）コンベア回路であり、図中に記したように、入力端子ｘ，ｙに印加される入力電圧Ｖｘ，Ｖｙ、入力端子に流入する電流Ｉｙおよび出力端子ｏから出力される出力電流Ｉｏの間に、Ｖｘ＝ＶｙおよびＩｏ＝−αＩｙという関係が成り立つよう機能するものである。なお、αは正定数である。図９の回路も、下式の条件を満たすとき直流的に安定する。

In the circuit of FIG. 9, CCII is a current conveyor circuit, and as described in the figure, the input voltages Vx and Vy applied to the input terminals x and y, and the current Iy flowing into the input terminals And the output current Io output from the output terminal o functions so that the relationship of Vx = Vy and Io = −αIy is established. Α is a positive constant. The circuit of FIG. 9 is also stabilized in a direct current when the following equation is satisfied.

図７，８の回路と同様に、上の（６）式を満たす安定点からのＶ_ＩＮ，Ｖ_ＯＵＴの変動分をそれぞれｖ_ｉｎ，ｖ_ｏｕｔとし、ｖ_ｉｎに応じて抵抗Ｒｃに流れる電流をｉ_ｏとすると、ｉ_ｏ＝−αＩｙ＝−αｖ_ｉｎ／Ｒ_１となる。これより、図９に示す回路のｖ_ｉｎとｖ_ｏｕｔの間の関係式は次式となる。

Similar to the circuits of FIGS. 7 and 8, the fluctuations of V _IN and V _OUT from the stable point satisfying the above equation (6) are defined as v _in and v _out , respectively, and the current flowing through the resistor Rc according to v _in is represented by If i _o , then i _o = −αIy = −αv _in / R ₁ . Than this, relation between _{v in} and _{v out} of the circuit shown in FIG. 9 becomes the following equation.

また、上式より、図９に示す回路の（安定点からの変動分に関する）伝達関数Ｔ（ｓ）は次式となる。

From the above equation, the transfer function T (s) (related to the fluctuation from the stable point) of the circuit shown in FIG.

（１），（４）および（７）式より、図７，８および９の回路は同じ直流安定点をもつことが分る。また、（３）式と（６）式を比較することにより、図８の回路のｇ_ｍＲ_２Ｒ_Ｃ／（Ｒ_１＋Ｒ_２）および｛Ｃ_Ｃ（Ｒ_１＋Ｒ_２）｝／ｇ_ｍＲ_２がそれぞれ図７の回路のＲ_Ｃ／Ｒ_１およびＣ_ＣＲ_１（＝時定数τ）と等しくなるよう調整すれば、図７，８の回路が同じ特性をもつことになる。同様に、（３）式と（９）式を比較することにより、図９の回路のαＲ_Ｃ／Ｒ_１およびＣ_ＣＲ_１／αがそれぞれ図７の回路のＲ_Ｃ／Ｒ_１およびＣ_ＣＲ_１（＝時定数τ）と等しくなるよう調整すれば、図７，９の回路が同じ特性をもつことになる。これにより、例えば図９の回路でαを小さくすることにより、コンデンサＣｃの容量値を集積回路に内蔵できる程度に小さくすることもできる。

From the equations (1), (4) and (7), it can be seen that the circuits of FIGS. 7, 8 and 9 have the same DC stable point. Further, by comparing the equations (3) and (6), g _m R ₂ R _C / (R ₁ + R ₂ ) and {C _C (R ₁ + R ₂ )} / g _m R in the circuit of FIG. by adjusting ₂ circuit _R C / _{R 1} and _C C _R 1, respectively, in FIG. 7 (= time constant tau) and equal way, the circuit of FIG. 7 and 8 have the same characteristics. Similarly, by comparing the equations (3) and (9), αR _C / R ₁ and C _C R ₁ / α of the circuit of FIG. 9 are respectively changed to R _C / R ₁ and C _C of the circuit of FIG. When adjusted to be equal to R ₁ (= time constant τ), the circuits of FIGS. 7 and 9 have the same characteristics. Thus, for example, by reducing α in the circuit of FIG. 9, the capacitance value of the capacitor Cc can be made small enough to be incorporated in the integrated circuit.

As described above, the current output type amplifier has the advantage that the number of terminals can be reduced and the capacitance value of the capacitor Cc can be reduced. On the other hand, when the bias current of the amplifier is increased to improve the transient response characteristic, Since the offset voltage increases, there is a problem that it is difficult to achieve both transient response characteristics and a low input offset voltage compared to the case where an operational amplifier (operational amplifier) is used.
FIG. 10 shows an example of a conventional voltage-current conversion circuit. In FIG. 10, 12 and 13 are positive and negative differential input terminals, 14 is a terminal for supplying a constant bias current to the differential circuit, 15 is an output terminal, and transistors M31, M33, M35, and M38. , M39 and M40 are P-channel MOSFETs, and transistors M32, M34, M36 and M37 are N-channel MOSFETs. Transistors M33, M34, M35, M36 and M39 form a differential stage, and transistors M31 and M32 form an output stage. The transistors M40 and M39 constitute a bias circuit that supplies a bias current proportional to the current Ib flowing through the terminal 14 to the differential stage. Transistors M36 and M37, transistors M38 and M31, and transistors M34 and M32 form a current mirror circuit, respectively.

  In general, in order for the voltage-current converter circuit to supply positive and negative currents, the difference between the current I1 discharged from the power supply (VDD) side and the current I2 flowing into the ground (GND) side of the output stage is the output current. A circuit configuration of I0 is taken. Also in the circuit of FIG. 10, the current I1 is determined by the current mirror circuit including the transistors M38 and M31 and the current mirror circuit including the transistors M36 and M37 with reference to the current flowing through the N-channel MOSFET M36. As a reference, the current I2 is determined by a current mirror circuit including transistors M34 and M32. Normally, when the input voltage (difference voltage between voltages V + and V− applied from the differential input terminals 12 and 13 to the gates of the P-channel MOSFETs M33 and M35) is 0, I1 = I2 and I0 = 0 Designed to be

In the voltage-current converter circuit using the current mirror circuit as described above, the mirror ratio of the current mirror circuit (current input to the current mirror circuit and the current mirror circuit is generated according to the input current due to variations in the manufacturing process) Let us consider the case where the ratio of output current to the design value deviates from the design value. In this case, even if the input voltage is 0, the output current does not become 0, and an offset current Ioff is generated. In other words, in order to set the output current to 0, it is necessary to add an offset voltage of −Ioff / gm as an input voltage (gm is a transfer conductance of the voltage-current conversion circuit).
In application to an error amplifying circuit, the offset voltage is directly connected to the error of the DC stable point of the control system, so that the value of the offset voltage must be kept within a small allowable range. In order to reduce the offset voltage, it is necessary to reduce the absolute value of the offset current Ioff. For this reason, a voltage-current conversion circuit that reduces the bias current Ib itself has been proposed (see, for example, Patent Document 1).
JP-A-6-169225 (page 2-4, FIGS. 1 and 2)

  The voltage-current conversion circuit shown in Patent Document 1 is based on the idea that if the bias current is reduced, the offset current Ioff is also reduced proportionally. However, if the bias current is reduced, the following problems occur. That is, in the circuit structure shown in FIG. 10, assuming that the mirror ratio of all the current mirror circuits is 1: 1, the current output range as the voltage-current conversion circuit is −Ib to + Ib (the input voltage range is −Ib / gm to + Ib). / Gm) (when the mirror ratio is not 1: 1, only -kIb to + kIb, and the following discussion is the same, where k is a positive constant). Therefore, the current output range or the input voltage range becomes narrower when the bias current Ib is reduced. As a result, when such a voltage-current converter circuit is applied to an error amplifier circuit, there is no problem because the output current is 0 in a steady state, but a large signal is input at the initial rise or due to a change in the control system, etc. In this case, there is a problem that the output current is limited and the response becomes slower than expected from the transfer function.

  The present invention has been made in view of the above points, and an object of the present invention is to solve the above-described problems and provide a voltage-current conversion circuit having a small input offset voltage and a wide output current range. It is another object of the present invention to provide a current output type error amplifying circuit using the voltage-current conversion circuit and having both a low input offset voltage and a fast transient response.

  In order to solve the above-described problem, the invention according to claim 1 is directed to a first P-channel MOSFET and a second P-channel that constitute first and second input terminals, an output terminal, and a first current mirror. MOSFET, a first N-channel MOSFET and a second N-channel MOSFET constituting a second current mirror, an operational amplifier, a bias voltage generating means, and a first resistor, and flows through the first P-channel MOSFET The ratio of the current flowing through the second P-channel MOSFET to the current is set to be equal to the ratio of the current flowing through the second N-channel MOSFET to the current flowing through the first N-channel MOSFET, and the first input A terminal and one end of the input resistor are connected, the other end of the input resistor, the first P-channel MOSFET , The drain of the first N-channel MOSFET, and the non-inverting input of the operational amplifier are connected, the second input terminal and the inverting input of the operational amplifier are connected, the output terminal, the second P The drain of the channel MOSFET and the drain of the second N-channel MOSFET are connected, the output terminal of the operational amplifier is connected to the gates of the first N-channel MOSFET and the second N-channel MOSFET, and the bias voltage generation The means is a voltage-current conversion circuit connected between a connection point between the output terminal of the operational amplifier and the gate of the first N-channel MOSFET and the gate of the second N-channel MOSFET. .

The invention according to claim 2 is the invention according to claim 1, wherein the bias generating means is a second resistor having one end connected to the output terminal of the operational amplifier and the other end connected to a constant current source. It is characterized by that.
The invention according to claim 3 is the invention according to claim 2, in which the third P-channel MOSFET in which the gate terminal and the drain terminal are connected between the power source and the reference potential, the third resistor, and the gate terminal and the drain terminal are connected. The third N-channel MOSFETs connected in series constitute a current generating circuit, and the ratio of the current flowing through the constant current source to the current flowing through the electric generating circuit and the third resistance with respect to the resistance value of the second resistor. The ratio of the resistance values of the resistors is set to be equal, and the W / L ratio, which is the ratio of the gate width W to the gate length L of the MOSFET, is related to the W / L ratio of the second P-channel MOSFET. The ratio of the W / L ratio of the N-channel MOSFET is equal to the ratio of the W / L ratio of the third N-channel MOSFET to the W / L ratio of the third P-channel MOSFET. And wherein the are.

The invention according to claim 4 is the invention according to claim 3, wherein the gate length of the second P-channel MOSFET and the gate length of the third P-channel MOSFET are equal, and the second N-channel MOSFET has the same gate length. The gate length is equal to the gate length of the third N-channel MOSFET.
The invention according to claim 5 is the invention according to claim 3 or 4, wherein the second P-channel MOSFET and the third P-channel MOSFET are unit P-channel MOSFETs having the same gate width and gate length, respectively. One or a plurality of unit N-channel MOSFETs connected in parallel, wherein the second N-channel MOSFET and the third N-channel MOSFET have the same gate width and gate length, respectively. It is characterized by being configured.

The invention according to claim 6 is an error amplifying circuit configured by connecting a capacitive element to the output terminal of the voltage-current converter circuit according to any one of claims 1 to 5.
The invention according to claim 7 is the invention according to claim 6, wherein the capacitive element is a fourth resistor and a capacitor connected in series between the output terminal and a reference potential.

  In the voltage-current converter according to the present invention, the current I1 discharged from the power supply (VDD) side by the first current mirror circuit at the output stage and the current I2 flowing into the ground (GND) side by the second current mirror circuit And the gate of the transistors constituting the first and second current mirrors is controlled by the operational amplifier operating in the voltage mode, so that a low offset voltage and a wide output current range are obtained. Can be made compatible. In addition, by connecting a capacitive element to the output terminal of the voltage-current converter circuit, a current output type error amplifier circuit that achieves both a low input offset voltage and a high-speed transient response can be easily realized. The first current mirror input section, the second current mirror input section, and the other end of the resistor connected to the first input terminal of the voltage-current converter circuit are connected to the non-inverting input terminal of the operational amplifier. Then, the second input terminal of the voltage-current conversion circuit is connected to the inverting input terminal of the operational amplifier, and the inverting input terminal and the non-inverting input terminal of the operational amplifier are virtually short-circuited.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram for explaining the basic configuration and operating principle of a voltage-current converter circuit according to the present invention. In FIG. 1, transistors M1 and M3 are P-channel MOSFETs, each of which has a source terminal connected to a power supply VDD and a gate terminal of each other connected in common to form a first current mirror circuit. Let the mirror ratio of the first current mirror circuit be α. The transistors M2 and M4 are N-channel MOSFETs, and their source terminals are connected to the ground potential (GND), and their gate terminals are commonly connected to form a second current mirror circuit. The mirror ratio of the second current mirror circuit is also set to the same α as the mirror ratio of the first current mirror circuit. The drain terminals of the transistors M1 and M2 are connected to the output terminal, and the drain terminals of the transistors M3 and M4 are connected to the non-inverting input terminal of the operational amplifier OP at the node X. The non-inverting input terminal of the operational amplifier OP is also connected to the first input terminal Vin via the input resistor R0. A second input terminal Vref is connected to the inverting input terminal of the operational amplifier OP. The common connection Y of both gates of the transistors M2 and M4 is connected to the output terminal of the operational amplifier OP, and the common connection Z of both gates of the transistors M1 and M3 is connected to the output terminal of the operational amplifier OP via the constant voltage source Vls. ing.

Here, the voltages input to the first and second input terminals Vin and Vref are also Vin and Vref, and the voltage generated by the constant voltage source Vls is Vls. The constant voltage source Vls shifts the potential of the connection part Z by the voltage Vls with respect to the potential of the connection part Y, and the voltage Vls becomes a level shift voltage. By the operation of the operational amplifier OP, the inverting input terminal and the non-inverting input terminal of the operational amplifier OP are virtually short-circuited so that the potential of the node X becomes equal to Vref, and the current Iin flowing from the input terminal Vin to the input resistor R0 is (Vin−Vref) / R. ₀ . R ₀ is the resistance value of the input resistor R ₀ . Further, assuming that currents flowing out from the drain terminals of the transistors M1 and M3 are I1 and I3, currents flowing into the transistors M2 and M4 are I2 and I4, respectively, and current flowing out to the output terminal OUT is Iout, Iin = I4−I3, I1 = I2 + Iout It becomes. From this and the relational expression I1 = αI3 and I2 = αI4, the following equation is derived.

[Equation 10]
Iout = I1−I2 = −α (−I3 + I4) = − αIin (10)
Assuming that the power supply voltage supplied from the power supply VDD is VDD and the potentials of the connecting portions Y and Z are Vy and Vz, respectively, the current I3 is a function of VDD-Vz, and the current I4 is a function of Vy. Vy, Vz, I3, and I4 are determined so as to satisfy the relational expressions of Iin = I4-I3 and Vz = Vy + Vls. If Vls is reduced here, VDD-Vz and Vy increase, and the absolute values of I3 and I4 increase while satisfying Iin = I4-I3. When Vls is increased, VDD−Vz and Vy are decreased, and the absolute values of I3 and I4 are decreased while satisfying Iin = I4−I3. If the voltage Vls is set to a sufficiently large value, the current flowing through the transistors M1 to M4 when Iin = Iout = 0, that is, the current passing through the output stage can be set to 0. In this case, the first and first Even if a deviation occurs between the mirror ratios of the two current mirror circuits, no offset current is generated. However, under this condition, the potentials of the connection portions Y and Z greatly change with respect to the change of the input voltage Vin in the vicinity of Iout = 0. Therefore, if the characteristics of the operational amplifier are not ideal, distortion and transient response It is better to pass a minute current in order to prevent the deterioration.

  The constant voltage source Vls can be configured using a resistor. An example thereof is shown in FIG. In FIG. 2, input terminals IN + and IN− are a non-inverting input terminal and an inverting input terminal of an operational amplifier, respectively, transistors M21, M22, M23, M24 and M25 are P-channel MOSFETs, and transistors M26, M27 and M28 are N-channel MOSFETs. It is. Input terminals IN +, IN−, constant current source Ib, transistors M21, M22, M24, M25, M26, M27, M28, resistor Rc2 and capacitor Cc2 correspond to the operational amplifier OP of FIG. 1, and constant current source Ib and transistor M21, M22 constitutes a bias circuit of the operational amplifier OP, input terminals IN + and IN− and transistors M22, M24, M25, M26 and M27 constitute a differential stage, and a transistor M28, a resistor Rc2 and a capacitor Cc2 constitute an output stage. ing. The resistor Rc2 and the capacitor Cc2 are phase compensation elements of the operational amplifier OP itself. The transistors M21 and M22 of the bias circuit are connected in common with each other to form a mirror circuit so that a constant current determined by the constant current source Ib flows, but the gate terminal of the transistor M23 is also a transistor M21, M22. The transistor M23 is configured to supply a constant current to the resistor Rls by being commonly connected to the gate terminal. If the constant current value supplied from the constant current source Ib is also Ib, and the mirror ratio of the current mirror circuit composed of the transistors M21 and M23 is A, a level shift voltage of Vls = A · Rls · Ib is generated by the resistor Rls. can do.

FIG. 3 shows the operating characteristics of the circuit shown in FIG. The relationship between the input voltage (Vin−Vref) and the currents I1, I2 and I0 when the values of the circuit parameters R ₀ and α are 1 MΩ and 0.2, respectively, is shown. FIG. 3A shows the characteristics when Vls is increased, and FIG. 3B shows the characteristics when Vls is decreased.
As described above, according to the present invention, the source-gate voltage of the transistors M1 to M4 in the vicinity of the output current Iout = 0 is suppressed by the action of the level shift voltage Vls so that the current flowing through the transistors M1 to M4 is reduced. be able to. That is, the input offset voltage generated in the transistors M1 to M4 can be reduced. Further, when the output current Iout is not near 0, the source-gate voltage of the transistors M1 and M3 or the transistors M2 and M4 can be increased, and the current flowing through the transistor can be increased. There is no need to sacrifice the current output range as in the voltage-current converter circuit. The input offset voltage of the operational amplifier OP itself becomes the input offset voltage as the voltage-current conversion circuit as it is, but there is no problem because the value of the input offset voltage is sufficiently smaller than that of the current output type amplifier.

When the error amplifier circuit is configured using the voltage-current converter circuit according to the present invention, a relatively high DC gain is obtained by reducing the current flowing through the transistors M1 to M4 in the vicinity of the output current Iout = 0 as described above. However, in order to obtain a higher DC gain, a cascode-connected MOSFET may be applied as the transistors M1 to M4 as necessary.
Next, an embodiment of an error amplifying circuit using the voltage-current converter circuit according to the present invention will be described with reference to FIG. FIG. 5 shows an example of parameter values of each circuit element of the circuit shown in FIG. 4, the same parts as those in FIGS. 1, 2, 8, and 9 are denoted by the same reference numerals, and detailed description thereof is omitted. This error amplifying circuit realizes a time constant τ = C _C · R ₁ / α = 50 μs, and the DC stable point is Vin = 2Vref (this value can be changed or adjusted by the variable resistor R2). Here, it is assumed that a CMOS process capable of using high-resistance polysilicon is used, and all circuit elements are built in the integrated circuit.

  In FIG. 4, the transistor M10 is a P-channel MOSFET, and the transistors M11 and M12 are N-channel MOSFETs. The drains and gates of the transistors M10 and M12 are connected via a resistor R10. The gates of the transistors M11 and M12 are connected to each other, and the transistors M11 and M12 constitute a current mirror circuit. The transistors M10, M11, M12 and the resistor R10 constitute a bias current generating circuit. The current Ib determined by the characteristics of the power supply voltage VDD, the resistor R10, and the transistors M10, M11 is folded by the current mirror circuit of M11, M12, and the next The bias current Ib is supplied to the operational amplifier of the stage + the level shift circuit and corresponds to the constant current source Ib in the circuit of FIG. 2 (as can be seen from FIG. 5, the mirror ratio of the current mirror circuit composed of M11 and M12) Is 1).

  The operational amplifier + level shift circuit including the transistors M21 to M28, the resistors Rls1 and Rls2, and the capacitor Cc is almost the same as the circuit of FIG. 2 except for the constant current source Ib, but the resistor Rc2 of FIG. The difference is that the two resistors Rls are divided into two resistors Rls1 and Rls2, and one end of the capacitor Cc2 is connected to the connection between the resistors Rls1 and Rls2. In this case, the resistor Rls1 also functions as the phase compensation resistor Rc2. The transistors M1 to M4 constituting the conversion circuit core are the same as those shown in FIG. The resistors R1, R2, Rc and the capacitor Cc are the same as those shown in FIGS. However, the resistor R2 is a variable resistor and can be changed or adjusted as described above. The present embodiment provides a new CCII that can achieve both a low offset voltage and a wide output current range with the configuration of a bias current generation circuit, an operational amplifier + level shift circuit, and a conversion circuit core, compared to the circuit of FIG. The overall operation is the same as in FIG.

In the embodiment shown in FIG. 4, when the output current of the voltage-current converter circuit output from the output stage constituted by the transistors M1 and M2 is 0, the current flowing through the output stage varies by orders of magnitude due to changes in device characteristics. The device which prevents doing is made. The details are as follows.
First, if the characteristics of the transistors constituting the current mirror are uniform (this can be fully expected in an integrated circuit), the mirror ratio of the current mirror circuit composed of the transistors M21 and M23 is 10 as can be seen from FIG. Therefore, the current flowing through the resistors Rls1 and Rls2 is 10 Ib, and the resistance ratio of the series resistors of the resistors R10 (1 MΩ), Rls1 (30 kΩ), and Rls2 (70 kΩ) is 1:10. Therefore, the voltage across the resistor R10 and Rls1 , Rls2 has equal voltage across the series resistance (that is, the potential difference between the gate of the transistor M1 and the gate of the transistor M2). As can be seen from FIG. 5, the transistor M10 and the transistor M1 are configured by the same unit P-channel MOSFET (W (gate width) / L (gate length) = 8 μm / 4 μm), and the transistor M11 and the transistor M2 are the same unit N channel. It is constituted by a MOSFET (W / L = 6 μm / 4 μm), and the unit transistor number ratio (40: 1) between the transistors M10 and M1 is equal to the unit transistor number ratio (40: 1) between the transistors M11 and M2 (in other words, (For example, the unit transistor number ratio (1: 1) of the transistors M10 and M11 is equal to the unit transistor number ratio (1: 1) of the transistors M1 and M2), and the output current of the voltage-current conversion circuit is 0. M10 and M1 gate voltage and transistor M11 The gate voltage of M2 becomes equal to each other. From the unit transistor number ratio, the current flowing through the transistors M1 and M2 is 1/40 of the current flowing through the transistors M10 and M11. As described above, the current Ib flowing through the transistors M10 and M11 is determined by the characteristics of the power supply voltage VDD, the resistor R10 and the transistors M10 and M11. If the power supply voltage VDD is high to some extent, the voltage applied to the resistor R10 increases. Since the main factor that determines Ib is the resistor R10, the influence of fluctuations in MOSFET characteristics can be mitigated. Depending on the process, it is possible to cancel the characteristic variation due to the temperature of the MOSFET by utilizing the temperature characteristic of the resistor.

It is a circuit diagram for demonstrating the basic composition and operating principle of the voltage-current converter circuit which concern on this invention. This is an embodiment of a constant voltage source configured by an operational amplifier and a resistor Rls. It is an operating characteristic of the circuit shown in FIG. It is a circuit diagram of the Example of the error amplifier circuit which concerns on this invention. It is a table | surface which shows the parameter value of each circuit element of the circuit shown in FIG. It is a circuit block diagram which shows the structural example of a switching power supply. It is a figure for demonstrating the conventional error amplifier circuit. It is a figure for demonstrating the error amplifier circuit comprised using the transconductance amplifier. It is a figure for demonstrating the error amplification circuit comprised using the current conveyor circuit. It is a figure for demonstrating the conventional voltage current conversion circuit.

Explanation of symbols

M1, M1, M10, M21 to M25 P-channel MOSFET
M2, M4, M11, M12, M26 to M28 N-channel MOSFET
R0, R1, R2, R3, R10, Rls, Rls1, Rls2 Resistance OP Operational amplifier VDD Power supply (Power supply voltage)
_VIN input terminal (input voltage)
_VOUT output terminal (output voltage)
Vref input terminal (reference voltage)
Vls constant voltage source (level shift voltage)

Claims (7)

The first and second input terminals, the output terminal, the first P-channel MOSFET and the second P-channel MOSFET constituting the first current mirror, the first N-channel MOSFET constituting the second current mirror, and the first Two N-channel MOSFETs, an operational amplifier, bias voltage generating means, and a first resistor,
The ratio of the current flowing through the second P-channel MOSFET to the current flowing through the first P-channel MOSFET is equal to the ratio of the current flowing through the second N-channel MOSFET to the current flowing through the first N-channel MOSFET. The first input terminal and one end of the input resistor are connected, the other end of the input resistor, the drain of the first P-channel MOSFET, the drain of the first N-channel MOSFET, and the operational amplifier And the second input terminal and the inverting input of the operational amplifier are connected, and the output terminal, the drain of the second P-channel MOSFET, and the drain of the second N-channel MOSFET are connected. And the output terminal of the operational amplifier is connected to the first N-channel MOSFET and the Connected to the gate of the second N-channel MOSFET, and the bias voltage generating means is connected between a connection point between the output terminal of the operational amplifier and the gate of the first N-channel MOSFET and the gate of the second N-channel MOSFET. A voltage-current conversion circuit characterized by being connected. 2. The voltage / current converter circuit according to claim 1, wherein the bias voltage generating means is a second resistor having one end connected to the output terminal of the operational amplifier and the other end connected to a constant current source. . A third P-channel MOSFET having a gate terminal and a drain terminal connected between a power supply and a reference potential, a third resistor, and a third N-channel MOSFET having a gate terminal and a drain terminal connected in series, are connected in series. And the ratio of the current flowing through the constant current source to the current flowing through the current generating circuit is set equal to the ratio of the resistance value of the third resistor to the resistance value of the second resistor, The ratio of the W / L ratio of the second N-channel MOSFET to the W / L ratio of the second P-channel MOSFET with respect to the W / L ratio, which is the ratio of the gate width W to the gate length L, and the third 3. The voltage current according to claim 2, wherein a ratio of a W / L ratio of the third N-channel MOSFET to a W / L ratio of the P-channel MOSFET is set to be equal. Circuit. The gate length of the second P-channel MOSFET and the gate length of the third P-channel MOSFET are equal, and the gate length of the second N-channel MOSFET and the gate length of the third N-channel MOSFET are equal. The voltage-current converter circuit according to claim 3. The second P-channel MOSFET and the third P-channel MOSFET are configured by connecting one or a plurality of unit P-channel MOSFETs having the same gate width and gate length in parallel, and the second N-channel MOSFET and 5. The voltage current according to claim 3, wherein the third N-channel MOSFET is configured by connecting one or a plurality of unit N-channel MOSFETs having the same gate width and gate length in parallel. Conversion circuit. 6. An error amplifier circuit comprising a capacitive element connected to the output terminal of the voltage-current converter circuit according to claim 1. The error amplifying circuit according to claim 6, wherein the capacitive element is a fourth resistor and a capacitor connected in series between the output terminal and a reference potential.

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