JP4082796B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having NAND memory cells in which a plurality of memory cells are connected in series.
[0002]
[Prior art]
FIG. 10A is a plan view of a NAND type cell array formed by connecting a plurality of memory cells in series in a conventional nonvolatile semiconductor memory device, and FIG. 10B shows an equivalent circuit thereof. FIG. FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. 10A, and FIG. 11B is a cross-sectional view taken along the line BB ′ in FIG.
[0003]
As can be seen from FIG. 11, each memory cell includes a floating gate FG and a control gate CG. Each memory cell is configured to be able to hold data by storing charges in the floating gate FG or discharging the stored charges.
[0004]
As can be seen from FIG. 10 and FIG. 11, in the nonvolatile semiconductor memory device according to this prior art, NAND memory cells are constituted by 16 memory cells M (1) to M (16). That is, 16 memory cells M (1) to M (16) are connected in series so as to share the source / drain region SD, thereby forming a NAND memory cell. A selection gate SG (1) is provided on the drain side of the memory cell M (1), and a selection gate SG (2) is provided on the source side of the memory cell M (16). As can be seen from FIG. 11A in particular, each of these selection gates SG (1) and SG (2) is composed of two selection lines. Here, the 16 floating gates FG (1) to FG (16) and the 16 control gates CG (1) to (16) are all formed with the same dimensions.
[0005]
As can be seen from FIG. 11A, a drain region D connected to the bit line BL is formed on the drain side of the select gate SG (1). A portion connected to the bit line BL forms a bit line contact BC shown in FIG. As can be seen from FIG. 11A, a source region S connected to the source line is formed on the source side of the selection gate SG (2). A portion connected to the source line forms a source line contact SC shown in FIG.
[0006]
[Problems to be solved by the invention]
Reading data in the nonvolatile semiconductor memory device having the NAND type cell array as described above is performed by setting the control gate CG of the selected memory cell M to 0 V and applying an on-voltage to the other control gates CG. It is determined how much the voltage applied to BL is reduced before being transmitted to the source region S. That is, it is determined whether the cell current flows or not.
[0007]
At this time, even if each memory cell M has the same neutral threshold value, the substrate bias due to the cell current flowing between the memory cell M close to the bit line BL and the memory cell far from the bit line BL. Due to the effect, variation occurs when the neutral threshold is viewed as a NAND type cell array. Here, the neutral threshold value refers to a threshold value in a state in which no charge is accumulated in the floating gate FG of each memory cell M or is not swept out. In other words, this is the threshold value when the number of electrons and the number of holes in the floating gate FG are the same, and therefore in a neutral state. FIG. 12 shows the relationship between the memory cells M (1) to M (16) of the NAND type memory cell and the neutral threshold value.
[0008]
FIG. 12 is a graph showing the result of measuring the neutral threshold value of each of the memory cells M (1) to M (16) by irradiating the NAND type cell array shown in FIGS. 10 and 11 with ultraviolet rays. As can be seen from FIG. 12, the memory cell M closer to the bit line BL has a higher neutral threshold value than the memory cell M far from the bit line BL. In other words, the neutral threshold value decreases in order from the memory cell M (1) close to the bit line BL to the memory cell M (16) far from the bit line BL. Thus, when the neutral threshold value of the memory cell M varies, the variation of the neutral threshold value of the entire NAND memory cell is expanded. If the dispersion of the neutral threshold value of the entire NAND type memory cell increases, the yield of the product decreases, which causes a problem in terms of reliability.
[0009]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that suppresses variations in the neutral threshold value of the entire NAND memory cell. It is another object of the present invention to provide a nonvolatile semiconductor memory device in which the yield of products is improved and the reliability is improved by suppressing variations in the neutral threshold value of the entire memory cell.
[0010]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device according to the present invention is
A memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate, and adjacent ones are connected in series so as to share a source / drain region of the first conductivity type to form a NAND type memory cell A nonvolatile semiconductor memory device comprising a plurality of
Each of the memory cells includes a channel implantation region of a second conductivity type different from the first conductivity type below the floating gate,
The impurity concentration of the second conductivity type in the channel implantation region of the memory cell upstream of the cell current is equal to the channel implantation of the memory cell downstream of the cell current with respect to the direction in which the cell current flows during reading of the NAND memory cell. The region is lower than the impurity concentration of the second conductivity type in the region.
In addition, the nonvolatile semiconductor memory device according to the present invention includes:
A non-volatile memory comprising a plurality of memory cells in which a floating gate and a control gate are stacked on a semiconductor substrate and connected in series so that adjacent ones share a source / drain region to form a NAND memory cell A semiconductor memory device,
The channel length of the memory cell on the upstream side of the cell current is shorter than the channel length of the memory cell on the downstream side of the cell current with respect to the direction in which the cell current flows during reading of the NAND memory cell.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
According to the first embodiment of the present invention, in a nonvolatile semiconductor memory device having NAND type memory cells, the impurity concentration in the channel implantation region of each memory cell increases as the cell current of each memory cell flows. By doing so, the neutral threshold value of each memory cell is sequentially increased so as to cancel the influence of the neutral threshold value due to the substrate bias effect at the time of reading. More details will be described below.
[0012]
FIG. 1 is a plan view showing a NAND memory cell of the nonvolatile semiconductor memory device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along the line CC ′ in FIG.
[0013]
As can be seen from FIG. 1, each of the 16 memory cells M (1) to M (16) constituting the NAND type memory cell has a control gate CG (1) to CG (16) and a floating gate FG (1), respectively. ) To FG (16). A selection gate SG (1) is provided on the drain side of the NAND type memory cell, and a selection gate SG (2) is provided on the source side. A bit line contact BC is formed on the drain side of the selection gate SG (1). A source line contact SC is formed on the source side of the selection gate SG (2).
[0014]
As can be seen from FIG. 2, the memory cells M (1) to M (16) are formed on the P-type semiconductor substrate 10. Each of the memory cells (1) to M (16) has an N-type transistor structure in which an N-type impurity is diffused after gate processing. It is the impurity concentration of the channel implantation regions 12 (1) to 12 (16) that determines the neutral threshold value of each of the memory cells M (1) to M (16). The dose of the impurity (boron) in the channel implantation regions 12 (1) to 12 (16) in the NAND type memory cell according to the present embodiment is 3E12 cm ^{−3 as} it goes from the bit line contact BC to the source line contact SC. from to 4.5E12cm ^-3, it is changing 0.1E12cm ^-3 increments. That is, the boron dose of the channel implantation region 12 (1) of the memory cell M (1) is 3E12 cm ⁻³ , and the boron dose of the channel implantation region 12 (2) of the memory cell (2) is 3.1E12 cm. ^-3 . The memory cells M (3)... Thereafter are increased in dose every 0.1E12 cm ^{−3 in the same} manner as above, and the boron dose in the channel implantation region 12 (15) of the memory cell 12 (15) is a 4.4E12cm ^-3, boron dose of channel implantation region 12 (16) of the memory cell 12 (16) is 4.5E12cm ^-3.
[0015]
As described above, the impurity dose in the channel implantation regions 12 (1) to 12 (16) is increased from the bit line contact BC side, which is the direction in which the cell current flows, toward the source line contact SC. The neutral threshold value of the memory cell M (1) is the lowest, and the neutral threshold value increases from the memory cell M (1) toward the source line contact SC. The neutral threshold is configured to be the highest.
[0016]
The channel implantation regions 12 (1) to 12 (16) of the NAND type memory cell as shown in FIGS. 1 and 2 can be obtained by the following manufacturing process.
[0017]
First, a resist having an opening on the channel implantation region 12 (1) is formed by a lithography process. Then, boron is implanted from above the resist at a concentration of 3E12 cm ⁻³ to form a channel implantation region 12 (1). Next, a resist having an opening on the channel implantation region 12 (2) is formed by a lithography process. Then, boron is implanted from above the resist at a concentration of 3.1E12 cm ⁻³ to form a channel implantation region 12 (2). Next, a resist having an opening on the channel implantation region 12 (3) is formed by a lithography process. Then, boron is implanted from above the resist at a concentration of 3.2E12 cm ⁻³ to form a channel implantation region 12 (3).
[0018]
In this manner, the process of increasing the boron dose by 0.1E12 cm ⁻³ is repeated to sequentially form the channel implant region 12 (4) and the subsequent layers. Finally, a resist having an opening on the channel implantation region 16 (16) is formed by a lithography process. Then, boron is implanted from above the resist at a concentration of 4.5E12 cm ⁻³ to form a channel implantation region 12 (16).
[0019]
In the nonvolatile semiconductor memory device having the NAND type memory cell as described above, for example, 2V is applied to the bit line BL and 0V is applied to the source line at the time of reading. In this case, the cell current flows from the bit line contact BC portion toward the source line contact SC portion. At this time, due to the substrate bias effect, even in the memory cell M having the same neutral threshold value, the neutral threshold value when the cell current flows is lowered as it goes toward the source line contact SC. Act on. However, as described above, the NAND type memory cell according to the present embodiment is configured such that the neutral threshold value is higher in the memory cell M on the source line contact SC side when no cell current flows. . For this reason, the change in the neutral threshold due to the substrate bias effect at the time of reading can be canceled.
[0020]
FIG. 3 is a graph showing the result of measuring the neutral threshold value by irradiating the NAND type memory cell shown in FIGS. 1 and 2 with ultraviolet rays. As can be seen from FIG. 3, the neutral threshold value of each of the memory cells M (1) to M (16) of the NAND type memory cell becomes substantially constant in a state where a cell current flows. Therefore, by using the NAND memory cell according to the present embodiment, a highly reliable nonvolatile semiconductor memory device in which the amount of charge of the floating gate FG is small in each memory cell with little variation in the neutral threshold value is obtained. be able to.
[0021]
In the first embodiment, in order to reduce the number of lithography processes and the number of implantation processes, the channel implantation regions 12 (1) to 12 (16) can be grouped into a predetermined group unit. For example, the channel implantation regions 12 (1) to 12 (8) of the memory cells M (1) to M (8) are formed as one group with the same impurity concentration, and the memory cells M (9) to M (16) are formed. ) Of channel implantation regions 12 (9) to 12 (16) as a group can be formed with the same impurity concentration as that of the channel implantation regions 12 (1) to 12 (8).
[0022]
In this case, a resist having an opening is collectively formed on the channel implantation regions 12 (1) to 12 (8), and boron implantation is performed at a dose of 3.3E12 cm ⁻³ , for example. Next, a resist having openings provided together on the channel implantation regions 12 (9) to 12 (16) is formed, and boron implantation is performed at a dose of 4.0E12 cm−3, for example. By doing in this way, the number of processes of a lithography process and an implantation process can be reduced. Moreover, even if the NAND type memory cell has such a configuration, it is possible to suppress variations in the neutral threshold when a cell current flows, compared to the conventional case.
[0023]
In addition, the channel implantation regions 12 (1) to 12 (16) are not necessarily divided into two equal parts of the channel implantation regions 12 (1) to 12 (8) and 12 (9) to 12 (16). . For example, a resist having an opening is formed by lithography only on the channel implantation region 12 (16) of the memory cell M (16) closest to the source line contact SC, and boron implantation is performed with a dose amount of 3.1E12 cm ^−3. . Next, a resist having an opening is formed by lithography on the channel implantation regions 12 (1) to 12 (15) of the remaining memory cells M (1) to M (15), and the dose is 3.0E12 cm ^−3. Boron implantation may be performed.
[0024]
Furthermore, these lithography process and implantation process can also serve as these processes for the select gates SG (1) and SG (2). It can also serve as these steps of the peripheral circuit.
[0025]
Contrary to the above-described embodiment, when reading, a voltage of 2 V, for example, is applied to the source line, and, for example, 0 V is applied to the bit line BL, and the cell current flows from the source line side to the bit line BL side. There is also. In such a case, contrary to the above-described embodiment, the neutral threshold value of the memory cell M may be set so as to increase from the source line contact SC toward the bit line contact BC.
[0026]
[Second Embodiment]
According to the second embodiment of the present invention, in a non-volatile semiconductor memory device having NAND type memory cells, the gate length of the memory cell is increased as it goes in the direction in which the cell current of each memory cell flows. The neutral threshold value of each memory cell is sequentially increased to cancel the influence of the neutral threshold value due to the substrate bias effect at the time of reading. More details will be described below.
[0027]
FIG. 4 is a plan view showing a NAND type cell array of the nonvolatile semiconductor memory device according to this embodiment, and FIG. 5 is a cross-sectional view along the line DD ′ in FIG.
[0028]
As can be seen from FIG. 4, the nonvolatile semiconductor memory device according to this embodiment is configured such that the gate lengths of the memory cells M (1) to M (16) are gradually increased from the bit line contact BC side. Yes. Specifically, the gate length of the control gate CG (1) and the floating gate FG (1) of the memory cell M (1) is set to 0.2 μm, and the control gate CG (2) and the floating gate of the memory cell M (2) are set. The gate length of FG (2) is set to 0.21 μm. Thus, the gate length is increased by 0.01 μm from the bit line contact BC toward the source line contact SC. Thus, when the gate length is increased by 0.01 μm, the gate length of the control gate CG (16) and the floating gate FG (16) of the memory cell M (16) becomes 0.35 μm. By configuring the gate length in this way, the neutral threshold value of the memory cell M having a short gate length is lowered and the neutral threshold value of the memory cell M having a long gate length is increased due to the short channel effect of the transistor. Become.
[0029]
In the nonvolatile semiconductor memory device having the NAND type memory cell as described above, for example, 2V is applied to the bit line BL and 0V is applied to the source line at the time of reading. In this case, the cell current flows from the bit line contact BC portion toward the source line contact SC portion. At this time, due to the substrate bias effect, even in the memory cell M having the same neutral threshold, the neutral threshold acts so as to decrease toward the source line contact SC. However, since the NAND type memory cell according to the present embodiment is configured such that the gate length increases from the bit line contact BC toward the source line contact SC as described above, in a state where no cell current flows. The memory cell on the source line contact SC side has a higher neutral threshold value. For this reason, the change in the neutral threshold due to the substrate bias effect at the time of reading can be canceled.
[0030]
The above-described graph shown in FIG. 3 can be obtained even when the neutral threshold value is measured by irradiating the NAND type memory cell shown in FIGS. 4 and 5 with ultraviolet rays. That is, it is possible to obtain a highly reliable nonvolatile semiconductor memory device in which the amount of charge in the floating gate FG is small in each memory cell and the neutral threshold variation is small.
[0031]
In the second embodiment, the gate length can be grouped in a predetermined memory cell unit in order to suppress an increase in cell area. For example, as shown in FIG. 6, the gate length of the memory cells M (1) to M (8) is 0.2 μm, and the gate length of the memory cells M (9) to M (16) is 0.21 μm. Is also possible. As a result, an increase in the cell area can be suppressed, and an improvement in variations in the neutral threshold value of the memory cell can be expected.
[0032]
Furthermore, only the gate length of the memory cell M (16) that is the most downstream side through which the cell current flows can be made longer than the gate lengths of the other memory cells M (1) to M (15). For example, the gate length of the memory cells M (1) to M (15) can be 0.2 μm, and the gate length of the memory cell M (16) can be 0.21 μm.
[0033]
Contrary to the above-described embodiment, when reading, a voltage of 2 V, for example, is applied to the source line, and, for example, 0 V is applied to the bit line BL, and the cell current flows from the source line side to the bit line BL side. There is also. In such a case, contrary to the above-described embodiment, the gate length of the memory cell M may be configured to increase from the source line contact SC toward the bit line contact BL.
[0034]
[Third Embodiment]
According to the third embodiment of the present invention, in a nonvolatile semiconductor memory device having NAND type memory cells, the gate length of the memory cell provided closest to the bit line contact is the shortest and provided closest to the source line contact. Neutral threshold value due to substrate bias effect at the time of reading by making the gate length of the memory cell the longest and aligning the gate length of other memory cells provided between these memory cells with the intermediate gate length The effect of canceling is canceled. More details will be described below.
[0035]
FIG. 7 is a plan view showing a NAND cell array of the nonvolatile semiconductor memory device according to this embodiment, and FIG. 8 is a cross-sectional view taken along the line EE ′ in FIG.
[0036]
As can be seen from FIG. 7, the interval between the selection gate SG (1) and the control gate CG (1) and the interval between the selection gate SG (2) and the control gate SG (16) are adjusted according to the processing of the slit portion. Considering this, the interval between the other control gates SC (2) to CG (15) is set wider. In this case, it is noted that only the control gates CG (1) and CG (16) are thinner than the others even if etching is performed with a resist having an opening with the same gate length due to the loading effect of the lithography process in the manufacturing process. There is a need to.
[0037]
The gate dimensions on the mask at the time of PEP are 0.2 μm for the memory cells M (1) to M (15), and only 0.22 μm for the memory cell M (16). When the thinning due to the loading effect is 0.01 μm, the memory cell gate length in this embodiment is 0.19 μm for the memory cell M (1), 0.20 μm for the memory cells M (2) to M (15), the memory Cell M (16) is formed at 0.21 μm. Therefore, when viewed from a single cell, the neutral threshold value of the memory cell M (1) is the lowest, and the neutral threshold values of the memory cells M (2) to M (15) are higher than this. The neutral threshold value of M (16) is the highest.
[0038]
In the nonvolatile semiconductor memory device having the NAND type memory cell as described above, for example, 2V is applied to the bit line BL and 0V is applied to the source line at the time of reading. In this case, the cell current flows from the bit line contact BC portion toward the source line contact SC portion. At this time, due to the substrate bias effect, even in the memory cell M having the same neutral threshold, the neutral threshold acts so as to decrease toward the source line contact SC. However, the NAND memory cell according to the present embodiment is configured such that the gate length becomes longer in the order of the memory cells M (1), M (2) to M (15), and M (16) as described above. Therefore, when the cell current does not flow, the neutral threshold value is higher in the memory cell on the source line contact SC side. For this reason, the change in the neutral threshold due to the substrate bias effect at the time of reading can be canceled. Therefore, it is possible to obtain a highly reliable nonvolatile semiconductor memory device in which the amount of charge of the floating gate FG with little neutral threshold variation is constant in each memory cell.
[0039]
FIG. 9 is a graph showing the result of measuring the neutral threshold value by irradiating the NAND type memory cell shown in FIGS. 7 and 8 with ultraviolet rays. As can be seen from FIG. 9, the variation in the neutral threshold value of each of the memory cells M (1) to M (16) of the NAND type memory cell in the state where the cell current flows can be suppressed as compared with the conventional case. Therefore, by using the NAND memory cell according to the present embodiment, a highly reliable nonvolatile semiconductor memory device in which the amount of charge of the floating gate FG is small in each memory cell with little variation in the neutral threshold value is obtained. be able to.
[0040]
Note that the present invention is not limited to the above embodiment, and various modifications can be made, and the impurity concentration, the gate length, and the like given in the above embodiment are merely examples.
[0041]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, the neutral threshold value of the memory cell is set in the memory cell provided on the upstream side with respect to the direction in which the current flows during reading. Since the neutral threshold value of the memory cell provided downstream is higher than the neutral threshold value, the influence of the neutral threshold value due to the substrate bias effect at the time of reading can be canceled. It is possible to provide a highly reliable memory in which the floating gate charge amount is small in each memory cell and the neutral threshold variation is small.
[Brief description of the drawings]
FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 3 is a graph showing a neutral threshold when a cell current is passed through each memory cell in the nonvolatile semiconductor memory device according to the first and second embodiments of the present invention.
FIG. 4 is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the invention.
FIG. 5 is a cross-sectional view of a nonvolatile semiconductor memory device according to a second embodiment of the invention.
FIG. 6 is a plan view showing a modification of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
FIG. 7 is a plan view of a nonvolatile semiconductor memory device according to a third embodiment of the invention.
FIG. 8 is a cross-sectional view of a nonvolatile semiconductor memory device according to a third embodiment of the invention.
FIG. 9 is a graph showing a neutral threshold when a cell current is passed through each memory cell in a nonvolatile semiconductor memory device according to a third embodiment of the present invention.
10A is a plan view of a conventional nonvolatile semiconductor memory device, and FIG. 10B is an equivalent circuit diagram of the conventional nonvolatile semiconductor memory device.
11A is a cross-sectional view taken along line AA ′ in FIG. 10, and FIG. 11B is a cross-sectional view taken along line BB ′ in FIG.
FIG. 12 is a graph showing a neutral threshold value when a cell current is passed through each memory cell in a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
SG (1), SG (2) Select gates CG (1) -CG (16) Control gates FG (1) -FG (16) Floating gates M (1) -M (16) Memory cell BC Bit line contact SC Source Line contact BL Bit line 10 Semiconductor substrate 12 Channel implantation region

Claims (6)

A memory cell in which a floating gate and a control gate are stacked on a semiconductor substrate, and adjacent ones are connected in series so as to share a source / drain region of the first conductivity type to form a NAND type memory cell A nonvolatile semiconductor memory device comprising a plurality of
Each of the memory cells includes a channel implantation region of a second conductivity type different from the first conductivity type below the floating gate,
The impurity concentration of the second conductivity type in the channel implantation region of the memory cell upstream of the cell current is equal to the channel implantation of the memory cell downstream of the cell current with respect to the direction in which the cell current flows during reading of the NAND memory cell. A non-volatile semiconductor memory device, wherein the concentration is lower than the impurity concentration of the second conductivity type in the region. 2. The nonvolatile semiconductor memory according to claim 1, wherein the impurity concentration of the second conductivity type in the channel implantation region of the memory cell increases sequentially from the upstream side to the downstream side of the cell current. apparatus. The impurity concentration of the second conductivity type in the channel implantation region of the memory cell is sequentially increased in units of groups in which one or a plurality of memory cells are grouped from the upstream side to the downstream side of the cell current. The nonvolatile semiconductor memory device according to claim 1. A non-volatile memory comprising a plurality of memory cells in which a floating gate and a control gate are stacked on a semiconductor substrate and connected in series so that adjacent ones share a source / drain region to form a NAND memory cell A semiconductor memory device,
Nonvolatile, characterized in that a channel length of a memory cell on the upstream side of the cell current is shorter than a channel length of a memory cell on the downstream side of the cell current with respect to a direction in which the cell current flows during reading of the NAND memory cell Semiconductor memory device.   5. The nonvolatile semiconductor memory device according to claim 4, wherein the channel length of the memory cell increases sequentially from the upstream side to the downstream side of the cell current.   5. The nonvolatile memory according to claim 4, wherein a channel length of the memory cell is sequentially increased in units of groups in which one or a plurality of memory cells are gathered from the upstream side to the downstream side of the cell current. Semiconductor memory device.

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