JP4082553B2 - DRAM control apparatus and control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DRAM control apparatus and control method for reading data randomly from a plurality of DRAMs (dynamic random access memories) at high speed by an interleaving method, and in particular, reducing the number of DRAMs required for reading data in real time. The present invention relates to a DRAM control device and a control method.
[0002]
[Prior art]
A DRAM used for a storage device of an information processing device accumulates data with a charge of a minute capacitor, so that data disappears due to leakage current over time. For this reason, it is necessary to refresh the memory contents at regular intervals, and the DRAM cannot be accessed during the refresh. In a general information processing apparatus, when DRAM refresh and memory access overlap, the memory access is weighted.
[0003]
However, depending on the device using the DRAM, the memory access wait may not be permitted. For example, a semiconductor test apparatus that inspects the electrical characteristics of a semiconductor integrated circuit (IC device) provides predetermined test pattern data to a device under test, and uses the output data of the device under test to perform basic operations and functions of the device under test. It is a device that inspects for problems. The test pattern data is stored in a plurality of DRAMs in the semiconductor test apparatus, and is read from the plurality of DRAMs in an interleaved manner according to a required test rate. In such a semiconductor test apparatus, it is necessary to supply test pattern data to a device under test in real time, and a memory access wait is not allowed.
[0004]
[Problems to be solved by the invention]
Conventionally, when interleaving is performed in a device that needs to read data in real time, the DRAM read time and the refresh operation time (hereinafter referred to as “refresh operation time”) so that the DRAM refresh and memory access do not overlap. ) To the DRAM cycle time. Therefore, there is a problem that the cycle time of the DRAM becomes long and the number of DRAMs necessary for interleaving increases.
[0005]
FIG. 3 is a configuration diagram of a DRAM control device of a conventional semiconductor test apparatus, and FIG. 4 is an explanatory diagram of its operation. In FIG. 3, access control circuits 61 to 68 are circuits for performing read (read) control of the DRAMs 71 to 78, respectively, which receive a selection signal from the selection control circuit 53 by inputting a common address signal 50. The read control signal for reading data from the address (address) of the DRAM designated by the address signal 50 is output to the corresponding DARM. The selection circuit 54 selects data read from the DRAMs 71 to 78 in accordance with a selection signal from the selection control circuit 53 and outputs a data signal 80. The DRAMs 71 to 78 that have been read by the access control circuits 61 to 68 are refreshed by a refresh control circuit (not shown) every time reading is completed.
[0006]
FIG. 4 shows the operation when the DRAM read time (Tread) is 100 ns (nanoseconds), the refresh operation time (Tref) is 100 ns, and the read cycle time (Tac) desired for interleaving is 25 ns. The cycle time of each of the DRAMs 71 to 78 is 200 ns as the sum (Tread + Tref) of the read time (Tread) and the refresh operation time (Tref). Therefore, the number of DRAMs required for interleaving is eight or more, which is the quotient ((Tread + Tref) / Tac) obtained by dividing the DRAM cycle time (Tread + Tref) by the desired read cycle time (Tac).
[0007]
An object of the present invention is to provide a DRAM control device and a control method capable of reading data in real time with a small number of DARMs when reading data from a plurality of DRAMs by an interleave method.
[0008]
[Means for Solving the Problems]
The DRAM controller according to the present invention is a DRAM controller that reads data from a plurality of DRAMs in an interleaved manner. The number of DRAMs necessary for interleaving when no refresh is performed and the number of DRAMs that perform refresh at a time. A total of (n + m) DRAMs combined with the number m, and (n + m) DRAMs that select and control the DRAM to be read and the DRAM to be refreshed out of the (n + m) DRAMs. In the DRAM, n is a whole number equal to or greater than the quotient obtained by dividing the read time of one DRAM by the read cycle time desired by interleaving, and the percentage of time in which a DRAM can be read out of the refresh cycle and the total number of DRAMs An integer m is determined so that the product of (n + m) is n or more, and selection control means , Sequentially as the refresh state of m DRAM at a time, in which the rest of the n DRAM and readable state therebetween.
[0009]
Further, the DRAM control method according to the present invention is a DRAM control method for reading data from a plurality of DRAMs in an interleaved manner. The number n of DRAMs necessary for interleaving when no refresh is performed is calculated by reading one DRAM. Let the time be an integer greater than or equal to the quotient divided by the desired read cycle time in interleaving, and the number of DRAMs to be refreshed at a time, m, the percentage of time in the refresh cycle that can be read for one DRAM and the total number of DRAMs (N + m) DRAMs are prepared as integers whose product of (n + m) is n or more, and among the (n + m) DRAMs, m DRAMs are sequentially refreshed at a time, and the remaining n The DRAM is made readable.
[0010]
An integer n equal to or greater than the quotient obtained by dividing the read time of one DRAM by the read cycle time desired for interleaving indicates the number of DRAMs required for interleaving when no refresh is performed. Also, the product of the ratio of the time in which a DRAM can be read out of the refresh cycle and the number of DRAMs (n + m) indicates the average number of DRAMs in a readable state. Therefore, in the present invention, the value of m is determined so that the average number of DRAMs in a readable state is equal to or greater than the number n of DRAMs necessary for interleaving when no refresh is performed.
[0011]
According to the present invention, n or more DRAMs are always readable by the action of the selection control means, so that data can be read in real time without waiting for memory access. Then, by determining the number of DRAMs (n + m) as described above, interleaving can be performed with a small number of DRAMs in total (n + m).
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a DRAM control device of a semiconductor test apparatus according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. In FIG. 1, a read control circuit 11 is a circuit for performing read (read) control provided in common to the DRAMs 31 to 35. The read control circuit 11 receives an address signal 10 and inputs an address (DRAM) specified by the address signal 10 ( A read control signal 20 for reading data from the address is output. The refresh control circuit 12 is a circuit for performing refresh control provided in common to the DRAMs 31 to 35, and outputs a refresh control signal 30 for refreshing the DRAMs 31 to 35 at regular intervals, which will be described later.
[0013]
The selection control circuit 13 is a circuit that selects and controls the DRAM to be read and the DRAM to be refreshed among the DRAMs 31 to 35, and outputs a selection signal to the selection circuits 21 to 25 and the selection circuit 14. Upon receiving the selection signal from the selection control circuit 13, the selection circuits 21 to 25 transfer the read control signal 20 from the read control circuit 11 or the refresh control signal 30 from the refresh control circuit 12 to the corresponding DRAMs 31 to 35. The selection circuit 14 selects data read from the DRAMs 31 to 35 in accordance with a selection signal from the selection control circuit 13 and outputs a data signal 40.
[0014]
FIG. 2 shows a DRAM read time (Tread) of 100 ns (nanoseconds), a refresh operation time (Tref) of 100 ns, an interleaved desired read cycle time (Tac) of 25 ns, and a refresh cycle (Tcyc) for one DRAM. Shows the operation in the case of 1500 ns. Note that the refresh cycle (Tref) of the DRAM is generally much longer than the read time (Tread). However, in the present embodiment, the above-described time is illustrated for easy understanding of the invention. .
[0015]
First, the number of DARMs necessary in this case (n + m) will be described. The quotient (Tread / Tac) obtained by dividing the read time (Tread) of one DRAM by the desired read cycle time (Tac) by interleaving is 4. An integer n greater than or equal to the quotient indicates the number of DRAMs required for interleaving when no refresh is performed. In the present embodiment, n is set to 4, which is the minimum required number.
[0016]
On the other hand, the time in which one DRAM can be read is the difference (Tcyc− (Tref + 2 × Tread) obtained by subtracting the refresh operation time (Tref) and the time (2 × Tread) overlapping with previous and subsequent readings from the refresh cycle (Tcyc). )). Therefore, an integer such that the product of the ratio of the refresh cycle time ((Tcyc− (Tref + 2 × Tread)) / Tcyc) of one DRAM and the number of DRAMs (n + m) is n or more. When m is determined, m is 1 or more. At this time, this product indicates the average number of DRAMs in a readable state.
[0017]
Accordingly, in this case, the number of DRAMs (n + m) required for interleaving is 5 or more. In the present embodiment, m is the minimum required number of 1 and the number of DRAMs (n + m) is 5. Incidentally, in the conventional apparatus shown in FIGS. 3 and 4, the number of DRAMs required for interleaving under the same conditions is 8 or more.
[0018]
Next, the operation of the DRAM control device will be described. In FIG. 2, the three-digit number indicated by the lead line of the address signal 10 indicates the address (address) of the DRAM that designates reading. The three-digit number indicated by the leader line of the data signal 40 indicates the address (address) of the DRAM where the read data is stored.
[0019]
In the present embodiment, first, the DRAM 32 is selected by the selection control circuit 13 in response to the reading designation at address 000 of the address signal 10, and data is read from address 000 of the DRAM 32. The DRAM 33 is selected by the selection control circuit 13 for the read designation of the address 001, the DRAM 34 is selected for the read designation of the address 002, and the DRAM 35 is selected by the selection control circuit 13 for the read designation of the address 003. Data is read from address 002, address 003.
[0020]
Subsequently, the DRAM 32 that has finished reading data from address 000 is selected by the selection control circuit 13 in response to the read designation at address 004 of the address signal 10, and data is read from address 004 of the DRAM 32. On the other hand, at this time, the DRAM 31 is selected to be refreshed by the selection control circuit 13, and the refresh of the DRAM 31 is started. The DRAM 31 is ready for reading after the refresh is completed after the refresh operation time (Tref). At that time, the DRAM 31 is selected by the selection control circuit 13 in response to the reading designation at the address 050 of the address signal 10, and data is read from the address 050 of the DRAM 31. Thereafter, reading and refreshing of data from the DRAMs 31 to 35 are performed in the same manner.
[0021]
In the present embodiment, since m is set to 1, the selection control means 13 sets one DRAM at a time in the refresh state, and sets the remaining four DRAMs in a readable state during that time. A time (Tcyc / (n + m)) indicated by an arrow in FIG. 2 indicates a time interval from the start of refresh of one DRAM to the start of refresh of the next DRAM. The refresh control circuit 12 A refresh control signal 30 is output at every interval.
[0022]
In the present embodiment, the refresh of the next DRAM 32 is started after a time (Tcyc / (n + m)) after the refresh of the DRAM 31 is started, and the refresh of the next DRAM 33 is started after a further time (Tcyc / (n + m)). The Thereafter, the DRAMs 34 to 35 are similarly refreshed, and the DRAM 31 starts refreshing again after a refresh cycle (Tcyc) after the first refresh is started.
[0023]
In the embodiment described above, the values of n and m are the minimum required numbers, but n and m may be more than that within the range of reducing the number of DRAMs. Needless to say, the DRAM control apparatus and control method of the present invention are not limited to the read time, the refresh operation time, the read cycle time desired for interleaving, the refresh cycle, and the like exemplified in the above embodiment.
[0024]
【The invention's effect】
According to the DRAM control device and the control method of the present invention, when data is read from a plurality of DRAMs by an interleave method, data can be read in real time with a small number of DARMs. Therefore, a device that needs to read data in real time can be configured in a small size at low cost, and a large-capacity device can be easily configured.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a DRAM control device of a semiconductor test apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the operation of the DRAM control device of the semiconductor test apparatus according to the embodiment of the present invention.
FIG. 3 is a configuration diagram of a DRAM control device of a conventional semiconductor test apparatus.
FIG. 4 is an explanatory diagram of the operation of a DRAM control device of a conventional semiconductor test apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Read control circuit 12 ... Refresh control circuit 13 ... Selection control circuit 14 ... Selection circuits 21-25 ... Selection circuits 31-35 ... DRAM

Claims (2)

In a DRAM controller that reads data from a plurality of DRAMs in an interleaved manner,
A total number (n + m) of DRAMs including the number n of DRAMs necessary for interleaving when no refresh is performed and the number m of DRAMs that are refreshed at a time ;
Selection control means for selecting and controlling a DRAM for reading and a DRAM for refreshing among the (n + m) DRAMs,
In the (n + m) DRAMs, an integer equal to or greater than the quotient obtained by dividing the read time of one DRAM by the read cycle time desired by interleaving is n, and the time in which one DRAM is in a readable state in the refresh cycle. An integer m is determined so that the product of the ratio and the total number of DRAMs (n + m) is n or more,
The DRAM control apparatus according to claim 1, wherein the selection control means sequentially sets m DRAMs at a time in a refreshed state, and sets the remaining n DRAMs in a readable state. In a DRAM control method for reading data from a plurality of DRAMs in an interleaved manner,
The number n of DRAMs required for interleaving when no refresh is performed is an integer greater than or equal to the quotient obtained by dividing the read time of one DRAM by the read cycle time desired for interleaving,
Assuming that the number m of DRAMs to be refreshed at a time is an integer in which the product of the percentage of time in which one DRAM can be read out of the refresh cycle and the total number of DRAMs (n + m) is n or more , (n + m) Prepared DRAM,
A DRAM control method characterized in that, among the (n + m) DRAMs, m DRAMs are sequentially refreshed at a time, and the remaining n DRAMs are in a readable state during that time.

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