JP4082409B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device comprising a step of dividing a substrate product having a nitride semiconductor layer formed on a GaN-based compound substrate into a plurality of semiconductor devices.

  In recent years, short wavelength LEDs such as blue LEDs and ultraviolet LEDs have been actively developed and put into practical use. As a semiconductor used for the light emitting layer of these LEDs, a nitride semiconductor having a relatively large band gap is used. Conventionally, a nitride semiconductor has been formed on an insulating sapphire substrate. However, recently, a high-quality GaN-based compound substrate has been obtained, and an LED having a structure in which a nitride semiconductor layer is formed on the main surface of the GaN-based compound substrate has been proposed.

  For example, when manufacturing a nitride semiconductor device such as the LED described above, a nitride semiconductor layer is epitaxially grown on a wafer made of a GaN compound, and then the device is formed by dividing the wafer into chips. The method is common. Conventionally, in such a manufacturing method, when dividing a wafer into chips, a dividing method such as blade dicing or braking has been used. Moreover, since the cutting surface of the nitride semiconductor layer on the wafer becomes rough in these dividing methods, the nitride semiconductor layer and the wafer are etched to a predetermined depth along the dividing line in advance, and then the wafer is divided by the dividing method described above. Many methods are used.

Although not a technique for dividing a wafer, as a technique related to the present invention, a single crystal gallium nitride substrate disclosed in Patent Document 1 and a manufacturing method thereof, and a nitride semiconductor etching method disclosed in Patent Document 2 are disclosed. There is.
JP 2003-183100 A Japanese Patent Laid-Open No. 10-233385

  When the nitride semiconductor layer and the wafer are etched to a predetermined depth in advance before performing blade dicing or breaking, anisotropic etching such as dry etching is generally used. However, in dry etching, the side surface of the nitride semiconductor layer is damaged, and the electrical characteristics of the device are limited.

  Further, when the nitride semiconductor layer and the wafer are etched, a mask is formed on the semiconductor layer, and when the wet etching is performed through the mask, the shape of the side surfaces of the nitride semiconductor layer and the wafer for isotropic etching. It becomes difficult to control. On the other hand, Patent Document 2 discloses a technique for controlling a side shape of a nitride semiconductor layer by forming a crystal defect portion in the nitride semiconductor layer and selectively removing the crystal defect portion by etching. Yes. However, this technique is a technique for etching a nitride semiconductor layer formed on a sapphire substrate, and does not etch the substrate itself.

  The present invention has been made in view of the above problems, and when dividing a substrate product in which a nitride semiconductor layer is formed on a GaN-based compound substrate into a plurality of semiconductor elements, the nitride semiconductor layer It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of suppressing side damage and controlling the shape of the side surfaces of a nitride semiconductor layer and a GaN-based compound substrate satisfactorily.

In order to solve the above-described problems, a first method for manufacturing a semiconductor device according to the present invention includes a substrate product having a GaN-based compound substrate and a nitride semiconductor layer formed on the GaN-based compound substrate. A method for manufacturing a semiconductor device comprising a step of dividing a device, wherein the GaN-based compound substrate includes a crystal inversion region in which a crystal plane orientation is inverted between regions to be a plurality of semiconductor devices, and a GaN And a step of etching and removing the crystal inversion region of the compound compound substrate and the nitride semiconductor layer on the crystal inversion region from the N terminal surface side of the crystal inversion region by wet etching using an alkaline aqueous solution as an etchant .

When a GaN-based compound substrate using alkaline product etchant during the wet etching, the GaN-based compound substrate Ga termination surface completely etched, only the N terminal end face is selectively etched. In the first method for manufacturing a semiconductor element described above, the GaN-based compound substrate includes a crystal inversion region in which the crystal plane orientation is inverted between regions to be a plurality of semiconductor elements. In one surface of such GaN-based compound substrate, the N-terminal end surface of the crystal inversion region between the Ga end face of the region to be a plurality of semiconductor elements are formed, by using a alkaline product etchant, The crystal inversion region can be selectively etched away from the N terminal end side . Therefore, according to the first method for manufacturing a semiconductor element, the GaN-based compound substrate can be divided while favorably controlling the side surface shape of the GaN-based compound substrate.

  In addition, the nitride semiconductor layer grown on the crystal inversion region of the GaN-based compound substrate tends to have a different crystal orientation with respect to other portions of the nitride semiconductor layer. This portion with a different crystal orientation is easier to etch than the other portions, so by selectively removing this portion by wet etching, the side surface shape of the nitride semiconductor layer is controlled and the side surface shape is controlled well. In addition, the nitride semiconductor layer can be divided.

  From the above, according to the first method for manufacturing a semiconductor element, when a substrate product having a nitride semiconductor layer formed on a GaN-based compound substrate is divided into a plurality of semiconductor elements, the nitride semiconductor The side surface shapes of the nitride semiconductor layer and the GaN-based compound substrate can be favorably controlled while suppressing damage to the side surfaces of the layer.

The second method for manufacturing a semiconductor device according to the present invention includes a step of dividing a substrate product having a GaN-based compound substrate and a nitride semiconductor layer formed on the GaN-based compound substrate into a plurality of semiconductor devices. A method of manufacturing a semiconductor device, wherein the GaN compound substrate includes a crystal inversion region in which a crystal plane orientation is inverted between regions to be a plurality of semiconductor elements, and the crystal inversion region of the GaN compound substrate And a step of etching the nitride semiconductor layer on the crystal inversion region from the N terminal surface side of the crystal inversion region to a predetermined depth by wet etching using an alkaline aqueous solution as an etchant, and a GaN-based compound substrate along the crystal inversion region And a mechanically dividing step.

  According to the second method for manufacturing a semiconductor device described above, the GaN compound substrate and the nitride semiconductor layer are separated by a predetermined depth along the dividing direction as a pre-process for mechanically dividing (cutting, cleaving, etc.) the GaN compound substrate. When etching up to this point, it is possible to suppress damage to the side surfaces of the nitride semiconductor layer as well as the side surface shapes of the GaN-based compound substrate and the nitride semiconductor layer as in the above-described first semiconductor element manufacturing method. .

The manufacturing method of the first and second semiconductor element may be characterized in that the temperature of the etchant in the U E Tsu preparative etched 80 ° C. or higher. Thereby, the etching rate of the crystal inversion region can be increased, and the time required for dividing the substrate product can be shortened.

The manufacturing method of the first and second semiconductor element, a U E Tsu preparative etching may be characterized in that in a closed state of the etchant. This prevents evaporation of the etchant during wet etching and reduces the amount of etchant required for dividing the substrate product.

  Further, in the first and second semiconductor element manufacturing methods, when wet etching is performed in a sealed state, when the temperature of the etchant exceeds 250 ° C., the pressure in the sealed container is excessively increased and it is difficult to maintain the sealed state. It becomes. Therefore, when wet etching is performed in a sealed state, the etchant temperature is preferably 250 ° C. or lower.

  According to the semiconductor device manufacturing method of the present invention, when a substrate product having a nitride semiconductor layer formed on a GaN-based compound substrate is divided into a plurality of semiconductor devices, damage to the side surfaces of the nitride semiconductor layer is suppressed. In addition, the side surface shapes of the nitride semiconductor layer and the GaN-based compound substrate can be controlled well.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
Before describing the first embodiment of the semiconductor device manufacturing method according to the present invention, the GaN-based compound substrate used in the present embodiment and the manufacturing method thereof will be described. FIG. 1 is a perspective view showing an appearance of a substrate 3 that is a GaN-based compound substrate used in the present embodiment. In the present embodiment, the substrate 3 is made of single-crystal GaN. Referring to FIG. 1, the substrate 3 includes a plurality of element regions 31 and a crystal inversion region 32, and a division line A is assumed on the main surface 3a. The division line A is a cutting line for dividing the substrate 3 and extends in the first direction and the second direction intersecting the first direction. In the present embodiment, the planned division line A extending in the first direction and the planned division line A extending in the second direction intersect with each other at an angle of 60 °.

  The plurality of element regions 31 are portions that respectively become semiconductor element substrates after the substrate 3 is divided. The plurality of element regions 31 are arranged two-dimensionally so as to sandwich the division line A between them. Each side in the planar shape of the plurality of element regions 31 is along the planned division line A, and the planar shape of the element region 31 is a rhombus. The crystal inversion region 32 is provided between the plurality of element regions 31. In other words, the crystal inversion region 32 penetrates in the thickness direction of the substrate 3 and is formed along the division line A.

  On the main surface 3a of the substrate 3, the plane orientation of the element region 31 is the (0001) plane (that is, the C plane), and the plane orientation of the crystal inversion region 32 is the (000-1) plane (that is, the -C plane). It has become. That is, the crystal inversion region 32 grows with the c-axis inverted with respect to the element region 31. Therefore, in the main surface 3a of the substrate 3, the surface of the element region 31 is a Ga termination surface, whereas the surface of the crystal inversion region 32 is an N termination surface. On the other hand, on the back surface 3 b of the substrate 3, the element region 31 is an N termination surface and the crystal inversion region 32 is a Ga termination surface. The boundary between the element region 31 and the crystal inversion region 32 is a surface defect (crystal grain boundary).

  Next, a method for manufacturing the substrate 3 shown in FIG. 1 will be described. FIG. 2A to FIG. 2C are cross-sectional views for explaining a method for manufacturing the substrate 3. First, as shown in FIG. 2A, a base substrate 60 made of GaAs, Si, or sapphire is prepared. When the base substrate 60 is made of Si, the main surface 60a of the base substrate 60 is the (111) plane. When the base substrate 60 is made of GaAs, the main surface 60a of the base substrate 60 is a (111) plane and a Ga termination surface. When the base substrate 60 is made of sapphire, the main surface 60a of the base substrate 60 is a (0001) plane, that is, a C plane.

Subsequently, a SiO ₂ film having a thickness of, for example, 100 nm is uniformly formed on the main surface 60 a of the base substrate 60. Then, using a normal photolithography technique, a mask pattern that matches the planar shape of the element region 31 (see FIG. 1) is formed on the SiO ₂ film, and the SiO ₂ film is etched through the mask pattern, A mask 53 is formed along the planned division line A (see FIG. 1). When the base substrate 60 is made of sapphire, for example, the longitudinal direction of the mask 53 is, for example, the <1-100> direction of the base substrate 60 (that is, the direction parallel to the {11-20} plane (A plane)), and the base The <11-20> direction of the substrate 60 (that is, the direction parallel to the {1-100} plane (M plane)) is preferable.

  Subsequently, a pattern for epitaxial lateral overgrowth (ELO) is formed in a portion where the mask 53 is not formed on the main surface 60a. At this time, the ELO pattern may be arranged in six-fold symmetry so that, for example, circular openings having a diameter of 2 μm are positioned at the apexes of regular triangles at a pitch of 4 μm. Further, the ELO pattern may be arranged so that the sides of the equilateral triangle are parallel to the longitudinal direction of the mask 53.

Subsequently, as shown in FIG. 2B, the GaN crystal 5 is grown on the base substrate 60 and the mask 53 by, for example, the HVPE method. In the HVPE apparatus, a Ga boat containing Ga metal is provided inside the vertically long reaction furnace, and a susceptor on which the base substrate 60 is placed is provided below the reaction furnace. Then, H ₂ gas and HCl gas are supplied to the Ga boat from above the reaction furnace, and NH ₃ gas and H ₂ gas (carrier gas) are supplied to the immediate vicinity of the base substrate 60 on the susceptor.

At this time, it is preferable to heat the Ga boat to 800 ° C. or higher and the base substrate to 1050 ° C. with the inside of the reactor at normal pressure. Ga and HCl react to synthesize GaCl once, and this GaCl descends to reach the vicinity of the base substrate 60 and react with NH ₃ gas. Then, GaN as a reaction product is deposited on the base substrate 60 and the mask 53, whereby the GaN crystal 5 grows. The following numerical values are examples of growth conditions for the GaN crystal 5.
Growth temperature: 1050 ° C
NH3 partial pressure: 0.3 atm (30 kPa)
HCl partial pressure: 0.02 atm (2 kPa)
Growth time: 10 hours

  In the GaN crystal 5, the element region 30 grows on the surface of the base substrate 60 (on the surface of the base substrate 60 but not on the mask 53), and the crystal inversion region 33 grows on the mask 53. That is, since the surface of the base substrate 60 is a (111) plane (in the case of GaAs or Si) or a C plane (in the case of sapphire), the element region 30 grown on the surface of the base substrate 60 also grows with the crystal orientation as the c axis. The upper surface 30a of the element region 30 becomes the C plane (Ga termination surface).

On the other hand, the crystal orientation of GaN grown on the mask 53 may be reversed. That is, on the mask 53 made of SiO ₂ , GaN may grow with the crystal orientation as the −c axis. In such a case, GaN grown on the mask 53 becomes the crystal inversion region 33, and the upper surface 33a of the crystal inversion region 33 becomes the -C plane (N termination surface). In addition, since the crystal inversion region 33 has a slower growth rate than the element region 30, the upper surface 30 a close to the crystal inversion region 33 among the upper surface 30 a of the element region 30 has its facet surface toward the upper surface 33 a of the crystal inversion region 33. Grow while tilting. Accordingly, the crystal defects inside the element region 30 gather at the boundary (crystal grain boundary) between the element region 30 and the crystal inversion region 33, and the crystal defect density inside the element region 30 decreases.

  Subsequently, as shown in FIG. 2C, the substrate 3 is formed by grinding the GaN crystal 5 at a surface intersecting the growth direction. First, the base substrate 60 on the bottom surface of the GaN crystal 5 is ground and scraped off. Thereafter, the GaN crystal 5 is ground into a flat plate shape, and the surface is polished to complete the substrate 3 having the flat main surface 3a. The substrate 3 includes an element region 31 and a crystal inversion region 32. Since the element region 30 of the GaN crystal 5 grows with the crystal orientation as the c-axis, the surface of the element region 31 in the main surface (upper surface) 3a of the substrate 3 becomes a Ga termination surface. Further, since the crystal inversion region 33 of the GaN crystal 5 is grown with the crystal orientation as the −c axis, the surface of the crystal inversion region 32 in the main surface (upper surface) 3a of the substrate 3 becomes an N termination surface.

  Here, as a method for confirming whether or not the surface of the crystal inversion region 32 on the main surface (upper surface) 3a of the substrate 3 is an N termination surface, there is the following method. That is, the Ga termination surface is not etched by the alkaline aqueous solution, and the N termination surface is easily etched by the alkaline aqueous solution. When the surface of the crystal inversion region 32 is more easily etched than the surface of the element region 31 by the alkaline aqueous solution, the surface of the crystal inversion region 32 is an N termination surface.

In the manufacturing method described above, SiO ₂ is used as the material of the mask 53. However, the crystal inversion region 33 can be preferably grown by using, for example, Si ₃ N ₄ as the material of the mask 53.

  The GaN compound substrate used in the semiconductor device manufacturing method according to the present embodiment and the manufacturing method thereof have been described above. Subsequently, the method for fabricating the semiconductor device according to the present embodiment will be explained. FIG. 3A to FIG. 3E are cross-sectional views for explaining the semiconductor device manufacturing method according to the present embodiment. FIG. 4 is a perspective view of the substrate product 23 in the step shown in FIG.

  In this manufacturing method, first, as shown in FIG. 3A, a substrate 3 made of a GaN compound and including an element region 31 and a crystal inversion region 32 is prepared. The substrate 3 is manufactured by the above-described substrate manufacturing method. The element region 31 is a region that becomes a plurality of semiconductor elements in the present embodiment. The crystal inversion region 32 is located between the element regions 31, and the crystal plane orientation is inverted with respect to the element region 31 as described above. Therefore, in the main surface 3a of the substrate 3, the surface of the element region 31 is a Ga termination surface, and the surface of the crystal inversion region 32 is an N termination surface.

  Subsequently, as illustrated in FIG. 3B, the nitride semiconductor layer 14 is formed on the main surface 3 a of the substrate 3. At this time, since the surface of the element region 31 of the main surface 3a of the substrate 3 is a C plane, the first portion 15 grown on the element region 31 of the nitride semiconductor layer 14 grows with the crystal orientation as the c axis. Further, since the surface of the crystal inversion region 32 is the -C plane, the second portion 17 grown on the crystal inversion region 32 in the nitride semiconductor layer 14 grows with a crystal orientation different from the c axis (for example, -c axis). Will be.

  In this embodiment, a case where an LED is manufactured as a semiconductor element will be described. That is, the nitride semiconductor layer 14 has an internal structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially stacked. Specifically, a buffer layer and a cladding layer made of an n-type nitride semiconductor, an active layer having a multiple quantum well structure, and a cladding layer and a contact layer made of a p-type nitride semiconductor are formed on the main surface 3a of the substrate 3. The nitride semiconductor layer 14 is formed by sequentially laminating.

  Subsequently, as illustrated in FIG. 3C, the anode electrode 11 is formed on the first portion 15 of the nitride semiconductor layer 14. At this time, the anode electrode 11 may be formed by sequentially vapor-depositing a metal material such as Ni / Au, and the anode electrode 11 and the nitride semiconductor layer 14 may be ohmic-bonded at a high temperature. Further, the cathode electrode 13 is formed on the back surface of each element region 31. At this time, the cathode electrode 13 may be formed by sequentially vapor-depositing a metal material such as Ti / Al, and the cathode electrode 13 and the substrate 3 may be ohmically coupled at a high temperature. Thus, a substrate product 23 having the substrate 3, the nitride semiconductor layer 14, the anode electrode 11, and the cathode electrode 13 is completed.

  Subsequently, as shown in FIGS. 3D and 4, wet etching is performed on the substrate product 23. First, a mask 19 is formed on the entire back surface of the substrate 3 so that the back surface of the substrate 3 is not etched. Next, the substrate product 23 is immersed in an etchant 21 made of an alkaline aqueous solution. At this time, since the first portion 15 grown on the element region 31 in the nitride semiconductor layer 14 grows in the c-axis direction, the surface thereof becomes a C plane (Ga termination plane), and the alkaline etchant 21 includes Is not etched. On the other hand, since the second portion 17 grown on the crystal inversion region 32 grows in a crystal direction different from the c-axis, its surface is different from the C plane (for example, -C plane), and an alkaline etchant. 21 is easily etched. Therefore, the second portion 17 is selectively removed by etching in the nitride semiconductor layer 14. The etchant 21 is preferably a strong alkaline aqueous solution such as an aqueous potassium hydroxide solution or an aqueous sodium hydroxide solution. Alternatively, the etchant 21 may be a weak alkaline aqueous solution such as an aqueous ammonia solution.

  Thus, when the second portion 17 of the nitride semiconductor layer 14 is removed by etching, the surface of the crystal inversion region 32 of the substrate 3 is exposed. The surface of the crystal inversion region 32 is a -C plane (N termination plane) and is easily etched in the alkaline etchant 21. Therefore, the crystal inversion region 32 is selectively removed by etching in the substrate 3.

  Subsequently, the substrate product 23 is taken out from the etchant 21 and the mask 19 formed on the back surface of the substrate 3 is removed. Thus, the substrate product 23 is divided into a plurality of semiconductor elements 25 as shown in FIG.

  The semiconductor device manufacturing method according to the present embodiment has the following effects. That is, in the semiconductor device manufacturing method according to the present embodiment, the substrate 3 includes the crystal inversion region 32 in which the crystal plane orientation is inverted between the device regions 31. Thereby, in the main surface 3 a of the substrate 3, the N termination surface of the crystal inversion region 32 is formed between the Ga termination surfaces of the element region 31, so that the crystal inversion region 32 can be changed by using, for example, the alkaline etchant 21. It can be selectively etched away. Therefore, according to this method for manufacturing a semiconductor element, the substrate 3 can be divided while favorably controlling the side surface shape of the substrate 3.

  In addition, the second portion 17 of the nitride semiconductor layer 14 grown on the crystal inversion region 32 of the substrate 3 has a crystal orientation with respect to the first portion 15 of the nitride semiconductor layer 14 grown on the element region 31. There is a different tendency. Accordingly, when the alkaline etchant 21 is used, the second portion 17 is more easily etched than the first portion 15. Therefore, the nitride semiconductor layer is selectively removed by wet etching. It is possible to divide the nitride semiconductor layer 14 while suppressing damage to the side surface of the first portion 15 and controlling the side surface shape well.

  From the above, according to the method of manufacturing a semiconductor device according to the present embodiment, when the substrate product 23 in which the nitride semiconductor layer 14 is formed on the substrate 3 is divided into the plurality of semiconductor devices 25, the nitride semiconductor The side surface shape of the first portion 15 of the nitride semiconductor layer 14 and the substrate 3 can be well controlled while suppressing damage to the side surface of the first portion 15 of the layer 14.

  Further, in the conventional mechanical dividing methods such as blade dicing and braking, chipping and cracks are likely to occur on the side surface of the substrate after the division. Such chipping and cracking are particularly noticeable when the wafer is made of a hard material such as GaN. Therefore, in the conventional mechanical dividing method, when the nitride semiconductor layer is etched in advance, the etching width along the line to be divided is set relatively wide, and the distance between the cut surface and the side surface of the nitride semiconductor layer is set. Since it is necessary to provide a margin, the number of elements obtained from one wafer is suppressed. On the other hand, in the semiconductor element dividing method according to the present embodiment, since the substrate product 23 can be divided only by wet etching, chipping and cracks do not occur. In addition, the width of the crystal inversion region 32 removed by etching can be arbitrarily set. Therefore, according to the semiconductor element dividing method according to the present embodiment, more semiconductor elements can be obtained from one wafer.

(Second Embodiment)
A second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described. FIG. 5A to FIG. 5C are cross-sectional views for explaining the semiconductor device manufacturing method according to the present embodiment. Note that this embodiment is different from the first embodiment in the method for dividing the substrate product 23. Accordingly, the processes until the substrate 3 and the substrate product 23 are manufactured are the same as those in the first embodiment, and a detailed description regarding these processes is omitted.

  First, as shown in FIG. 5A, wet etching is performed on the substrate product 23. Similar to the first embodiment, the mask 19 is formed on the entire back surface of the substrate 3 so that the back surface of the substrate 3 is not etched. Next, the substrate product 23 is immersed in an etchant 21 made of an alkaline aqueous solution. At this time, the second portion 17 is selectively etched away in the nitride semiconductor layer 14, and the crystal inversion region 32 is selectively etched in the substrate 3. Here, in the present embodiment, after the second portion 17 of the nitride semiconductor layer 14 is removed, the crystal inversion region 32 of the substrate 3 is etched to at least a predetermined depth. That is, by adjusting the etching time, the crystal inversion region 32 is removed by etching to an intermediate depth, leaving a portion from the back surface of the substrate 3 to a certain thickness.

  Subsequently, the substrate product 23 is taken out from the etchant 21 and the mask 19 formed on the back surface of the substrate 3 is removed. Then, the substrate 3 is mechanically divided along the longitudinal direction of the crystal inversion region 32. Here, mechanically dividing means that, as shown in FIG. 5B, for example, the braking device 40 is applied from the back side of the substrate 3 along the longitudinal direction of the crystal inversion region 32 to cleave the substrate 3. This is a simple division method. Alternatively, the mechanical division may be a division method in which the substrate 3 is cut along the longitudinal direction of the crystal inversion region 32 using, for example, a blade dicing apparatus. Thus, the substrate product 23 is divided into a plurality of semiconductor elements 27 as shown in FIG.

  The semiconductor device manufacturing method according to the present embodiment has the following effects. That is, according to the method of manufacturing a semiconductor device according to the present embodiment, when the substrate 3 and the nitride semiconductor layer 14 are etched to a predetermined depth along the planned dividing line as a pre-process for mechanically dividing the substrate 3, nitriding is performed. It is possible to suppress damage to the side surfaces of the semiconductor layer 14 and to favorably control the side surfaces of the substrate 3 and the nitride semiconductor layer 14.

(Example)
Now, examples of the first embodiment will be described. In this embodiment, in the step of dividing the substrate product 23 into a plurality of semiconductor elements 25 by wet etching (see FIGS. 3D and 3E), the etching conditions are set to the following four patterns. The speed required for dividing the substrate 3 was observed. In this example, a GaN substrate having a thickness of 400 μm including the element region and the crystal inversion region was formed in advance as the substrate 3 by the steps shown in FIGS. Then, a mask was formed in advance on the entire back surface of the GaN substrate.

(1) Etching condition 1
First, a GaN substrate having a beaker filled with an 8N aqueous potassium hydroxide solution to a depth of 2 cm and a mask formed on the back surface was placed horizontally in the aqueous potassium hydroxide solution. At this time, the temperature of the potassium hydroxide aqueous solution was set to room temperature (25 ° C.). After 2 hours, the GaN substrate was taken out from the aqueous potassium hydroxide solution. As a result, the GaN substrate was not divided under these etching conditions, and the crystal inversion region was etched only 1 μm deep with respect to the GaN substrate having a thickness of 400 μm. That is, the etching rate for the crystal inversion region was 0.5 μm per hour.

(2) Etching condition 2
First, an 8N aqueous potassium hydroxide solution was filled to a depth of 2 cm in a beaker, and the temperature of the aqueous potassium hydroxide solution was maintained at 80 ° C. by a hot plate placed at the bottom of the beaker. Then, the GaN substrate with the mask formed on the back surface was placed horizontally in the potassium hydroxide aqueous solution. At this time, when the etching rate for the crystal inversion region was measured, it was 20 μm per hour. However, since the aqueous potassium hydroxide solution was maintained at a high temperature of 80 ° C., the aqueous potassium hydroxide solution evaporated and the surface of the GaN substrate was exposed after 1 hour. Therefore, an 8N aqueous potassium hydroxide solution was added to a depth of 40 cm in the beaker, and after 20 hours, the GaN substrate was taken out from the aqueous potassium hydroxide solution. As a result, the GaN substrate could be immersed in an aqueous potassium hydroxide solution until the end, and the GaN substrate could be completely divided by removing all the crystal inversion regions by etching.

(3) Etching condition 3
In this example, a sealed container 70 and a sealing device 75 as shown in FIG. 6 were prepared. The hermetic container 70 is configured by a water tank 71 having a depth of 6 cm with an upper opening and a lid 72 that closes the opening of the water tank 71. The sealing device 75 includes a stage 75 a on which the sealed container 70 is placed and a holding bolt 74 for pressing the lid 72 of the sealed container 70. The sealed container 70 is sealed via the holding plates 73 and 76. It has a structure to do.

  First, an 8N potassium hydroxide aqueous solution 22 was filled to a depth of 2 cm in the water tank 71, and the GaN substrate 3 was placed horizontally in the potassium hydroxide aqueous solution 22. Then, after closing the opening of the water tank 71 with the lid 72, the sealed container 70 was placed on the stage 75 a of the sealing device 75 via the pressing plate 76. And the airtight container 70 was sealed by pressing down the lid | cover 72 in the state which pinched | interposed the presser plate 73 between the presser bolt 74 and the lid | cover 72. FIG. In this state, the entire sealed device was left inside the constant temperature layer at 80 ° C., and the temperature of the aqueous potassium hydroxide solution 22 was maintained at 80 ° C., and the pressure inside the sealed container 70 was 2 atm (200 kPa). Further, when the etching rate for the crystal inversion region was measured, it was 20 μm per hour. Since the potassium hydroxide aqueous solution 22 was in the sealed container 70, it did not evaporate, and after 20 hours, the entire crystal inversion region was removed by etching and the GaN substrate could be completely divided.

(4) Etching condition 4
First, an 8N potassium hydroxide aqueous solution 22 was filled to a depth of 2 cm in the water tank 71, and the GaN substrate 3 was placed horizontally in the potassium hydroxide aqueous solution 22. Then, the sealed container 70 was sealed by the same method as in the etching condition 3. In this state, the entire sealed device was left inside the constant temperature layer at 150 ° C., and the temperature of the aqueous potassium hydroxide solution 22 was maintained at 150 ° C., and the pressure inside the sealed container 70 was 5 atm (500 kPa). Moreover, when the etching rate with respect to the crystal inversion area | region was measured, it was 300 micrometers per hour. Since the potassium hydroxide aqueous solution 22 was in the sealed container 70, it did not evaporate, and after 80 minutes, the entire crystal inversion region was removed by etching to completely divide the GaN substrate.

  If the temperature of the potassium hydroxide aqueous solution 22 exceeds 250 ° C. with the potassium hydroxide aqueous solution 22 and the GaN substrate 3 sealed in the sealed container 70 in the same manner as the etching condition 4, the pressure inside the sealed container 70 is The pressure becomes as high as 40 atm (4 MPa), and it becomes difficult to maintain the airtightness of the sealed container 70. Therefore, it is not practical as a mass production process.

  As can be seen from the above embodiments, when the temperature of the potassium hydroxide aqueous solution 22 in wet etching is set to 80 ° C. or higher (more preferably 150 ° C. or higher), the etching rate for the crystal inversion region 32 is increased. Compared to the above, the time required for dividing the substrate 3 can be shortened, and the manufacturing cost can be reduced. In addition, when the temperature of the potassium hydroxide aqueous solution 22 is set high as described above, the potassium hydroxide aqueous solution 22 is required as much as the potassium hydroxide aqueous solution 22 evaporates as shown in the etching condition 2. . Therefore, by performing wet etching in the sealed container 70, evaporation of the potassium hydroxide aqueous solution 22 can be prevented, the amount of the potassium hydroxide aqueous solution 22 required for dividing the GaN substrate 3 can be reduced, and the manufacturing cost can be reduced. . And when performing wet etching in the airtight container 70 in this way, in order to maintain the airtightness of the airtight container 70 easily, it is preferable to set the temperature of the potassium hydroxide aqueous solution 22 to 250 degrees C or less.

  The semiconductor device manufacturing method according to the present invention is not limited to the above-described embodiments, and various other modifications are possible. For example, in each of the above-described embodiments, the longitudinal direction of the crystal inversion region 32 is set as two directions intersecting each other at 60 °, but the longitudinal direction of the crystal inversion region 32 is not limited to this, and an arbitrarily set substrate It can be in various directions along the planned cutting line of the product.

FIG. 1 is a perspective view showing an appearance of a GaN-based compound substrate used in the first embodiment. FIG. 2A to FIG. 2C are cross-sectional views for explaining a method for manufacturing a GaN-based compound substrate. FIG. 3A to FIG. 3E are cross-sectional views for explaining the semiconductor device manufacturing method according to the first embodiment. FIG. 4 is a perspective view of the substrate product in the step shown in FIG. FIG. 5A to FIG. 5C are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the second embodiment. FIG. 6 is a diagram illustrating a configuration of a hermetic container and a hermetic device used in the examples.

Explanation of symbols

  3 ... substrate, 5 ... crystal, 11 ... anode electrode, 13 ... cathode electrode, 14 ... nitride semiconductor layer, 15 ... first part, 17 ... second part, 19 ... mask, 21 ... etchant, 23 ... substrate Product, 25, 27 ... Semiconductor element, 30, 31 ... Element region, 32, 33 ... Crystal inversion region, 53 ... Mask, 60 ... Base substrate.

Claims (5)

A method of manufacturing a semiconductor device comprising a step of dividing a substrate product having a GaN-based compound substrate and a nitride semiconductor layer formed on the GaN-based compound substrate into a plurality of semiconductor devices,
The GaN-based compound substrate includes a crystal inversion region in which a crystal plane orientation is inverted between the regions to be the plurality of semiconductor elements,
Etching and removing the crystal inversion region of the GaN-based compound substrate and the nitride semiconductor layer on the crystal inversion region from the N termination surface side of the crystal inversion region by wet etching using an alkaline aqueous solution as an etchant. A method for manufacturing a semiconductor device, characterized in that: A method of manufacturing a semiconductor device comprising a step of dividing a substrate product having a GaN-based compound substrate and a nitride semiconductor layer formed on the GaN-based compound substrate into a plurality of semiconductor devices,
The GaN-based compound substrate includes a crystal inversion region in which a crystal plane orientation is inverted between the regions to be the plurality of semiconductor elements,
Etching the crystal inversion region of the GaN-based compound substrate and the nitride semiconductor layer on the crystal inversion region from the N termination surface side of the crystal inversion region to a predetermined depth by wet etching using an alkaline aqueous solution as an etchant. When,
A step of mechanically dividing the GaN-based compound substrate along the crystal inversion region. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the etchant in the wet etching is 80 ° C. or higher. The wet etching, and performing in a closed state of the etchant, a method of manufacturing a semiconductor device according to any one of claims 1-3. The method for manufacturing a semiconductor device according to claim 4 , wherein the temperature of the etchant in the wet etching is 250 ° C. or less.

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