JP4073829B2 - Programmable logic circuit and semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for reducing the circuit scale in a programmable logic circuit, and relates to a technique effective when applied to a sequencer in a hard disk controller LSI, for example.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor integrated circuit is known in which circuit data defining circuit functions such as connection information and logic functions is stored in a memory cell or the like so that necessary circuit functions can be programmed. Such a semiconductor integrated circuit is called a programmable integrated circuit, and the circuit function can be changed by rewriting circuit data.
[0003]
A general programmable logic circuit is assumed to be a product-sum type logic, but in order to suppress an increase in circuit scale in such a circuit, a feedback path is provided for returning a part of the product term line to the condition input side through the product logic operation circuit. A method has been proposed (see, for example, Patent Document 1).
[0004]
In addition, OR circuits having a small number of product term lines are used as a plurality of sets, which are used as inputs of a subsequent OR circuit having different numbers of inputs, and an output of the preceding OR circuit or the subsequent OR circuit is selectively selected by a pass transistor circuit. A method of outputting to an output terminal has been proposed (see, for example, Patent Document 2).
[0005]
[Patent Document 1]
JP-A-7-66717 (FIG. 2)
[Patent Document 2]
Japanese Patent Laid-Open No. 5-300005 (FIG. 3)
[0006]
[Problems to be solved by the invention]
In the case of a simple product-sum logic type, it is difficult to increase the gate usage efficiency, so it is necessary to provide a margin for the product term line, which increases the scale of the programmable logic circuit in proportion to the number of inputs. . In particular, in the case of a programmable logic circuit applied to a sequencer, a plurality of outputs are required, a product-sum logic circuit is required for each output, and the same bit pattern is input to a plurality of product term lines. Therefore, efficiency is bad. Except when taking the sum of product operations as logic, it is necessary to feed back the output signal to the input side or increase the number of product term lines, and the circuit scale becomes large due to redundant product term lines.
[0007]
An object of the present invention is to provide a technique for eliminating the need for redundant product term lines by enabling a plurality of signal outputs for each product term line .
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
That is, a plurality of product term lines, a plurality of condition input signal lines formed so as to intersect the product term line, and an intersection of the product term line and the condition input signal line are provided, and the condition input A plurality of switch circuits for determining the logic of the product term line based on the logic of the signal line, and an output logic that enables a plurality of signal outputs for each product term line, A plurality of memories each capable of 1-bit information programming, and a plurality of AND circuits arranged corresponding to the memories and capable of performing a logical operation between the output signal of the product term line and the output signal of the memory; By programming the information into the memory, a programmable logic circuit is configured so that the logic outputs from the plurality of AND circuits can be set in a programmable manner even though the product term line is common .
[0011]
In the case of a simple product-sum logic type programmable logic circuit, it is difficult to increase the gate usage efficiency, so it is necessary to provide a margin in advance for the number of product term lines. A plurality of signal outputs can be performed for each product term line , and a redundant product term line is not required in a simple product-sum logic type programmable logic circuit . As a result, when a simple product-sum logic type programmable logic circuit is formed, it is not necessary to provide a margin for the number of product term lines.
[0012]
When applied to a sequencer, in order to be able to capture a state input signal for indicating the current state, a plurality of state input signal lines formed to intersect the product term line, and the product term line And a comparison circuit for driving the product term line according to the comparison result obtained by comparing the logic of the state input signal line with a preset logic. It is good to provide.
[0013]
In order to reduce the usage amount of the product term line, a priority control logic circuit capable of overwriting the state of the product term line with the lower priority with the product term line with the higher priority according to the priority of the product term line is provided. it can.
[0014]
In addition, a logic circuit that forms a determination signal as to whether or not there is a product term line that matches the condition input signal fetched via the condition input signal line can be provided.
[0015]
Further, in the semiconductor integrated circuit, the plurality of programmable logic circuits can be cascaded.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a programmable logic circuit included in a semiconductor integrated circuit according to the present invention. The programmable logic circuit 705 shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
[0017]
The programmable logic circuit 705 shown in FIG. 1 is not particularly limited, but is a circuit applied to a sequencer in a hard disk controller LSI that enables control of a hard disk device. A single crystal silicon substrate is formed by a known semiconductor integrated circuit manufacturing technique. Formed on one semiconductor substrate.
[0018]
A plurality of product term lines 102 and a plurality of condition input signal lines (C0 to Cn) 101 are arranged to cross each other, and a switch circuit 100 is formed at the intersection. For each of the plurality of product term lines 102, the output logic 10 is arranged correspondingly.
[0019]
The switch circuit 100 is not particularly limited, but selectively outputs the output signals of the memories 13 and 14 to the corresponding product term lines 102 in accordance with the logic of the memories 13 and 14 for logic programming and the condition input signal line 101. And AND circuits 11 and 12 which can be transmitted. The condition input signal line 101 is input to the AND circuit 12 and logically inverted before being input to the AND circuit 11. Thereby, the information stored in the memories 13 and 14 is selectively transmitted to the product term line 102 in accordance with the condition input signal. That is, the output logic of the wired-and-circuit 107 corresponding to the logic of the condition input signal line 101 can be set programmable by information programming to the memories 13 and 14. The memories 13 and 14 are not particularly limited, but are memory elements having a static 1-bit storage capacity.
[0020]
The output logic 10 is not particularly limited, but a wired-and circuit 107 for obtaining wired-and logic of the plurality of product term lines 102, a plurality of memories 105 having a 1-bit storage capacity, and an output of the wired-and circuit 107 A plurality of AND circuits 103 for obtaining an AND logic between the signal and the output signals of the plurality of memories 105 are included. By the information programming to the memory 105, a plurality of outputs corresponding to the output of the memory 105 can be obtained with respect to the output of the corresponding wired and circuit 107. That is, although the product term line 102 is common, the logic output from the plurality of AND circuits 103 can be set programmably by the information program to the memory 105. The memory 105 is not particularly limited, but is a static storage element having a storage capacity of 1 bit.
[0021]
The output signals from the plurality of output logics 10 having the above-described configuration can obtain a plurality of outputs (Y0, Y1, Y2,...) 104 through a plurality of wired-and-circuits 106. The plurality of outputs (Y0, Y1, Y2,...) 104 are supplied to a control circuit 500 that enables operation control of each unit in the hard disk device.
[0022]
The memories 13, 14, and 15 are addressed from the outside and information is written in the same manner as general-purpose memories. The memories 13, 14, and 15 may be non-volatile storage elements such as flash memory cells.
[0023]
Here, a circuit to be compared with the programmable logic circuit 705 will be described with reference to FIGS.
[0024]
The programmable logic circuit shown in FIG. 10 includes a plurality of product-sum logic circuits 306. In one product-sum logic circuit 306, a switch circuit 300 is arranged at a location where a plurality of condition input signal lines 301 and a plurality of product term lines 302 intersect, and the output of the wired-and-circuit 303 depends on the state of the switch circuit 300. Logic is determined. The output signals of the plurality of wired-and-circuits 303 are transmitted to the wired OR circuit 304 at the subsequent stage, and the OR logic is taken there to obtain an output signal (Y0) 305.
[0025]
In such a configuration, the product term line 302 is fixed, and when the logic of the unit of the unit that the user wants to realize is simple, the product term line 302 becomes redundant and the use efficiency of the circuit is lowered. Further, when it is desired to realize complicated logic, it is necessary to prepare a large number of product term lines 302, which increases the circuit scale.
[0026]
In the configuration shown in FIG. 11, a feedback path 341 for feeding back a part of the product term line as a condition input signal via the logic operation circuit 340 is provided through the product logic operation circuit. Further, in the configuration shown in FIG. 12, the OR circuit 304 having a small number of product term lines 302 is used as a plurality of sets as inputs of the subsequent OR circuit 350 having a different number of inputs, and the preceding OR circuit 304 or the subsequent OR circuit 304 is input. The output of the OR circuit 350 is selectively output to the subsequent circuit by the pass transistor circuit 351.
[0027]
In the circuit configuration shown in FIGS. 10 to 12, one output signal is obtained for a plurality of product term lines, whereas in the configuration shown in FIG. A plurality of memories 105 are arranged, and an AND logic between an output signal of the plurality of memories 105 and an output signal of the wired-and circuit 107 is obtained by an AND circuit 103, and an output signal of the AND circuit 103 is a wired-and circuit. The signal is transmitted to the subsequent circuit via 106. Therefore, a plurality of signal outputs can be performed per one wired-and-circuit 107. That is, in the case of a simple product-sum logic type, it is difficult to increase the gate usage efficiency, so it is necessary to provide a margin for the number of product term lines, whereas according to the configuration shown in FIG. By providing a plurality of AND circuits 103 for each product term line 102 and simultaneously driving a plurality of outputs (Y0, Y1, Y2,...) 104, redundant product term lines are not required. The reduction can reduce the chip occupation area of the programmable logic circuit.
[0028]
FIG. 2 shows another configuration example of the programmable logic circuit.
[0029]
The programmable logic circuit shown in FIG. 2 differs from that shown in FIG. 1 in that a plurality of state input signal lines (S0 to Sn) are provided so as to intersect with a plurality of product term lines 102, and the intersections thereof. The comparison circuit 110 is formed. This is because the state input signal for representing the current state is taken in when this circuit is applied to the sequencer.
[0030]
The comparison circuit 110 is not particularly limited, but includes a memory 15 having a storage capacity of 1 bit, and an exclusive OR circuit 16 for obtaining an exclusive OR logic of the output signal of the memory 15 and the state input signal line 111. Are combined. The output signal of the exclusive OR circuit 16 is transmitted to the corresponding product term line 102. Only when the output signal of the memory 15 matches the signal logic of the state input signal line 111, the corresponding product term line is driven to the high level by the exclusive OR circuit 16.
[0031]
Here, according to the prior art, the number of memory bits consumed per product term line is twice that of the state input signal line 111. On the other hand, in the configuration shown in FIG. 2, since the comparison circuit 110 is configured by the memory 15 and the exclusive OR circuit 16, the number of memories per product term line when a sequential circuit is configured. The number of state input signal lines 111 is the same as the number of state input signal lines 111, so that the memory usage can be reduced.
[0032]
FIG. 3 shows a main part in another configuration example of the programmable logic circuit.
[0033]
The configuration shown in FIG. 3 differs greatly from the configuration shown in FIGS. 1 and 2 by providing the priority control logic circuit 206 and the priority ignoring instruction memory 207, so that the sum in the product-sum logic is one. This is the point where the part is replaced with the difference. The priority control logic circuit 206 includes AND circuits 21 and 22 and an OR circuit 22. The AND logic between the output signal of the wired-and-circuit 107 and the logic inverted signal of the priority control signal 208 is obtained by the AND circuit 21, and the OR logic of the output signal and the priority control signal 208 is obtained by the OR circuit 22. An AND logic between the output signal of the OR circuit 22 and the output signal of the memory 207 is obtained by the AND circuit 23. The output signal of the AND circuit 23 is transmitted to the adjacent circuit as a priority control signal.
[0034]
The operation of the above configuration will be described.
[0035]
FIG. 4 shows an example of state transition in the sequential circuit.
[0036]
The state S10 (400) and the state S01 (401) are represented by 2-bit state variables, the 2-bit state input signal 11 is taken in, and the transition 1 (402) and the transition 2 (402) are performed according to the 2-bit condition input signal 101. It is assumed that the user logic has a 2-bit output signal (104) for realization.
[0037]
Here, a simple product-sum logic type programmable logic circuit requires a 24-bit memory in at least three product term lines 302 and a switch circuit 300 with a memory, as shown in FIG. This means that one product term line 410 representing the transition 1 (402) from the state S10 to S10 and two product term lines 411 and 412 representing the transition 2 (403) from the state S10 to S01 are required. by. On the other hand, when the configuration shown in FIG. 3 is adopted, a total of 18 bits of memory including two product term lines 102 and output memory element 105 is sufficient as shown in FIG. Realizes a 25% reduction in memory size.
[0038]
A product term line 420 corresponding to the transition 1 (402) from the state S10 to S10, and a product term line 421 for executing the transition 2 (403) from the state S10 to the S01 when the conditions do not match, A priority ignore instruction memory 207 is set. By assigning priorities to product term lines in this way, it is possible to overwrite the coincidence state of product term lines with lower priority with product term lines with higher priority, and to reduce the usage of product term lines. Can do.
[0039]
When the above prioritization is performed, the overhead of the operation speed increases due to the delay of the priority control logic circuit 206. However, according to the configuration examples shown in FIGS. By adding the circuit 23, it is possible to minimize the overhead of the operation speed by ignoring the priority order between the product term lines which are not matched at the same time. That is, the state of the AND circuit 23 is controlled by the output signal of the priority order ignoring instruction memory 207, and the priority order is ignored as necessary. Specifically, the priority order control is valid when the output of the memory 207 is a logical value “1”, and the priority order is ignored when the output of the memory 207 is a logical value “0”.
[0040]
FIG. 7 shows another configuration example of the programmable logic circuit 705. The programmable logic circuit 705 shown in FIG. 7 is greatly different from that shown in FIG. 6 by obtaining the NOR logic of the output signals of the plurality of eye-and-circuits 107 to form the mismatch signal NH. A NOR circuit 220 is provided. In the programmable logic circuit 705, when the condition for state transition does not occur, in other words, the logic of the state input signal line 111 and the logic of the memory 15 are compared. The mismatch signal NH is asserted to a high level only when the output signal is set to a low level.
[0041]
FIG. 8 shows a case where the programmable logic circuit 705 having the above configuration is applied to a sequencer.
[0042]
The output signal of the programmable logic circuit 705 is latched in a state holding latch 701 disposed in the subsequent stage, and the output signal of the latch circuit 701 is transmitted to the programmable logic circuit 705 as a state input signal. If all product term lines do not match, it can be considered a malfunction in the sequencer. Therefore, if no coincidence is found in all product term lines, the programmable logic circuit 705 asserts the mismatch signal NH at a high level. The holding state of the latch circuit 701 is cleared by asserting the mismatch signal NH. In this way, an output (NH) when no coincidence occurs in all product term lines with respect to the input is obtained, and the holding state of the latch circuit 701 is thereby cleared, so that the normal operation when the sequencer malfunctions. Returning to is easy.
[0043]
FIG. 9 shows a configuration example when a plurality of programmable logic circuits 705 are cascade-connected as a sequencer. In the configuration example shown in FIG. 9, a tri-state buffer 702 is provided after the two programmable logic circuits 705, and a latch circuit 701 is provided after the tri-state buffer 702. The operation of the tristate buffer 702 is controlled by a mismatch signal NH from the corresponding programmable logic circuit 705. When the mismatch signal NH is asserted, the corresponding tri-state buffer is set to a high impedance state. In the period when the mismatch signal NH is negated, the tristate buffer 702 is turned on, and the output signal of the corresponding programmable logic circuit 705 is transmitted to the latch circuit 701.
[0044]
In this manner, the plurality of programmable logic circuits 705 can be cascaded to increase the scale.
[0045]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0046]
In the above description, the case where the invention made by the present inventor is applied to the hard disk controller LSI, which is the field of use behind the invention, has been described. However, the present invention is not limited to this and is applied to various semiconductor integrated circuits. Can be widely applied.
[0047]
The present invention can be applied on condition that at least a plurality of product term lines are included.
[0048]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0049]
That is, by enabling a plurality of signal outputs for each product term line , redundant product term lines are not required in a simple product-sum logic type programmable logic circuit .
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a configuration example of a programmable logic circuit included in a semiconductor integrated circuit according to the present invention.
FIG. 2 is a circuit diagram showing another configuration example of the programmable logic circuit.
FIG. 3 is a circuit diagram illustrating another configuration example of a main part in the programmable logic circuit.
FIG. 4 is an explanatory diagram of a state transition example in a sequential circuit.
5 is a circuit diagram of a configuration example in a case where the state transition shown in FIG. 4 is realized by a simple product-sum logic type programmable logic circuit.
FIG. 6 is a circuit diagram showing another configuration example of the programmable logic circuit.
FIG. 7 is a circuit diagram illustrating another configuration example of the programmable logic circuit.
FIG. 8 is an explanatory diagram when the programmable logic circuit is applied to a sequencer.
FIG. 9 is an explanatory diagram when the programmable logic circuit is applied to a sequencer.
FIG. 10 is a circuit diagram of a configuration example of a circuit to be compared with a programmable logic circuit included in the semiconductor integrated circuit according to the present invention.
FIG. 11 is a circuit diagram of a configuration example of a circuit to be compared with a programmable logic circuit included in the semiconductor integrated circuit according to the present invention.
FIG. 12 is a circuit diagram of a configuration example of a circuit to be compared with a programmable logic circuit included in the semiconductor integrated circuit according to the present invention.
[Explanation of symbols]
10 output logic 100 switch circuit 101 condition input signal line 102 product term line 111 state input signal line 206 priority control logic circuit 701 latch circuit 702 tristate buffer 705 progulable logic circuit

Claims (5)

Multiple product term lines;
A plurality of condition input signal lines formed to intersect the product term line;
A plurality of switch circuits provided at intersections of the product term line and the condition input signal line, and determining the logic of the product term line based on the logic of the condition input signal line;
Output logic that enables a plurality of signal outputs for each product term line, and
The output logic includes a plurality of memories each capable of 1-bit information programming,
A plurality of AND circuits arranged corresponding to the memory and enabling logical operation of the output signal of the product term line and the output signal of the memory,
A programmable logic circuit capable of programmably setting logic outputs from the plurality of AND circuits by information programming to the memory . A plurality of state input signal lines formed to intersect the product term line;
Provided at the intersection of the product term line and the state input signal line, for comparing the logic of the state input signal line with a preset logic and driving the product term line according to the comparison result The programmable logic circuit according to claim 1, further comprising a comparison circuit.   3. The programmable logic circuit according to claim 1, further comprising a priority control logic circuit capable of overwriting a state of a product term line having a low priority with a state of a product term line having a high priority according to the priority of the product term line.   4. The programmable circuit according to claim 1, further comprising a logic circuit that forms a determination signal as to whether or not there is a product term line that matches a condition input signal fetched via the condition input signal line. Logic circuit. A first programmable logic circuit;
A first tri-state buffer disposed downstream of the first programmable logic circuit and controlled in response to the determination signal;
A second programmable logic circuit cascaded to the first programmable logic circuit;
A second tri-state buffer disposed downstream of the second programmable logic circuit and controlled in response to the determination signal;
5. A semiconductor device comprising: a latch circuit in which the first tri-state buffer and the second tri-state buffer are commonly connected, wherein the first and second programmable logic circuits are the programmable logic circuit according to claim 4. Integrated circuit.

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