JP4061653B2 - Abnormal state detection circuit - Google Patents

Abnormal state detection circuit Download PDF

Info

Publication number
JP4061653B2
JP4061653B2 JP2005022946A JP2005022946A JP4061653B2 JP 4061653 B2 JP4061653 B2 JP 4061653B2 JP 2005022946 A JP2005022946 A JP 2005022946A JP 2005022946 A JP2005022946 A JP 2005022946A JP 4061653 B2 JP4061653 B2 JP 4061653B2
Authority
JP
Japan
Prior art keywords
resistor
switch
current source
current
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005022946A
Other languages
Japanese (ja)
Other versions
JP2006208282A (en
Inventor
薫 佐野
久 齋藤
公英 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP2005022946A priority Critical patent/JP4061653B2/en
Publication of JP2006208282A publication Critical patent/JP2006208282A/en
Application granted granted Critical
Publication of JP4061653B2 publication Critical patent/JP4061653B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Description

本発明は、電流源の電流を取り込んで上位側の機器に電流入力信号を出力するモジュールの異常状態検出回路に関するものである。   The present invention relates to an abnormal state detection circuit for a module that takes in a current from a current source and outputs a current input signal to a higher-level device.

計装システムにおけるプロセス制御に用いられる電圧入力回路において、電圧発生源との間の接続部の断線を検出する方式に関する技術としては例えば下記のようなものが知られている。   In the voltage input circuit used for process control in an instrumentation system, for example, the following is known as a technique related to a method for detecting disconnection of a connection portion between a voltage generation source.

特開2000−131368号公報JP 2000-131368 A

また、電流源の電流を取り込んで上位側の機器に電流入力信号を出力するモジュールの異常状態検出回路に関するものとして図5に示すものがある。   FIG. 5 shows an abnormal state detection circuit for a module that takes in a current from a current source and outputs a current input signal to a higher-level device.

図5において、1は例えば4〜20mAの電流源、2はモジュールで電流源1とはコネクタ端子C,C’を介して接続されている。第1抵抗R1の一端は電流源のコネクタCに接続され、他端はFET(第1スイッチ)3のソース端子に接続されている。   In FIG. 5, 1 is a current source of 4 to 20 mA, for example, 2 is a module, and is connected to the current source 1 via connector terminals C and C '. One end of the first resistor R1 is connected to the connector C of the current source, and the other end is connected to the source terminal of the FET (first switch) 3.

FET3のドレイン端子には第2抵抗R2の一端が接続されその他端は電流源1のコネクタ端子C’に接続されている。
FET3のドレイン端子と第2抵抗R2の接続点には第2スイッチ4を介して増幅手段(以下OPアンプという)5の非反転入力端子が接続されている。
One end of the second resistor R2 is connected to the drain terminal of the FET 3, and the other end is connected to the connector terminal C ′ of the current source 1.
A non-inverting input terminal of an amplifying means (hereinafter referred to as an OP amplifier) 5 is connected to a connection point between the drain terminal of the FET 3 and the second resistor R 2 through a second switch 4.

OPアンプ5の出力端はA/D変換器6の入力端子に接続されると共にOPアンプ5の反転入力端子に接続されている。A/D変換器6の出力は制御装置7に入力され、FET3のゲートは制御装置7に接続されている。   The output terminal of the OP amplifier 5 is connected to the input terminal of the A / D converter 6 and to the inverting input terminal of the OP amplifier 5. The output of the A / D converter 6 is input to the control device 7, and the gate of the FET 3 is connected to the control device 7.

上述の構成において、第2スイッチ4をオンとし、制御装置7からFET3のゲートに対して電圧を印加するとFET(第1スイッチ)3がオンとなり、抵抗R2の両端電圧が第2スイッチ4を介してOPアンプ5に入力する。OPアンプ5の出力端子はA/D変換器6の入力端子に接続されると共にOPアンプ5の反転端子に接続されていて、例えば1:1に増幅され制御装置7に入力する。制御装置7はその入力を電流源の電流として外部に出力する。 In the above-described configuration, when the second switch 4 is turned on and a voltage is applied from the control device 7 to the gate of the FET 3, the FET (first switch) 3 is turned on, and the voltage across the resistor R 2 passes through the second switch 4. Input to the OP amplifier 5. The output terminal of the OP amplifier 5 is connected to the input terminal of the A / D converter 6 and is connected to the inverting terminal of the OP amplifier 5, and is amplified, for example, 1: 1 and input to the control device 7. The control device 7 outputs the input as the current of the current source to the outside.

上述の構成において、制御装置7からの出力が0となった場合は電流源1に断線が発生したことがわかる。しかしながら、モジュール内部に異常が発生した場合はどの部分における異常なのかがわからないという問題があった。   In the above-described configuration, when the output from the control device 7 becomes 0, it can be seen that the current source 1 is disconnected. However, when an abnormality occurs in the module, there is a problem that it is not possible to know which part is abnormal.

本発明は上述の問題点を解決するためになされたもので、モジュール内部に異常が発生した場合、どの部分で発生したかを判断可能な異常状態検出回路を提供することを目的とするものである。   The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide an abnormal state detection circuit capable of determining in which part an abnormality has occurred in a module. is there.

電流源からの電流を入力し制御装置を介して上位側に電流入力信号を出力する電流入力モジュールであって、電流源の一方のコネクタ端子に一端が接続された第1抵抗と、この第1抵抗の他端に一端が接続された第1スイッチと、この第1スイッチの他端に一端が接続され他端が前記電流源の他方のコネクタ端子にダイオードを介して接続された第2抵抗と、前記第1スイッチの他端と第2抵抗の接続点に第2スイッチを介して入力端子が接続された増幅手段と、この増幅手段の出力端子に接続されたA/D変換器と、このA/D変換器の後段に接続され、前記第1スイッチのオンオフを行う制御装置を有する異常状態検出回路において、
前記電流源の一方のコネクタ端子と前記第1抵抗の接続点と前記増幅手段の入力端子と前記第2スイッチの接続点を第3スイッチを介して接続し、前記電流源から電流を流したときに前記第2抵抗に生じる電圧をVin、前記第1抵抗と第1スイッチと第2抵抗を加えた抵抗に生じる電圧をVin’としたときに、前記モジュールに断線が生じた場合、前記電圧Vin,Vin’の関係を断線前の電圧の関係と比較することにより断線箇所を判別することを特徴とする。
A current input module for inputting a current from a current source and outputting a current input signal to a higher-order side via a control device, a first resistor having one end connected to one connector terminal of the current source, and the first resistor A first switch having one end connected to the other end of the resistor; a second resistor having one end connected to the other end of the first switch and the other end connected to the other connector terminal of the current source via a diode ; Amplifying means having an input terminal connected to a connection point between the other end of the first switch and the second resistor via a second switch; an A / D converter connected to the output terminal of the amplifying means; In an abnormal state detection circuit having a control device connected to the subsequent stage of the A / D converter and for turning on and off the first switch,
When a connection point between one connector terminal of the current source and the first resistor, an input terminal of the amplifying means and a connection point of the second switch are connected via a third switch, and a current flows from the current source When the voltage generated in the second resistor is Vin, and the voltage generated in the resistor obtained by adding the first resistor, the first switch, and the second resistor is Vin ′, if the module is disconnected, the voltage Vin , Vin ′ is compared with the voltage relationship before disconnection to determine the disconnection location .

本発明によれば次のような効果がある。
流源と第1抵抗の接続点と増幅手段の入力端子と第2スイッチの接続点の間を第3スイッチを介して接続したので、異常が発生した場合は第1抵抗と第1スイッチと第2抵抗を加えた抵抗に発生する電圧と第2抵抗R2に発生する電圧が変化する。その変化した電圧の関係を異常が発生する前の電圧の関係と比較して異常箇所を見つけることができる。
The present invention has the following effects.
Since between the input terminal and the connection point of the second switch of the current source and the first resistor connecting point between the amplifying means is connected via a third switch, when an abnormality occurs with the first resistor and the first switch The voltage generated in the resistor including the second resistor and the voltage generated in the second resistor R2 change. The abnormality the relationship changed voltage Ru can find the abnormal point as compared to the relationship between the previous voltage generated.

以下本発明を図面を用いて詳細に説明する。図1は本発明に係る異常状態検出回路の一例を示すもので、図5に示す従来例と異なる点は、電流源1のコネクタ端子Cと第1抵抗R1の接続点とOPアンプ5の入力端子と第2スイッチ4の接続点の間を第3スイッチ8を介して接続したものである。 Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows an example of an abnormal state detection circuit according to the present invention. The difference from the conventional example shown in FIG. 5 is that the connection point between the connector terminal C of the current source 1 and the first resistor R1 and the input of the OP amplifier 5. between the connection point of the terminal and the second switch 4 which are connected via a third switch 8.

図1において、電流源1に流れる電流を4〜20mAとし、抵抗R1は電流が20mA流れたときに5Vの電圧が発生するように設計され、抵抗R2は電流が20mA流れたときに1Vの電圧が発生するように設計されているものとする。また、OPアンプ5は10Vの電圧で駆動されているものとする。   In FIG. 1, the current flowing through the current source 1 is 4 to 20 mA, the resistor R1 is designed to generate a voltage of 5 V when the current flows 20 mA, and the resistor R2 is a voltage of 1 V when the current flows 20 mA. Is designed to occur. The OP amplifier 5 is assumed to be driven with a voltage of 10V.

上述の構成において、通常制御装置7は第2スイッチ4、第3スイッチ8を切換えながら第2抵抗の両端電圧と、第2抵抗+第1スイッチ(FET)3+第1抵抗の電圧を測定している。また、先に述べたようにモジュール2は電流源1を流れる電流に関連した電流を制御装置7から出力している。
In the above-described configuration, the normal controller 7 measures the voltage across the second resistor and the voltage across the second resistor + first switch (FET) 3 + first resistor while switching the second switch 4 and the third switch 8. Yes. Further, as described above, the module 2 outputs a current related to the current flowing through the current source 1 from the control device 7.

電流源1が異常のときはFET3と第2抵抗R2の接続点とFET3を介してOPアンプ5に印加される電圧Vinおよび電流源1と第1抵抗R1の接続点と増幅手段5の入力端子間に印加される電圧Vin’は共に0となるので電流源1若しくはモジュール外部のケーブルに異常があるということが分かる。   When the current source 1 is abnormal, the connection point between the FET 3 and the second resistor R2, the voltage Vin applied to the OP amplifier 5 through the FET 3, the connection point between the current source 1 and the first resistor R1, and the input terminal of the amplification means 5 Since the voltage Vin ′ applied between them is 0, it can be seen that there is an abnormality in the current source 1 or the cable outside the module.

次に、FET3に異常が発生した場合は、回路に流れる電流は0となるが電流源1は一定の電流を流そうとするので第1抵抗R1の電圧Vin’が上昇する。このことによりFET3に異常が発生したことが分かる。   Next, when an abnormality occurs in the FET 3, the current flowing through the circuit becomes 0, but the current source 1 tries to flow a constant current, so the voltage Vin 'of the first resistor R1 rises. This shows that an abnormality has occurred in the FET 3.

次に、第2抵抗R2に異常が発生した場合は電流は第1抵抗R1、第2抵抗R2共に流れないが電流源1は一定の電流を流そうとするので第1抵抗R1の電圧Vin’および第2抵抗R2の電圧Vinともに上昇する。   Next, when an abnormality occurs in the second resistor R2, the current does not flow in both the first resistor R1 and the second resistor R2, but the current source 1 tries to pass a constant current, so the voltage Vin ′ of the first resistor R1. And the voltage Vin of the second resistor R2 rises.

次に、例えばOPアンプ5の駆動電圧が10Vだったとし、回路を流れる電流が20mAであったとする。そして、このOPアンプに異常が発生し、OPアンプの駆動電圧が10Vから4Vに低下したとする。この場合第2抵抗Rの電圧Vinには1Vが印加されるのでOPアンプ5からは1Vが出力される。 Next, for example, it is assumed that the driving voltage of the OP amplifier 5 is 10 V, and the current flowing through the circuit is 20 mA. Then, it is assumed that an abnormality occurs in the OP amplifier and the drive voltage of the OP amplifier is reduced from 10V to 4V. In this case, since 1 V is applied to the voltage Vin of the second resistor R 2 , 1 V is output from the OP amplifier 5.

一方第1抵抗と第1スイッチと第2抵抗を加えた抵抗に発生する電圧Vin’は5Vであるが、OPアンプ5を通すとOPアンプ5の駆動電圧4Vが出力される(Rale to RaleのOPアンプの場合)。Vin’は5V電圧となるべきところ4Vしか出力しないのでVin’との間に矛盾が生じOPアンプの異常を検出することが可能となる。
VinとVin’の関係は図2の通りとなる。
即ち、OPアンプ5が正常に機能していればVin’の出力電圧は図2のイで示す直線になるが、異常が発生し駆動電圧が10Vから4Vに低下した場合はロで示すように4Vとなる。ハはVinの出力電圧である。
On the other hand, the voltage Vin ′ generated in the resistor including the first resistor , the first switch, and the second resistor is 5V, but when the OP amplifier 5 is passed through, the drive voltage 4V of the OP amplifier 5 is output (Rare to Rare). (For OP amp). Since Vin ′ outputs only 4V where it should be a 5V voltage, a contradiction occurs between Vin ′ and it becomes possible to detect an abnormality of the OP amplifier.
The relationship between Vin and Vin ′ is as shown in FIG.
That is, if the OP amplifier 5 is functioning normally, the output voltage of Vin ′ becomes a straight line indicated by a in FIG. 2, but if an abnormality occurs and the drive voltage decreases from 10V to 4V, as indicated by B. 4V. C is the output voltage of Vin.

本発明の以上の説明は、説明および例示を目的として特定の好適な実施例を示したに過ぎない。例えば、本実施例では第1スイッチはFETとしたが同様の機能を有するものであれば他のスイッチでもよい。また、電流源を流れる電流は4〜20mAとしたが、本実施例に限るものではない。また、OPアンプの駆動電圧を10Vとしたがこの電圧に限るものではない。   The foregoing description of the present invention has only shown certain preferred embodiments for purposes of illustration and illustration. For example, although the first switch is an FET in this embodiment, another switch may be used as long as it has a similar function. Moreover, although the current flowing through the current source is 4 to 20 mA, it is not limited to this embodiment. Further, although the driving voltage of the OP amplifier is 10V, it is not limited to this voltage.

したがって本発明はその本質から逸脱せずに多くの変更、変形をなし得ることは当業者に明らかである。特許請求の範囲の欄の記載により定義される本発明の範囲は、その範囲内の変更、変形を包含するものとする。   Accordingly, it will be apparent to those skilled in the art that the present invention can be modified and modified in many ways without departing from the essence thereof. The scope of the present invention defined by the description in the appended claims is intended to include modifications and variations within the scope.

本発明に係る異常状態検出回路の一実施例を示す構成図である。It is a block diagram which shows one Example of the abnormal condition detection circuit which concerns on this invention. OPアンプ異常の場合の出力を示す説明図である。It is explanatory drawing which shows the output in case of OP amplifier abnormality. 従来の異常状態検出回路の構成を示す斜視図である。It is a perspective view which shows the structure of the conventional abnormal condition detection circuit.

符号の説明Explanation of symbols

1 電流源
2 モジュール
3 第1スイッチ
4 第2スイッチ
5 OPアンプ
6 AD変換器
7 制御装置
8 第3スイッチ
R1 第1抵抗
R2 第2抵抗
D1 ダイオード
DESCRIPTION OF SYMBOLS 1 Current source 2 Module 3 1st switch 4 2nd switch 5 OP amplifier 6 AD converter 7 Control apparatus 8 3rd switch R1 1st resistance R2 2nd resistance D1 Diode

Claims (1)

電流源からの電流を入力し制御装置を介して上位側に電流入力信号を出力する電流入力モジュールであって、電流源の一方のコネクタ端子に一端が接続された第1抵抗と、この第1抵抗の他端に一端が接続された第1スイッチと、この第1スイッチの他端に一端が接続され他端が前記電流源の他方のコネクタ端子にダイオードを介して接続された第2抵抗と、前記第1スイッチの他端と第2抵抗の接続点に第2スイッチを介して入力端子が接続された増幅手段と、この増幅手段の出力端子に接続されたA/D変換器と、このA/D変換器の後段に接続され、前記第1スイッチのオンオフを行う制御装置を有する異常状態検出回路において、
前記電流源の一方のコネクタ端子と前記第1抵抗の接続点と前記増幅手段の入力端子と前記第2スイッチの接続点を第3スイッチを介して接続し、前記電流源から電流を流したときに前記第2抵抗に生じる電圧をVin、前記第1抵抗と第1スイッチと第2抵抗を加えた抵抗に生じる電圧をVin’としたときに、前記モジュールに断線が生じた場合、前記電圧Vin,Vin’の関係を断線前の電圧の関係と比較することにより断線箇所を判別することを特徴とする異常状態検出回路。
A current input module for inputting a current from a current source and outputting a current input signal to a higher-order side via a control device, a first resistor having one end connected to one connector terminal of the current source, and the first resistor A first switch having one end connected to the other end of the resistor; a second resistor having one end connected to the other end of the first switch and the other end connected to the other connector terminal of the current source via a diode ; Amplifying means having an input terminal connected to a connection point between the other end of the first switch and the second resistor via a second switch; an A / D converter connected to the output terminal of the amplifying means; In an abnormal state detection circuit having a control device connected to the subsequent stage of the A / D converter and for turning on and off the first switch,
When a connection point between one connector terminal of the current source and the first resistor, an input terminal of the amplifying means and a connection point of the second switch are connected via a third switch, and a current flows from the current source When the voltage generated in the second resistor is Vin, and the voltage generated in the resistor obtained by adding the first resistor, the first switch, and the second resistor is Vin ′, if the module is disconnected, the voltage Vin , Vin ′ is compared with the voltage relationship before disconnection to determine the location of disconnection .
JP2005022946A 2005-01-31 2005-01-31 Abnormal state detection circuit Active JP4061653B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005022946A JP4061653B2 (en) 2005-01-31 2005-01-31 Abnormal state detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005022946A JP4061653B2 (en) 2005-01-31 2005-01-31 Abnormal state detection circuit

Publications (2)

Publication Number Publication Date
JP2006208282A JP2006208282A (en) 2006-08-10
JP4061653B2 true JP4061653B2 (en) 2008-03-19

Family

ID=36965300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005022946A Active JP4061653B2 (en) 2005-01-31 2005-01-31 Abnormal state detection circuit

Country Status (1)

Country Link
JP (1) JP4061653B2 (en)

Also Published As

Publication number Publication date
JP2006208282A (en) 2006-08-10

Similar Documents

Publication Publication Date Title
CN100454709C (en) Apparatus for detecting over current of motor in vehicle
JP4296811B2 (en) Physical quantity sensor device
JP4743135B2 (en) Detection system
JP6612583B2 (en) Open / Circuit detection circuit
JP4882710B2 (en) Load drive device failure detection device and load drive IC
CN102057573A (en) Overcurrent protective device for load circuit
JP4061653B2 (en) Abnormal state detection circuit
WO2018092475A1 (en) Wiring line abnormality detecting device
JP2006349466A (en) Temperature detecting device
JP2006064596A (en) Current detector
JP5989171B1 (en) CURRENT DETECTION CIRCUIT AND ELECTRIC CONTROL DEVICE FOR VEHICLE HAVING THE CIRCUIT
JP4300773B2 (en) Anomaly detection device
JP2006047006A (en) Disconnection detection circuit
JP2007333666A (en) Disconnection detection method and device
JP2006137280A (en) Electric power steering device
JP2007218664A (en) Electrical current detector
JP6797035B2 (en) Magnetic sensor and magnetic sensor device
JP2001108712A (en) Current detector
JP2007046992A (en) Electric device
JP4447350B2 (en) Overcurrent protection circuit of signal output circuit
KR101902293B1 (en) Leakage current monitoring system for bidirectional DC motor
JP4710848B2 (en) Detection system
JP2004247367A (en) Linear solenoid driving-gear
JP5325559B2 (en) Speaker diagnosis method and apparatus
JP2004166291A (en) Signal output circuit

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070423

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070426

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070615

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071101

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071112

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071203

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071216

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4061653

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140111

Year of fee payment: 6