JP4058117B2 - Data storage device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a data storage device.
[0002]
[Prior art]
Generally, in a disk-type secondary storage device connected to a computer, a data storage location is divided into units of a certain capacity called a sector and is continuously arranged on a track in the disk. Disk-type secondary storage devices are diversified into hard disks, floppy disks, MO disks, and the like. In the case of the MO disk, two types of sectors of 1024 bytes and 512 bytes are standardized in the 5.25 inch ISO format.
[0003]
FIG. 7 shows the 5.25 inch ISO format in the case of 1024 bytes / sector.
[0004]
In this format, the first area 41 is an area indicating the head of a sector called a sector mark, and is configured with a special pattern different from other areas. The second area 42 is an area called VFO, and is an area for drawing a read clock. The third area 43 is an area called an address mark, and is an area for obtaining synchronization for reading the next fourth area. The fourth area 44 is an area called ID and is an area in which the address (track number, sector number) of the sector is stored. The fifth area 45 is an area called a postamble and is an area necessary for completing modulation / demodulation.
[0005]
The first area 41 to the fifth area 45 are also called preformatted areas, and a pattern (prepit) is formed by a depression having an appropriate depth on the disk surface for reproducing information by the intensity of reflected light. This is a playback-only area.
[0006]
The sixth area 46 is an area for gaps, flags, etc., for adjusting actuator servos, adjusting laser power, and the like. The seventh area 47 is a VFO area and is an area for drawing the read clock in the ninth area 49. The eighth area 48 is an area called a sink, and is an area indicating the head of the next ninth area. The ninth area 49 is a data area where data from the host computer is recorded and reproduced.
[0007]
In the ninth area 49, redundant information such as an error correction code (ECC) and a detection code (CRC) calculated by a predetermined generator polynomial is used to deal with medium defects such as pinholes in the recording film. The added data is recorded. The data recorded in the ninth area 49 is decoded at the time of reading, error correction is performed, and the data is reproduced as one sector data.
[0008]
Furthermore, the 10th area | region 50 is an area | region for absorbing a rotation deviation etc. of a motor by the area | region called a buffer.
[0009]
The seventh area 47 to the tenth area 50 are areas for recording and reproduction. Recording is performed by thermomagnetic recording using a laser beam and a bias magnetic field, and reproduction is performed by rotating the polarization plane of reflected light (Kerr rotation). ) By detecting the component.
[0010]
Here, 512 bytes are generally used as the sector size on the computer side. Since an error correction code is added at 1024 bytes on the MO disk, only a specific 512 bytes cannot be rewritten.
[0011]
Therefore, in the conventional MO driver, when rewriting 512-byte data of the logical sector M + 1 among the 1024-byte data of the physical sector N composed of the logical sector M and the logical sector M + 1, for example, as shown in the flowchart of FIG. When a write request is received from the host computer side, first, 1024 bytes of data in the physical sector N including the corresponding data is read into addresses corresponding to the logical sector M and logical sector M + 1 in the buffer memory (step 1). The 512-byte data to be rewritten is transferred from the host computer side to another address of the buffer memory (step 2), the completion of the data transfer from the host computer side is confirmed (step 3), and the data of sector N is read. Confirm the end of (step 4) The new 1024-byte data after rewriting is synthesized in the buffer memory (step 5), and write data obtained by adding an error correction code to the new 1024-byte data is written to the MO disk (step 6). It was like that.
[0012]
Alternatively, as shown in the flowchart of FIG. 9, when there is a write request from the host computer side, first, the 1024-byte data of sector N including the corresponding data is assigned to the addresses corresponding to logical sector M and logical sector M + 1 in the buffer memory. Read (step 1), confirm the end of reading of data in sector N (step 2), and directly transfer 512-byte data to be rewritten from the host computer side to the address corresponding to logical sector M + 1 of the buffer memory (step 3) After confirming the end of data transfer from the host computer side (step 4), write data in which an error correction code is added to the new 1024 bytes of data after rewriting is written to the MO disk (step 5). It was like that.
[0013]
[Problems to be solved by the invention]
However, when data is rewritten by the procedure shown in the flowchart of FIG. 8 described above, it is necessary to synchronize with the end of data transfer from the host computer side and the end of reading of data in sector N of the disk. In order to synthesize new 1024 bytes of data after rewriting in the buffer memory, there is a problem that the effective processing time becomes long.
[0014]
Further, when data is rewritten by the procedure shown in the flowchart of FIG. 9 described above, there is a problem that data transfer from the host computer side must be performed after completion of reading of data of sector N of the disk. there were.
[0015]
Therefore, in view of the conventional problems as described above, an object of the present invention is to provide a data storage device that can perform data transfer in a short transfer time without having to control the arrival order of data with respect to the data rewrite section. It is to provide.
[0017]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a data storage device including a storage unit capable of storing data by designating an address where data is stored with a constant bit length as one data unit, and a first data length of the first data First input means for inputting a first request signal for requesting storage to the storage means, and second data shorter than the first data length replaced with a part of the first data Second input means for receiving a second request signal for requesting storage of the second long data in the storage means irrespective of the arrival order of the data input from the first input means; First address generation means for generating an address for storing data input from the first input means in the storage means, and data input from the second input means are stored in the storage means Part of the first data The basis of the second address generating means for generating an address for recombinant stores, and inhibition starting address and prohibition release address part of the storage of the first data to be replaced with the second data that is set in advance in the Address detecting means for detecting an address area in which the second data is stored, and an address at which the second data is stored based on a detection result by the address detecting means. In the case where the first data is stored in the storage means, the first data storage address is not the address where the second data is stored. to release the suppression of storage operation of the data of the storage means, and characterized in that the first data and a control means for controlling to store into the memory means That.
[0018]
A data storage device according to a second aspect of the invention is the data storage device according to the first aspect of the invention, wherein the response signal outputs a response signal based on the output of the first input means to which the first request is input. An output means is further provided.
[0019]
Further, the data storage device according to the third invention is the data storage device according to the second invention, wherein the response signal output means is a period during which the storage of the first data in the storage means is suppressed. Is also characterized by outputting a response signal.
[0020]
Further, the data storage device according to the fourth invention is the data storage device according to the first invention, wherein the address detection means includes an address generated from the first address generation means, a write prohibition start address, and a prohibition. Two comparison means for comparing with each of the release addresses are provided.
[0021]
[Action]
In the data storage device according to the first aspect of the present invention, the first data length of the first data is stored in the storage means capable of storing the data by designating an address where the data is stored with a constant bit length as one data unit . A first request signal for requesting storage is input to the first input means, and the second data having a second data length shorter than the first data length is replaced with a part of the first data. A second request signal for requesting storage in the storage means is input to the second input means regardless of the arrival order of the data input from the first input means, and input from the first input means An address for storing the data to be stored in the storage means is generated by the first address generation means, and the data input from the second input means is one of the first data stored in the storage means. Replace with part An address for storing generated by the second address generating means, the address detecting means of the first data to be replaced with the second above data Ru preset address area stored the second data temporary Is detected on the basis of the prohibition start address and prohibition release address of the storage of the data , and the control means detects that the storage address of the first data is the address where the second data is stored. In the case where the first data is stored, the storage operation of the first data in the storage unit is suppressed, and when the storage address of the first data is not the address where the second data is stored, the first data is stored. The control of storing the first data in the storage unit is performed by releasing the suppression of the storage operation of the data in the storage unit .
[0022]
In the data storage device according to the second invention, in the data storage device according to the first invention, a response signal is output based on the output of the first input means to which the first request is inputted by the response signal output means To do.
[0023]
Further, in the data storage device according to the third invention, in the data storage device according to the second invention, the response signal output means suppresses the storage of the first data in the storage means. Also outputs a response signal.
[0024]
Furthermore, in the data storage device according to the fourth invention, in the data storage device according to the first invention, the address detection means includes an address generated from the first address generation means, a write prohibition start address, and a prohibition. Each is compared with the two comparison means with the release address.
[0025]
【Example】
Hereinafter, an embodiment of a data storage device according to the present invention will be described in detail with reference to the drawings.
[0026]
The embodiment shown in the block diagram of FIG. 1 is one in which the present invention is applied to an MO disk driver that records and reproduces data with respect to an MO disk 1 of 5.25 inch ISO format.
[0027]
In this MO disk driver, the MO disk 1 is rotationally driven by a spindle motor 2 at a predetermined rotational speed. An optical pickup 3 disposed so as to face the recording / reproducing surface of the MO disk 1 incorporates an actuator controlled by an actuator control unit 4 so as to focus the light beam on the recording / reproducing surface. Focus servo and tracking servo for scanning the track on the recording / reproducing surface with the boom spot of the light beam.
[0028]
A coil 5 disposed so as to face the optical pickup 3 with the MO disk 1 in between is driven by a drive circuit 7 controlled by a system controller 6 and generates a magnetic field during recording.
[0029]
The signal optically read from the track on the recording / reproducing surface of the MO disk 1 by the optical pickup 3 is amplified by the RF signal processing block 8 and then binarized, and is converted into data and clock by the data separator 9. The result is separated and input to the modulation / demodulation format control unit 10.
[0030]
The modulation / demodulation / format control unit 10 performs various mark detection, data modulation / demodulation, error correction encoding, decoding, etc. according to the disk format, and transfers only data to be sent to the host computer to the buffer memory control unit 11. In the buffer memory control unit 11, data is written into the buffer memory 12 while performing competition control with transfer from other transfer channels. The data stored in the buffer memory 12 is read from the buffer memory 12 and sent to the host interface control unit 13 as appropriate in accordance with the use of the interface with the host computer. Forwarded to
[0031]
When recording, on the contrary, the data transferred from the host computer via the host interface 14 is stored in the buffer memory 12 via the host interface control unit 13, and the buffer memory control unit 11 performs timely recording. The data is read from the buffer memory 12 and input to the modulation / demodulation / format control unit 10. The modulation / demodulation / format control unit 10 generates write data by adding data modulation, error correction code, and the like. Then, the write data is synchronously controlled with the address of the sector to be written, etc., transferred to the laser drive unit 15 and written on the MO disk 1.
[0032]
As shown in FIG. 2, the buffer memory control unit 11 in the MO disk driver includes a transfer request receiving unit 21, an ACK selector 22, an address counter 23, and a timing generator controlled by the output of the transfer request receiving unit 21. 24, first and second comparators 25 and 26 to which the output of the address counter 23 is supplied, an RS flip-flop 27 to which the outputs of the first and second comparators 25 and 26 are supplied, and the timing generator An AND gate 28 to which 24 outputs are supplied, first and second OR gates 29, 30 and the like are provided.
[0033]
The transfer request receiving unit 21 receives transfer requests REQA and REQB from the two data transfer channels A and B, and also performs contention control when REQA and REQB come simultaneously. For example, when data is written from the channel A, the address counter 23 generates a transfer destination memory address, and the timing generator 24 generates write signals CS and WE for the buffer memory 12 and a transfer acknowledge ACK. It is generated at the timing.
[0034]
The ACK selector 22 is a selector that returns an ACK of the channel corresponding to the transfer request, and operates based on the output of the transfer request reception unit 21.
[0035]
Further, the first and second comparators 25 and 26 are comparators that compare a preset value with an address counter value obtained by the address counter 23, respectively, and detect a match between them . The comparator 25 detects the coincidence with the address counter value a when the write is prohibited, and the second comparator 26 detects the coincidence with the address counter value b when the write inhibition is released.
[0036]
For example, when writing data from channel A, when the address counter value of channel A reaches a, the output of the first comparator 25 becomes active, and the output of the RS flip-flop 27 (write inhibit signal WD). ) Becomes active. As a result, as shown in the timing chart of FIG. 3, the data write signals CS and WE from the channel A are prohibited from becoming active. However, for subsequent transfers from channel A, the REQ / ACK handshake is performed as it is, and the channel A address counter continues counting. When the address counter value reaches b, the output of the second comparator 26 becomes active, and the output (write inhibit signal WD) of the RS flip-flop 27 becomes inactive. As a result, as shown in the timing chart of FIG. 3, the data write signals CS and WE from channel A become active.
[0037]
As described above, writing of data from the channel A to the buffer memory 12 can be prohibited only in a section where the address counter value is a to b.
[0038]
When rewriting only 512 bytes of data from the host computer, 1024 bytes from the sector including rewrite data are read from the MO disk 1 on the channel A while receiving the data to be rewritten from the host computer in the buffer memory 12. On the other hand, the first and second comparators 25 and 26 compare and detect the address corresponding to the rewrite data with predetermined address counter values a and b, so that the rewrite data data out of the read data from the MO disk 1 is detected. Only the part of is prohibited from writing.
[0039]
That is, when rewriting 512-byte data of the logical sector M + 1, for example, among the 1024-byte data of the physical sector N composed of the logical sector M and the logical sector M + 1 as shown in FIG. As shown in the flowchart, when there is a write request from the host computer side, first, the 512-byte data to be rewritten is directly transferred from the host computer side to the address corresponding to the logical sector M + 1 of the buffer memory 12 (step 1). 1024 bytes of data is read out, and only the data of the logical sector M is read into the address corresponding to the logical sector M in the buffer memory 12 (step 2), and the completion of reading of the data of the sector N is confirmed (step 3). Data from the host computer Verify the completion of the transfer (Step 4), and writes the new 1024-byte data of write data by adding error correction codes to the MO disc (step 5).
[0040]
In the above-described embodiment, the second comparator 26 detects that the address counter value has reached b and cancels the prohibition of data writing to the buffer memory 12. Instead of the comparator 26, a presettable down counter 36 for counting the number of ACKs may be used as shown in FIG.
[0041]
The presettable down counter 36 is controlled in counting operation by the output of the RS flip-flop 27 (write inhibit signal WD), and performs a count operation only during write inhibit. In the presettable down counter 36, the number of data for which only input transfer is performed without writing in the buffer memory 12 during the write inhibition is set in the presettable down counter 36 in advance.
[0042]
When the number of transfer data during write inhibit reaches a set value, the RS flip-flop 27 is reset by the ripple carry output (CY) from the presettable down counter 36, and the write inhibit signal WD is made inactive. To do. As a result, the data write signals CS and WE from channel A become active.
[0043]
【The invention's effect】
In the data storage device according to the first aspect of the present invention, the first data length of the first data is stored in the storage means capable of storing the data by designating an address where the data is stored with a constant bit length as one data unit . A first request signal for requesting storage is input to the first input means, and the second data having a second data length shorter than the first data length is replaced with a part of the first data. A second request signal for requesting storage in the storage means is input to the second input means regardless of the arrival order of the data input from the first input means, and input from the first input means An address for storing the data to be stored in the storage means is generated by the first address generation means, and the data input from the second input means is one of the first data stored in the storage means. Replace with part An address for storing generated by the second address generating means, the address detecting means of the first data to be replaced with the second above data Ru preset address area stored the second data temporary Is detected on the basis of the prohibition start address and prohibition release address of the storage of the data , and the control means detects that the storage address of the first data is the address where the second data is stored. In the case where the first data is stored, the storage operation of the first data in the storage unit is suppressed, and when the storage address of the first data is not the address where the second data is stored, the first data is stored. after release the suppression of the storage operation to the memory means of the data, which the first data since the control for storing into the memory means, two independent of Performs the transfer of data in parallel from, it is not necessary to control the like arrival order data for the rewriting interval, it is possible to shorten the transfer time.
[0044]
In the data storage device according to the second invention, in the data storage device according to the first invention, a response signal is output based on the output of the first input means to which the first request is inputted by the response signal output means can do.
[0045]
Further, in the data storage device according to the third invention, in the data storage device according to the second invention, the response signal output means suppresses the storage of the first data in the storage means. Can also output a response signal.
[0046]
Furthermore, in the data storage device according to the fourth invention, in the data storage device according to the first invention, the address detection means includes an address generated from the first address generation means, a write prohibition start address, and a prohibition. By comparing with each other by means of two comparison means with the release address, it is possible to securely inhibit the data writing and release it.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an MO disk driver to which the present invention is applied.
FIG. 2 is a block diagram showing a main configuration of a buffer memory control unit in the MO disk driver.
FIG. 3 is a timing chart showing an operation of the buffer memory control unit.
FIG. 4 is a diagram schematically showing a sector structure of an MO disk in which data is rewritten by the MO disk driver.
FIG. 5 is a flowchart showing a procedure for rewriting data in the MO disk driver.
FIG. 6 is a block diagram showing another example of the main configuration of the buffer memory control unit.
FIG. 7 is a diagram showing a 5.25 inch ISO format of 1024 bytes / sector.
FIG. 8 is a flowchart showing a procedure for rewriting data in a conventional MO disk driver.
FIG. 9 is a flowchart showing another procedure for rewriting data in the MO disk driver.
[Explanation of symbols]
1... MO disk 8... Modulation / demodulation / format control unit 11... Buffer memory control unit 12... Buffer memory 13. Control unit 21 ··· Transfer request accepting unit 22 ··· ACK selector 23 ··· Address counter 24 ··· Timing generators 25 and 26 ··· Comparator 27 ··· ··· RS flip-flop 28 ··· AND gates 29 and 30 ··· OR gate 36 ······ Presettable down counter

Claims (4)

Storage means capable of storing data by designating an address in which data is stored with a fixed bit length as one data unit ;
First input means to which a first request signal for requesting storage of the first data of the first data length to the storage means is input;
The second data having a second data length shorter than the first data length to be replaced with a part of the first data is stored in the memory regardless of the arrival order of the data input from the first input means. A second input means for receiving a second request signal for requesting storage in the means;
First address generation means for generating an address for storing data input from the first input means in the storage means;
A second address generating means for generating an address for storing the data input from said second input means by replacing a portion of the first data stored in the memory means,
Address detecting means for detecting an address area in which the second data is stored on the basis of the inhibition starting address and prohibition release address part of the storage of the first data to be replaced with the second data that is set in advance When,
Based on the detection result by the address detecting means, the when the storage address of the first data is an address where the second data is stored, a storage operation to the first data in the storage means If the storage address of the first data is not the address where the second data is stored, the suppression of the storage operation of the first data in the storage means is released, and the first data A data storage device comprising: control means for performing control for storing the data in the storage means.   The data storage device according to claim 1, further comprising response signal output means for outputting a response signal based on an output of the first input means to which the first request is input.   The data storage device according to claim 2, wherein the response signal output means outputs a response signal even during a period in which the storage of the first data in the storage means is suppressed.   2. The data storage device according to claim 1, wherein the address detecting means comprises two comparing means for comparing each of the address generated from the first address generating means, the write prohibition start address, and the prohibition release address.

Images