JP4052137B2 - Preamble path position detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a preamble path position detection circuit in random access of a mobile communication system, and more particularly to a preamble path position detection circuit capable of reducing the amount of delay profile accumulation during delay profile calculation.
[0002]
[Prior art]
A conventional multipath detection circuit of this type of CDMA receiver measures a delay profile by multipath search, and performs a maximum value search of all data blocks of the delay profile data when detecting the first peak, When the second and subsequent peaks are detected, the maximum value search is performed again only for the data block in which the delay profile data is updated, and the maximum value information in the memory block is updated. The other data blocks (memory blocks) use the maximum value information retrieved at the first time, so that the number of peak detection cycles after the second place can be greatly reduced (see, for example, Patent Document 1). ).
[0003]
However, although this conventional technique divides the delay profile data representing the measured delay profile into a plurality of data blocks, the plurality of data blocks are respectively stored in the corresponding memory blocks, that is, the same size as the search section. Since a memory is required, there is a problem that the circuit scale is large and integration is difficult.
[0004]
[Patent Document 1]
JP-A-2002-164815 [0005]
[Problems to be solved by the invention]
The conventional preamble path position detection circuit described above requires a memory having the same size as the search section when storing the delay profile data representing the measured delay profile in the memory, so the circuit scale is large and integration is difficult. There is a drawback of being.
[0006]
An object of the present invention is to divide the entire search range into two sections, the first half and the second half, to eliminate such conventional drawbacks, and to select either the first half or the second half of the search range, and the rest. For the interval of, a preamble path position detection circuit that stores delay profile data based on path position information in the previous access slot and reduces the memory capacity and circuit scale by performing preamble detection. Is to provide.
[0007]
[Means for Solving the Problems]
The preamble path position detection circuit according to the present invention generates a delay profile by calculating a correlation power for each delay time with respect to an input received signal (digital data), and performs preamble path position detection periodically (for each slot). ) In which the delay profile is divided into the first half and the second half based on the delay time, and either the first half or the second half is alternately detected for each cycle, and the remaining one for each cycle. This section is characterized in that only the preamble path position detected in the previous period is detected for the first half or the second half different from the detection section.
[0008]
The preamble path position detection circuit of the present invention generates a delay profile by calculating correlation power for each delay time with respect to an input received signal (digital data), and periodically detects the preamble path position ( A preamble path position detection circuit for each slot), wherein the delay profile is divided into a first half and a second half based on the delay time, and a preamble is detected alternately for each first half or second half for each period. The remaining section is characterized in that only the preamble path position detected by using the transmission power step-up from the previous period is detected for the first half or the second half different from the detection section.
[0009]
The preamble path position detection circuit according to the present invention includes a despreading circuit that despreads an input received signal to measure a preamble delay profile and obtains a correlation value, and a delay amount of 1 to N (N is a positive integer). A scramble code generation circuit for generating a scramble code, a first address generation circuit for generating addresses 1 to N that are the same as the delay amount of the scramble code for each slot, and dividing the addresses 1 to N into two slots An address decoding circuit that outputs a write signal that is alternately selected every time, an N / 2 word memory that stores the delay profile based on the write signal, and the N / 2 word memory that is selected for each slot An m × L word memory storing the delay profile for a delay profile different from the address; and the N / 2 word. A second address generation circuit for outputting a read signal corresponding to the write signal to the memory and the m × L word memory, and the correlation stored in the N / 2 word memory and the m × L word memory A signature detection circuit that calculates a correlation between a value and m (m is a positive integer) signatures, outputs a maximum correlation value and a maximum correlation value for each signature, and path position information (maximum correlation) And an m word memory that stores updated path position information when the value is larger than the previous value.
[0010]
Further, the despreading circuit despreads an input received signal using the scramble code having the delay amounts 1 to N, measures the preamble delay profile, and calculates the correlation value obtained from the delay profile. And output to the N / 2 word memory 4 and the m × L word memory.
[0011]
Further, the N / 2 word memory alternates the preamble delay profile of the delay amounts 1 to N (all search intervals) output from the despreading circuit and either the first half or the second half of the correlation value for each slot. It is characterized by being stored in.
[0012]
In addition, the m × L word memory may include the path position information stored in the m word memory in the search section excluding the section stored in the N / 2 word memory in the entire search section. A preamble delay profile and a correlation value corresponding to an address different from the section stored in the N / 2 word memory are stored.
[0013]
The signature detection circuit performs correlation calculation between the correlation values stored in the N / 2 word memory and the m × L word memory and m signatures, and the maximum correlation value and the maximum correlation value are obtained for each signature. Are stored in an m word memory.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a block diagram showing an embodiment of a preamble path position detection circuit of the present invention.
[0016]
The embodiment shown in FIG. 1 includes a despreading circuit 2, a scramble code generating circuit 3, an N / 2 word memory 4, an address generating circuit 5, an address decoding circuit 6, a position information generating circuit 10, The delay profile generation circuit 1 includes an m × L word memory 11 and a counter 12, a signature detection circuit 7, an m word memory 8, and an address generation circuit 9.
[0017]
Next, the preamble path position detection circuit of this embodiment will be described in detail with reference to FIG.
[0018]
The despreading circuit 2 of the delay profile generation circuit 1 performs despreading on the input received signal using the scramble code generated by the scramble code generation circuit 3, measures the preamble delay profile, and obtains it from the delay profile. Together with the correlation value, the data is output to the N / 2 word memory 4 and the m × L word memory 11.
[0019]
The scramble code generation circuit 3 outputs a scramble code having a delay amount of 1 to N (N is a positive integer) to the despreading circuit 2 in synchronization with the write address signal generated by the address generation circuit 5.
[0020]
The address generation circuit 5 generates, for each slot, addresses 1 to N that are the same as the scramble code delay amount generated by the scramble code generation circuit 3, and generates N / 2 word memory 4 and m × L word memory as write address signals. 11 and the address decoding circuit 6.
[0021]
The address decode circuit 6 alternately selects when the write address signal output from the address generation circuit 5 is 1 to N / 2 and when it is N / 2 + 1 to N by the slot number, and write enable indicating the selected section. The signal 1 is output to the N / 2 word memory 4. In addition, when the position information (address value) stored in the m word memory 8 is input and the two addresses match within the range of the non-selected section, the write enable signal 2 is set to the m × L word memory 11. Output to the counter 12.
[0022]
The counter 12 outputs a write address obtained by counting up the write enable signal 2 output to the m × L word memory 11 to the m × L word memory 11.
[0023]
The N / 2 word memory 4 is either the first half or the second half according to the write enable signal 1 output from the address decode circuit 6 among the preamble delay profile and correlation value of all search sections N output from the despreading circuit 2. Is stored.
[0024]
The m × L word memory 11 includes position information (addresses) in accordance with the write enable signal 2 output from the address decode circuit 6 in the search period except for the period stored in the N / 2 word memory 4 among all search periods N. The preamble delay profile, the correlation value, and the write address signal (position information) generated by the address generation circuit 5 are stored only in addresses that match (value).
[0025]
When the signature detection circuit 7 reads the correlation value stored in the N / 2 word memory 4 and the m × L word memory 11, the address generation circuit 9 receives the N / 2 word memory 4 and the m × L word memory 11. In response to this, a read address and a read enable signal are output, and an address value (= position information) in the range of 1 to N is output to the m word memory 8.
[0026]
The signature detection circuit 7 calculates the correlation between the correlation values stored in the N / 2 word memory 4 and the m × L word memory 11 and m signatures, and the maximum correlation value and the maximum correlation value address for each signature. The value is stored in the m word memory 8.
[0027]
The m word memory 8 receives path position information (including the maximum correlation value and the maximum correlation value address value) from the signature detection circuit 7, and stores and outputs the updated path position information when it is larger than the previous value. To do.
[0028]
The position information generation circuit 10 generates an address for performing preamble detection of the next slot from the updated path position information and outputs it to the address decoding circuit 6.
[0029]
Next, a specific example of the address decoding circuit will be described. FIG. 2 is a block diagram showing a configuration example of the address decoding circuit shown in FIG.
[0030]
As shown in FIG. 2, the address decoding circuit 6 includes decoding circuits 61 to 64, a selection circuit 65, an OR circuit 66, and an AND circuit 67.
[0031]
The decode circuit 61 outputs an enable signal when the write address signal output from the address generation circuit 5 is 1 to N / 2 in the first half of all addresses N, and the decode circuit 62 outputs N / 2 + 1 in the second half of all addresses N. An enable signal is output when .about.N.
[0032]
The selection circuit 65 receives the two enable signals output from the decode circuits 61 and 62, selects them alternately according to the slot number, and writes the write enable signal 1 to the N / 2 word memory 4 for the N / 2 word memory 4. Output.
[0033]
The decode circuit 63 outputs an enable signal when the address output from the address generation circuit 5 is equal to the signature 1 position information, and the decode circuit 64 is similarly enabled when the address is equal to the signature m (m is a positive integer) position information. Is output.
[0034]
The OR circuit 66 receives the enable signals from the decoding circuits 63 and 64 and a decoding circuit (not shown) (decoding circuit corresponding to the signature 2 to the signature m-1) and inputs the enable signal obtained by the OR operation to the AND circuit. Output to 67.
[0035]
The AND circuit 67 disables the output of the OR circuit 66 when the output of the selection circuit 65 is enabled, and enables the output of the OR circuit 66 when the output of the selection circuit 65 is disabled. Signal 2 is output to the m × L word memory 11.
[0036]
The operation of the address decoding circuit having the above configuration will be described with reference to FIG. FIG. 3 is a time chart showing the operation of the address decoding circuit shown in FIG.
[0037]
The decode circuit 61 is “1” when the output from the address generation circuit 5 is the first half (N = 1 to 128) of all addresses (N = 1 to 256), and the second half (N = 129 to 256). ) Is “0”. The decode circuit 62 is “0” when the output from the address generation circuit 5 is N = 1 to 128, and is “1” when N = 129 to 256. Therefore, the selection circuit 65 outputs to the N / 2 word memory 4 the write enable signal 1 that selects the output of the decode circuit 61 when the slot number is an even number and the output of the decode circuit 62 when the slot number is an odd number. The N / 2 word memory 4 is selected and written when the write enable signal 1 is "1". As a result, the N / 2 word memory 4 stores the correlation results of N = 1 to 128 in the slots 2K, 2K + 2,... (FIG. 4), and in the slots 2K-1, 2K + 1,. The correlation result of N = 129 to 256 is stored (FIG. 5). That is, the first half / second half are alternately stored in the memory capacity of 1/2 of all addresses.
[0038]
The write enable signal 2 is the m × L word memory 11 only at the position corresponding to the position information (address value) of the signatures 1 to m output from the m word memory 8 when the write enable signal 1 is “0”. Is output.
[0039]
Next, a specific example of the address generation circuit will be described. FIG. 6 is a block diagram showing a configuration example of the address generation circuit shown in FIG.
[0040]
As shown in FIG. 6, the address generation circuit 9 includes an N counter 91, an m counter 92, and a selection circuit 93.
[0041]
The N counter 91 receives a slot number and receives a read enable signal 1 indicating the first half (count values 1 to N / 2) or the second half (count values N / 2 + 1 to N) of the count values 1 to N generated for each slot. Generate. The count value with the most significant bit masked is output to the N / 2 word memory 4 together with the read enable signal 1 as a read address (address output 1).
[0042]
The m counter 92 generates count values 1 to m (address output 2) and a read enable signal 2 in the first half or the second half of each slot according to the slot number, and outputs them to the m × L word memory 11.
[0043]
When read from the N / 2 word memory 4 by the read enable signal 1, the selection circuit 93 outputs the count values 1 to N of the N counter 91 output as the pass position output, and the m × L word memory 11 by the read enable signal 2. Is read out from the m × L word memory 11, the position information (path position input) is selected and output to the m word memory 8 as a path position output (position information for preamble detection).
[0044]
The operation of the address generation circuit having the above configuration will be described with reference to FIG. FIG. 7 is a time chart showing the operation of the address generation circuit shown in FIG.
[0045]
According to FIG. 7, in the first half (N = 1 to 128) of the slot 2K-1, the address generation circuit 9 uses the address output 2 (count value 1 to m) output from the m counter 92 and the read enable signal 2 to The path position input read from the m × L word memory 11 is selected and output as a path position output. A correlation value based on this path position output is read from the m × L word memory 11 by the signature detection circuit 7. Further, in the second half of slot 2K-1 (N = 129 to 256), the correlation value between the N / 2 word memory 4 and the pass positions 129 to 256 is obtained by the address output 1 and the read enable signal 1 output from the N counter 91. Read by the signature detection circuit 7.
[0046]
As a result of the above operation, the first half of slots 2K-1, 2K + 1,... And the second half of slots 2K, 2K + 2,... N correspond to the count values (address values) of the first half / second half of each slot. Then, the position information of the path position input read from the m × L word memory 11 is output, and the second half of the slots 2K-1, 2K + 1,... And the first half of the slots 2K, 2K + 2,. Then, position information corresponding to each successive count value (address value), that is, an address value corresponding to the latter half or the first half is output to the m word memory 8 as a pass position.
[0047]
The m word memory 8 stores the correlation value with each signature output from the signature detection circuit 7 at each address position and when the position information is larger than the stored correlation value.
[0048]
Next, the operation when the delay amount N = 256 (search range 1 to 256) and signature m = 8 (8 types) will be described.
[0049]
FIG. 8 shows an example of the preamble detection result stored in the m word memory in slot 2K-1.
[0050]
According to FIG. 8, in slot 2K−1, continuous sections from positions 129 to 256 of the N / 2 word memory 4 and addresses of detection positions 5, 10, 30, 20, 100, 50 of the m × L word memory 11 This is a result of preamble detection of a value (position information). Signature 1 has detection position = 5 and correlation value = 5, signature 2 has detection position = 10, correlation value = 120, signature 3 has detection position = 200, correlation value = 190, and the like. The position information of these preamble detection results is input to the address decoding circuit 6 via the position information generation circuit 10.
[0051]
FIG. 9 shows the relationship between the write enable signal 2 and the counter in the second half of the slot 2K. The write enable signal 2 becomes “1” at the position 200 corresponding to the signature 3 and the position 220 corresponding to the signature 7 in the latter half count value (position information) of the slot 2K, and becomes “0” at other positions. Further, the counter 12 outputs “1” at the position 200 and “2” at the position 220 to the m × L word memory 11 as an address signal.
[0052]
As a result, in the m × L word memory 11 in the slot 2K, as shown in FIG. 10, the address 1 stores 200 and the correlation value 1 at that position, and the address 2 stores 220 and 220 as position information. The correlation value 2 at that position is stored. Further, in the address generation circuit 9, in the second half of the slot 2K, as shown in FIG. 7, position information 200, 220 is output as a path position output.
[0053]
Next, a case where a preamble trial is performed by a power ramping step (transmission power level increase) will be described. FIG. 11 is a diagram illustrating a preamble detection result of signature 3.
[0054]
FIG. 11 shows the detection timing (corresponding to the position) on the horizontal axis and the correlation value on the vertical axis. When performing a preamble trial while increasing the transmission power by 1.5 times for each slot, if the correlation value 190 is equal to or less than the detection threshold value 250 in slot 2K-1, the transmission power is 1.5 times in slot 2K. A correlation value 285 is detected. Since the detection threshold 250 is exceeded in this slot 2K, the preamble trial is completed here, and no correlation value appears in the slot 2K + 1.
[0055]
FIG. 12 shows the state of the signature 3 among the states of the m word memory 8 as a result of the operations of the signature detection circuit and the address generation circuit in the slot 2K of FIG.
[0056]
According to the above-described embodiment of the present invention, the entire search range is divided into two sections, the first half and the second half, and is alternately selected. In other words, the entire search range is divided into two access slot periods. In the remaining section, an address based on a preamble detection result having the maximum value of the m value of the signature among the addresses corresponding to the first half or the second half that are excluded from the search target of each slot is performed. Therefore, the preamble detection operation in all sections can be performed with a memory capacity reduced to ½ + number of signatures with respect to the memory capacity of the same size as the conventional search section.
[0057]
【The invention's effect】
As described above, according to the preamble path position detection circuit of the present invention, the entire search range is divided into two sections, the first half and the second half, and either the first half or the second half of the search range is selected. For the remaining section, the delay profile data is stored based on the path position information in the previous access slot, and the preamble detection is performed, so that the memory capacity can be reduced to about ½ and the circuit scale can be reduced. There is an effect that can be done.
[0058]
Therefore, the circuit scale can be greatly reduced, so that the integration is possible, and the capacity of the apparatus can be increased and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a preamble path position detection circuit of the present invention.
FIG. 2 is a block diagram showing a configuration example of an address decoding circuit shown in FIG.
FIG. 3 is a time chart showing an operation of the address decoding circuit shown in FIG. 1;
FIG. 4 is a diagram illustrating a case where correlation results of N = 1 to 128 in slots 2K, 2K + 2,... Are stored in an N / 2 word memory.
FIG. 5 is a diagram showing a case where correlation results of N = 129 to 256 in slots 2K-1, 2K + 1,... Are stored in an N / 2 word memory.
6 is a block diagram illustrating a configuration example of an address generation circuit illustrated in FIG. 1. FIG.
7 is a time chart showing the operation of the address generation circuit shown in FIG. 1. FIG.
FIG. 8 is a diagram showing an example of a preamble detection result stored in an m word memory in slot 2K-1.
9 is a diagram showing the relationship between the write enable signal 2 and the counter in the second half of the slot 2K shown in FIG.
FIG. 10 shows the contents of an m × L word memory in slot 2K.
11 is a diagram illustrating a preamble detection result of signature 3. FIG.
12 is a diagram showing the state of signature 3 among the states of the m word memory as a result of the operations of the signature detection circuit and the address generation circuit in slot 2K of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Delay profile generation circuit 2 Despreading circuit 3 Scramble code generation circuit 4 N / 2 word memory 5 Address generation circuit 6 Address decoding circuit 7 Signature detection circuit 8 m word memory 9 Address generation circuit 10 Position information generation circuit 11 m × L word Memory 12 Counters 61, 62, 63, 64 Decoding circuits 65, 93 Selection circuit 66 OR circuit 67 AND circuit 91 N counter 92 m counter 93 selection circuit

Claims (7)

This is a preamble path position detection circuit that generates a delay profile by calculating correlation power for each delay time with respect to an input received signal (digital data) and periodically detects a preamble path position (for each slot). The delay profile is divided into the first half and the second half based on the delay time, and either the first half or the second half is alternately detected for each period, and the remaining period for each period is a first half or a different period from the detection period. A preamble path position detection circuit that detects only the preamble path position detected in the previous cycle for the latter half. This is a preamble path position detection circuit that generates a delay profile by calculating correlation power for each delay time with respect to an input received signal (digital data) and periodically detects a preamble path position (for each slot). The delay profile is divided into the first half and the second half based on the delay time, and either the first half or the second half is alternately detected for each period, and the remaining period for each period is a first half or a different period from the detection period. A preamble path position detection circuit that detects only a preamble path position detected using a transmission power step-up from the previous period for the latter half. A despreading circuit that despreads an input received signal to measure a preamble delay profile and obtain a correlation value; a scramble code generation circuit that generates a scramble code of delay amounts 1 to N (N is a positive integer); A first address generation circuit that generates addresses 1 to N that have the same delay amount as the scramble code for each slot, and a write signal that divides the addresses 1 to N into two and selects them alternately for each slot are output. The delay profile is applied to an address decoding circuit, an N / 2 word memory for storing the delay profile based on the write signal, and a delay profile different from an address at which the N / 2 word memory is selected for each slot. For the m × L word memory to be stored, the N / 2 word memory, and the m × L word memory A second address generation circuit for outputting a read signal corresponding to the embedded signal, the correlation value stored in the N / 2 word memory and the m × L word memory, and m (m is a positive integer) signatures The signature detection circuit that outputs the maximum correlation value and the maximum correlation value address value for each signature, and the path position information (including the maximum correlation value and the maximum correlation value address value) are input. A preamble path position detection circuit comprising: an m word memory for storing updated path position information when greater than the previous value; The despreading circuit despreads an input received signal using the scramble code having the delay amounts 1 to N, measures the preamble delay profile, and matches the correlation value obtained from the delay profile. 4. The preamble path position detection circuit according to claim 3, wherein the preamble path position detection circuit outputs the data to the N / 2 word memory 4 and the m × L word memory. The N / 2 word memory alternately stores the preamble delay profile of the delay amounts 1 to N (all search intervals) output from the despreading circuit and either the first half or the second half of the correlation value for each slot. The preamble path position detection circuit according to claim 3 or 4, wherein The m × L word memory includes the N / L of the path position information stored in the m word memory in a search interval except for the interval stored in the N / 2 word memory. 5. The preamble path position detection circuit according to claim 3, wherein a preamble delay profile and a correlation value corresponding to an address different from a section stored in a 2-word memory are stored. The signature detection circuit calculates a correlation between the correlation values stored in the N / 2 word memory and the m × L word memory and m signatures, and the maximum correlation value and the maximum correlation value address for each signature. 4. The preamble path position detection circuit according to claim 3, wherein the value is stored in an m word memory.

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