JP4045213B2 - Light switch - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an optical switch used for optical path setting and switching in an optical communication system or the like.
[0002]
[Prior art]
Conventionally, devices that set and switch optical paths by switching a plurality of optical waveguides provided in a substrate have been proposed.
[0003]
[Patent Document 1]
JP-A-9-133932
For example, as described in Patent Document 1, a plurality of optical waveguides intersect with each other, a pipe having a predetermined angle is formed at the intersection, and a part that transmits and reflects light is installed in the pipe. A method for setting and switching the optical path is proposed.
[0004]
In Patent Document 1, a liquid is used as a component that transmits and reflects light. Specifically, it has been proposed to use a refractive index matching liquid such as silicone oil. A heater is formed in the periphery of the pipe, and an electric current is supplied to the heater to generate heat, the interfacial tension of the liquid is changed, and the liquid is moved by moving the liquid.
[0005]
[Patent Document 2]
Japanese Patent Laid-Open No. 10-90735
Further, as described in Patent Document 2, a gap is formed at the intersection of at least two optical waveguides, and a fluid is filled in the gap. It has been proposed to switch light by heating a fluid with a heater, generating bubbles in the fluid, and moving the fluid.
[0006]
In particular, in Patent Document 1, a heater is disposed at an intersection of m optical waveguides and n optical waveguides, and m + n electrical wirings are formed by two-layer wirings to supply power to the heaters. It is described.
[0007]
In this patent document 1, a circuit configuration as shown in FIG. 8 is proposed, and a heater circuit 31 including a heating resistor 32 and a diode 33 located at the intersection of the lower layer electric wiring 35 and the upper layer electric wiring 36 is provided. It is composed of In this case, in order to drive a desired heater circuit 31, a desired lower layer electrical wiring 35 and upper layer electrical wiring 36 are selected, and a voltage is applied to the selected heater circuit 31.
[0008]
[Problems to be solved by the invention]
In the prior art, particularly when the heater circuit is driven by m + n electrical wirings, there is a problem in that power is supplied to other than the heater circuit specified by crosstalk, causing the optical switch to malfunction.
[0009]
For example, when the heater circuit 31 is driven with the circuit configuration shown in FIG. 8, a voltage is applied between the center line of the lower layer electrical wiring 35 and the center line of the upper layer electrical wiring 36. However, in addition to the heater circuit 31, there is a current path as indicated by a dotted line in FIG. For this reason, heater circuits other than the desired heater circuit 31 operate.
[0010]
Accordingly, an object of the present invention is to provide a highly reliable and highly integrated optical switch that can operate a desired switch.
[0011]
[Means for Solving the Problems]
  The present invention provides an optical switch that electrically selects a heater to drive a desired optical switch.HIt is to provide.
[0012]
FIG. 1 is a schematic circuit diagram of the present invention, in which a thin film transistor (TFT) 2 as an optical switch is arranged in a heater 1 and a gate electrode wiring 3 is newly added. A desired optical switch can be driven by selecting the gate electrode wiring 3 and the drain electrode wiring 4 and supplying power from the drain electrode wiring 4 to the heater 1. In particular, by forming the TFT2 directly on the optical waveguide substrate, a highly integrated and highly reliable optical switch can be manufactured in a compact manner.
[0013]
FIG. 2 is a schematic perspective view of the optical switch of the present invention, and FIG. 3 is a schematic cross-sectional view taken along the line AA ′. In order to form this optical switch device, first, the cladding 22 of the optical waveguide 5 is formed on the substrate 7. Form. As the substrate 7, quartz, Si substrate or the like is used. In forming the optical waveguide 5, first, the lower clad 8 is formed on the substrate 7.
[0014]
Examples of the clad forming method include sputtering, PECVD (Plasma Enhanced Chemical Vapor Deposition), and FHD (Flame Hydrosis Deposition). In the case of sputtering method, SiO₂Or SiO₂And GeO₂And TiO₂As a target, a rare gas such as Ar and O₂Are mixed to form a film by RF (Radio Frequency) high frequency discharge. After film formation, O₂Heat treatment is performed at a temperature of 1000 ° C. or higher in an atmosphere.
[0015]
Next, in the formation of the core 9, SiO 2₂And GeO₂And TiO₂Using a target with a mixed ratio of noble gas such as Ar and O₂Are mixed and RF high frequency discharged to form a film. After film formation, heat treatment is performed at a temperature of 1000 ° C. or higher. Further, after forming a thin film (for example, WSi) as a mask for the core 9 by sputtering or the like and forming a resist pattern by a photoresist process, the thin film to be the mask is etched. Using this thin film as a mask, RIE ( Core 9 is processed by Reactive Ion Etching.
[0016]
Further, heat treatment at 1000 ° C. or higher is applied, and then the upper clad 10 is formed in the same manner as the lower clad.
[0017]
When the optical waveguide 5 is formed using PECVD, SiH_Four, GeH_Four, Si (O (C₂H_Five))_Four, Ge (O (C₂H_Five))_Four, O₂Is introduced into the film forming chamber as a source gas, RF discharge is performed, the source gas is decomposed, and a film is formed. In the case of the PECVD method, since the refractive index can be controlled by controlling the flow rate of various gases, feedback is possible. For the clad and core deposited by PECVD method, heat treatment at 1000 ° C or higher is applied to stabilize the refractive index as in the sputtering method. The core is processed by the same patterning method as described above.
[0018]
When the optical waveguide 5 is formed by the FHD method, the lower cladding 8 is made of SiO.₂Powder or SiO₂Or GeO₂A mixture of powders is applied onto a substrate and then melt-formed with a flame. The core 9 is also made of SiO₂Powder or GeO₂Powder or TiO₂A powder mixture is applied, and a melt film is formed by a flame. The core is also processed by the same patterning method as described above. Further, the upper clad 10 is formed by the FHD method in the same manner as the lower clad 8. In the case of a quartz substrate, it is also possible to form the core directly on the substrate and then form the upper cladding 10.
[0019]
After the core 9 and the clads 8 and 10 are formed, the surface is smoothed by a CMP (Chemical Mechanical Polishing) method. Next, the heater film 1 is formed. As this method, for example, TaN film, TaSi₂A film or the like is formed by a sputtering method and patterned by a photolithography process. Thereafter, the heater film is heat treated and stabilized.
[0020]
A TFT is formed on this. TFT has reverse stagger, normal stagger, and coplanar structure. 2 and 3 show a schematic perspective view and a schematic cross-sectional view of an inverted stagger structure.
[0021]
In the case of the reverse stagger structure, first, the common electrode wiring 6, the heater film 1, and the contact electrode 11 of the source electrode 17 are formed on the heater film 1. These electrodes 6 and 11 have Al, Cr, Mo, Ta, Ti, W, Nb, Fe, Co, Ni, Cu, Ag, Au, and alloys thereof. In addition, different types of metal films may be stacked in order to improve contact characteristics and electrical conductivity. These materials are formed into a film by a sputtering method or a vapor deposition method, and patterned by a photolithography process. At this time, the common electrode wiring 6 and the contact electrode 11 are electrically connected to the heater film 1.
[0022]
An interlayer insulating layer 12 is formed thereon. Examples of the interlayer insulating layer 12 include a Si film containing nitrogen or oxygen. As a method for forming this film, there is a PECVD method or the like. Si film containing nitrogen is SiH_FourAnd NH_ThreeOr N₂Etc. as raw material gas, and H₂Or a rare gas such as Ar may be added. Also, the Si film containing oxygen is SiH._Four, Si (O (C₂H_Five))_Four, O₂Is introduced into the film forming chamber as a source gas, RF discharge is performed, the source gas is decomposed, and a film is formed.
[0023]
A gate electrode wiring 3 is formed thereon. The gate electrode wiring 3 has Al, Cr, Mo, Ta, Ti, W, Nb, Fe, Co, Ni, Cu, Ag, Au, and alloys thereof. In addition, different types of metal films may be stacked in order to improve contact characteristics and electrical conductivity. These materials are formed into a film by a sputtering method or a vapor deposition method, and patterned by a photolithography process.
[0024]
On this, a gate insulating layer 13, a semiconductor layer 14, and a contact layer 15 are formed. The gate insulating layer 13 includes a Si film containing nitrogen or oxygen. Alternatively, a high dielectric constant film 23 and a low dielectric constant film 24 may be stacked as the gate insulating layer 13.
[0025]
  In the present invention, the semiconductor layer 14 is notably Si._1-XGe_XMembrane (0 <X <1; X:Atomic composition ratio) Was used. Si_1-XGe_XSince the film is easily crystallized by low-temperature film formation and can increase the mobility, in particular, the power supplied to the heater 1 can be realized by the relatively small TFT element 2. For this reason, it is easy to highly integrate the optical waveguide 5, and a large-scale optical switch of 4 × 4 or more can be manufactured in a compact manner. Further, when X is increased, the off-state current of the TFT element 2 is reduced. Therefore, it is preferable that 0 <X ≦ 0.2, and more preferably 0.01 ≦ X ≦ 0.1.
[0026]
  For the contact layer 15, a Si film doped with a Group VI element such as P or a Group III element such as B or Si_1-XGe_XApply the membrane. As methods for forming these films 13, 14, and 15, there are a PECVD method, a thermal CVD method, a reactive thermal CVD method, and the like. Si film 13 containing nitrogen is SiH_FourAnd NH_ThreeOr N₂Etc. as raw material gas, and H₂Or a rare gas such as Ar may be added. These gases are introduced into the film formation chamber and decomposed by the PECVD method to form a film. Si_1-XGe_XFilm 14 is SiH_Four, Si₂H₆Si etc._nH _{2 n + 2}(n: integer), SiF4, GeH_FourGe_nH_{2n + 2}(n: integer), GeF_FourOr F₂, H₂A rare gas such as Ar is mixed and formed by PECVD, thermal CVD, reactive thermal CVD, etc. Further, the Si film 15 containing P is made of PH._ThreeAnd Si_nH_{2n + 2}And formed by PECVD, thermal CVD, reactive thermal CVD, etc.
[0027]
Next, the contact layer 15 and the semiconductor layer 14 are processed into an island shape by photolithography, and further, through holes 16 are formed in the gate insulating layer 13 and the interlayer insulating film 12 so as to be connected to a thin film serving as the heater 1 by photolithography. .
[0028]
Next, metal films 4 and 17 are formed. This metal has Al, Cr, Mo, Ta, Ti, W, Nb, Fe, Co, Ni, Cu, Ag, Au, and alloys thereof. In addition, different types of metal films may be stacked in order to improve contact characteristics and electrical conductivity. The metal layer is processed by photolithography to form the source electrode 17 and the drain electrode wiring 4. At this time, the source electrode 17 and the heater 1 are connected through the through hole 16.
[0029]
Next, the contact layer 15 between the source electrode 17 and the drain electrode wiring 4 is etched. A protective layer 18 is formed thereon. Examples of the protective layer include Si containing nitrogen and Si containing oxygen. Next, through holes are formed in the respective terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4 by photolithography. The through hole processing here can be omitted. When omitted, this through hole processing is performed together with the through hole processing of the planarizing layer 19 described later. Next, a planarization layer 19 is formed. Examples of the planarizing layer 19 include Si containing nitrogen and Si containing oxygen. After the planarization layer 19 is formed, the surface is planarized by CMP. The planarizing layer 19 and the protective layer 18 may be the same.
[0030]
After planarization, a Si film for anodic bonding of the lid 26 is formed. Thereafter, through holes are formed in the respective terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4 in the Si film. Further, an Au pattern resist for wire bonding is processed by photolithography to deposit an Au film. The Au film is processed by a lift-off method when removing the resist.
[0031]
Thereafter, in order to process the groove 20 into which the liquid is injected, a WSi film is formed, the WSi film is processed by photolithography, and the groove is etched by RIE using the WSi film as a mask. After the groove 20 is processed, the WSi film is removed. The groove 20 is similar to the pipe line in Patent Document 1 or the gap in Patent Document 2.
[0032]
Thereafter, an Au film for wire bonding is formed and processed to form the groove 20, and then a refractive index matching liquid or a liquid metal is injected as the liquid 21 into the groove. Thereafter, the lid 26 is put on, the substrate is sandwiched between the electrodes, heated to 450 ° C., and 900 V is applied between the electrodes to perform anodic bonding, thereby completing the optical switch.
[0033]
FIG. 4 is a schematic perspective view of an optical switch when a positive stagger structure is adopted as the TFT 2, and FIG. As described above, the heater 1 is manufactured. Next, the common electrode wiring 6 and the contact electrode 11 are formed. This material is the same as that described in the case of the above-described inverted staggered structure TFT. An interlayer insulating layer 12 is formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT.
[0034]
Next, the through hole 16 is formed by photolithography. On this, the drain electrode wiring 4 and the source electrode 17 are formed. This material is the same as that described in the case of the above-described inverted staggered structure TFT. At this time, the source electrode 17 is electrically connected to the heater 1. A contact layer 15 is formed thereon. As the contact layer 15, a Si film doped with a group III or group VI or Si_1-XGe_XSuch as a membrane.
[0035]
The contact layer 15 is processed by photolithography. Further, the contact layer 15 may be formed by being laminated on the drain electrode wiring 4 and the source electrode 17, and may be simultaneously processed by a photolithography method.
[0036]
Next, the semiconductor layer 14 is formed. As described above, the semiconductor layer is Si._1-XGe_XApply membrane (0 <X <1). The semiconductor layer is processed into an island shape by photolithography. Next, the gate insulating layer 13 is formed. This material is the same as that described in the case of the above-described inverted staggered structure TFT.
[0037]
Next, the gate electrode wiring 3 is formed. This material is the same as that described in the case of the above-described inverted staggered structure TFT. A protective layer 18 is formed thereon. Examples of the protective layer 18 include Si containing nitrogen and Si containing oxygen. This protective layer 18 is the same as the planarization layer 19 described in the case of the inverted staggered TFT. Next, it is flattened by CMP. A Si film for anodic bonding is formed on this. Next, through holes are formed in the respective terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4 by photolithography.
[0038]
After that, as in the case of using the above-mentioned inverted stagger type TFT, an Au film for wire bonding is formed and processed, and after forming the groove 20, a refractive index matching liquid or liquid metal is injected into the groove as the liquid 21. Then, the lid 26 is covered and anodically bonded to complete the optical switch.
[0039]
A perspective schematic view of an optical switch when a coplanar structure is adopted as the TFT 2 is shown in FIG. 6, and a CC ′ cross-sectional schematic view thereof is shown in FIG. The heater 1 is manufactured as in the case of the above-mentioned reverse stagger. An interlayer insulating layer 12 is formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT.
[0040]
Next, Si as the semiconductor layer 14_1-XGe_XA film (0 <X <1) is formed. The semiconductor layer 14 is processed into an island shape by a photolithography process. A gate insulating layer 13 is formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT. Further, a gate electrode was formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT.
[0041]
Further, in order to form the impurity active layer 25, a group III element such as B or a group V element ion such as P is implanted. Next, an interlayer insulating layer 12 is formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT. Next, through holes 16 are formed in the interlayer insulating layer 12 and the gate insulating layer 13 by photolithography. Next, the drain electrode wiring 4 and the source electrode 17 are formed. This material is the same as that described in the case of the above-described inverted staggered structure TFT.
[0042]
A protective layer 18 is formed thereon. This material is the same as that described in the case of the above-described inverted staggered structure TFT. Also in this case, the protective layer 18 and the planarizing layer 19 are the same. Next, it is flattened by CMP. A Si film for anodic bonding is formed on this. Next, through holes are formed in the respective terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4 by photolithography.
[0043]
After that, similarly to the case of using the above-mentioned inverted stagger type TFT, an Au film for wire bonding is formed and processed, and after forming the groove 20, a refractive index matching liquid or a liquid metal is injected into the groove as the liquid 21. Then, cover 26 and anodic bond to complete the optical switch.
[0044]
The matrix optical switch manufactured by the above process can select the predetermined heater 1 by the gate wiring electrode 3 and the drain wiring electrode 4, and supplies the current required for the movement of the liquid injected into the groove 20 to the designated heater. Is possible. Also, since TFTs are fabricated on an optical waveguide substrate, highly integrated and reliable optical switches can be fabricated.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
An embodiment of the present invention will be described below with reference to FIGS.
First, the lower clad layer 8 of the clad 22 is formed on the Si substrate 7. As a cladding formation method, PECVD method is used, and as source gas, SiH_FourAnd O₂A film was formed using this mixture. After film formation, O at 1100 ° C₂The refractive index was stabilized by annealing in an atmosphere.
[0046]
Subsequently, the core 9 was formed. Core 9 is also made of SiH by PECVD_Four, GeH_Four, O₂As a raw material, a film was formed. After film formation, O at 1100 ° C₂Annealed in atmosphere. Next, WSi was formed by sputtering. The WSi film was processed by photolithography, and the core 9 was processed by RIE using this as a mask.
[0047]
After processing the core 9, the WSi film was removed by etching. Then O₂Annealed at 1200 ° C in an atmosphere to stabilize the refractive index. Thereafter, the upper clad 10 was formed by PECVD. Raw material is SiH_FourAnd O₂It was formed by PECVD method. After formation, O₂The refractive index was stabilized by annealing at 1100 ° C. Then, the surface was flattened by CMP.
[0048]
Next, a TaN film was formed as the heater 1 by sputtering. Subsequently, it was patterned by a photolithography process. Furthermore, it heat-processed at 600 degreeC. Here, as the heat treatment, the TFT is molded at less than 600 ° C., but the optical waveguide is molded at 600 ° C. or more.
[0049]
A TFT was formed on the heater 1. First, the contact electrode 11 for connecting the common electrode wiring 6 and the heater 1 to the source electrode 17 was formed. In this process, a CrMo alloy was formed by a sputtering method and patterned into the common electrode wiring 6 and the contact electrode 11 film by a photolithography process. At this time, the common electrode wiring 6 and the contact electrode 11 are electrically connected to the heater 1.
[0050]
An interlayer insulating layer 12 is formed thereon. SiN film as an interlayer insulation layer by SiCVD by PECVD method_Four, NH_Three, N₂Was formed as a source gas. A gate electrode wiring 3 was formed thereon. As the gate electrode wiring, a CrMo film was formed by sputtering. The gate electrode wiring 3 was formed by patterning in a photolithography process. On this, gate insulating layers 23 and 24 were formed.
[0051]
For the gate insulating layers 23 and 24, a SiN film as a high dielectric constant layer 23 is formed by PECVD with SiH._Four, NH_Three, N₂Was formed as a source gas. Further, as the low dielectric constant layer 24, SiO₂A film of Si (O (C₂H_Five))_Four, O₂Was formed as a source gas. By laminating in this way, the electric capacity per area of the gate insulating layer is increased, and SiO 2₂Si_1-XGe_XBy using it at the film interface, Si_1-XGe_XImproved crystallinity.
[0052]
Semiconductor layer 14 is Si_1-XGe_XA membrane (X = 0.02) was used. Si_1-XGe_XThe film is formed by reactive thermal CVD.₂H₆And GeF_FourAnd He. Next, an n + Si film was formed as the contact layer 15 by PECVD. n + Si film is SiH_Four, PH_Three, H₂It was formed by PECVD method using as a raw material.
[0053]
Subsequently, the contact layer 15 and the semiconductor layer 14 were processed into an island shape by photolithography, and a through hole 16 for connecting the heater 1 was formed in the gate insulating layer 13 by photolithography. Next, a CrMo film was formed as a metal layer. The CrMo film was processed by photolithography to form the source electrode 17 and the drain electrode wiring 4. At this time, the source electrode 17 and the heater 1 were connected through the through hole 16.
[0054]
Next, the n + Si film between the source electrode 17 and the drain electrode wiring 4 was etched. Overetched Si_1-XGe_XThe film was also slightly etched. On top of this, a SiN film is formed as a protective layer 18 by SiCVD using PECVD._Four, NH_ThreeAnd a mixed gas of N2. Further, as the planarizing layer 19, SiO₂A film was formed by PECVD and planarized by CMP. After planarization, a Si film for anodic bonding of the lid 26 was formed by a sputtering method.
[0055]
Thereafter, through holes were formed in the Si film, the planarization layer 19 and the protective layer 18 of the terminal portions of the gate electrode wiring 3, the common electrode wiring 6 and the drain electrode wiring 4 by photolithography. Further, an Au pattern resist for wire bonding was processed by photolithography to deposit an Au film. The Au film was processed by the lift-off method when removing the resist.
[0056]
Next, in order to process the groove 20 for injecting the liquid, a WSi film was formed by sputtering, the WSi film was processed by photolithography, and the groove 20 was etched by RIE using the WSi film as a mask. After the groove 20 was processed, the WSi film was removed by etching.
[0057]
Thereafter, silicone oil was injected as a refractive index matching liquid for the liquid 21 into the formed groove, and the lid was capped and anodic bonded. With the matrix optical switch completed through the above steps, a predetermined heater or resistance heater can be selected by the gate wiring electrode 13 and the drain wiring electrode 14, and the current necessary for the movement of the liquid 21 can be supplied to the heater 1. became.
[0058]
[Example 2]
An embodiment of the present invention will be described below with reference to FIGS.
First, the lower cladding layer 8 was formed on the Si substrate 7. As a cladding formation method, SiO₂The powder was applied and formed into a film by flame deposition (FHD) method. Subsequently, the core 9 was formed. Core 9 is also SiO by FHD method.₂And GeO₂A film was formed using a powder mixture as a raw material. Next, WSi was formed by sputtering. The WSi film was processed by photolithography, and the core 9 was processed by RIE using this as a mask.
[0059]
After processing the core 9, the WSi film was removed by etching. After that, the upper clad 10 is made of SiO by FHD method.₂Formed from powder. Then, the surface was flattened by CMP. Next, a TaN film was formed as the heater 1 by sputtering. Subsequently, it was patterned by a photolithography process. Furthermore, it heat-processed at 600 degreeC. Here, as the heat treatment, the TFT is molded at less than 600 ° C., but the optical waveguide is molded at 600 ° C. or more. A TFT was formed on the heater 1. First, the common electrode wiring 6 and the contact electrode 11 between the source electrode 17 and the heater 1 were formed in the same manner as in Example 1.
[0060]
An interlayer insulating film 12 was formed thereon. SiO as interlayer insulating layer 12₂Si (O (C₂H_Five))_FourAnd O₂It was formed using the mixed gas. Further, a through hole 16 was formed on the contact electrode 11 by a photolithography process. Next, a metal film for the source electrode 17 and the drain electrode wiring 4 was formed thereon. This was done by forming a Cr film by sputtering. Further, an n + Si film was formed as the contact layer 15 in the same manner as in Example 1. Subsequently, the source electrode 17 and the drain electrode wiring 4 were processed by a photolithography process.
[0061]
The semiconductor layer 14 is made of Si._1-XGe_XA membrane (X = 0.1) was used. Si_1-XGe_XThe film is made of SiH by PECVD method._FourAnd GeH_FourAnd H2. SiH_FourFlow rate: GeH_FourFlow rate: H₂The flow rate was 9: 1: 100. Further, the semiconductor layer 14 was processed by photolithography. On this, a gate insulating layer 13 was formed.
[0062]
For the gate insulating layer 13, a SiN film is made of SiH by PECVD._Four, NH_Three, N₂A film was formed using a mixed gas of Further, the gate electrode wiring 3 was formed thereon. As the gate electrode 13, an Al film and a CrMo film were formed by sputtering. Thereafter, patterning was performed by a photolithography process to form the gate electrode wiring 3. Further, a SiN film was formed thereon as a protective layer 18 by PECVD. Furthermore, the protective layer was planarized by CMP. After planarization, a Si film for anodic bonding of the lid 26 was formed by a sputtering method.
[0063]
Thereafter, in order to form the terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4, through holes 16 were formed in the Si film by photolithography. Further, an Au pattern resist for wire bonding was processed by photolithography to deposit an Au film. The Au film was processed by the lift-off method when removing the resist.
[0064]
Thereafter, in order to process the groove 20 for injecting the liquid, a WSi film was formed by sputtering, the WSi film was processed by photolithography, and the groove 20 was etched by RIE using the WSi film as a mask. After the groove 20 was processed, the WSi film was removed by etching. Thereafter, an electrolyte solution was injected as a refractive index matching solution 21 into the formed groove 20, and the lid 20 was capped and anodically bonded.
[0065]
With the matrix optical switch completed through the above steps, a predetermined heater 1 can be selected by the gate electrode wiring 3 and the drain electrode wiring 4, and a current necessary for moving the liquid 21 can be supplied to the heater 1.
[0066]
[Example 3]
An embodiment of the present invention will be described below with reference to FIGS.
First, the clad 22 and the core 9 of the optical waveguide 5 were formed on the Si substrate 7 in the same manner as in Example 1. Furthermore, the heater 1 was formed by the same method as in Example 1. A TFT was formed on this. First, the common electrode wiring 6 and the contact electrode 11 were formed in the same manner as in Example 1. An interlayer insulating layer 12 was formed thereon.
[0067]
SiO as interlayer insulating layer 12₂Si (O (C₂H_Five))_FourAnd O₂It was formed using the mixed gas. Furthermore, on this, as a semiconductor layer 14, Si_1-XGe_XA film (X = 0.01) was formed. Si_1-XGe_XThe film is formed by reactive thermal CVD.₂H₆And GeF_FourAnd Ar. Subsequently, the semiconductor layer 14 was processed by photolithography. On this, a gate insulating layer 13 was formed.
[0068]
The gate insulating layer 13 includes SiO₂A film of Si (O (C₂H_Five))_FourAnd O₂A film was formed using a mixed gas of Further, the gate electrode wiring 3 was formed thereon. As the gate electrode 3, an Nb film was formed by sputtering. Thereafter, patterning was performed by a photolithography process to form the gate electrode wiring 3. Further, in order to form the impurity active layer 25, P ions were implanted. Next, a SiN film is formed thereon as an interlayer insulating layer 12 by PECVD._Four, NH_Three, N₂Was used as a raw material. Next, the through hole 16 was formed by photolithography. Subsequently, a CrMo film was formed as a metal film by a sputtering method. The CrMo film was processed by photolithography to form the source electrode 17 and the drain electrode wiring 4.
[0069]
Further, as the protective layer 18, SiO₂A film of Si (O (C₂H_Five))_FourAnd O₂Was used as a raw material. Furthermore, the protective layer was planarized by CMP. After planarization, a Si film for anodic bonding of the lid 26 was formed by a sputtering method. Thereafter, through holes through the Si film, the protective layer 18, the interlayer insulating layer 12, and the gate insulating layer 13 were formed in the terminal portions of the gate electrode wiring 3, the common electrode wiring 6, and the drain electrode wiring 4 by photolithography. . Further, an Au pattern resist for wire bonding was processed by photolithography to deposit an Au film. The Au film was processed by the lift-off method when removing the resist.
[0070]
Thereafter, in order to process the groove 20 for injecting the liquid, a WSi film was formed by sputtering, the WSi film was processed by photolithography, and the groove 20 was etched by RIE using the WSi film as a mask. After the groove 20 was processed, the WSi film was removed by etching. Thereafter, mercury and an electrolyte solution, which is a refractive matching solution, were injected into the formed groove 20 as the liquid 21, and the lid 20 was capped and anodically bonded.
[0071]
The matrix optical switch completed through the above steps makes it possible to select a predetermined heater or resistance heater by the gate electrode wiring 3 and the drain electrode wiring 4 and supply a current necessary for the movement of the liquid 21 to the heater. It was.
【The invention's effect】
In the matrix optical switch of the present invention, a predetermined heater can be selected by the gate wiring electrode and the drain wiring electrode, and a current necessary for liquid movement can be supplied to the designated heater. In addition, TFT is formed on the waveguide substrate, and high mobility Si_1-XGe_XSince the film is applied to the semiconductor layer, the TFT size can be reduced, and highly integrated and reliable optical switches can be manufactured.
[Brief description of the drawings]
FIG. 1 is a schematic circuit diagram of an optical switch according to the present invention.
FIG. 2 is a schematic perspective view of the optical switch of the present invention.
FIG. 3 is a schematic cross-sectional view taken along the line A-A ′ of FIG.
FIG. 4 is a schematic perspective view of the optical switch of the present invention.
FIG. 5 is a schematic cross-sectional view taken along the line B-B ′ of FIG.
FIG. 6 is a schematic perspective view of the optical switch of the present invention.
7 is a schematic cross-sectional view taken along C-C ′ of FIG. 6;
FIG. 8 is a schematic circuit diagram of a conventional optical switch.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Heater or heating resistor, 2 ... Thin-film transistor (TFT), 3 ... Gate electrode wiring, 4 ... Drain electrode wiring, 5 ... Optical waveguide, 6 ... Common electrode wiring, DESCRIPTION OF SYMBOLS 7 ... Board | substrate, 8 ... Lower clad, 9 ... Core, 10 ... Upper clad, 11 ... Contact electrode, 12 ... Interlayer insulation layer, 13 ... Gate insulation layer, 14 ... Semiconductor layer, 15 ... Contact layer, 16 ... Through hole, 17 ... Source electrode, 18 ... Protective layer, 19 ... Flattening layer, 20 ... Groove, 21 ..Liquid, 22 ... cladding, 23 ... high dielectric constant layer, 24 ... low dielectric constant layer, 25 ... impurity active layer, 26 ... lid,
31 ... heater circuit, 32 ... heating resistor, 33 ... diode, 35 ... lower electrical wiring, 36 ... upper electrical wiring

Claims (9)

A plurality of optical waveguides formed on a substrate, and the intersection groove formed in said optical waveguide, and the liquid sealed in said groove, and a heater disposed in the vicinity of the groove, on the heater A source electrode, a drain electrode, a gate electrode , and a semiconductor layer having Si _1-X Ge _X (0 <X <1) (X: atomic composition ratio) are formed and are electrically connected to the heater. and a thin film transistor, by moving the liquid by heating the heater by applying electrical signals to the said drain electrode of the thin film transistor gate, light, characterized by switching the optical signal in the waveguide switch. In claim 1 ,
An optical switch characterized in that the liquid has a refractive index matching liquid. In claim 1 ,
An optical switch, wherein the liquid has a liquid metal. In claim 1 ,
An optical switch, wherein the optical waveguide is a silica-based. In claim 1 ,
The optical switch, wherein the thin film transistor has an inverted stagger structure. In claim 1 ,
The optical switch, wherein the thin film transistor has a positive stagger structure. In claim 1 ,
The optical switch, wherein the thin film transistor has a coplanar structure. In claim 1 ,
An optical switch, wherein the gate insulating film of the thin film transistor has a stacked of high and low dielectric constant. In claim 1 ,
An optical switch, wherein a plurality of said heaters cladding surface of the optical waveguide is formed in an array, are the thin film transistor electrically connected.

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