JP4041297B2 - Power converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power conversion device having a power conversion semiconductor switching element as a main circuit element for power conversion.
[0002]
[Prior art]
BACKGROUND ART Power conversion semiconductor switching elements are widely used as basic components of power conversion devices such as motor drive inverters and power transmission converters. Many of these power converters have a great impact on society due to failures. Such a power conversion device is designed to be able to continue operation even if a semiconductor switching element for power conversion breaks down by performing a redundant design. And it operates so that the semiconductor switching element for power conversion which failed at the time of periodic inspection may be replaced.
[0003]
In recent years, semiconductor switching elements for power conversion are replaced with gate turn-off thyristors (GTOs) that excel in high voltage and large current, and voltages represented by insulated gate bipolar transistors (IGBT) that excel in high voltage, large current and high-speed switching. Drive-type power conversion semiconductor switching elements (hereinafter simply referred to as semiconductor switching elements) tend to be used.
[0004]
The number of semiconductor switching elements used in the power converter varies depending on the main circuit and the capacity of the device. In addition, since a socially important device has a limited allowable stop time of the device, it is necessary to provide a circuit for specifying the location of the failed semiconductor switching element.
[0005]
FIG. 8 shows a typical three-phase bridge circuit. In the figure, a semiconductor switching element 1 and a freewheeling diode 2 are connected in reverse parallel to form an arm 3 on one side, and a three-phase bridge circuit 4 is configured by connecting three series connection circuits of the arms 3 in parallel. Yes. The DC buses P and N are connected to both ends of the series connection circuit of each arm, and the three-phase AC buses R, S, and T are connected to the interconnection points of the arms connected in series.
[0006]
FIG. 9 is a circuit diagram partially shown in blocks for explaining gate control and element failure detection of the semiconductor switching element 1 shown in FIG. Here, the semiconductor switching element 1 performs a switching operation by applying an on / off gate voltage between the gate G and the emitter E via the gate resistor 8. At this time, the main circuit voltage VCE is applied between the collector C and the emitter E of the semiconductor switching element 1 during the OFF period, and the ON voltage of the semiconductor switching element 1 (ideally substantially zero during the ON period. Voltage). The first control circuit 5 provided corresponding to each of the semiconductor switching elements 1 includes a gate control signal GP (GP-U for the semiconductor switching element forming the positive arm, and the semiconductor switching element forming the negative arm). GP-X,... (Which are collectively abbreviated as GP), and a function of applying an on / off gate voltage to the semiconductor switching element 1, and a collector C and an emitter of the semiconductor switching element 1. A function of detecting the presence or absence of a main circuit voltage applied between the second control circuit 6 and the voltage control signal CF.
[0007]
FIG. 10 is a block diagram showing a schematic configuration of an abnormality detection circuit for a semiconductor switching element provided corresponding to the U-phase arm. In the second control circuit 6, a comparison means 51 is provided in the first control circuit 5. The comparison means 61 is provided. Here, the comparing means 51 compares the reference value of the U-phase CE voltage VCE-U with the actually generated voltage, and if the actually generated voltage exceeds the reference value, it is determined that there is a voltage. The voltage monitoring signal CF-U between CE is output. Then, the comparing means 61 compares the gate control signal GP-U with the CE voltage monitoring signal CF-U described above, and when the voltage cannot be observed at the timing when the voltage should be originally observed. , The abnormality detection signal CFD is output.
FIGS. 11A and 11B are time charts for explaining each operation when the semiconductor switching element is normal and abnormal. In the normal state, as shown in (a), the gate circuit operates and the normal gate voltage VGE-U is applied between the gate G and the emitter E with respect to the gate control signal GP-U. If the semiconductor switching element 1 is turned on, the CE voltage VCE-U disappears. If the semiconductor switching element 1 is turned off, the CE voltage VCE-U is observed. The comparison means 51 compares this voltage with a reference value, and outputs a voltage monitoring signal CF-U between CE in phase with the voltage between CE as presence / absence of the observation voltage. In this case, the gate control signal GP-U is zero, that is, the voltage is observed between CE while the power semiconductor element 1 is in the OFF state, and the failure detection signal CFD is not output from the comparison means 61.
[0008]
On the contrary, at the time of abnormality, as shown in (b), the gate control signal GP-U is zero, that is, the voltage monitoring signal CF-U between CE even though the power semiconductor element 1 is in the OFF state. Is not observed, the comparison means 61 outputs a failure detection signal CFD. The comparison means 61 shown in FIG. 10 makes it possible to specify the semiconductor switching element in which the failure detection signal CFD is incorporated, so that the place where element replacement is necessary can be known. As a result, it is possible to quickly replace the element at the time of periodic inspection or emergency maintenance response.
[0009]
[Problems to be solved by the invention]
In recent years, there has been a demand for further improvement in the operational reliability of equipment. If it is possible to predict which element has shown an abnormal sign, and which element will have an element failure, rather than after the occurrence of an element failure, make an equipment shutdown plan in consideration of the operation status of the equipment. It is also possible. In general, since the semiconductor switching element has a long lead time from when it is arranged to when it is delivered, it can also be arranged in advance.
[0010]
The present invention has been made in view of the above circumstances, and a first object of the invention is to provide a power conversion device that can detect which semiconductor switching element shows an abnormal sign.
[0011]
A second object of the present invention is to provide a power conversion device capable of predicting when and when which semiconductor switching element will cause an element failure.
[0013]
[Means for Solving the Problems]
As a result of conducting various device immunity evaluations, it was experimentally found that the gate leakage current increases as a preliminary sign of device failure, although further investigation is necessary for the cause. Therefore, in the present invention, a change in gate leakage current is monitored as a state quantity for observing a sign of failure of the semiconductor switching element. In this case, the circuit configuration can be simplified using the principle that the gate voltage decreases as the leakage current increases.
[0014]
Therefore, the invention according to claim 1
In a power conversion device having a power conversion semiconductor switching element such as a gate turn-off thyristor or an insulated gate bipolar transistor as a main circuit element for power conversion,
A leakage current detecting means for detecting a gate leakage current of the semiconductor switching element for power conversion;
An element abnormality detection means for outputting an element abnormality detection signal indicating a sign of abnormality when the magnitude of the leakage current at the start of use of the device changes as a reference value or more,
It is provided with.
[0015]
According to a second aspect of the present invention, in the power conversion device according to the first aspect, a voltage detection circuit for detecting a voltage between the gate and the emitter of the semiconductor switching element for power conversion is provided as a leakage current detection means, and this voltage detection A gate leakage current is indirectly detected by a circuit.
[0016]
According to a third aspect of the present invention, in the power conversion device according to the second aspect, the element abnormality detecting means includes initial value storage means for storing voltage data between the gate and the emitter at the start of use of the apparatus, and a current gate. A voltage difference calculation means for calculating the difference between the detected value of the voltage between the emitters and the voltage data stored in the initial value storage means, and a reference value in which the voltage difference calculated by the voltage difference calculation means is set in advance. Comparing means for outputting an element abnormality detection signal when exceeding is provided.
[0017]
According to a fourth aspect of the present invention, there is provided a power conversion device according to the third aspect, wherein a timer for measuring a usage time from the start of use of the device and a timer at the time when the element abnormality detection means outputs an element abnormality detection signal. And a calculation means for predicting a life estimation time until the power conversion semiconductor switching element is failed based on a measurement time and a preset reference value.
[0018]
The invention according to claim 5 is the power conversion device according to claim 4, comprising a plurality of sets of initial value storage means, voltage difference calculation means, comparison means, and timer, and the front machine comparison means is calculated by the voltage difference calculation unit. The voltage difference is compared using different reference values, and the calculation means sequentially predicts the estimated life time each time an element abnormality detection signal is received from the comparison means.
[0019]
According to a sixth aspect of the present invention, in the power conversion device according to any one of the first to fifth aspects, a high voltage application for increasing the voltage between the gate and the emitter of the semiconductor switching element for power conversion is higher than that during normal operation. Means for detecting leakage current using the high voltage applying means during a period in which the operation of the apparatus is not hindered.
[0020]
The invention according to claim 7 is the power conversion device according to any one of claims 1 to 6, wherein the collector electrode is formed on one main surface of the semiconductor substrate, and a plurality of emitter electrodes are formed on the other main surface. A power conversion semiconductor switching element having a gate electrode formed and the emitter electrode disposed adjacent to and adjacent to the gate electrode as a dedicated electrode for voltage detection is used as a main circuit element for power conversion. To do.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on preferred embodiments shown in the drawings. FIG. 1 is a circuit diagram partially showing in block form the configuration of a first embodiment of a power converter according to the present invention. In FIG. 1, the same elements as those in FIG. A description thereof will be omitted. In this embodiment, as a leakage current detection means between the gate G and the emitter E of the semiconductor switching element 1, the interconnection point of the gate resistor 8 represented by Rg and the gate G of the semiconductor switching element 1, and the semiconductor switching element A VGE detection circuit 9 for detecting a gate voltage VGE applied to one emitter E is provided, and the detection signal is transmitted to the first control circuit 5A, and the monitor signal VGE is transmitted by the first control circuit 5A. 9 is different from FIG. 9 in that the device abnormality detection signal CFDL is transmitted to the second control circuit 6 when it is monitored and it is determined that the gate leakage current is increasing. It is configured identically. Note that the gate control signals GP-U and GP-X shown in FIG. 9 are omitted for simplification of the drawing.
[0023]
FIG. 2 shows a specific configuration example of the first control circuit 6 and particularly shows the U-phase positive side arm. The portion for receiving the monitor signal VGE-U from the VGE detection circuit 9 and judging the abnormality is shown. It is shown. Here, the first control circuit 5 </ b> A provided corresponding to the U phase includes an initial value storage means 52 and a comparison means 53. Among these, the initial value storage means 52 is an initial gate voltage value of the semiconductor element 1 detected by the VGE detection circuit 9, for example, manually or automatically registered one hour after the start of use, and the comparison means 53 is an initial value. Built-in voltage difference calculation means for calculating the difference between the initial gate voltage value registered in the value storage means 52 and the current voltage value, and the element when the calculated voltage difference becomes larger than a preset reference value 1 An abnormality detection signal CFDL is output.
[0024]
The operation of the first embodiment configured as described above will be described below with reference to the time chart of FIG. For example, the initial gate voltage value of the semiconductor element 1 detected by the VGE detection circuit 9 manually or automatically after one hour from the start of the operation of the three-phase bridge circuit 4, that is, the voltage value between the gate and the emitter. Is registered in the initial value storage means 52. As shown in the time chart of FIG. 3, the comparison means 53 obtains a difference ΔVGE-U between the initial value Vi of the monitor signal VGE-U detected by the VGE detection circuit 9 and the current value Vr, and subsequently the difference. When ΔVGE-U exceeds a preset reference value 1, an element abnormality detection signal CFDL is output and applied to the second control circuit 6. In this case, by appropriately setting the reference value 1, an abnormality sign can be detected before an element failure occurs.
[0025]
The abnormality detection of the U-phase positive semiconductor switching element 1 constituting the three-phase bridge circuit 4 has been described above. The first control circuit 5A provided corresponding to the other semiconductor switching element 1 is also illustrated in FIG. Element abnormality detection means similar to that shown in FIG. 2 is provided, whereby an element showing an abnormality sign before an element failure can be detected.
[0026]
In the first embodiment described above, the element abnormality is detected depending on whether or not the difference ΔVGE-U between the actual initial value Vi of the gate drive voltage and the current value Vr exceeds the reference value 1. Another gate voltage application circuit is provided, and an intentionally boosted gate voltage is applied during the period that hinders the operation of the device, and the initial gate voltage value at the start of operation and the periodically boosted gate voltage It is also possible to calculate the difference from the gate voltage value when the voltage is applied, and to determine whether or not there is an abnormality by determining whether or not the difference exceeds a reference value. Thus, by using a higher voltage than during normal operation, it is possible to detect signs of device abnormality earlier.
[0027]
In the above embodiment, the comparison means 53 includes the voltage difference calculation means. Instead, the difference between the current detected value of the voltage between the gate and the emitter and the voltage data held in the initial value storage means 52 is used. The voltage difference calculation means for calculating the difference and the comparison means for outputting an element abnormality detection signal when the voltage difference calculated by the voltage difference calculation means exceeds a preset reference value are configured separately. You can also.
[0028]
FIG. 4 is a circuit diagram partially showing in block form the configuration of the second embodiment of the power converter according to the present invention. In the figure, the same reference numerals are given to the same elements as those in FIG. 1 showing the first embodiment, and the description thereof is omitted. In the second embodiment, in the first control circuit 5B, abnormality detection corresponding to an abnormality sign before an element failure is performed and an element abnormality detection signal CFDL is added to the second control circuit 6, and the semiconductor switching element The configuration is different from the first embodiment in that the time until the failure state is calculated and the estimated life time data tE is added to the second control circuit 6 is different from the first embodiment. The configuration is the same as that of the embodiment.
[0029]
FIG. 5 is a block diagram showing a configuration of a part of the first control circuit 5B that particularly performs abnormality detection and life estimation. This is provided with the initial value storage means 52 and the comparison means 53 described above, and further compares with a timer 54 that detects the operating time of the apparatus and outputs time data t1 when the comparison means 53 detects an abnormality sign. A calculating unit 55 for calculating a time tE to reach the element failure determination value ΔVGEM after the sign of abnormality is detected by the means 53, outputting an element abnormality detecting signal CFDL, and outputting life estimation time data tE; ing.
[0030]
The operation of the second embodiment configured as described above will be described below. The initial gate voltage value of the semiconductor element 1 detected by the VGE detection circuit 9 is registered in the initial value storage means 52, for example, manually or automatically after one hour from the start of the operation of the three-phase bridge circuit 4. The comparison means 53 obtains a difference ΔVGE-U between the initial value Vi of the monitor signal VGE-U detected by the VGE detection circuit 9 and the current value Vr, and then the difference ΔVGE-U is set to a reference value 1 set in advance. Is added to the timer 54. The timer 54 measures the time from the start of operation of the apparatus, and adds the operation time data t1 to the calculator 55 when the comparison means 53 outputs the element abnormality detection signal CFDL. The arithmetic unit 55 reaches the difference with respect to the initial value Vi of the monitor signal VGE-U based on the reference value 1 inputted in advance and the operation time data t1, that is, the element failure judgment value ΔVGE inputted in advance. The estimated lifetime tE to be calculated is calculated, for example, as being approximately proportional to time (or logarithm of time), and is transmitted to the second control circuit 6 together with the element abnormality detection signal CFDL. The second control circuit 6 displays that the element abnormality detection signal CFDL has been sent and the estimated lifetime tE until failure. Thereby, the power converter device which can grasp | ascertain the estimated time until it reaches an element failure can be provided.
[0031]
FIG. 6 is a block diagram showing a configuration of a part of the third embodiment of the power conversion device according to the present invention, that is, the first control circuit. Here, the comparison means 53A to 53C, the timers 54A to 54C, and the arithmetic unit 56 are all provided in the first control circuit 5B in FIG. 4, and the comparison means 53A to 53C are initial values not shown. The storage means 52 is attached, and the comparison means 53A calculates the difference ΔVGE-U between the initial value Vi of the monitor signal VGE-U and the current value Vr, and the difference ΔVGE-U exceeds the preset reference value 1. A signal indicating this is added to the timer 54A. The comparison means 53B obtains a difference ΔVGE-U between the initial value Vi of the monitor signal VGE-U and the current value Vr, and indicates that the difference ΔVGE-U exceeds a preset reference value 2 (> reference value 1). A signal is applied to timer 54B. The comparison means 53C obtains a difference ΔVGE-U between the initial value Vi and the current value Vr of the monitor signal VGE-U, and indicates that the difference ΔVGE-U exceeds a preset reference value 3 (> reference value 2). A signal is applied to timer 54C.
[0032]
Each time the timers 54 </ b> A to 54 </ b> C receive a signal indicating that the reference value has been exceeded, the operation time data t <b> 1 to t <b> 3 at the time of reception is added to the calculator 56. The computing unit 56 predicts the estimated life time tE until failure based on the operation time data t1 to t3 and the reference values 1 to 3 from the timers 54A to 54B, respectively.
[0033]
Next, the operation of the third embodiment shown in FIG. 6 will be described. The embodiment shown in FIG. 5 assumes that the difference ΔVGE-U between the initial value Vi of the monitor signal VGE-U and the current value Vr is approximately proportional to time (or the logarithm of time), and the element failure determination value ΔVGE. The estimated life time tE to reach is calculated. However, the difference ΔVGE-U with respect to the initial value of the gate voltage has a relatively large time change rate immediately after the use of the semiconductor switching element 1 is started, and the time change rate immediately before reaching the estimated life time tE becomes larger. It has the following characteristics. In the third embodiment shown in FIG. 6, calculation and correction of the estimated lifetime tE is performed for each reference value having a different size set in advance according to the characteristics of the semiconductor switching element 1.
[0034]
Therefore, when the difference ΔVGE-U with respect to the initial value of the gate voltage reaches the reference value 1, the lifetime estimation time tE is calculated in consideration of the characteristics of the semiconductor switching element 1 itself obtained by experiments or simulations, and then When the gate voltage difference ΔVGE-U reaches the reference value 2, the life estimation time tE is calculated and corrected, and when the gate voltage difference ΔVGE-U reaches the reference value 3, the life estimation time tE is calculated and corrected again. . Thereby, the life estimation time tE can be accurately detected. In this case, the calculator 56 transmits to the second control circuit 6 as an element abnormality detection signal, distinguishing that the reference values 1, 2, and 3 have been exceeded, and calculating the lifetime estimated time tE at that time. Is transmitted to the second control circuit 6. The second control circuit 6 displays these signals in the order received, or changes or corrects the display values. As a result, it is possible to provide more accurate information than in the second embodiment by correcting the predicted value of the estimated lifetime tE until failure.
[0035]
In the third embodiment, three kinds of reference values 1, 2, and 3 having different levels are used. However, by providing more combination circuits of comparison means and timers and increasing the number of operations, an element failure occurs. The time estimation accuracy can be further improved. Further, when the characteristics of the semiconductor switching element 1 are stable, it is of course possible to remove the comparison means 53C and the timer 54C shown in FIG. 6 and perform the calculation only twice. Even in this case, it is possible to improve the estimation accuracy of the time required for the device failure than in the second embodiment shown in FIG.
[0036]
In each of the above embodiments, the initial value storage means 52, the comparison means 53, 53A, 53B, and 53C, the timers 54, 54A, 54B, and 54C, and the arithmetic units 55 and 56 are all provided in the first control circuit 5. However, even if these components are provided separately in the first control circuit 5 and the second control circuit 6, or provided only in the second control circuit 6, the same effect as described above can be obtained. .
[0037]
FIGS. 7A and 7B are a plan view and a cross-sectional view showing the configuration of the semiconductor switching element 1 suitable for use in the power converter according to the present invention. In the figure, a collector electrode 13 for forming a collector is formed on one main surface of a semiconductor substrate 10, and a plurality of emitter electrodes 14 constituting an emitter are formed on the other main surface, only for detection of a gate-emitter voltage. An emitter electrode 15 and a gate electrode 16 constituting a gate are formed. In this case, the periphery of the gate electrode 16 is surrounded by the emitter electrode 15, and further, in order to achieve creeping insulation between the collector electrode side and the emitter electrode side, the entire periphery of the main surface on which the emitter electrodes 14 and 15 are formed is provided. The insulator 11 is formed in a protruding state.
[0038]
In this case, the emitter electrodes 14 are arranged in two rows on the left and right in the figure, but one of the emitter electrodes 14 in one row is formed so as to surround the gate electrode 16 in a plan view. The emitter electrode is used for detecting the gate leakage current, that is, the emitter electrode 15 for detecting VGE. In this way, by arranging the VGE detection emic electrode 15 at a position closest to the gate electrode 16 as compared with the other emic electrode 14,
The voltage between the gate G and the emitter E can be accurately detected.
[0039]
【The invention's effect】
As is apparent from the above description, according to the present invention, it is possible to detect which semiconductor switching element has shown an abnormality sign. It is also possible to predict when and which semiconductor switching element will cause an element failure .
[Brief description of the drawings]
FIG. 1 is a circuit diagram partially showing in block form the configuration of a first embodiment of a power conversion device according to the present invention.
FIG. 2 is a block diagram showing a specific configuration of a first control circuit constituting the first embodiment shown in FIG. 1;
FIG. 3 is a time chart for explaining the operation of the first embodiment shown in FIGS. 1 and 2;
FIG. 4 is a circuit diagram partially showing in block form the configuration of a second embodiment of the power conversion device according to the present invention.
FIG. 5 is a block diagram showing a specific configuration of a first control circuit constituting the second embodiment shown in FIG. 4;
FIG. 6 is a block diagram showing a detailed configuration of some elements according to the third embodiment of the present invention.
7A and 7B are a plan view and a cross-sectional view showing a configuration of an insulated gate bipolar transistor as a power conversion semiconductor switching element suitable for applying the present invention.
FIG. 8 is a circuit diagram showing a configuration of a typical three-phase bridge circuit constituting the power converter.
9 is a circuit diagram partially shown in blocks for explaining gate control and element failure detection of the semiconductor switching element 1 shown in FIG. 8. FIG.
10 is a block diagram showing a schematic configuration of an abnormality detection circuit for a semiconductor switching element provided corresponding to the U phase of the circuit shown in FIG. 9;
11 is a time chart for explaining the operation of the abnormality detection circuit shown in FIG. 10;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor switching element 2 for power conversion Free-wheeling diode 3 Arm 4 Three-phase bridge circuit 5, 5A, 5B 1st control circuit 6 2nd control circuit 8 Gate resistance 9 VGE detection circuit 10 Semiconductor substrate 13 Collector electrodes 14, 15 Emitter Electrode 16 Gate electrodes 51, 61 Comparison means 52 Initial value storage means 53, 53A, 53B, 53C Comparison means 54, 54A, 54B, 54C Timers 55, 56

Claims (7)

In a power conversion device having a power conversion semiconductor switching element such as a gate turn-off thyristor or an insulated gate bipolar transistor as a main circuit element for power conversion,
Leakage current detecting means for detecting a gate leakage current of the semiconductor switching element for power conversion;
An element abnormality detection means for outputting an element abnormality detection signal indicating a sign of abnormality when the magnitude of the leakage current at the start of use of the device changes as a reference value or more,
A power conversion device comprising:   As the leakage current detecting means, a voltage detection circuit for detecting a voltage between a gate and an emitter of the semiconductor switching element for power conversion is provided, and the gate leakage current is indirectly detected by the voltage detection circuit. The power conversion device according to claim 1.   The element abnormality detection means is stored in the initial value storage means for storing the voltage data between the gate and the emitter at the start of use of the device, and the current detection value of the voltage between the gate and the emitter and the initial value storage means. Voltage difference calculation means for calculating a difference with voltage data, and comparison means for outputting an element abnormality detection signal when the voltage difference calculated by the voltage difference calculation means exceeds a preset reference value. The power conversion device according to claim 2.   Based on the timer that measures the usage time from the start of use of the device, the measurement time of the timer when the element abnormality detection means outputs the element abnormality detection signal, and the preset reference value, The power conversion device according to claim 3, further comprising a calculation unit that predicts an estimated life time until the semiconductor switching element for power conversion reaches a failure.   The initial value storage means, the voltage difference calculation means, the comparison means, and a timer are provided in a plurality of sets, and the front unit comparison means compares the voltage difference calculated by the voltage difference calculation section using different reference values, and the calculation means 5. The power conversion device according to claim 4, wherein the life estimation time is sequentially predicted every time an element abnormality detection signal is received from the comparison unit.   It is equipped with high voltage application means that makes the voltage between the gate and emitter of the semiconductor switching element for power conversion higher than that during normal operation, and leakage current is detected using this high voltage application means during periods when there is no hindrance to the operation of the device. The power conversion device according to any one of claims 1 to 5, wherein: The collector electrode is formed on one main surface of the semiconductor substrate, the other to form a plurality of emitter electrodes and gate electrodes on a main surface, nearest to the adjacent arranged the emitter electrode of the voltage detection dedicated electrode of said gate electrode The power conversion device according to claim 1, wherein the power conversion semiconductor switching element is used as a main circuit element for power conversion.

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