JP4033284B2 - DC clamp circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DC clamp circuit that fixes a DC level of an analog signal to a predetermined level when A / D converting an analog signal including a DC component such as a video signal, and the clamp circuit. The present invention relates to a direct current clamp circuit in which the loop band of the above changes within one screen unit.
[0002]
[Prior art]
Conventionally, when a video signal as shown in FIG. 6A is A / D converted by an A / D converter, it is necessary to clamp the DC level in the video signal to a constant value by a DC clamp circuit. For this clamping, a clamping pulse as shown in FIG. 6B generated based on the video signal is used. The video signal whose DC level is clamped in this way is amplified so as to be within the dynamic range of the A / D converter and then A / D converted by the A / D converter.
[0003]
In such a DC clamp circuit, it is desired that there is no fluctuation in the DC level (DC level) of the video signal, and if there is a fluctuation in the DC level for some reason, it can be reconverged in a certain band. I need it. As a prior art for realizing this, an invention described in US Pat. No. 4,473,846, an invention described in Japanese Patent No. 4970594, and the like are known.
[0004]
[Problems to be solved by the invention]
However, in these conventional inventions, it is discussed that the re-clamping when the DC level fluctuates for some reason causes convergence in a certain band, and the band is dynamically changed for each clamp pulse. It has not been devised.
[0005]
Actually, when the A / D conversion result of the video signal A / D converter including such a clamp circuit is viewed as a screen of the display device, several lines of information for each clamp pulse (each line) are collected. Since it is recognized as a single screen (still image), and that single screen changes on the time axis and is recognized as a moving image, the band of the clamp circuit is a very important factor in terms of image quality. Come.
[0006]
For example, if the band of the clamp circuit is large (fast convergence), noise for each line appears on the display screen, and so-called horizontal stripe noise occurs. On the other hand, if the band of this clamp circuit is small (slow convergence), it takes time to reconverge if the DC level fluctuates for some reason, and the pull-in process appears on the display screen, which causes cracking noise. It will end up.
[0007]
The fluctuation of the direct current level is not caused by the video signal source itself, but is mostly generated by the video signal A / D converter itself including a clamp circuit and an amplifier. For example, when the amplification factor of the video signal A / D converter is changed in accordance with the fluctuation of the level of the video signal source, an alternative example is that, in this case, the amplification factor has changed, The clamp level value to the A / D converter fluctuates and needs to be reconverged by the clamp circuit.
[0008]
Accordingly, an object of the present invention is to generate no horizontal stripe noise or flicker noise by changing the band of a DC clamp circuit in A / D conversion of an analog signal including a DC component for each clamp pulse within one screen. It is to provide a direct current clamp circuit.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, each invention described in claims 1 to 5 is configured as follows.
That is, the invention described in claim 1 adds an input analog signal including a direct current component and a feedback signal for clamping the input analog signal, amplifies the output of the addition means, and externally. Amplifying means capable of setting an amplification factor, A / D converting means for A / D converting the output of the amplifying means and outputting this as an output signal, and comparing the output of the A / D converting means with a predetermined value Initializing at the time of setting the amplification factor of the amplifying means, the integrating means for integrating the output of the comparing means during the output period of the enable signal and feeding back to the adding means as the feedback signal, It is characterized by comprising counting means for counting the enable signal and integration constant varying means for varying the integration constant of the integrating means in accordance with the output of the counting means.
[0010]
According to a second aspect of the present invention, in the DC clamp circuit according to the first aspect, the integral constant varying unit varies the resistance value of the integrating resistor of the integrating unit according to the output of the counting unit. It is characterized by becoming.
According to a third aspect of the present invention, there is provided an adding means for adding an input analog signal including a direct current component and a feedback signal for clamping the input analog signal, an output of the adding means, and an amplification factor from the outside. Amplifying means capable of setting the output, A / D converting means for A / D converting the output of the amplifying means and outputting this as an output signal, and comparison for comparing the output of the A / D converting means with a predetermined value Means, D / A converting means for D / A converting the output of the comparing means, and integrating the output of the D / A converting means during the output period of the enable signal and feeding back to the adding means as the feedback signal. An integrating means, a counting means that is initialized when setting the amplification factor of the amplifying means, and counts the enable signal, and an output that varies the output level of the D / A converting means according to the output of the counting means level It is characterized in that it comprises a variable means.
[0011]
According to a fourth aspect of the present invention, in the DC clamp circuit according to the third aspect, the output level varying means is for D / A conversion supplied to the D / A converting means in accordance with the output of the counting means. It is characterized by comprising reference level changing means for changing the reference level.
According to a fifth aspect of the present invention, in the DC clamp circuit according to the fourth aspect, the reference level changing means includes a plurality of switches for selecting a plurality of reference voltages, and one of the plurality of switches. Is closed according to the output of the counting means, whereby one of the plurality of reference voltages is supplied to the D / A conversion means.
According to a sixth aspect of the present invention, in the DC clamp circuit according to the third aspect, the output level variable means bit shifts a digital signal input to the D / A conversion means in accordance with the output of the counting means. It is characterized by comprising a bit shifter means.
[0012]
Thus, according to the inventions according to claims 1 and 2, the integration constant of the integrating means can be varied according to the output of the counting means. For this reason, for example, the counting means is initialized at the timing when the amplification factor of the amplifying means is changed, and counting of the enable signal is started. At this time, the integral constant is increased (the loop band is increased), Thereafter, when the count of the counting means reaches a predetermined value, if the integration constant is changed so as to be reduced (the loop band is reduced), the DC clamp circuit in the A / D conversion of the analog signal including the DC component is changed. The band is changed for each clamp pulse.
[0013]
Therefore, according to each of the inventions according to claim 1 and claim 2, when the A / D conversion result from the A / D conversion means is observed on the display screen, the horizontal stripe noise generated when the clamp loop is too fast. In addition, it is possible to suppress both of the flicker noise that occurs when it is too slow, and the optimum loop band can be selected.
Further, according to the inventions according to claims 3 to 6 , the output level of the D / A conversion means can be varied according to the output of the counting means. Therefore, for example, the counting means is initialized at the timing when the amplification factor of the amplifying means is changed and counting of the enable signal is started. At this time, the output level of the D / A converting means is increased (the loop After that, when the count of the counting means reaches a predetermined value, if the output level is changed to be small (the loop bandwidth is small), the same operation and effect as described above can be obtained. It is done.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the DC clamp circuit of the present invention.
As shown in FIG. 1, the DC clamp circuit according to the first embodiment includes an adder 1 as an adding means, an amplifier circuit 2 as an amplifying means, and an A / D converter 3 as an A / D converting means. And a comparator 4 as a comparison means, a D / A converter 5, a switch 6, an integrator 7 as an integration means, and a counter 8 as a counting means.
[0015]
Further, in the DC clamp circuit according to the first embodiment, the amplification factor of the amplifier circuit 2 can be arbitrarily set by the amplification factor setting signal S1, and the counter 8 is reset at the timing of setting the amplification factor and the count value is set. (Count value) is initialized.
The adder 1 adds an analog signal including a direct current component such as a video signal and a feedback signal output from the integrator 7 to clamp the analog signal, and outputs the added value to the amplifier circuit 2. It is like that. The amplifier circuit 2 amplifies the addition signal output from the adder 1 and outputs the amplified signal to the A / D converter 3.
[0016]
The A / D converter 3 A / D converts the analog output signal from the amplifier circuit 2 into a digital signal composed of predetermined bits, and outputs the A / D converted digital signal to the output terminal as an output signal. At the same time, it is output to the comparator 4. The comparator 4 compares the digital signal output from the A / D converter 3 with a predetermined set value in digital form, and outputs a digital signal corresponding to the comparison.
[0017]
Here, the predetermined set value is determined by how much the A / D conversion value (output of the A / D converter 3) for the direct current included in the analog signal is set when a clamp loop described later is formed. Value.
The D / A converter 5 D / A converts the digital signal from the comparator 4 into an analog signal and outputs the analog signal to the integrator 7. The switch 6 is provided between the output side of the D / A converter 5 and the input side of the integrator 7, and its contact can be opened and closed by an enable signal S2.
[0018]
The integrator 7 integrates the output signal from the D / A converter 5 when the contact of the switch 6 is closed by the enable signal S2, and outputs the integrated value to the adder 1 as the feedback signal. It has become. Further, the integrator 7 can be varied by an integral constant control signal S3 that is the count output of the counter 8.
[0019]
The counter 8 is reset by the amplification factor setting signal S1 when the amplification factor of the amplifier 2 is set, and the count value is initialized, and thereafter, the enable signal S2 is counted (counted). The count output of the counter 8 is used as an integration constant control signal S3 for changing the integration constant of the integrator 7.
Next, the operation of the DC clamp circuit according to the first embodiment having such a configuration will be described with reference to FIG.
[0020]
Now, when the enable signal S2 for opening and closing the switch 6 is set to the “H” level, the switch 6 is closed and a clamp loop is formed. At this time, when an analog signal including a direct current component is input to the adder 1 like a video signal, the analog signal and a feedback signal output from the integrator 7 for clamping the analog signal are added to the adder 1. The added signal is output to the amplifier circuit 2.
[0021]
In the amplifier circuit 2, the added signal is amplified and output to the A / D converter 3. In the A / D converter 3, the output of the amplifier circuit 2 is A / D converted into a digital signal of a predetermined bit, and the digital signal is output to the output terminal as an output signal and simultaneously output to the comparator 4.
In the comparator 4, the digital signal is compared with a set value, and the comparison result is output to the D / A converter 5 as a digital signal. In the D / A converter 5, the digital signal is D / A converted into an analog signal. Since the contact of the switch 6 is closed when the clamp loop is formed, the analog signal output from the D / A converter 5 is integrated by the integrator 7 during the closed state. The output signal of the integrator 7 is fed back to the adder 1 as a feedback signal.
[0022]
By such an operation, the difference between the set value of the comparator 4 and the A / D conversion value of the A / D converter 3 becomes zero during the period when the enable signal S2 forming the clamp loop is at the “H” level. As a result, the output of the integrator 7 is converged to a predetermined value.
Next, when it is necessary to change the amplification factor of the amplifier circuit 2 for some reason after the completion of the clamp convergence, the amplification factor of the amplifier circuit 2 is changed by the amplification factor setting signal S1. After that, when the enable signal S2 for opening and closing the switch 6 is set to the “H” level again, the switch 6 is closed to form a crank loop, and before the input analog signal and the amplification factor of the amplifier circuit 2 are changed. The adder 1 adds the output of the integrator 7 which has completed the convergence of the crank loop, and outputs the result to the amplifier circuit 2. At this time, if there is no change in the DC component of the input analog signal, the output value to the amplifier circuit 2 is the same as before the gain is changed.
[0023]
However, since the amplification factor of the amplifier circuit 2 has changed, the output value to the A / D converter 3 has changed from before the amplification factor was changed. Since the convergence of the digital output value of the A / D converter 3 that performs A / D conversion of the output of the amplifier circuit 2 is the same as the set value before the gain is changed, the change in the gain is changed. Thereafter, a difference from the set value occurs, and as described above, the output of the integrator 7 changes so that the difference from the set value becomes zero again, and the crank loop is reconverged.
[0024]
On the other hand, the counter 8 is reset (initialized) triggered by changing the amplification factor of the amplifier circuit 2 by the amplification factor setting signal S1, and then the counter value is changed by the enable signal S2 for forming a crank loop. Further, the output of the counter 8 is used as an integration constant control signal S3 to change the integration constant of the integrator 7. For example, if the counter 8 is initialized, the integration constant of the integrator 7 is maximized, and then the integration constant is decreased for each count. Immediately after the amplification factor of the amplifier circuit 2 is changed. However, it is possible to form a circuit in which the crank loop band is maximized and then the crank loop band gradually decreases each time an enable signal is input.
[0025]
As a result, the noise caused by re-convergence of the crank loop immediately after changing the amplification factor of the amplifier circuit 2 is eliminated due to the high speed of the loop, and the noise of the horizontal stripe due to the high speed of the loop Is solved by slowing down.
Next, a specific configuration for variably controlling the integration constant of the integrator 7 will be described with reference to FIG.
[0026]
As shown in FIG. 2, the integrator 7 includes an operational amplifier (op-amp) 11, a capacitor C1, a resistor R1, a resistor R2, a switch SW1, an analog signal input terminal 12, a digital signal output terminal 13, and the like. . Each value of the capacitor C1 and the resistors R1 and R2 is an element that determines an integration constant of the integrator 7, as will be described later.
[0027]
More specifically, a resistor R1 is connected between the input terminal 12 and the negative input terminal of the operational amplifier 11, and a capacitor C1 is connected between the negative input terminal and the output terminal of the operational amplifier 11. Yes. The positive input terminal of the operational amplifier 11 is grounded. A series circuit in which a resistor R2, a switch, and SW1 are connected in series is connected in parallel to both ends of the resistor R1. The switch SW1 can be opened and closed according to the output of the counter 8.
[0028]
The counter 8A is initialized by the amplification factor setting signal S1, counts the subsequent enable signal S2, and when the count value reaches N, generates an overflow signal S4. The overflow signal S4 is supplied to the switch SW1 as an opening / closing signal for the contact of the switch SW1.
Next, an operation example of the circuit of FIG. 2 having such a configuration will be described.
[0029]
Now, when the counter 8A is initialized by the amplification factor setting signal S1, counting of the enable signal S2 is started. After the count is started, the counter 8A does not generate the overflow signal S4 until the count value reaches N. If it is assumed that the state of the switch SW1 is closed at this time, the integration constant Int1 of the integrator 7 is expressed by the following equation (1).
[0030]
Int1 = C1 × (R1 + R2) / (R1 + R2) (1)
Thereafter, if the count value of the counter 8A reaches N and an overflow signal is generated. At this time, if the state of the switch SW1 is opened, the integration constant Int2 of the integrator 7 is expressed by the following equation (2). Become.
Int2 = C1 × R1 (2)
Comparing the integration constants Int1 and Int2, it can be seen that Int1 <Int2, and thereby the value of the integration constant of the integrator 7 can be decreased (changed) before and after the count value N of the counter 8A.
[0031]
The configuration of the counter 8A is such that the set value N for generating the overflow signal can be set in a programmable manner, or the overflow signal is generated in several steps within the set value N. If a series circuit corresponding to the series circuit of the resistor R2 and the switch SW1 shown in FIG. 2 is connected in parallel to the resistor R1 so that the switch can be opened and closed stepwise, the integration constant of the integrator 7 can be further reduced. Can be controlled.
[0032]
Next, a DC clamp circuit according to a second embodiment of the present invention will be described with reference to FIG.
The DC clamp circuit according to the second embodiment includes a D / A converter 5 shown in FIG. 1 as a D / A converter 5A shown in FIG. 3, and an integrator 7 shown in FIG. 1 as an integrator 7A shown in FIG. The output state of the D / A converter 5A is changed by the output level control signal S5 from the counter 8, and the integrator 7A outputs the signal depending on the signal from the counter 8 on the contrary. The state does not change.
[0033]
Since the structure of the other parts of the second embodiment is the same as that of the first embodiment of FIG. 1, the same parts are denoted by the same reference numerals and the description thereof is omitted, and integrators 7A and D having different structures are used. The configuration of the / A converter 5A will be described in detail.
The integrator 7A has a configuration in which the series circuit of the resistor R2 and the switch SW1 is omitted from the components of the integrator 7 in FIG.
[0034]
As shown in FIG. 4, the D / A converter 5A corresponds to the D / A converter 5 of FIG. 1, and in addition to the D / A converter 21 for D / A converting the digital output from the comparator 4, A selection circuit 22 for selecting a reference level (reference voltage) necessary for D / A conversion supplied from the outside to the D / A converter 21 is included.
As shown in FIG. 4, the selection circuit 22 includes a switch SW2 that selects the first reference voltage V1 and a switch SW3 that selects the second reference voltage V2. The switch SW2 has its contact point opened / closed in response to the overflow signal S4 from the counter 8A, and the switch SW3 has its contact point opened / closed by a signal obtained by inverting the overflow signal S4 from the counter 8A by the inverter 23. Yes. Accordingly, the switches SW2 and SW3 are opened when one is closed depending on the presence or absence of the overflow signal S4.
[0035]
Next, an example of operation | movement of 2nd Embodiment which consists of such a structure is demonstrated with reference to drawings.
In the second embodiment, the operation until the switch 6 is closed and the clamp loop is formed and the convergence of the clamp is completed is basically the same as the operation of the first embodiment, and thus the description thereof is omitted. The operation of the D / A converter 5A and the counter 8A shown in FIG. 4 will be described.
[0036]
In FIG. 4, the relationship between the magnitudes of the reference voltage V1 and the reference voltage V2 supplied to the D / A converter 21 is V1> V2.
Now, when the counter 8A is initialized by the amplification factor setting signal S1, the counter 8A starts counting the enable signal S2, but the counter 8A does not generate the overflow signal S4 until the count value reaches N. At this time, the switch SW2 is closed, the switch SW3 is opened, and the D / A converter 21 is supplied with the reference voltage V1.
[0037]
Thereafter, when the count value of the counter 8A reaches N and generates an overflow signal S4, the switch SW2 is opened, the switch SW3 is closed, and the D / A converter 21 is supplied with the reference voltage V2.
Therefore, the D / A converter 21 takes in the reference voltage V1 during the period from the initialization of the counter 8A until the count value becomes N, and takes in the reference voltage V2 after the count value becomes N, thereby D / A conversion is performed. For this reason, even if the D / A converter 21 has the same digital input, the analog output until the count value reaches N can be made larger than the analog output after the count value reaches N, This corresponds to changing the integration constant of the integrator 7 of the first embodiment.
[0038]
The configuration of the counter 8A is such that the set value N for generating the overflow signal can be set in a programmable manner, or the overflow signal is generated in several steps within the set value N. If the reference voltage and switch shown in FIG. 4 are added and the reference voltage is changed stepwise, the reference voltage supplied to the D / A converter 21 can be controlled more finely.
[0039]
As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained.
Next, another configuration example of the D / A converter will be described with reference to FIG.
As shown in FIG. 5, the D / A converter 5B receives a bit shifter 31 that receives an M-bit digital input signal from the comparator 4 and outputs an (M + L) -bit digital output signal, and a bit shifter 31 It comprises a (M + L) bit D / A converter 32 that D / A converts a digital output signal of (M + L) bits, and a bit shifter 31 generates a data shift of L bits.
[0040]
The output of the bit shifter 31 is controlled as described later by the overflow signal S4 from the counter 8A.
Next, an operation example of the D / A converter 5B configured as described above will be described with reference to FIG.
When the counter 8A is initialized by the amplification factor setting signal S1, the counter 8A starts counting the enable signal S2, but the counter 8A does not generate the overflow signal S4 until the count value reaches N. At this time, the bit shifter 31 outputs the M-bit input digital signal to the M bits on the MSB (most significant bit) side of the (M + L) -bit digital output. At this time, zero is output as the L bit on the LSB (least significant bit) side.
[0041]
Thereafter, when the count value of the counter 8A reaches N and generates an overflow signal S4, the bit shifter 31 outputs an M-bit input digital signal to the M bits on the LSB side of the (M + L) -bit digital output. The L bit on the MSB side outputs zero.
By such an operation, a data shift of L bits occurs before and after the count value of the counter 8A is around the set value N. As a result, the analog output level of the D / A converter 5B becomes the same digital input value. On the other hand, the output level is decreased by 1/2 ^L (1 / L power of 2). That is, it is the same as the case where the reference voltage is varied as in the case of the D / A converter 5A in FIG. 4, and the same effect is obtained.
[0042]
In FIG. 5, if the configuration of the counter 8A is made programmable or the bit shifter 31 also makes the bit shift variable, the output of the D / A converter 5B can be controlled more finely.
[0043]
【The invention's effect】
As described above, according to the present invention, when the A / D conversion result output from the A / D conversion means is observed on the display screen, the horizontal stripe noise generated when the clamp loop is too fast, It is possible to suppress both flicker noises that occur when the time is too slow.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of a DC clamp circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration example of an integrator and a counter shown in FIG.
FIG. 3 is a block diagram showing an overall configuration of a DC clamp circuit according to a second embodiment of the present invention.
4 is a circuit diagram showing a specific configuration example of the D / A converter shown in FIG. 3. FIG.
5 is a circuit diagram showing another specific configuration example of the D / A converter shown in FIG. 3. FIG.
FIG. 6 is a waveform diagram for explaining the prior art.
[Explanation of symbols]
C1 Capacitors R1, R2 Resistors SW1 to SW3 Switch 1 Adder 2 Amplifying circuit 3 A / D converter 4 Comparator 5, 5A, 5B D / A converter 5A D / A converter 7 Integrator 8, 8A Counter 11 Calculation Amplifier 21 D / A converter 22 Select circuit 23 Inverter 31 Bit shifter 32 (M + L) Bit D / A converter

Claims (6)

An adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal;
Amplifying means capable of amplifying the output of the adding means and setting an amplification factor from the outside;
A / D conversion means for A / D converting the output of the amplification means and outputting it as an output signal;
Comparison means for comparing the output of the A / D conversion means with a predetermined value;
Integrating means for integrating the output of the comparing means during the output period of the enable signal and feeding back to the adding means as the feedback signal;
Counting means that is initialized when setting the amplification factor of the amplification means and counts the enable signal;
Integration constant variable means for changing the integration constant of the integration means in accordance with the output of the counting means;
A direct current clamp circuit comprising:   2. The DC clamp circuit according to claim 1, wherein the integral constant varying means varies the resistance value of the integrating resistor of the integrating means according to the output of the counting means. An adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal;
Amplifying means capable of amplifying the output of the adding means and setting an amplification factor from the outside;
A / D conversion means for A / D converting the output of the amplification means and outputting it as an output signal;
Comparison means for comparing the output of the A / D conversion means with a predetermined value;
D / A conversion means for D / A converting the output of the comparison means;
Integrating means for integrating the output of the D / A converting means during the output period of the enable signal and causing the adding means to feed back as the feedback signal;
Counting means that is initialized when setting the amplification factor of the amplification means and counts the enable signal;
Output level varying means for varying the output level of the D / A converting means according to the output of the counting means;
A direct current clamp circuit comprising:   4. The output level varying means comprises reference level changing means for changing a reference level for D / A conversion supplied to the D / A converting means in accordance with an output of the counting means. The direct current clamp circuit described in 1.   The reference level changing means has a plurality of switches for selecting a plurality of reference voltages, and closes one of the plurality of switches according to the output of the counting means, whereby the plurality of reference voltages 5. The DC clamp circuit according to claim 4, wherein one of the two is supplied to the D / A conversion means. 4. The DC clamp circuit according to claim 3, wherein the output level varying means comprises bit shifter means for bit-shifting a digital signal input to the D / A conversion means in accordance with the output of the counting means.

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