JP4032494B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having two or more types of effective gate oxide film thicknesses in one gate oxidation (one kind of gate oxide film thickness) and its manufacture. Regarding the method.
[0002]
[Prior art]
With the increase in LSI integration scale, software development has become a bottleneck for shortening the LSI development period only with a combination of a conventional processor and memory. For this reason, there is a growing demand for incorporating LSIs for specific applications (ASIC) into LSI chips in advance. Also, this ASIC cannot be separated from the system using the ASIC as the integration scale increases, and has recently been developed into what is called a system LSI.
Devices integrated in such system LSIs are currently being integrated into a single chip including not only processors and DRAMs but also non-volatile memories and various interface circuits.
[0003]
However, the complexity of such a wafer process for making various devices into one chip is rapidly increasing. For example, as for the gate oxide film, one type of film thickness is often used in the conventional LSI, whereas in the system LSI, one type of gate oxide film thickness is used as the number of device types increases. This is unlikely, and a multi-oxide process has become common. This is because even if the design rule is the same, the required characteristics differ from device to device.
For example, in a logic circuit, the driving capability (operation speed, etc.) of a transistor is required, so the gate oxide film must be relatively thin. On the other hand, in a memory such as a DRAM, a voltage higher than the external power supply voltage may be used due to internal boosting, for example, from the viewpoint of improving the operation speed. From the viewpoint of securing a withstand voltage accompanying this, or to improve retention characteristics. In addition, a relatively thick gate oxide film is used. In addition, in many LSIs including other memories, in the case of a multi-power supply LSI that internally drops or boosts the power supply voltage, the gate oxide film thickness of the interface circuit and the high voltage part is relatively set due to the problem of withstand voltage. May be thicker.
[0004]
When such a multi-oxide process is used, the gate oxidation film is normally formed twice (by additional oxidation) in the thick portion where the gate oxide film is formed. On the other hand, in the portion where the thin gate oxide film is formed, an oxide film grown in a later oxidation process is used as the gate oxide film. Therefore, in the portion where the thin gate oxide film is formed, it is necessary to selectively remove the oxide film after the first oxidation step using a resist mask process.
[0005]
Thus, the conventional method requires a resist mask process according to the type of gate oxide film thickness. However, in this resist mask process, there is a problem of substrate contamination particularly in a portion where a thin gate oxide film is formed because ashing for removing the resist is necessary after the substrate region where the transistor is formed is exposed. Also, resist application and ashing must be performed with the gate oxide film exposed, and the problems of contamination and damage introduction from the resist to the gate oxide film cannot be ignored.
[0006]
On the other hand, Japanese Patent Laid-Open No. 3-94464 proposes a semiconductor device in which the effective gate capacitance is changed by changing the impurity concentration of the polycrystalline silicon (PolySi) gate electrode.
FIG. 10A is a cross-sectional view showing regions having different gate oxide film thicknesses, and FIG. 10B shows various parameters described in the above publication.
In FIG. 10, a chip portion that originally requires a thin gate oxide film is defined as region A, and a portion that originally requires a thick gate oxide film is defined as region B. In the figure, reference numeral 100 denotes a semiconductor substrate, 102 denotes LOCOS, 104a and 104b denote gate oxide films, 106a and 106b denote gate electrodes made of polysilicon, 108 denotes an interlayer insulating film, 110 denotes a connection plug, and 112 denotes a wiring layer. Show.
[0007]
In this semiconductor device, as shown in FIG. 10B, the impurity concentration in the polysilicon is changed between the regions A and B by using the resist mask process twice. Therefore, the effective gate oxide film thickness can be realized with different values between the regions A and B. Here, the “effective gate oxide film thickness” is the thickness of a region having no electric charge that determines the gate capacitance, and the polysilicon layer portion in contact with the physical gate oxide film thickness. And the thickness of a depletion layer formed when a predetermined potential is applied.
[0008]
If this method of changing the impurity concentration in the polysilicon of the gate electrode is used, a transistor having effectively a plurality of types of gate oxide thicknesses by one gate oxidation (one type of physical gate oxide thickness). Can be formed.
[0009]
[Problems to be solved by the invention]
However, the technique disclosed in Japanese Patent Laid-Open No. 3-94464 has a problem that the work function and sheet resistance of the finished gate electrode are also changed. In particular, in order to provide an effective difference in the effective gate oxide film thickness, it is necessary to considerably reduce the impurity concentration in one side (region B) polysilicon, and the resulting sheet resistance due to the reduction in the impurity concentration. The rise in is fatal. In this regard, as shown in “IEEE TRANSACTION ON ELECTRON DEVICES, VOL.ED-32, NO.3, 1985 p620”, the impurity concentration is, for example, 10¹⁹cm^-3It is known that the sheet resistance increases exponentially with decreasing impurity concentration below the order.
This increase in sheet resistance affects the operation speed of the element without routing the gate electrode wiring, and as a result, the degree of freedom in device and circuit design is lost. In addition, especially on the low-concentration polysilicon side, the work function and sheet resistance of the gate electrode change significantly due to the influence of the gate bias and temperature. Don't be.
From the above, in this method of changing the impurity concentration in the polysilicon, it is essential to start over from the device and circuit design, and as a result, the conventional design assets cannot be utilized.
[0010]
In view of the above background, there is a demand for a method of forming an insulated gate transistor that can locally control only the gate capacitance without greatly changing the work function of the gate electrode and the finished sheet resistance.
[0011]
The present invention has been made in view of such circumstances, and provides a semiconductor device having a plurality of types of effective gate oxide film thicknesses while performing gate oxidation once (one type of gate oxide film thickness). An object of the present invention is to realize a gate electrode without significant variation in work function and sheet resistance.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problems of the prior art and achieve the above object, the present inventors have made various studies. As a result, in the silicide single layer gate electrode such as WSix, the finished silicide grain size is We found experimentally that the larger the growth, the greater the effective gate oxide thickness. This is considered due to the fact that the capacitive material is condensed in the grain boundary portion.
[0013]
  The present inventionPolycrystalline gate electrode layer, especially polycrystalline electrode layer gate electrode material of refractory metal silicideIt uses the nature of.
  A semiconductor device according to the present invention is a semiconductor device having a plurality of types of transistors having characteristic differences depending on a gate insulating film thickness, and the film thickness of the gate insulating film is different between the plurality of types of transistors. Set to a constant value and on the gate insulating film (for example, made of refractory metal silicide)Polycrystalline electrode layer gate electrode of refractory metal silicideGreIThe transistor size is changed according to the type of transistor.
[0014]
  In addition, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a plurality of types of transistors having characteristic differences depending on a gate insulating film thickness, and the gates of the plurality of types of transistors. An insulating film is collectively formed in a single film formation process on the surface of the semiconductor substrate, and a gray film is formed on the gate insulating film.IChange the gate size according to the type of transistorLayer, ie, polycrystalline electrode layer of refractory metal silicideA gate electrode is formed.
[0015]
  GureIThere are the following two methods for locally changing the size.
(1) For examplePolycrystalline gate electrode layer gate electrodeBefore the heat treatment after film formation, change at least one of the type of impurity and the amount of introduction according to the type of the transistor,Polycrystalline electrode layer of refractory metal silicideImpurities are introduced into the.
(2) For examplePolycrystalline gate electrode layer gate electrodeAfter the film to be formed is formed, the film is locally thinned by etching or the like to a film thickness corresponding to the type of the transistor.
[0016]
In the method of manufacturing a semiconductor device according to the present invention, the substrate is not exposed in a state where the oxidation process for forming the gate oxide film is performed only once and the photoresist is formed. By a process that can avoid this substrate contamination, the effective gate oxide film thickness can be set to different values within the same wafer by changing the grain size of silicide or the like. For this reason, although there is a difference in the sheet resistance of the gate electrode corresponding to the thickness of the silicide and the grain size, the sheet resistance is changed by orders of magnitude as in the method disclosed in Japanese Patent Laid-Open No. 3-94464. There is nothing. In addition, silicide doped with impurities is a metal in terms of material, and its sheet resistance and work function temperature characteristics are relatively small.
For the above reasons, when applying the method of manufacturing a semiconductor device according to the present invention, it is only necessary to change the process without changing already designed devices and circuit specifications.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
As described above, the present inventor has found through experiments that the effective gate oxide film thickness increases as the grain size grows larger in the silicide single layer gate electrode. Since the present invention has been devised based on the experimental results, in the following, after briefly describing the experimental results, embodiments of the semiconductor device and the manufacturing method thereof according to the present invention will be described. Details will be described with reference to FIG.
[0018]
FIG. 8 is a graph showing the result of CV measurement in which the change in gate capacitance according to the type of impurity ions was examined. FIG. 9 is a graph showing the relationship between the effective gate oxide film thickness obtained by calculation from the measured gate capacitance value and the ion dose.
In this experiment, the dose of WSix to the film was set to 5 × 10.¹⁵cm^-2As a constant, a sample obtained by performing ion implantation by changing the kind of impurities such as Phos, As, Sb, and B, and annealing it under a predetermined condition was used as an evaluation target.
[0019]
As shown in FIG. 8, the value of the gate capacitance Cg differs particularly on the positive gate bias side depending on the type of doped impurity (Phos, As, Sb, B, etc.). This is because the crystallization speed in the annealing is different in the silicide film of each sample, and the grain size is different. The reason why the gate capacitance Cg changes due to the difference in grain size is considered to be because the capacitive material is condensed at the grain boundary portion. By using the gate capacitance value at a predetermined gate bias, the effective gate oxide film thickness Tox.eff can be obtained by calculation.
As shown in FIG. 9, this effective gate oxide film thickness Tox.eff depends on the dose amount of impurity ions, and the larger the dose amount, the wider the Tox.eff difference when various impurities are used. I understand. This agrees with the observation result that the grain size increases as the dose increases.
In general, it is known that the grain size of a polycrystalline material is such that the larger the film thickness, the larger the final crystal grain size.
[0020]
From the above, by controlling the grain size of the finished silicide in the gate electrode of a single silicide layer, it is possible to produce multiple types of transistors with different finished effective gate oxide thicknesses even with the same oxide thickness I found out that In order to change the grain size of the completed silicide, it has been found that the type and dose of impurities introduced into the silicide may be changed, or the thickness of the silicide may be locally changed.
[0021]
For example, for WSix, set As or Phos to ~ 5x10²⁰cm^-3In both cases, the work function is about 0.3V from the center of the silicon band gap.⁺It is possible to shift to the PolySi side. In the case of As doping, the resulting grain size is larger than that of Phos doping, and the effective gate oxide film thickness Tox.eff increases. In other words, in the combination of As and Phos, two types of transistors are produced which differ only in the effective gate oxide film thickness Tox.eff of the finished product while shifting the work function by the same direction and amount and substantially the same sheet resistance value. it can.
Further, in the combination of p-type impurities and n-type impurities, for example, B and As, the difference in effective gate oxide film thickness Tox.eff can be further increased although the shift direction of the work function differs and a difference occurs.
On the other hand, if the film thickness of WSix is locally changed by the resist mask process, the grain size of the completed WSix changes greatly depending on the film thickness even with the same heat treatment. Even with this method alone, the effective gate oxide film thickness Tox.eff can be locally changed. However, a larger Tox. eff difference can be realized.
[0022]
Hereinafter, a more specific embodiment of the present invention will be described by taking the formation of a gate electrode of a MOS semiconductor device as an example.
[0023]
First embodiment
In the present embodiment, the type of impurity and the dose amount are changed.
FIG. 1 is a cross-sectional view of a main part of the MOS type semiconductor device according to the present embodiment.
In FIG. 1, reference numeral 1 denotes a MOS type semiconductor device, 2 denotes a silicon substrate, 4 denotes an element isolation region such as LOCOS, 6 denotes a gate oxide film, 8a and 8b denote gate electrodes made of WSix, and 10 denotes an interlayer insulating film. In FIG. 1, a chip region A in which the effective gate oxide film thickness Tox.eff is desired to be thinned is shown on the left side, and a chip region B in which Tox.eff is desired to be thickened on the right side.
[0024]
In this embodiment, gate electrodes 8a and 8b made of, for example, WSix are formed on the gate oxide film 6 formed on the silicon substrate 2 that becomes Bulk. The thickness of the gate oxide film 6 is about ˜5 nm, for example, and the thickness of the gate electrodes 8a and 8b is about ˜100 nm, for example.
The gate electrode 8a in one region A has phos of, for example, about 5 × 10 × 10.²⁰cm^-3As for the gate electrode 8b in the other region B, for example, ˜1 × 10^{twenty one}cm^-3Each is doped at a concentration of. In this example, the type and concentration of the n-type impurity in WSix are changed in this way, for example, the grain size after completion of the heat treatment at a maximum heat treatment temperature of 850 ° C. for about 30 minutes, as shown in FIG. The region B side is sufficiently larger than the region A side.
As a result, the effective gate oxide film thickness Tox.eff (calculated value) thus completed is different by ˜6 nm on the region A side and ˜8 nm on the region B side. In this example, the work function of WSix is n from the center of the silicon bandgap, regardless of which impurity is used.⁺It is located at a position shifted by ~ 0.3V to the Si side.
[0025]
In such a semiconductor device 1 of this example, the type and / or concentration of impurities introduced into WSix while the physical oxide film thickness immediately after deposition (As Grown) is constant, that is, by one gate oxidation. By changing the effective gate oxide film thickness locally.
[0026]
In the example of FIG. 1, phos and As are used as different types of impurities. However, in this embodiment, the types of impurities are not limited. For example, boron (B) can be used as an impurity that inhibits grain growth. At this time, the work function of WSix is p from the center of the band gap of silicon.⁺It will shift ~ 0.3V to the Si side. Therefore, the work function is different from that of WSix doped with other n-type impurities, but the effective gate oxide film thickness Tox.eff is about 5.5 nm, which is close to that immediately after the film formation. There is an advantage that a Tox.eff difference can be obtained. In any case, basically, as the impurity dose is increased, the growth of the finished grains can be promoted or suppressed.
Other configurations are not limited to the above description. A semiconductor device to which the present invention can be applied may be any MIS type semiconductor device that is insulated from the substrate by a gate insulating film (not limited to an oxide film). The substrate may be an SOI or the like, and the gate electrode may be a general polycrystalline silicide or metal, such as MoSix, TaSix, Mo, W, Ta or the like. The polycrystalline material may be other polysilicon. Also, the types of impurities to be introduced and their concentrations are just examples.
[0027]
Next, a method for manufacturing the semiconductor device having the above-described configuration will be described with reference to the drawings.
2-5 is sectional drawing which shows each manufacturing process of this manufacturing method.
[0028]
First, in FIG. 2A, an element isolation region 4 is formed on a prepared silicon substrate 2 by a LOCOS method or the like.
Next, in FIG. 2B, the gate oxide film 6 is grown by a thermal oxidation method or the like so as to have a thickness of about 6 nm immediately after the film formation. On the gate oxide film 6, a WSix film 8 is deposited, for example, by about 100 nm by, for example, a CVD method. The WSix deposition conditions at this time are, for example, as shown below.
[0029]
[WSix deposition conditions],
Cold Wall type LP-CVD equipment,
Pressure: 133Pa,
Susceptor temperature: 595 ° C,
Introduced gas: SiH₂Cl₂/ WF₆= 100 / 1.8 sccm.
[0030]
In FIG. 3C, a resist pattern 9 having an opening in the region A is formed on the WSix film 8. And Phos on the whole surface⁺Is doped by ion implantation. The ion implantation conditions are, for example, acceleration voltage: 25 KeV, dose amount: 5 × 10¹⁵cm^-2And As a result, Phos is introduced only into the WSix film portion in the region A through the opening 9 a of the resist pattern 9.
[0031]
Subsequently, in FIG. 3D, a resist pattern 11 different from the previously formed resist pattern 11 is formed on the WSix film 8, and the As 11 is formed through the opening 11b.⁺Is doped only into the WSix film portion of region B by ion implantation. The ion implantation conditions at this time are, for example, acceleration voltage: 50 KeV, dose amount 1 × 10¹⁶cm^-2And
[0032]
As shown in FIG. 4E, a photoresist 13 for obtaining a gate electrode pattern is formed on the WSix film 8 doped with different impurities in this way, and this photoresist 13 is formed. The WSix film 8 and the gate oxide film 6 are etched on the mask by a method such as RIE.
Although the photoresist 13 is removed and the LDD region and the high-concentration impurity region are formed, although not particularly shown, an interlayer insulating film is deposited. These impurity regions are formed in the same manner as a normal MOS transistor manufacturing process. That is, the LDD region is formed after the gate electrode is formed, and the high-concentration impurity diffusion region is formed after the sidewall insulating layer is further formed, using the gate electrode pattern and LOCOS (and the sidewall insulating layer) as a self-aligned mask, and Different impurities are separated while protecting one of the nMOS and the pMOS with a resist mask.
[0033]
Next, heat treatment for activating impurities is performed under the following conditions, for example. As a result, as shown in detail in FIG. 1, the gate electrode 8a on the region A side has a small grain size, and the gate electrode 8b on the region B side has a large grain size.
[0034]
[Heat treatment conditions]; Electric furnace annealing,
N₂850 ° C. for 30 minutes in the atmosphere.
[0035]
After that, as shown in FIG. 5H, in the same manner as in a normal MOS transistor manufacturing process, the connection plug 12 is formed (contact hole formation and metal filling) and the wiring 14 is sequentially formed. To complete.
[0036]
In the manufacturing method of this example, the gate oxide film is formed once (FIG. 2B) and is immediately covered with the WSi film 8. The gate oxide film 6 and the substrate surface never appear until the patterning is performed in FIG. As a result, the gate oxide film 6 and the substrate surface are not contaminated or damaged by organic substances.
In this manufacturing method, there is an advantage that the gate forming process is highly reliable and the effective gate oxide film thickness can be easily changed by the impurity separation.
[0037]
In addition, the formation method of each part mentioned above is an example, and is not limited to the method and conditions. For example, as the film formation method for WSix, a physical film formation method such as a vapor deposition method or a sputtering method can be employed in addition to the CVD method. In any film forming method, a layered film of polysilicon and a refractory metal may be formed, for example, instead of WSix, and this may be reacted at the time of heating to change to a single layer film of WSix. Also, various methods such as co-evaporation for supplying metal and silicon from separate sources, co-sputtering, and sputtering using a hot-pressed silicide target can be employed.
[0038]
Second embodiment
This embodiment is a case where the film thickness of the polycrystalline gate electrode is locally changed to change the grain size upon completion.
FIG. 6 is a fragmentary cross-sectional view of the MOS semiconductor device according to the present embodiment. FIG. 7 is a cross-sectional view showing a step of setting the thickness of a silicide film to be a polycrystalline gate electrode in the manufacturing process of the MOS type semiconductor device of FIG. FIG. 7 corresponds to the process of FIG. 3 in the first embodiment, and other processes are basically the same as those of the first embodiment. Also, the configuration is the same as that of the first embodiment except for the thickness of the silicide film, and in the following, the same components are denoted by the same reference numerals and detailed description thereof is omitted.
[0039]
In general, a polycrystalline material such as silicide has a larger grain size as the film thickness increases. Therefore, if the thickness of the local polycrystalline material is reduced using a mask after depositing a certain thickness, the grain size of the finished polycrystalline film can be locally changed within the wafer. It becomes.
For example, in the example of FIG. 6, although the region A and the region B are ion-implanted with the same impurity to make the WSix film conductive, only the film thickness of the WSi film is controlled. The grain size of the B gate electrode 22b can be made larger than that of the region A on the gate electrode 22a side.
More specifically, if the maximum annealing temperature of annealing is 850 ° C. and the time is about 30 minutes, and the film thickness of WSix 22a is about 50 nm in the region A, the effect is almost equal to the gate oxide film thickness immediately after film formation. It is possible to obtain a typical gate oxide film thickness Tox.eff. On the other hand, when the film thickness of WSix 22b is increased to about 150 nm in the region B, the effective oxide film thickness Tox.eff obtained under the same annealing conditions is about 7 nm. The higher the maximum heat treatment temperature at the time of annealing, the more the grain growth is promoted in the thick portion of WSix, and the grain size becomes larger when impurities such as As are introduced to promote grain growth.
[0040]
Specifically, as a method of providing a difference in WSix film thickness, first, a photoresist 9 having an opening only in the region A is formed in FIG. Next, in the step of FIG. 7B, only the region A through the opening 9a of the photoresist 9 is locally thinned by etching from the thickness (˜150 nm) after deposition of the WSix 22 to about −50 nm. . The thinning of WSix 22 may be performed by dry etching such as RIE or wet etching. In this example, it is necessary to dose a predetermined amount of a predetermined impurity by whole surface ion implantation before and after the step of FIG.
[0041]
In such a method, as compared with the case of the first embodiment, the ion implantation and the formation of the photoresist mask pattern can be omitted once, and the process is simple.
This grain size change by controlling the film thickness can be combined with the first embodiment, that is, the type and / or dose of impurities to be introduced and the film thickness of WSix can be changed simultaneously. Thereby, although the number of processes increases, the effective oxide film thickness Tox.eff can be further expanded between the regions A and B. Here, it is the same as in the first embodiment that the polycrystalline material, the type of impurities, and the processing method and conditions can be modified.
[0042]
【The invention's effect】
According to the semiconductor device and the manufacturing method thereof according to the present invention, a transistor having two or more effective oxide film thicknesses can be manufactured by one oxidation (a constant oxide film thickness immediately after film formation). As a result, the multi-oxide process can be performed without being affected by contamination from the resist or the like. In addition, since a gate electrode such as metal or silicide is used, the sheet resistance of the gate electrode does not change greatly depending on the effective gate oxide film thickness and grain size. For this reason, it is possible to cope with only the change of the process without changing the basic part of the already designed device and circuit specification, and it is possible to use the assets of such a design.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a relevant part of a MOS semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing each manufacturing process of the MOS type semiconductor device shown in FIG. 1 and shows a process up to formation of a WSix film.
3 is a cross-sectional view subsequent to FIG. 2, showing the process up to impurity ion implantation into the WSix film. FIG.
4 is a cross-sectional view subsequent to FIG. 3, showing the process up to WSix film processing (gate electrode formation). FIG.
FIG. 5 is a cross-sectional view subsequent to FIG. 4, showing the formation up to the upper layer wiring;
FIG. 6 is a fragmentary cross-sectional view of a MOS semiconductor device according to a second embodiment of the present invention.
7 is a cross-sectional view showing a step of setting the thickness of a silicide film to be a polycrystalline gate electrode in the manufacturing process of the MOS type semiconductor device shown in FIG. 6;
FIG. 8 is a graph showing a result of CV measurement in which a change in gate capacitance according to the type of impurity ions is examined.
FIG. 9 is a graph showing the relationship between the effective gate oxide film thickness and the ion dose obtained by calculation from the gate capacitance.
FIG. 10 is a diagram showing a cross-sectional structure in two regions having different gate oxide film thicknesses together with various manufacturing parameters in a MOS type semiconductor device manufactured by a conventional method for changing the effective gate oxide film thickness.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,20 ... MOS type semiconductor device (semiconductor device), 2 ... Silicon substrate, 4 ... Element isolation region, 6 ... Gate oxide film (gate insulating film), 8, 22 ... WSix film, 8a, 8b, 22a, 22b ... Gate electrode (polycrystalline gate electrode), 9, 11, 13 ... photoresist, 10 ... interlayer insulating film, 12 ... connection plug, 14 ... wiring, Cg ... gate capacitance, Tox.eff ... finished effective gate oxide film Thickness.

Claims (7)

A semiconductor device having a plurality of types of transistors having characteristic differences depending on the gate insulating film thickness,
The gate electrodes of the plurality of types of transistors comprise a single layer of a refractory metal silicide polycrystalline electrode layer ,
The gate insulating film is set to the same material and the same film thickness among the plurality of types of transistors, and the grain size of the polycrystalline electrode layer gate electrode of the refractory metal silicide on the gate insulating film is set to the transistor Depending on the type of
Semiconductor device. For the impurities introduced into the polycrystalline electrode layer of the refractory metal silicide, at least one of the type of impurity and the amount of introduction differs depending on the type of the transistor,
The semiconductor device according to claim 1. The film thickness of the polycrystalline metal layer of the refractory metal silicide varies depending on the type of the transistor,
The semiconductor device according to claim 1. A method of manufacturing a semiconductor device having a plurality of types of transistors having characteristic differences depending on a gate insulating film thickness,
The gate insulating films of the plurality of types of transistors are collectively formed in a single film formation process on the surface of the semiconductor substrate,
A polycrystalline gate electrode layer is formed on the gate insulating film by changing the grain size according to the type of the transistor,
In the formation of the polycrystalline gate electrode layer, a single refractory metal silicide film is formed, and the grain size is changed by heat treatment.
A method for manufacturing a semiconductor device. In the formation of the polycrystalline gate electrode layer, after laminating polycrystalline or amorphous silicon and a refractory metal, grains are generated or changed in size when silicidized by heat treatment,
A method for manufacturing a semiconductor device according to claim 4. In the formation of the polycrystalline gate electrode layer, for the impurities to be introduced into the polycrystalline gate electrode material, the grain size is controlled according to the type of the transistor by changing at least one of the type of impurity and the amount introduced.
A method for manufacturing a semiconductor device according to claim 4. In the formation of the polycrystalline gate electrode layer, the grain size is controlled according to the type of the transistor by changing the film thickness setting,
A method for manufacturing a semiconductor device according to claim 4.

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