JP4015346B2 - Semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for reducing the access time of a semiconductor memory. In particular, the present invention relates to a technique for optimally operating a circuit corresponding to a column address according to latency.
[0002]
[Prior art]
FIG. 11 shows a general SDRAM (Synchronous DRAM) sense amplifier and its periphery.
In the figure, column switches 6a and 6b comprising a sense amplifier 2, a precharge circuit 4, and nMOS transistors (hereinafter simply referred to as nMOS) are connected to complementary bit lines BL and / BL.
[0003]
The sense amplifier 2 is formed by connecting the inputs and outputs of two CMOS inverters 2a to each other. The nMOS source of the CMOS inverter 2a is connected to the ground line VSS through the nMOS 2b. The gate of the nMOS 2b is controlled by a sense amplifier enable signal LEZ. The source of the pMOS transistor (hereinafter simply referred to as pMOS) of the CMOS inverter 2a is connected to the power supply line VDD via the pMOS 2c. The gate of the pMOS 2c is controlled by a sense amplifier enable signal LEX. The output of the CMOS inverter 2a is connected to the bit lines / BL and BL, respectively.
[0004]
The precharge circuit 4 includes an nMOS 4a that equalizes the bit lines BL and / BL, and nMOSs 4b and 4c that connect the bit lines BL and / BL to the precharge line VPR, respectively. The gates of the nMOSs 4a, 4b and 4c receive the precharge signal PRE.
One of the source / drain of the column switches 6a and 6b is connected to the bit lines BL and / BL, respectively, and the other is connected to the data buses DBZ and DBX, respectively. The gates of the column switches 6a and 6b are connected to the column line selection signal CLZ.
[0005]
The bit lines BL and / BL are connected to memory arrays arranged on both sides of the sense amplifier 2 via nMOSs 8a and 8b. The gates of the nMOSs 8a and 8b are controlled by the isolation signals ISO and / ISO, respectively. When one of the nMOSs 8a and 8b becomes conductive, the other becomes non-conductive.
Next, the SDRAM read operation will be described.
[0006]
FIG. 12 shows the SDRAM read operation when the CAS latency is “1”. CAS latency is the number of clock cycles from when the read command RD is supplied until read data is output. The CAS latency is set according to, for example, the clock frequency of a system equipped with SDRAM. In this example, the frequency of the clock signal CLK is 100 MHz (period = 10 ns).
[0007]
First, a command signal CMD indicating an active command ACTV and a row address signal (not shown) are supplied in synchronization with the clock signal CLK (FIG. 12A). Upon receipt of the active command ACTV, the control circuit corresponding to the row address operates, and the word line selection signal WL is activated (high level) (FIG. 12B). Here, the word line selection signal WL is a signal transmitted onto the word line that controls the transfer gate of the memory cell formed in the memory array. By activation of the word line selection signal WL, the memory cell is connected to the bit line BL (or / BL), and the data held in the memory cell is transmitted to the bit line on BL (or / BL) (see FIG. 12 (c)).
[0008]
After a predetermined time from the activation of the word line selection signal WL, the sense amplifier enable signals LEZ and LEX are activated (high level and low level, respectively) (FIG. 12 (d)). Activation of the sense amplifier enable signals LEZ and LEX activates the sense amplifier 2 and amplifies the read data transmitted to the bit lines BL and / BL (FIG. 12 (e)). Here, the period T1 from when the active command ACTV is supplied to when the sense amplifier enable signals LEZ and LEX are activated depends on the operation time of the control circuit and does not depend on the frequency of the clock signal CLK.
[0009]
A period T2 from the activation of the sense amplifier enable signals LEZ and LEX is a period necessary for the read data to be sufficiently amplified by the sense amplifier 2 and read stably. If the column line selection signal CLZ is activated during this period T2, the amplified read data may be destroyed due to the influence of the parasitic capacitances of the data buses DBZ and DBX. Therefore, the column line selection signal CLZ must be activated after the period T2, as will be described later. Note that the period T2 depends on the operation time of the control circuit and does not depend on the frequency of the clock signal CLK. That is, even if the frequency of the clock signal CLK changes, the period T2 does not change.
[0010]
After receiving the active command ACTV, a command signal CMD indicating a read command RD and an address signal AD (column address) (not shown) are supplied in synchronization with the next clock signal CLK (FIG. 12 (f)). Upon receipt of the read command RD, the control circuit corresponding to the column address operates, and the column line selection signal CLZ is activated (high level) (FIG. 12 (g)). Here, a period T3 from when the read command RD is supplied to when the column line selection signal CLZ is activated depends on the operation time of the control circuit and does not depend on the frequency of the clock signal CLK. In order to read the read data correctly, the column line selection signal CLZ is activated after the period T2. As the column line selection signal CLZ is activated, read data amplified on the bit lines BL and / BL is transmitted to the data buses DBZ and DBX (FIG. 12 (h)). Then, read data is output from the input / output terminal DQ in synchronization with the next clock signal CLK signal after receiving the read command RD (the rising edge of the clock signal CLK numbered “1” in the figure) (FIG. 12). (I)). The access time tRAC (/ RAS Access time from Clock) from when the ACTV command is supplied to when the read data is output is 17 ns.
[0011]
FIG. 13 shows an SDRAM read operation when the CAS latency is “2”. The frequency of the clock signal CLK is higher than that in FIG. In this example, the frequency of the clock signal CLK is 150 MHz (period = 6.7 ns).
The operations from the reception of the active command ACTV to the activation of the word line selection signal WL and the sense amplifier enable signals LEZ and LEX (FIGS. 13A to 13E) are the same as those in FIG. To do.
[0012]
The period T3 ′ in the figure is the period from the rising edge of the clock signal CLK to the activation of the column line selection signal CLZ when the read command RD is supplied in synchronization with the next clock signal CLK after the active command ACTV is received. Is shown. In this case, the rising timing of the column line selection signal CLZ is included in the period T2. For this reason, the read command RD must be supplied in synchronization with the second clock signal CLK (rising edge of the clock signal CLK numbered “0” in the figure) after receiving the active command ACTV (see FIG. 13 (f)).
[0013]
Upon receipt of the read command RD, the control circuit corresponding to the column address operates, and the column line selection signal CLZ is activated (high level) after a period T3 from the rising edge of the clock signal CLK (FIG. 13 (g)). The read data amplified on the bit lines BL and / BL is transmitted to the data buses DBZ and DBX as in FIG. 12 (FIG. 13 (h)). Then, after receiving the read command RD, read data is output from the input / output terminal DQ in synchronization with the next clock signal CLK signal (rising edge of the clock signal CLK numbered “1” in the figure) (FIG. 13). (I)). The access time tRAC at this time is 23 ns, which is longer than that in FIG.
[0014]
[Problems to be solved by the invention]
As described above, the conventional SDRAM has a problem that the access time tRAC becomes longer when the frequency of the clock signal CLK is higher. As a result, there is a problem that the higher the frequency of the clock signal CLK, the lower the data bus occupation ratio. The bus occupation ratio is a ratio at which valid data is transmitted on the data bus in the system in a predetermined period. If the bus occupancy is low, the performance of the entire system with SDRAM will be degraded.
[0015]
An object of the present invention is to shorten the access time of a semiconductor memory.
Another object of the present invention is to provide a semiconductor memory capable of improving the bus occupation ratio.
[0016]
[Means for Solving the Problems]
  The semiconductor memory of claim 1 comprises:Latency indicating the number of clock cycles from the supply of a column control command to the start of data input / outputHave a plurality of operation modes different from each other and includes a row control circuit, a column control circuit, and an input circuit. The row control circuit operates in response to the supply of the row control command and controls the word line. The column control circuit operates in response to the supply of the column control command and controls the bit line. The input circuit sequentially receives a row control command and the column control command. After the row control command is supplied (start of the memory operation), the time until the column control circuit operates is constant regardless of the operation mode. Further, the time until the column control circuit operates after receiving the command for operating the column control circuit can be changed according to the operation mode. Therefore, in a semiconductor memory in which the column control circuit starts to operate after the operation of the row control circuit starts, the column control circuit can be operated at an optimum timing according to the operation mode, and access to the memory cell is performed in each operation mode. Time can be minimized. As a result, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory.
[0017]
According to another aspect of the semiconductor memory of the present invention, the command for operating the column control circuit is at least one of a read command and a write command. A read operation is executed by supplying a read command, and a write operation is executed by supplying a write command. These commands are supplied in synchronization with the clock signal. The operation timing is changed, that is, the operation mode is switched by setting the latency to a predetermined value. Here, the latency is a value indicating the number of clock cycles from the supply of the read command or the write command to the start of data input / output. Therefore, the operation timing of the column control circuit can be set optimally according to the start timing (operation mode) of data input / output.
[0018]
According to another aspect of the semiconductor memory of the present invention, after the read operation and the write operation are completed, a precharge operation for setting the bit line to a predetermined voltage is performed. Then, after receiving the read command for executing the read operation or the write command for executing the write operation, the time until the precharge operation is started is changed according to the operation mode. For this reason, the precharge operation can be executed at an optimal timing according to the operation mode. As a result, the next memory operation can be started quickly, and the number of data inputs / outputs per unit time can be increased. That is, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory. In particular, when the present invention is applied to a semiconductor memory that automatically executes a precharge operation after completion of a read operation and a write operation, a remarkable effect can be obtained.
[0019]
According to another aspect of the present invention, there is provided a semiconductor memory having a precharge command for executing a precharge operation for setting a bit line to a predetermined voltage. The time until the precharge operation is started after receiving the precharge command can be changed according to the operation mode. For this reason, the precharge operation can be executed at an optimum timing according to the operation mode, and the bus occupancy rate of the system equipped with the semiconductor memory can be improved.
[0020]
  According to another aspect of the semiconductor memory of the present invention, the word line is deactivated in synchronization with the start of the precharge operation. For this reason, after stopping reading data to the bit line or after stopping writing data to the bit line, the precharge operation is performed at the optimum timing and the minimum time.You can start.
[0021]
  Claim 6In the semiconductor memory, after the read operation and the write operation are completed, a precharge operation for setting the bit line to a predetermined voltage is performed. And after receiving the row control command, the time until the precharge operation is started isMade constant.For this reason, the precharge operation can be executed at an optimal timing according to the operation mode. As a result, the next memory operation can be started quickly, and the number of data inputs / outputs per unit time can be increased. That is, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory.
[0022]
  Claim 7The semiconductor memory includes a timing adjustment circuit having a plurality of delay circuits. Then, by selecting a predetermined delay circuit, the time until the column control circuit operates after the command for operating the column control circuit is changed. Further, the timing adjustment circuit finely adjusts the delay time of the delay circuit according to the operation mode. For this reason, the characteristics of the delay circuit that varies due to fluctuations in the manufacturing conditions of the semiconductor memory can be adjusted after manufacturing.
[0023]
  Claim 8In this semiconductor memory, the delay time of the delay circuit is finely adjusted by blowing the fuse. For this reason, the delay time of the delay circuit can be set optimally according to each manufactured semiconductor memory. As a result, the operation timing of each operation mode can be optimized after the semiconductor memory is manufactured.
  Claim 9In the semiconductor memory, first, in the test process, the test circuit is operated, and the delay time of the delay circuit is finely adjusted. Thereafter, a predetermined fuse is blown based on the test result, and the delay time of the delay circuit is set. As a result, the operation timing of each operation mode can always be optimized without changing the photomask and the manufacturing process.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The signal lines indicated by bold lines in each drawing indicate that they are composed of a plurality of lines. A part of the block to which the thick line is connected is composed of a plurality of circuits.
  FIG. 1 shows a first embodiment of a semiconductor memory according to the present invention.Show.The same circuits / signals as those described in the prior art are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0025]
This semiconductor memory is formed as an FCRAM (Fast Cycle RAM) having an SDRAM interface on a silicon substrate using a CMOS process technology. In other words, this FCRAM receives the address signal AD separately into a row address and a column address (address multiplexing method), selects a word line corresponding to the row address, and performs a read operation corresponding to the column address. Or perform a write operation.
[0026]
The FCRAM has an input / output circuit 10, a control circuit 12, and a memory core 14 including a plurality of memory arrays. The input / output circuit 10 includes a clock buffer 16 and a command decoder 18. The clock buffer 16 amplifies a clock signal CLK supplied from the outside and outputs it as an internal clock signal ICLK. The command decoder 18 operates as an input circuit for a command signal CMD supplied from the outside. The command decoder 18 decodes the command signal CMD and outputs it as an internal command signal ICMD. The input / output circuit 10 receives the clock signal CLK, the command signal CMD, and the address signal AD, and outputs the internal clock signal ICLK, the internal command signal ICMD, and the internal address signal IAD to the control circuit 12, and the data input / output signal DQ and the internal data I / O signal IDQ is being input / output. The symbol DQ is also used as the name of the data input / output terminal.
[0027]
The control circuit 12 includes a mode register 20, a CLZ generation circuit 22, and a column decoder 24. The CLZ generation circuit 22 and the column decoder 24 operate as a column control circuit that controls the bit lines BL and / BL in response to supply of a read command RD, a write command WR, and the like (column control command). The control circuit 12 operates as a row control circuit that controls a word line in response to the supply of an active command ACTV or the like (row control command) other than those illustrated. The control circuit 12 receives an internal clock signal ICLK, an internal command signal ICMD, and an internal address signal IAD (row address or column address), and receives a word line selection signal WL, sense amplifier enable signals LEZ and LEX, a precharge signal PRE, and a column line. The selection signal CLZ is output, and the internal data input / output signal IDQ and the data signals DBZ, DBX are input / output. The symbols DBZ and DBX are also used as data bus names.
[0028]
The mode register 20 has a function of holding CAS latency set from the outside. The mode register 20 activates the latency signal CL1 when the CAS latency is set to “1”, and activates the latency signal CL2 when the CAS latency is set to “2”.
The CLZ generation circuit 22 receives the internal command signal ICMD and the latency signals CL1 and CL2 and outputs a timing signal CLZ0. The column decoder 24 receives the timing signal CLZ0 and the internal address signal IAD (column address) and activates a predetermined column line selection signal CLZ.
[0029]
The memory core 14 includes a memory cell MC, a sense amplifier 2, a precharge circuit 4, and a column switch 6. The configurations of the sense amplifier 2, the precharge circuit 4, the column switch 6, and the bit lines BL, / BL are the same as those in FIG. Memory cell MC includes a capacitor that holds data and a transfer MOS that transmits data to the capacitor. One end of the capacitor is connected to the bit line BL (or / BL), and the other end is connected to the plate electrode. The gate of the transfer MOS is connected to a word line that transmits a word line selection signal WL.
[0030]
FIG. 2 shows details of the CLZ generation circuit 22.
The CLZ generation circuit 22 is configured by arranging switch circuits SW1, SW2, and SW3 between delay circuits 22a and 22b and a pulse generation circuit 22c connected in series. The delay circuit 22a receives the internal command signal ICMD (read command RD or write command WR) and outputs the received signal with a predetermined delay. The delay circuit 22b receives the signal from the delay circuit 22a via the switch circuit SW2, and outputs the received signal with a predetermined time delay. The pulse generation circuit 22c receives signals from the delay circuit 22a or the delay circuit 22b via the switch circuits SW1 and SW3, respectively, and generates a timing signal CLZ0 having different activation timings.
[0031]
The switch circuit SW1 is turned on when the latency signal CL1 output from the mode register 20 is activated. The switch circuits SW2 and SW3 are turned on when the latency signal CL2 output from the mode register 20 is activated. Therefore, when the CAS latency is set to “1”, the timing signal CLZ0 is generated depending on the delay time of only the delay circuit 22a. When the CAS latency is set to “2”, the timing signal CLZ0 is generated depending on the delay times of both delay circuits 22a and 22b. That is, the CLZ generation circuit 22 operates as a timing adjustment circuit that changes the generation timing of the timing signal CLZ0 (column selection line signal CLZ). The time from when the read command RD or the write command WR is supplied until the timing signal CLZ0 is activated is variable, and becomes longer as the CAS latency is larger. The delay time of the delay circuit 22b is the same as the period DIF in FIG.
[0032]
Next, the above-described SDRAM read operation will be described.
Note that the read operation when the CAS latency is “1” is the same as that in FIG. At this time, the access time tRAC is 17 ns.
FIG. 3 shows the SDRAM read operation when the CAS latency is “2”. The frequency of the clock signal CLK is set to 150 MHz (period = 6.7 ns), which is the same as in FIG. 13 (conventional).
[0033]
The operations from the acceptance of the active command ACTV to the activation of the word line selection signal WL and the sense amplifier enable signals LEZ and LEX (FIGS. 3A to 3E) are the same as those in FIG. Is omitted.
After receiving the active command ACTV, a command signal CMD indicating a read command RD and an address signal AD (column address) (not shown) are supplied in synchronization with the next clock signal CLK (FIG. 3 (f)). That is, even when the frequency of the clock signal CLK is high, the read command RD can be supplied in synchronization with the next clock signal CLK after receiving the active command ACTV. Upon receipt of the read command RD, the control circuit corresponding to the column address operates. Here, when the CAS latency is “2”, the CLZ generation circuit 22 shown in FIG. 2 activates the timing signal CLZ0 using the delay circuits 22a and 22b. Therefore, the column line selection signal CLZ is activated after a period T4 from the rising edge of the clock signal CLK that has received the read command RD (FIG. 3 (g)). The difference between the period T4 and the period T3 corresponds to the delay time of the delay circuit 22b. In the period T4, the column line selection signal CLZ is set to be activated after the period T2. Therefore, the read data sufficiently amplified by the sense amplifier 2 is transmitted to the data buses DBZ and DBX via the column switch 6 (FIG. 3 (h)). Then, after receiving the read command RD, read data is output from the input / output terminal DQ in synchronization with the next clock signal CLK signal (rising edge of the clock signal CLK numbered “1” in the figure) (FIG. 3). (I)). The access time tRAC at this time is 17 ns, which is the same as when the frequency of the clock signal CLK is 100 MHz, and is shortened by 6 ns compared to the conventional case (FIG. 13). Since the access time tRAC is shortened, the bus occupancy rate of the system equipped with FCRAM is improved.
[0034]
FIG. 4 shows the relationship between the period T3 and the period T4.
In the figure, a period DIF indicates a difference in the period of the clock signal CLK when the frequency is 100 MHz and 150 MHz. Then, the period T4 when the frequency of the clock signal CLK is high is a period T3 + period DIF. Therefore, the period from acceptance of the ACTV command to activation of the column line selection signal CLZ is always constant regardless of the frequency of the clock signal CLK. Therefore, the column line selection signal CLZ is always activated after the period T2 without depending on the frequency of the clock signal CLK, and the activation timing is the same.
[0035]
  As described above, in the FCRAM according to the present embodiment, the column selection signal CLZ can be activated at an optimum timing according to the set latency, and the access time tRAC can be minimized. As a result, the bus occupancy rate of the system equipped with FCRAM can be improved.
  FIG. 5 shows the details of the main part in the second embodiment of the semiconductor memory of the present invention.Show.The same circuits and signals as those described in the prior art and the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0036]
In this embodiment, fuse circuits 26a and 26b for finely adjusting the delay times of the delay circuits 22a and 22b of the CLZ generation circuit 22 are formed. The configuration other than the fuse circuits 26a and 26b is the same as that of the first embodiment.
The fuse circuits 26a and 26b have a plurality of fuses (not shown) made of polysilicon or the like. The fuse circuit 26a (or 26b) activates one of the plurality of fuse signals FUSa (or FUSb) in response to the blow of these fuses. The delay times of the delay circuits 22a and 22b are finely adjusted according to the activated fuse signals FUSa and FUSb, respectively. That is, the delay circuits 22a and 22b operate as variable delay circuits with programmable delay times. Then, the fuse is blown so that the column line selection signal CLZ shown in FIG. 1 is activated at an optimal timing according to the operating frequency.
[0037]
Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, in this embodiment, by fusing the fuse, the characteristics of the delay circuits 22a and 22b, which vary due to variations in manufacturing conditions, can be adjusted after manufacturing. Variations in the characteristics of the delay circuits 22a and 22b occur depending on manufacturing conditions, chip positions on the wafer, and wafer positions in the manufacturing lot. As a result, it is possible to always generate the column line selection signal CLZ with the optimum timing without changing the photomask and the manufacturing process.
[0038]
  FIG. 6 shows the main part of the third embodiment of the semiconductor memory of the present invention.Show.The same circuits and signals as those described in the prior art and the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  In this embodiment, a test circuit 28 is further added to the configuration shown in FIG.
[0039]
For example, the test circuit 28 receives a test signal TEST activated at the time of the probe test, and activates one of the plurality of activation signals ACTa and one of the activation signals ACTb. The activation signals ACTa and ACTb are signals corresponding to the fuse signals FUSa and FUSb, respectively. By operating the test circuit 28, the delay times of the delay circuits 22a and 22b can be finely adjusted without blowing the fuse. That is, the delay times of the delay circuits 22a and 22b are finely adjusted according to the fuse signals FUSa and FUSb or the activation signals ACTa and ACTb, respectively.
[0040]
In this embodiment, first, after manufacturing the FCRAM, an operation test (probe test) is performed in a wafer state in which a plurality of FCRAMs are connected. At this time, by sequentially activating the activation signals ACTa and ACTb and executing an operation test, the timing of the column line selection signal CLZ at which the FCRAM operates optimally becomes clear. Thereafter, as in the fourth embodiment, the fuses corresponding to the optimum activation signals ACTa and ACTb are blown. The FCRAM is assembled in a package state and shipped after the final operation test is executed.
[0041]
Also in this embodiment, the same effects as those of the first and second embodiments described above can be obtained. Further, in this embodiment, the fuse is blown based on the result of the characteristic evaluation of FCRAM. For this reason, the characteristics of the delay circuits 22a and 22b, which vary due to variations in manufacturing conditions, etc., can be adjusted in a test process after manufacturing. As a result, it is possible to always generate the column line selection signal CLZ with the optimum timing without changing the photomask and the manufacturing process.
[0042]
  FIG. 7 shows the main part of the fourth embodiment of the semiconductor memory of the present invention.Show.The same circuits and signals as those described in the prior art and the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  This embodiment is characterized by a RASZ generation circuit 30 that generates a row control signal RASZ, which is a basic signal for operating a control circuit corresponding to a row address. The configuration other than the RASZ generation circuit 30 is the same as that of the first embodiment.
[0043]
The RASZ generation circuit 30 is configured by arranging switch circuits SW4, SW5, and SW6 between delay circuits 30a and 30b and a pulse generation circuit 30c connected in series. The arrangement / connection relationship of the delay circuits 30a, 30b and the switch circuits SW4, SW5, SW6 is the same as that of the delay circuits 22a, 22b and the switch circuits SW1, SW2, SW3 shown in FIG. The delay circuit 30a receives an internal command signal ICMD (read command RD or write command WR), and outputs the received signal with a predetermined delay. The delay circuit 30b receives the signal from the delay circuit 30a via the switch circuit SW5, and outputs the received signal with a predetermined time delay. The pulse generation circuit 30c receives the internal command signal (active command ACTV), activates the row control signal RASZ, receives signals from the delay circuit 30a or the delay circuit 30b via the switch circuits SW4 and SW6, respectively, The row control signal RASZ is deactivated at the timing. Row control signal RASZ is used to generate word line selection signal WL and precharge signal PRE.
[0044]
Next, the read operation of the FCRAM of this embodiment will be described.
FIG. 8 shows the FCRAM read operation when the CAS latency is “1”. In this example, the frequency of the clock signal CLK is 100 MHz (period = 10 ns).
The operations from the reception of the active command ACTV to the activation of the word line selection signal WL and the sense amplifier enable signals LEZ and LEX (FIGS. 8A to 8E) are the same as those in FIG. To do. The activation of the word line selection signal WL and the deactivation (reset) of the precharge signal PRE are performed in response to the row control signal RASZ (FIG. 7).
[0045]
After receiving the active command ACTV, a command signal CMD indicating a read command RDA and an address signal AD (column address) (not shown) are supplied in synchronization with the next clock signal CLK (FIG. 8 (f)). The read command RDA is a command for automatically executing a precharge operation after the read operation (auto precharge command). Upon receipt of the read command RDA, the control circuit corresponding to the column address operates, and the column line selection signal CLZ is activated (high level) (FIG. 8 (g)). As the column line selection signal CLZ is activated, the read data amplified on the bit lines BL and / BL is transmitted to the data buses DBZ and DBX (FIG. 8 (h)). Then, the read data is output from the input / output terminal DQ in synchronization with the clock signal CLK signal (the rising edge of the clock signal CLK numbered “1” in the figure) next to the reception of the read command RD (FIG. 8 ( i)).
[0046]
  Thereafter, in response to the inactivation of the row control signal RASZ (not shown), the word line selection signal WL is inactivated and the precharge signal PRE is activated (set) (FIG. 8 (j, k)). ). Precharge signal PREactivationIs performed after the elapse of the period T5 from the deactivation of the column line selection signal CLZ. Note that the RASZ inactivation timing is generated depending on the delay time of only the delay circuit 30a shown in FIG. Activation of the precharge signal PRE equalizes the bit lines BL and / BL (FIG. 8 (l)).
[0047]
FIG. 9 shows the read operation of the FCRAM when the CAS latency is “2”. In this example, the frequency of the clock signal CLK is 150 MHz (period = 6.7 ns).
The operations from the reception of the active command ACTV to the activation of the word line selection signal WL and the sense amplifier enable signals LEZ and LEX (FIGS. 9A to 9E) are the same as those in FIG. To do. The activation of the word line selection signal WL and the deactivation (reset) of the precharge signal PRE are performed in response to the row control signal RASZ (FIG. 7).
[0048]
After receiving the active command ACTV, a command signal CMD indicating a read command RDA and an address signal AD (column address) (not shown) are supplied in synchronization with the next clock signal CLK (FIG. 9 (f)). When the read command RDA is received, the control circuit corresponding to the column address operates as in FIG. 3, and the column line selection signal CLZ is activated after a period T4 from the rising edge of the clock signal CLK that has received the read command RDA. (FIG. 9 (g)). By activation of the column line selection signal CLZ, read data amplified on the bit lines BL and / BL is transmitted to the data buses DBZ and DBX (FIG. 9 (h)). Then, read data is output from the input / output terminal DQ in synchronization with the next clock signal CLK signal (the rising edge of the clock signal numbered “1” in the figure) after acceptance of the read command RD (FIG. 9 ( i)).
[0049]
  Thereafter, in response to the deactivation of the row control signal RASZ (not shown), the word line selection signal WL is deactivated and the precharge signal PRE is activated (set) (FIG. 9 (j, k)). ). Note that the deactivation timing of the row control signal RASZ is generated depending on the delay times of both delay circuits 30a and 30b shown in FIG. And the precharge signal PREactivationAs in FIG. 8, this is performed after the elapse of the period T5 from the deactivation of the column line selection signal CLZ. The generation timing of the column line selection signal CLZ is the same regardless of the frequency of the clock signal CLK, as in the first embodiment. Therefore, the deactivation timing of the word line selection signal WL and the column line selection signal CLZ is always the same regardless of the frequency of the clock signal CLK. Thereafter, the activation of the precharge signal PRE equalizes the bit lines BL and / BL (FIG. 9 (l)).
[0050]
The rising timing of the precharge signal PRE when the deactivation timing of the row control signal RASZ is the same as that in FIG. 8 is indicated by a broken line. The bit lines BL and / BL are equalized by deactivation of the precharge signal PRE. Therefore, if the present invention is not applied, the decharge signal PRE may be deactivated before the column line selection signal CLZ is deactivated, and erroneous read data may be transmitted to the data buses DBZ and DBX. There is. That is, it causes a malfunction.
[0051]
  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, in this embodiment, the precharge signal PRE is not dependent on the frequency of the clock signal CLK, and is always in synchronization with the deactivation timing of the column line selection signal CLZ.activationdid. For this reason, it is possible to prevent erroneous data from being read.
  FIG. 10 shows a fifth embodiment of the semiconductor memory of the present invention.Show.The same circuits and signals as those described in the prior art and the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0052]
In this embodiment, the RASZ generation circuit 32 is different from the RASZ generation circuit 30 of the fourth embodiment described above.
The RASZ generation circuit 32 is configured by removing the delay circuits 30a and 30b and the switch circuits SW4, SW5, and SW6 from the RASZ generation circuit 30 shown in FIG. The pulse generation circuit 30c receives a signal obtained by inverting the timing signal CLZ0 by the inverter 32a and an internal command signal (active command ACTV), and generates a row control signal RASZ. The row control signal RASZ is activated based on the activation of the active command ACTV, and deactivated based on the deactivation of the timing signal CLZ0. That is, in this embodiment, the deactivation timing of the row control signal RASZ is generated using the CLZ generation circuit 22.
[0053]
Also in this embodiment, the same effects as those in the first and fourth embodiments described above can be obtained. Furthermore, in this embodiment, since the row control signal RASZ is deactivated by using the CLZ generation circuit 22, the configuration of the RASZ generation circuit 32 can be simplified.
In the above-described embodiment, the example in which the present invention is applied to the FCRAM has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to SDRAM or a DRAM core of a system LSI.
[0054]
In the above-described embodiment, the example in which the generation timing of the column line selection signal CLZ is changed according to the operation frequency during the read operation has been described. However, the present invention is not limited to such an embodiment. For example, the generation timing of the column line selection signal CLZ may be changed during the write operation.
For example, during the write operation, the generation timing of the column line selection signal CLZ may be changed according to the operating frequency. In this case, the column line selection signal CLZ can be deactivated after the write data is sufficiently transmitted to the bit lines BL and / BL without delaying the supply timing of the write command WR. Therefore, write data having a sufficient signal amount can be written in the memory cell.
[0055]
  In addition, in the write command WRA that automatically executes the precharge operation after the write operation, the column line selection signal CLZ and the precharge signal PRE are changed according to the operation frequency.activationThe timing may be changed. In this case, the precharge signal PRE is always applied after the column line selection signal CLZ is deactivated according to the CAS latency.activationit can. Therefore, erroneous data can be prevented from being written into the memory cell MC.
[0056]
In the above-described fourth embodiment, the example in which the present invention is applied during the auto precharge operation has been described. However, the present invention is not limited to such an embodiment. For example, the present invention may be applied to a precharge operation based on a precharge command supplied from the outside (corresponding to claim 4).
Further, by applying the fuse circuits 26a and 26b of the second embodiment to the fourth embodiment (or the fifth embodiment), the delay circuits 22a, 22b, 30a and 30b (or the delay circuits 22a and 22b) are applied. Fine adjustments may be made. At that time, the test circuit 28 of the third embodiment may be added.
[0057]
As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.
The invention described in the above embodiments is organized and disclosed as an appendix.
(Supplementary note 1) Having multiple operation modes with different operation timings,
A row control circuit for controlling a word line; a column control circuit for controlling a bit line; and an input circuit for sequentially receiving a plurality of commands.
2. The semiconductor memory according to claim 1, wherein a time until the column control circuit operates after receiving the command for operating the column control circuit varies depending on the operation mode.
[0058]
(Appendix 2) In the semiconductor memory described in Appendix 1,
The command for operating the column control circuit is at least one of a read command for executing a read operation and a write command for executing a write operation, and the command is supplied in synchronization with a clock signal,
2. The semiconductor memory according to claim 1, wherein the operation mode is switched according to a latency setting indicating a clock cycle number from the supply of the read command or the write command to the start of data input / output.
[0059]
(Appendix 3) In the semiconductor memory described in Appendix 2,
The semiconductor memory according to claim 1, wherein the time until the column control circuit operates is longer as the latency is larger.
(Appendix 4) In the semiconductor memory described in Appendix 1,
After completion of the read operation and the write operation, a precharge operation for setting the bit line to a predetermined voltage is performed,
The semiconductor memory according to claim 1, wherein a time until the precharge operation is started after receiving a read command for executing the read operation and a write command for executing the write operation is different according to the operation mode.
[0060]
(Appendix 5) In the semiconductor memory described in Appendix 1,
The command includes a precharge command for executing a precharge operation for setting the bit line to a predetermined voltage,
The semiconductor memory according to claim 1, wherein the time from when the precharge command is received until the precharge operation is started varies depending on the operation mode.
[0061]
(Appendix 6)Appendix 4OrAppendix 5In the described semiconductor memory,
  The semiconductor memory according to claim 1, wherein the word line is deactivated in synchronization with the start of the precharge operation.
(Appendix 7) Having multiple operation modes with different operation timings,
  A row control circuit that operates in response to supply of a row control command and controls a word line; a column control circuit that operates in response to supply of a column control command and controls a bit line;Line controlCommand and aboveColumn controlAn input circuit for receiving commands sequentially,
  SaidLine controlA semiconductor memory characterized in that the time from when a command is supplied until the column control circuit operates is constant regardless of the operation mode.
[0062]
(Appendix 8) In the semiconductor memory described in Appendix 7,
After completion of the read operation and the write operation, a precharge operation for setting the bit line to a predetermined voltage is performed,
2. A semiconductor memory according to claim 1, wherein a time until the precharge operation is started after the supply of the row command is constant regardless of an operation mode.
[0063]
(Appendix 9) In the semiconductor memory according to Appendix 1 or Appendix 7,
A timing adjustment circuit having a plurality of delay circuits, selecting a predetermined delay circuit according to the operation mode, and changing the time;
A semiconductor memory characterized in that the delay time of the delay circuit can be finely adjusted.
(Supplementary note 10) In the semiconductor memory according to supplementary note 9,
A semiconductor memory comprising a fuse for finely adjusting a delay time of the delay circuit.
[0064]
(Supplementary note 11) In the semiconductor memory according to supplementary note 10,
A semiconductor memory comprising a test circuit for finely adjusting a delay time of the delay circuit.
In the semiconductor memory of appendix 3, the time until the column control circuit operates after receiving the supply of the read command or the write command is increased as the latency is increased. Therefore, the operation timing of the column control circuit can be optimally set according to the set latency.
[0065]
【The invention's effect】
In the semiconductor memory of the first aspect, the access time to the memory cell can be minimized in each operation mode. As a result, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory.
In the semiconductor memory according to the second aspect, the operation timing of the column control circuit can be optimally set according to the start timing (latency) of data input / output.
[0066]
In the semiconductor memory according to the third and fourth aspects, the precharge operation can be executed at an optimum timing according to the operation mode. As a result, the next memory operation can be started quickly, and the number of data inputs / outputs per unit time can be increased. That is, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory.
[0067]
  According to another aspect of the semiconductor memory of the present invention, after stopping reading data to the bit line or stopping writing data to the bit line, the precharge operation is performed at an optimal timing and at a minimum time.You can start.
[0068]
  Claim 6In this semiconductor memory, the precharge operation can be executed at an optimal timing according to the operation mode. As a result, the next memory operation can be started quickly, and the number of data inputs / outputs per unit time can be increased. That is, it is possible to improve the bus occupancy rate of a system equipped with a semiconductor memory.
  Claim 7In this semiconductor memory, the characteristics of the delay circuit, which varies due to variations in the manufacturing conditions of the semiconductor memory, can be adjusted after manufacturing.
[0069]
  Claim 8In this semiconductor memory, the delay time of the delay circuit can be set optimally according to each manufactured semiconductor memory. As a result, the operation timing of each operation mode can be optimized after the semiconductor memory is manufactured.
  Claim 9In this semiconductor memory, the operation timing of each operation mode can always be optimized without changing the photomask and the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory of the present invention.
FIG. 2 is a block diagram showing details of the CLZ generation circuit of FIG. 1;
FIG. 3 is a timing chart showing a read operation in the first embodiment.
FIG. 4 is a timing chart showing a relationship between periods T3 and T4.
FIG. 5 is a block diagram showing a main part of a second embodiment of a semiconductor memory of the present invention.
FIG. 6 is a block diagram showing a main part of a third embodiment of the semiconductor memory of the present invention.
FIG. 7 is a block diagram showing a main part of a fourth embodiment of the semiconductor memory of the present invention.
FIG. 8 is a timing chart showing a read operation and a precharge operation in the fourth embodiment.
FIG. 9 is a timing chart showing a read operation and a precharge operation in the fourth embodiment.
FIG. 10 is a block diagram showing main parts of a semiconductor memory according to a fifth embodiment of the present invention.
FIG. 11 is a circuit diagram illustrating a conventional SDRAM sense amplifier and its periphery.
FIG. 12 is a timing chart showing a conventional SDRAM read operation.
FIG. 13 is a timing chart showing a conventional SDRAM read operation.
[Explanation of symbols]
2 sense amplifiers
4 Precharge circuit
6 Column switch
10 I / O circuit
12 Control circuit
14 Memory core
16 clock buffers
18 Command decoder
20 Mode register
22 CLZ generator
22a, 22b delay circuit
22c Pulse generation circuit
24 column decoder
26a, 26b Fuse circuit
28 Test circuit
30 RASZ generation circuit
30a, 30b delay circuit
30c pulse generation circuit
32 RASZ generator
32a inverter
ACTa, ACTb activation signal
AD address signal
BL, / BL bit line
CL1, CL2 latency signal
CLK clock signal
CLZ Column line selection signal
CLZ0 timing signal
CMD command signal
DBZ, DBX data signal
DQ data input / output signal
FUSa, FUSb Fuse signal
IAD internal address signal
ICLK Internal clock signal
ICMD internal command signal
IDQ internal data input / output signal
LEZ, LEX Sense amplifier enable signal
MC memory cell
PRE Precharge signal
RD read command
SW1, SW2, SW3 Switch circuit
SW4, SW5, SW6 Switch circuit
WL Word line selection signal
WR write command

Claims (9)

A plurality of operation modes having different latencies indicating the number of clock cycles from the supply of the column control command to the start of data input / output ,
A row control circuit for controlling the operation and the word lines in response to the supply line control command, a column control circuit for controlling the operation and the bit lines in response to the supply of the column control command, the line control command and the column control commands And an input circuit for sequentially receiving
After receiving the supply of the line control command, time to the column control circuit is operated is constant regardless of the said operating mode, after receiving the train control command for operating the column control circuit, wherein A semiconductor memory characterized in that the time until the column control circuit operates varies depending on the operation mode. The semiconductor memory according to claim 1.
The column control command for operating the column control circuit is at least one of a read command for executing a read operation and a write command for executing a write operation, and the command is supplied in synchronization with a clock signal,
The semiconductor memory according to claim 1, wherein the operation mode is switched according to the setting of the latency . The semiconductor memory according to claim 1.
After completion of the read operation or the write operation, a precharge operation for setting the bit line to a predetermined voltage is performed,
2. A semiconductor memory according to claim 1, wherein a time until the precharge operation is started after receiving a read command for executing the read operation or a write command for executing the write operation differs according to the operation mode. The semiconductor memory according to claim 1.
The command includes a precharge command for executing a precharge operation for setting the bit line to a predetermined voltage,
The semiconductor memory according to claim 1, wherein the time from when the precharge command is received until the precharge operation is started varies depending on the operation mode. The semiconductor memory according to claim 3 or 4 ,
The semiconductor memory according to claim 1, wherein the word line is deactivated in synchronization with the start of the precharge operation. The semiconductor memory according to claim 1.
After completion of the read operation or the write operation, a precharge operation for setting the bit line to a predetermined voltage is performed,
2. A semiconductor memory according to claim 1, wherein the time from when the row control command is supplied to when the precharge operation is started is constant regardless of the operation mode. The semiconductor memory according to claim 1.
A timing adjustment circuit having a plurality of delay circuits, selecting a predetermined delay circuit according to the operation mode, and changing the time;
A semiconductor memory characterized in that the delay time of the delay circuit can be finely adjusted . The semiconductor memory according to claim 7.
A semiconductor memory comprising a fuse for finely adjusting a delay time of the delay circuit . The semiconductor memory according to claim 8.
A semiconductor memory comprising a test circuit for finely adjusting a delay time of the delay circuit .

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