JP4014473B2 - Method for manufacturing ultra-flat p-type oxide semiconductor NiO single crystal thin film - Google Patents
Method for manufacturing ultra-flat p-type oxide semiconductor NiO single crystal thin film Download PDFInfo
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- JP4014473B2 JP4014473B2 JP2002254050A JP2002254050A JP4014473B2 JP 4014473 B2 JP4014473 B2 JP 4014473B2 JP 2002254050 A JP2002254050 A JP 2002254050A JP 2002254050 A JP2002254050 A JP 2002254050A JP 4014473 B2 JP4014473 B2 JP 4014473B2
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Description
【0001】
【発明の属する技術分野】
本発明は、有機ELディスプレイ等の表示デバイス等のホール注入電極や、発光ダイオード(LED)、レーザーダイオード(LD)、紫外線検出器のp型層として使用できるp型酸化物半導体NiO単結晶薄膜の製造方法に関する。
【0002】
【従来の技術】
NiOは反強磁性金属単結晶基板として磁気素子(特開平10−36956号公報)や高密度磁気記録媒体用の配向性下地膜(特開平7−97296号公報、特開平9−125233号公報)として用いられることが知られている。また、発光ダイオードやレーザーダイオード(LD)などの透光性接触部として用いることが知られている(特開平2001−7398号公報)。
【0003】
【発明が解決しようとする課題】
NiOはp型酸化物半導体の一つであり、例えば、n型酸化物半導体ZnOと組み合わせたヘテロ接合LEDが提案されているが、従来のNiO薄膜は、多結晶体の集合体であり、表面の凹凸が大きい。そのため、例えば、NiO多結晶薄膜上にZnO薄膜を成長させても、ZnOの結晶性が悪くなり、ヘテロ接合を製造することができないという問題があった。
【0004】
【課題を解決するための手段】
本発明は、p型酸化物半導体NiO単結晶薄膜、特に表面が原子オーダーで平坦なp型酸化物半導体NiO単結晶薄膜の製造方法を提供する。
【0005】
すなわち、本発明は以下のものである。
【0006】
(1)基板温度を100℃以下に保持し、気相成長法により、耐熱性単結晶基板上に多結晶p型酸化物NiO薄膜を成膜し、次いで、600〜1500℃でアニールして単結晶とすることを特徴とするp型酸化物半導体NiO単結晶薄膜の製造方法。
(2)気相成長法におけるターゲットとしてLiを含有するNiO焼結体を用いることを特徴とする上記(1)記載のp型酸化物半導体NiO単結晶薄膜の製造方法。
(3)耐熱性単結晶基板としてYSZ(イットリア安定化ジルコニア)を用いることを特徴とする上記(1)記載のp型酸化物半導体NiO単結晶薄膜の製造方法。
(4)p型酸化物半導体NiO単結晶薄膜が原子レベルで平坦なテラスとサブナノメータ(nm)のステップから構成されていることを特徴とする上記(1)記載のp型酸化物半導体NiO単結晶薄膜の製造方法。
(5)p型酸化物半導体NiO単結晶薄膜がアクセプターとしてLiを30at%以下含有することを特徴とする上記(1)記載のp型酸化物半導体NiO単結晶薄膜の製造方法。
(6)p型酸化物半導体NiO単結晶薄膜の室温の導電率が10 −4 S/cm以上であることを特徴とする上記(1)記載のp型酸化物半導体NiO単結晶薄膜の製造方法。
【0007】
本発明の製造方法で得られる超平坦p型酸化物半導体NiO単結晶薄膜は、薄膜表面が原子オーダーで平坦であるので、例えば、LEDまたはLD用の結晶材料を結晶性良く堆積させることができ、自らがホール注入電極の役割をする。
【0008】
【発明の実施の形態】
本発明の製造方法において、p型酸化物半導体NiO単結晶薄膜の基板には、耐熱性単結晶である、酸化物単結晶基板、Si基板、SiC基板、CaF2基板などを用いる。酸化物単結晶基板には、例えば、YSZ(イットリア安定化ジルコニア)、サファイア、MgO、ZnOなどがある。これらの基板の表面平均二乗粗さRmsは、1.0 nm以下のものを用いることが好ましい。Rmsは原子間力顕微鏡で、例えば、1μm角を走査することによって算出できる。
【0009】
基板の表面は、通常、その製造工程における光学研磨による研磨痕があり、結晶そのものにもダメージが入っている。このような基板を大気中もしくは真空中で1000℃以上に加熱することによって表面拡散を起こさせ超平坦化した表面が得られる。超平坦化した酸化物単結晶基板の表面には結晶構造を反映した構造が現れる。すなわち、数100nm程度の幅を持つテラスとサブナノメータ(nm)程度の高さを持つステップからなる構造で、一般に原子状に平坦化された構造と呼ばれる。
【0010】
テラス部分は平面状に配列した原子からなり、若干存在する欠陥の存在を無視すれば、完全に平坦化された表面である。ステップの存在により、試料全体で完全平坦化された表面とはならない。この構造を平均二乗粗さ測定方法による粗さRmsで表現すれば、Rmsは1.0nm以下のものである。Rmsは、例えば、原子間力顕微鏡で、例えば、1μm角の範囲を走査することによって算出した値である。
【0011】
Si基板、SiC基板も酸化物単結晶基板と同様な加熱処理や化学的エッチングを用いて表面Rmsが1.0nm以下のものを用いなければならない。Rmsが大きい、表面の荒れた基板上には、超平坦p型酸化物半導体NiO単結晶薄膜を形成することができない。
【0012】
これらの超平坦化基板の上にp型酸化物半導体NiO単結晶薄膜を成膜する。成膜方法には、パルス・レーザー蒸着法、スパッタリング法、CVD法、MO−CVD法、MBE法などを用いることができる。成膜上、最も重要なパラメーターは基板温度である。成膜時の基板温度は100℃以下でなければならない。100℃を超える場合には、p型酸化物半導体NiO薄膜の組成ずれや粒成長が起こりやすくなり平坦化が阻害される。真空チャンバー内から薄膜を取り出す際に結露が生じるため、下限温度は0℃である。成膜時の基板温度はより好ましくは10〜50℃である。
【0013】
これにより、表面が原子オーダーで平坦なp型酸化物半導体NiO薄膜が得られる。原子オーダーで平坦という概念は、単結晶基板を用いる場合には、表面が原子レベルで平坦なテラスと分子層ステップから構成されていることを言い、厳密にいうと表面粗さでは定義できないが、平均二乗粗さ測定方法による粗さが1nm以下、より好ましくは、0.5nm以下である。
【0014】
基板温度が100℃以下で成膜したp型酸化物半導体NiO薄膜は三次元的に堆積された粒子が観察されるのみで、原子レベルで平坦なテラスと分子層ステップの構造は見られないが、これを高温でアニールしてp型酸化物半導体NiO単結晶薄膜を製造する。アニール温度は600℃〜1500℃が好ましい。600℃未満では原子が十分に薄膜表面でマイグレーションすることができず、p型酸化物半導体NiO単結晶薄膜は得られない。また1500℃を超える高温ではほとんどの基板材料と該NiO薄膜の化学反応が起こるために好ましくない。
【0015】
当該NiO単結晶薄膜の導電率はアクセプターであるLiの濃度を変化させることにより制御することができる。例えば、Liを全く加えない場合には10−4S/cmの導電率を示すが、Liを10at%ドーピングすることにより、導電率は0.3S/cmになる。ドーピングは、焼結体ターゲット中のLi濃度を変化させることにより制御できる。アクセプターとしてのLi濃度は30at%以下でなくてはならない。30at%を越えるLiをドーピングするとNiOではない化合物であるLiNiO2に変化してしまうからである。
【0016】
また、600℃以上でアニールする場合、NiO薄膜中に添加したLiイオンなどが蒸発しやすい。こうしたLiイオンの蒸発を防ぐためには、NiO薄膜表面を、YSZ単結晶基板などで覆うことが好ましい。アニール中の雰囲気は大気または酸素ガスが好ましい。真空中や不活性ガス中ではLiイオンの蒸発が起こりやすいためである。
【0017】
【実施例】
以下、実施例により、本発明を説明する。
(実施例1)
YSZ単結晶基板(111)面(明浄金属(株)社製、10mm角)を大気中1350℃に加熱して、原子状平坦面を作製した。レーザー・アブレーション用超高真空容器(入江工研(株)社製)に、このYSZ単結晶基板を設置して温度を室温に保持した。容器中に3×10−3 Paの酸素ガスを導入し、KrFエキシマーレーザー光(ラムダ・フィジクス(株)社製レーザー発光装置)を10at% Liを含有するNiO焼結体ターゲットに照射、ターゲットから30mm離して対向させた基板上にNiO:Li薄膜を堆積させた。膜厚は300nmとした。次に、作製したNiO:Li薄膜を真空容器から取り出し、アニール中のLi成分の蒸発を防ぐため当該薄膜上にYSZ単結晶板を乗せて薄膜表面を覆い、大気中、1300℃で30分間アニールした後、室温まで冷却した。
【0018】
アニール後の薄膜の光電子分光により測定したLi含有量は単位体積当たり原子数で1×1020cm−3であった。X線回折装置(理学電機製:ATX−G)により、試料の回折パターンを測定した。図1にXRDパターンを示す。YSZ (111)基板上にNiO (111)が強く配向して成長していることが分かる。またNiO (111)回折ピーク周辺に見られる小さな回折ピークはペンデル縞と呼ばれる等厚干渉縞であり、薄膜表面が原子レベルで平坦であることを示している。
【0019】
4端子法により測定した導電率は0.3S/cmであり、室温におけるゼーベック係数(Seebeck係数)は+0.6mV/Kであった。p型酸化物半導体と言える。図2に、得られた薄膜表面の原子間力顕微鏡像を示す。原子レベルで平坦なテラスとステップからなる超平坦構造が観察された。原子間力顕微鏡を用いて1μm角の範囲を走査して求めた表面の平均二乗粗さRms値は1nmであった。
【図面の簡単な説明】
【図1】図1は、実施例1で製造したNiO単結晶薄膜のXRDパターンを示すグラフである。
【図2】図2は、実施例1で製造したNiO単結晶薄膜の微細表面構造を示す原子間力顕微鏡像により示す図面代用写真である。[0001]
BACKGROUND OF THE INVENTION
The invention, and the hole injection electrode of the display device such as organic EL display, a light emitting diode (LED), a laser diode (LD), p-type oxide semiconductor NiO single crystal thin film which can be used as p-type layer of the UV detector It relates to the manufacturing method.
[0002]
[Prior art]
NiO is an antiferromagnetic metal single crystal substrate as a magnetic element (Japanese Patent Laid-Open No. 10-36956) or an orientation base film for high-density magnetic recording media (Japanese Patent Laid-Open No. 7-97296, Japanese Patent Laid-Open No. 9-125233). It is known to be used as Moreover, it is known to use as a translucent contact part, such as a light emitting diode and a laser diode (LD) (Unexamined-Japanese-Patent No. 2001-7398).
[0003]
[Problems to be solved by the invention]
NiO is one of p-type oxide semiconductors. For example, a heterojunction LED combined with an n-type oxide semiconductor ZnO has been proposed, but a conventional NiO thin film is an aggregate of polycrystals and has a surface. The unevenness is large. Therefore, for example, even if a ZnO thin film is grown on a NiO polycrystalline thin film, there is a problem that the crystallinity of ZnO deteriorates and a heterojunction cannot be manufactured.
[0004]
[Means for Solving the Problems]
The present invention, p-type oxide semiconductor NiO single crystal thin film, in particular surface to provide a method of manufacturing a flat p-type oxide semiconductor NiO single crystal thin film in atomic order.
[0005]
That is, the present invention is as follows.
[0006]
( 1 ) A polycrystalline p-type oxide NiO thin film is formed on a heat-resistant single crystal substrate by vapor phase growth while maintaining the substrate temperature at 100 ° C. or lower, and then annealed at 600 to 1500 ° C. p-type oxide semiconductor NiO method for producing a single crystal thin film you characterized in that the crystals.
( 2 ) The method for producing a p-type oxide semiconductor NiO single crystal thin film according to ( 1 ), wherein a NiO sintered body containing Li is used as a target in the vapor phase growth method.
( 3 ) The method for producing a p-type oxide semiconductor NiO single crystal thin film according to (1) , wherein YSZ (yttria stabilized zirconia) is used as the heat resistant single crystal substrate.
(4) The p-type oxide semiconductor NiO single crystal thin film is composed of a flat terrace at atomic level and a sub-nanometer (nm) step. A method for producing a crystalline thin film.
(5) The method for producing a p-type oxide semiconductor NiO single crystal thin film according to the above (1), wherein the p-type oxide semiconductor NiO single crystal thin film contains 30 at% or less of Li as an acceptor.
(6) The method for producing a p-type oxide semiconductor NiO single crystal thin film according to (1) , wherein the p-type oxide semiconductor NiO single crystal thin film has a room temperature conductivity of 10 −4 S / cm or more. .
[0007]
The ultra-flat p-type oxide semiconductor NiO single crystal thin film obtained by the manufacturing method of the present invention has a flat surface on the atomic order, so that, for example, a crystal material for LED or LD can be deposited with good crystallinity. , It plays the role of a hole injection electrode.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
In the manufacturing method of the present invention, the substrate of the p-type oxide semiconductor NiO single crystal thin film is a heat-resistant single crystal, such as an oxide single crystal substrate, a Si substrate, a SiC substrate, or a CaF 2 substrate. Examples of the oxide single crystal substrate include YSZ (yttria stabilized zirconia), sapphire, MgO, and ZnO. These substrates preferably have a surface mean square roughness Rms of 1.0 nm or less. Rms can be calculated by scanning a 1 μm square with an atomic force microscope, for example.
[0009]
The surface of the substrate usually has polishing marks due to optical polishing in the manufacturing process, and the crystal itself is damaged. By heating such a substrate to 1000 ° C. or higher in the air or in a vacuum, a surface that is super flattened by surface diffusion can be obtained. A structure reflecting the crystal structure appears on the surface of the ultra flattened oxide single crystal substrate. That is, it is a structure composed of a terrace having a width of about several hundred nm and a step having a height of about a sub-nanometer (nm), and is generally called an atomically flattened structure.
[0010]
The terrace portion is composed of atoms arranged in a plane, and is a completely flattened surface if the presence of some defects is ignored. The presence of the step does not result in a completely flattened surface throughout the sample. If this structure is expressed in terms of roughness Rms by the mean square roughness measurement method, Rms is 1.0 nm or less. Rms is a value calculated by, for example, scanning an area of 1 μm square with an atomic force microscope, for example.
[0011]
As for the Si substrate and the SiC substrate, those having a surface Rms of 1.0 nm or less must be used by using the same heat treatment and chemical etching as those of the oxide single crystal substrate. An ultra flat p-type oxide semiconductor NiO single crystal thin film cannot be formed on a substrate having a large Rms and a rough surface.
[0012]
A p-type oxide semiconductor NiO single crystal thin film is formed on these ultra flat substrates. As a film formation method, a pulse laser deposition method, a sputtering method, a CVD method, an MO-CVD method, an MBE method, or the like can be used. The most important parameter for film formation is the substrate temperature. The substrate temperature during film formation must be 100 ° C. or lower. When the temperature exceeds 100 ° C., composition deviation and grain growth of the p-type oxide semiconductor NiO thin film are likely to occur, and flattening is hindered. Since dew condensation occurs when the thin film is taken out from the vacuum chamber, the lower limit temperature is 0 ° C. The substrate temperature during film formation is more preferably 10 to 50 ° C.
[0013]
Thereby, a p-type oxide semiconductor NiO thin film having a flat surface in atomic order is obtained. The concept of flatness in the atomic order means that when a single crystal substrate is used, the surface is composed of a flat terrace and molecular layer steps at the atomic level, and strictly speaking, it cannot be defined by surface roughness. The roughness measured by the mean square roughness measurement method is 1 nm or less, more preferably 0.5 nm or less.
[0014]
The p-type oxide semiconductor NiO thin film formed at a substrate temperature of 100 ° C. or lower can only observe three-dimensionally deposited particles, but does not show a flat terrace and molecular layer step structure at the atomic level. This is annealed at a high temperature to produce a p-type oxide semiconductor NiO single crystal thin film. The annealing temperature is preferably 600 ° C to 1500 ° C. Below 600 ° C., atoms cannot sufficiently migrate on the surface of the thin film, and a p-type oxide semiconductor NiO single crystal thin film cannot be obtained. Further, a high temperature exceeding 1500 ° C. is not preferable because a chemical reaction between most of the substrate material and the NiO thin film occurs.
[0015]
The conductivity of the NiO single crystal thin film can be controlled by changing the concentration of Li as an acceptor. For example, when Li is not added at all, the conductivity is 10 −4 S / cm, but by doping Li at 10 at%, the conductivity becomes 0.3 S / cm. Doping can be controlled by changing the Li concentration in the sintered compact target. The Li concentration as an acceptor must be 30 at% or less. This is because doping with Li exceeding 30 at% changes to LiNiO 2 which is a compound that is not NiO.
[0016]
Further, when annealing at 600 ° C. or higher, Li ions added to the NiO thin film tend to evaporate. In order to prevent such evaporation of Li ions, the surface of the NiO thin film is preferably covered with a YSZ single crystal substrate or the like. The atmosphere during annealing is preferably air or oxygen gas. This is because Li ions easily evaporate in a vacuum or in an inert gas.
[0017]
【Example】
Hereinafter, the present invention will be described by way of examples.
Example 1
A YSZ single crystal substrate (111) surface (manufactured by Meijo Metal Co., Ltd., 10 mm square) was heated to 1350 ° C. in the atmosphere to produce an atomic flat surface. The YSZ single crystal substrate was placed in an ultra-high vacuum vessel for laser ablation (Irie Koken Co., Ltd.) to keep the temperature at room temperature. An oxygen gas of 3 × 10 −3 Pa was introduced into the container, and a KrF excimer laser beam (Laser luminescence device manufactured by Lambda Physics Co., Ltd.) was irradiated to a NiO sintered body target containing 10 at% Li. A NiO: Li thin film was deposited on the substrate facing away by 30 mm. The film thickness was 300 nm. Next, the produced NiO: Li thin film is taken out from the vacuum vessel, and in order to prevent evaporation of the Li component during annealing, a YSZ single crystal plate is placed on the thin film to cover the surface of the thin film and annealed at 1300 ° C. for 30 minutes in the air. And then cooled to room temperature.
[0018]
The Li content measured by photoelectron spectroscopy of the annealed thin film was 1 × 10 20 cm −3 in terms of the number of atoms per unit volume. The diffraction pattern of the sample was measured with an X-ray diffractometer (manufactured by Rigaku Corporation: ATX-G). FIG. 1 shows an XRD pattern. It can be seen that NiO (111) is strongly oriented and grown on the YSZ (111) substrate. Moreover, the small diffraction peak seen around the NiO (111) diffraction peak is an equi-thickness interference fringe called a Pendell fringe, indicating that the thin film surface is flat at the atomic level.
[0019]
The conductivity measured by the four-terminal method was 0.3 S / cm, and the Seebeck coefficient (Seebeck coefficient) at room temperature was +0.6 mV / K. It can be said that it is a p-type oxide semiconductor. FIG. 2 shows an atomic force microscope image of the obtained thin film surface. An ultra-flat structure consisting of flat terraces and steps at the atomic level was observed. The average square roughness Rms value obtained by scanning the range of 1 μm square using an atomic force microscope was 1 nm.
[Brief description of the drawings]
1 is a graph showing an XRD pattern of a NiO single crystal thin film produced in Example 1. FIG.
2 is a drawing-substituting photograph shown by an atomic force microscope image showing the fine surface structure of the NiO single crystal thin film produced in Example 1. FIG.
Claims (6)
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