JP4012832B2 - Receiver circuit having serial communication function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving circuit having a serial communication function.
[0002]
[Prior art]
In asynchronous serial data transmission, it is necessary to generate a clock signal having a frequency corresponding to the serial data transfer speed on the receiving side.
The frequency divider value that determines the frequency of the clock signal on the receiving side does not change even when the transfer rate changes during data transfer, so the sampling timing of serial data is shifted and data can be captured accurately. It may disappear.
[0003]
In order to solve such a problem, for example, in the invention of Japanese Patent Application Laid-Open No. 2001-168853, the transfer rate of serial data is recognized by measuring the bit width of the start bit, and according to the recognized data transfer rate. Divide the receive clock by the division value. Then, data is sampled for every p clock signals obtained by frequency division so that the data can be taken in accurately.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-168853 (Abstract “Solution”)
[0005]
[Problems to be solved by the invention]
By the way, when the CPU receives serial data transmitted from a communication IC or the like, if the CPU processing speed is slow, processing time is taken to match the serial data reception timing, and other processing can be executed. Disappear. Therefore, it is necessary to use a CPU with a high processing speed, but there is a problem that a CPU with a high processing speed is expensive. Further, in order to transmit serial data from the communication IC side to the CPU, a circuit for detecting whether or not the CPU can receive the data is required, and the circuit becomes complicated accordingly.
[0006]
An object of the present invention is to be able to capture a signal from a receiving circuit in accordance with the processing speed of a processor. Another problem is to reduce the number of output ports of the receiving circuit.
[0007]
[Means for Solving the Problems]
The receiving circuit having the asynchronous serial communication function of the present invention includes a receiving electric field strength determining circuit that determines whether or not the receiving electric field strength is equal to or higher than a predetermined value, and whether the frequency of the intermediate frequency signal is higher or lower than the reference frequency. An intermediate frequency determination circuit for determining, a conversion circuit for receiving serial data output from an external processor and converting it into parallel data, a data holding circuit for holding parallel data converted by the conversion circuit, and the data holding When the parallel data held in the circuit is decoded and the decoding result is data requesting output of the determination result of the reception field strength determination circuit, the 1-bit signal of the determination result of the reception field strength determination circuit And output the signal from one output port to the outside at the timing requested by the processor. A data output circuit that selects a 1-bit signal of the determination result of the intermediate frequency determination circuit and outputs the data to the outside from the output port when the data requests output of the determination result of the intermediate frequency determination circuit; Prepare.
[0008]
According to the present invention, the signal to be output from the output port of the receiving circuit can be arbitrarily specified from among a plurality of signals, and the processor can determine the timing to output the signal, so that it can be set according to the processing speed of the processor. Can be captured. As a result, the processing load for receiving data is reduced, so that, for example, a processor having a relatively low processing speed can be used. In addition, since any signal among a plurality of signals can be specified and output from one output port, the number of output ports of the receiving circuit can be reduced. This is highly effective when the receiving circuit is formed on a semiconductor integrated circuit.
[0009]
In addition, since data is transmitted from the receiving circuit to the processor using the output port, a circuit on the receiving circuit side for detecting whether or not the processor can receive data becomes unnecessary.
In the above invention, the data output circuit may determine whether the parallel data obtained by converting the serial data output from the processor has a received electric field strength of a predetermined value or more, and the frequency of the intermediate frequency signal is predetermined. Whether one of the determination results is selected or not from the output port depending on whether the data matches the frequency, or is data that requests output of a determination result that is higher or lower than a predetermined frequency. You may make it output to a processor.
[0010]
With this configuration, the processor determines whether the received electric field strength is equal to or higher than a predetermined value, whether the frequency of the intermediate frequency signal matches the predetermined frequency, whether the frequency is higher or lower than the predetermined frequency. The serial data requesting the output is output and the signal output from the output port of the semiconductor integrated circuit corresponding to the serial data is read to obtain the determination results. As a result, the processing load for the processor to receive data is reduced, so that a processor with a low processing speed can be used.
[0011]
The receiving circuit of the present invention includes a stereo determination circuit that determines whether the reception is stereo reception or monaural reception, and the data output circuit includes the decoding result, the determination result of the stereo determination circuit, and the electric field strength determination. Depending on the determination result of the circuit and the determination result output from the determination result of the intermediate frequency determination circuit, the 1-bit signal of the corresponding determination result is selected and output from the output port to the outside. Output.
[0012]
The plurality of determination circuits include a reception field strength determination circuit that determines whether or not the reception field strength is equal to or higher than a predetermined value, and an intermediate frequency determination circuit that determines whether the frequency of the intermediate frequency signal is higher or lower than the predetermined frequency. The data output circuit outputs 1-bit data output from the reception field strength determination circuit from the output port when the parallel data is data requesting output of a determination result of the reception field strength determination circuit. When the parallel data is data requesting output of the determination result of the intermediate frequency determination circuit, the processor outputs the 1-bit data output from the intermediate frequency determination circuit to the processor from the output port. Output.
[0013]
With the configuration described above, the processor can acquire the determination result of the determination circuit by reading 1-bit data output from the output port of the reception circuit. This makes it possible to use a processor with a slow processing speed.
The plurality of determination circuits include a reception electric field strength determination circuit that determines whether or not the reception electric field strength is a predetermined value or more, and an intermediate frequency signal obtained by mixing the reception signal and the local oscillation signal has a predetermined frequency. An intermediate frequency determination circuit for determining whether they match, higher than a predetermined frequency, lower than a predetermined frequency, and the data output circuit includes parallel data held in the data holding circuit And a decoder that selects one signal out of a plurality of signals output from the reception electric field strength determination circuit and the intermediate frequency determination circuit based on a decoding result of the decoder, and outputs the processor from the output port. It consists of a selector to be output to.
[0014]
For example, when the processor wants to know the determination result of the reception field strength determination circuit, it outputs serial data requesting output of the reception field strength determination result. The data output circuit decodes the converted parallel data, selects a determination result signal output from the reception field strength determination circuit based on the decoding result, and causes the processor to output the signal from the output port.
[0015]
When the processor wants to know whether or not the frequency of the intermediate frequency signal matches a predetermined frequency, it outputs serial data requesting output of the determination result. The data output circuit decodes the parallel data, selects a signal indicating whether or not the frequency of the intermediate frequency signal output from the intermediate frequency determination circuit matches a predetermined frequency based on the decoding result, and selects the signal Output from the output port to the processor.
[0016]
By configuring as described above, the processor can acquire the determination result of the received electric field strength and the determination result of the intermediate frequency determination circuit simply by reading the data output from the output port, so the processing burden for receiving the data Is reduced. Thereby, a processor with a low processing speed can be used.
[0017]
The plurality of signals output from the intermediate frequency determination circuit include a signal indicating whether the intermediate frequency signal matches a predetermined frequency and a signal indicating whether the intermediate frequency signal is higher or lower than the predetermined frequency.
Alternatively, the plurality of signals output from the intermediate frequency determination circuit include a signal indicating whether the intermediate frequency signal matches a predetermined frequency, a signal indicating whether the intermediate frequency signal is higher than the predetermined frequency, and a predetermined frequency. It consists of a signal indicating whether it is low or not.
[0018]
The receiving circuit may be formed on a semiconductor circuit substrate by a MOS process. With this configuration, the output signals of a plurality of circuits can be output from the same output pin, so that the number of pins can be reduced when the number of output pins is limited as in a semiconductor circuit board.
[0019]
The conversion circuit corresponds to the conversion circuit 15 in FIG. 1, the data holding circuit corresponds to the latch circuit 21 in FIG. 1, and the determination circuits are the reception electric field strength determination circuit 23 and the intermediate frequency determination circuit 24 in FIG. The data output circuit corresponds to the decoder / selector 22 in FIG. 1, and the processor corresponds to the CPU 12 in FIG.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. FIG. 1 is a diagram showing a main part of a receiving circuit 11 of an FM / AM receiver according to an embodiment of the present invention.
The receiving circuit 11 includes a CPU 12 and a semiconductor integrated circuit 13 having an FM / AM receiving circuit and a serial communication circuit. The semiconductor integrated circuit 13 is manufactured by a CMOS process, and an internal FM / AM receiving circuit, serial communication circuit, and the like are configured by MOSFETs.
[0021]
In FIG. 1, serial data output from the CPU 12 is input from the serial port 14 to the conversion circuit 15. The conversion circuit 15 is composed of, for example, a 10-bit shift register, a timing control circuit, and the like. The conversion circuit 15 sequentially shifts serial data at a timing synchronized with the clock signal CK supplied from the clock signal generation circuit 16 to provide 8-bit data. If the amount of data is fetched, 8-bit data is output as parallel data.
[0022]
In this embodiment, the CPU 12 outputs a start bit, 8-bit serial data, and a stop bit. First, address data designating an output destination of data is output as 4-bit data out of 8-bit data, and then 8-bit data is output.
[0023]
The address decoder 17 decodes the parallel data output from the conversion circuit 15 and enables the corresponding latch circuits 18 to 21 when the decoded result matches the address assigned to the latch circuits 18 to 21. Output address selection signals A0 to A3.
[0024]
The latch circuits 18 to 20 are circuits for latching data for setting a reference frequency of a local oscillation circuit (not shown), setting data for a frequency of a broadcasting station, and the like, and output the latched data to a corresponding circuit. .
The latch circuit 21 requests output of 8-bit serial data output from the CP 12, that is, a determination signal of the reception electric field strength determination circuit 23, a plurality of determination signals of the intermediate frequency determination circuit 24, or a determination signal of the stereo determination circuit 25. The 8-bit data is latched, and data of a predetermined number of bits out of the 8 bits is output to the decoder / selector 22.
[0025]
The reception electric field strength determination circuit 23 is a circuit for determining whether the electric field strength of the FM or AM reception signal is equal to or greater than a predetermined value, and outputs a 1-bit determination signal of 1, 0 as a determination result to the decoder / selector 22. To do.
The intermediate frequency counter 27 is a counter that measures the frequency fi of the intermediate frequency signal IF obtained by mixing the reception signal and the local oscillation signal, and outputs the count result to the intermediate frequency determination circuit 24.
[0026]
The intermediate frequency determination circuit 24 compares the frequency fi of the intermediate frequency signal IF measured by the intermediate frequency counter 27 with a predetermined reference frequency f0, and determines whether or not the two frequencies match, the frequency fi of the intermediate frequency signal IF. Is higher than the reference frequency f0, and whether the frequency fi of the intermediate frequency signal IF is lower than the reference frequency f0 is determined.
[0027]
From the intermediate frequency determination circuit 24, a 1-bit determination signal SDIF1 (fi = f0) indicating whether or not the frequency fi of the intermediate frequency signal IF matches the reference frequency f0, and whether or not it is higher than the reference frequency f0. Three types of signals, a 1-bit determination signal SDIF2 (fi> f0) and a 1-bit determination signal SDIF3 (fi <f0) indicating whether the frequency is lower than the reference frequency f0, are output to the decoder / selector 22. Instead of the determination signals SDIF2 and SDIF3, the intermediate frequency determination circuit 24 may output a 1-bit signal indicating whether the frequency fi of the intermediate frequency signal IF is higher or lower than the reference frequency f0.
[0028]
The stereo determination circuit 25 outputs a 1-bit determination signal ST indicating whether the reception is stereo or monaural to the decoder / selector 22. For example, the stereo determination circuit 25 outputs “1” as the determination signal ST for stereo reception and “0” for monaural reception.
[0029]
The decoder / selector 22 includes a decoder that decodes data output from the latch circuit 21 and a selector that selects and outputs one of a plurality of determination signals based on the decoding result of the decoder.
The selector of the decoder / selector 22 includes a determination signal SDS output from the received electric field strength determination circuit 23, a plurality of determination signals SDIF 1 to 3 output from the intermediate frequency determination circuit 24, and a determination signal output from the stereo determination circuit 25. ST is input, and one of the plurality of determination signals is selected based on the decoding result of the internal decoder and output from the output port 26 to the external CPU 12.
2A and 2B are diagrams illustrating an example of a configuration of serial data output from the CPU 12.
[0030]
FIG. 2A shows a data configuration in the case of transmitting an address and data with 2 bytes. First, an 8-bit address is transmitted, and then 8-bit data is transmitted. In this case, the lower 4 bits are used as address data. Then, following the address, data specifying a signal to be output to the output port 26 is transmitted.
[0031]
FIG. 2B shows a data configuration in the case where both address and data are transmitted in one byte. The upper 4 bits are assigned to the address and the lower 4 bits are assigned to the data.
Note that the CPU 12 may designate a signal to be output from the output port 26 by address data. In this case, when a specific address is output, the selector outputs a first signal (for example, signal SDS) to the output port 26, and when another address is output, the selector outputs a second signal (for example, ST) may be output to the output port 26.
[0032]
FIG. 3 is a detailed circuit diagram of the transmission / reception circuit 15 and the address decoder 17 shown in FIG.
A serial / parallel conversion circuit 41 including a 10-bit shift register converts 8-bit serial data output from the CPU 12 into parallel data, and outputs the parallel data to the address latch circuit 51 and the latch circuits 18 to 21.
[0033]
The 10-bit counter 42 counts the clock signal output from the clock signal generation circuit 16 and outputs the count-up signal a to the T flip-flop 43 when 10 clocks are counted.
The T flip-flop 43 is a circuit whose Q output is inverted by the count-up signal a of the 10-bit counter 42. The Q output signal b of the T flip-flop 43 is output to the rising edge detection circuit 44 and the falling edge detection circuit 45.
[0034]
The rising edge detection circuit 44 detects the rising edge of the Q output signal b of the T flip-flop 43 and outputs a high level latch signal c having a constant width to the address latch circuit 51.
The address latch circuit 51 latches 8-bit address data output from the serial / parallel conversion circuit 41 when the latch signal c becomes high level.
[0035]
The fall detection circuit 45 detects the fall of the Q output signal b of the T flip-flop 43 and outputs a high level signal d having a constant width to the inverter 46 and the AND gates 53 to 56. The output of the inverter 46 is output to a delay circuit 47 composed of a shift register or the like, subjected to a certain delay, and then output to one input terminal of the AND gates 48 and 49. A hardware reset signal that is normally at a high level is input to the other input terminal of the AND gate 48. The output of the AND gate 48 is input to the reset terminal of the 10-bit counter 42. Similarly, a hardware reset signal is input to the other input terminal of the AND gate 49.
[0036]
When the hardware reset signal becomes low level by the inverter 46, the delay circuit 47, and the AND gates 48 and 49, or the falling of the Q output signal b of the T flip-flop 43 is detected by the falling detection circuit 45. When a certain delay time has elapsed since then, the 10-bit counter 42 and the T flip-flop 43 are reset.
[0037]
The address decoder 52 decodes the address data latched by the address latch circuit 51 and outputs a signal designating the corresponding latch circuit among the latch circuits 18 to 21 to the AND gates 53 to 56.
The AND gates 53 to 56 select one of the latch circuits 18 to 21 when a high level signal is output from the address decoder 52 and a high level detection signal d is output from the falling detection circuit 45. The selection signals A0 to A3 to be output are output.
[0038]
The address latch circuit 51, the address decoder 52, and the AND gates 53 to 56 correspond to the address decoder 17 in FIG.
Next, the operation when the signal output from the output port 26 is switched in the receiving circuit 11 having the above configuration will be described with reference to the timing chart of FIG.
[0039]
When the serial communication is started, the CPU 12 outputs a start bit that is at a low level for a certain period, 8-bit serial data, and a stop bit that is at a high level for a certain period, as shown in FIG.
First, the case where the signal SDS is output from the output port 26 will be described. The CPU 12 outputs address data designating the latch circuit 21 after transmitting a start bit notifying the start of data transmission.
[0040]
The 10-bit counter 42 counts the clock signal output from the clock signal generation circuit 16, and outputs the count-up signal a at the timing shown in FIG.
As shown in FIG. 4 (3), before the count-up signal a is output, the T flip-flop 43 is reset and the Q output signal b is at a low level. When the address data designating the latch circuit 21 is output from the CPU 12 and the count-up signal a is output from the 10-bit counter 42, the Q output signal b changes to high level.
[0041]
When the Q output signal b of the T flip-flop 43 changes from the low level to the high level, the rising edge detection circuit 44 detects the rising edge of the signal b, and as shown in FIG. A level rising detection signal c is output. The address latch circuit 51 latches the address data (address specifying the latch circuit 21) output from the serial / parallel conversion circuit 41 at a timing synchronized with the rising detection signal c. The address latched by the address latch circuit 51 is decoded by the address decoder 52, and a high level signal e for selecting the latch circuit 21 is output (FIG. 4 (6)).
[0042]
Next, when the data A designating the signal SDS is output from the CPU 12, the count-up signal a is output from the 10-bit counter 42 when the next stop bit is received.
When the count-up signal a is output from the 10-bit counter 42, the Q output signal b of the T flip-flop 43 changes from high level to low level as shown in FIG. 4 (3). The change in the Q output signal b is detected by the falling detection circuit 45, and a high level falling detection signal d having a constant width is output from the falling detection circuit 45 as shown in FIG.
[0043]
When the falling detection signal d becomes high level, the AND gate 56 to which the high level signal e is output from the address decoder 52 is opened at this time, and the high level selection signal f (A3) is sent from the AND gate 56 to the latch circuit 21. Is output (FIG. 4 (7)).
[0044]
The latch circuit 21 latches the data A specifying the signal SDS output from the serial / parallel conversion circuit 41 when the selection signal f is output from the AND gate 56.
The decoder / selector 22 decodes the data A latched by the latch circuit 21, selects a signal (in this case, the signal SDS) from among a plurality of input signals, and outputs the selected signal to the output port 26 ( FIG. 4 (8)). As a result, the signal SDS is output from the output port 26 to the CPU 12 (FIG. 4 (9)).
[0045]
Next, a case where the signal SD is output from the output port 26 will be described. When the address specifying the latch circuit 21 is output from the CPU 12 and then the data B specifying the signal ST is output, the count-up signal a is received from the 10-bit counter 42 when the next stop bit is received. Is output.
[0046]
When the count-up signal a is output, the Q output signal b of the T flip-flop 43 changes from high level to low level as shown in FIG. 4 (3). The change in the Q output signal b is detected by the falling detection circuit 45, and a high level falling detection signal d having a constant width is output from the falling detection circuit 45 as shown in FIG.
[0047]
When the falling detection signal d becomes high level, the AND gate 56 to which the high level signal e is output from the address decoder 52 is opened at this time, and the high level selection signal f (A3) is sent from the AND gate 56 to the latch circuit 21. Is output (FIG. 4 (7)).
[0048]
When the selection signal f is output from the AND gate 56, the latch circuit 21 latches the data B specifying the signal SDS output from the serial / parallel conversion circuit 41. The data B latched by the latch circuit 21 is decoded by the decoder / selector 22, selects a designated signal (in this case, the signal ST) among a plurality of signals input to the decoder / selector 22, and outputs the output port 26. (FIG. 4 (8)). As a result, the signal ST is output from the output port 26 to the CPU 12 (FIG. 4 (9)).
[0049]
According to this embodiment, the CPU 12 outputs data designating an arbitrary signal in a plurality of signals (SDS, ST, SDIF1, etc.) to the receiving circuit, whereby the signal designated from the output port of the receiving circuit 11 is output. Can be output. Thus, for example, the CPU 12 can capture a plurality of signals using one output port. In addition, since the CPU 12 itself can determine the timing at which the CPU 12 captures the signal (data), the signal can be captured according to the processing speed of the CPU 12. Thereby, even when the processing speed of the CPU 12 is slow, the data can be reliably received.
[0050]
Next, FIG. 3 is a flowchart of seek processing when a receivable station is automatically detected.
When an automatic channel selection button or the like is operated by the user, the CPU 12 outputs serial data instructing seek on to the serial port 14 to detect a receivable station (S11 in FIG. 3).
[0051]
Next, serial data for requesting output of a seek level determination result, that is, a reception field strength determination result is output (S12). At this time, address data for enabling the latch circuit 21 is output first.
Next, the tuning frequency f is increased or decreased by the frequency Δf (S13).
[0052]
When serial data requesting the output of the reception field strength determination result is output from the CPU 12, the conversion circuit 15 converts the received serial data into parallel data, and the latch circuit 21 latches the parallel data. The decoder / selector 22 decodes the parallel data latched by the latch circuit 21 and outputs the received field strength determination circuit 23 when the decoded result is data requesting output of the received field strength determination result. A signal SDS indicating whether the received electric field strength is equal to or higher than a predetermined value is selected and output to the output port 26.
[0053]
The CPU 12 reads a 1-bit signal SDS indicating whether or not the received electric field intensity output from the output port 26 is equal to or higher than a predetermined value, and determines whether or not the signal SDS is “1” (S14).
When SDS = 0 (S14, NO), it is a case where a reception signal of a certain level or higher is not received, so the process returns to step S13 to increase or decrease the tuning frequency.
[0054]
On the other hand, if SDS = 1 (S14, YES), that is, if the electric field strength of the received signal is greater than or equal to a predetermined value, the process proceeds to step S15 to output serial data requesting output of the determination result of the intermediate frequency determination circuit 24.
When serial data requesting output of the determination result of the intermediate frequency determination circuit 24 is output from the CPU 12, the conversion circuit 15 converts the received serial data into parallel data, and the latch circuit 21 latches the parallel data.
[0055]
The decoder / selector 22 decodes the parallel data latched by the latch circuit 21. When the decoding result is data requesting output of a determination result as to whether or not it matches the reference frequency f0, the frequency fi of the intermediate frequency signal IF output from the intermediate frequency signal determination circuit 24 is the reference frequency f0. Is selected and output to the output port 26.
[0056]
When the decoder / selector 22 is data requesting output of a determination result as to whether or not the decoding result is higher than the reference frequency f0, the frequency fi of the intermediate frequency signal IF output from the intermediate frequency determination circuit 24 is determined. A signal SDIF2 indicating whether the frequency is higher than the reference frequency f0 is selected and output to the output port 26.
[0057]
Further, when the decoder / selector 22 is data requesting output of a determination result as to whether or not the decoding result is lower than the reference frequency f0, the frequency fi of the intermediate frequency signal IF output from the intermediate frequency determination circuit 24 is determined. A signal SDIF3 indicating whether the frequency is lower than the reference frequency f0 is selected and output to the output port 26.
[0058]
The CPU 12 reads a signal output from the output port 26, and based on the read signal, whether or not the frequency fi of the intermediate frequency signal IF matches the reference frequency f0, that is, falls within a certain frequency range of the reference frequency f0. Whether it is higher than the reference frequency f0 or lower than the reference frequency f0 (S16). Since the CPU 12 knows the serial data transmitted immediately before, the CPU 12 can determine which of the three types of signals SDIF1 to SDIF3 is output from the output port 26.
[0059]
When the frequency fi of the intermediate frequency signal IF is higher than the reference frequency f0 (fi> f0) or lower than the reference frequency f0 (fi <f0), the received signal is not a broadcast station signal, so the process returns to step S13 to tune. The seek is continued by increasing or decreasing the frequency f by the predetermined frequency Δf.
[0060]
On the other hand, when the frequency fi of the intermediate frequency signal IF matches the reference frequency f0, the CPU 12 stops the seek operation (seek stop) and outputs serial data (S17).
When the FM / AM receiving circuit of the semiconductor integrated circuit 13 receives the serial data for stopping the seek operation, it switches to the normal mode. At this time, the decoder / selector 22 decodes the serial data for stopping the seek operation, and outputs a signal ST output from the stereo determination circuit 25 based on the decoding result, that is, a signal ST indicating whether the reception is stereo or monaural. Select and output from the output port 26.
[0061]
In the embodiment described above, the CPU 12 requests the semiconductor integrated circuit 13 to output a determination result, and the semiconductor integrated circuit 13 responds to the request with the determination signal of the reception field strength determination circuit 23 and the intermediate frequency. A plurality of determination signals indicating whether the intermediate frequency signal output from the determination circuit 24 matches the reference frequency f0, whether it is higher than the reference frequency f0, or lower than the reference frequency f0, and the stereo determination circuit 25 1 is selected and output from the output port 26.
[0062]
This eliminates the need for the CPU 12 to capture serial data at a timing synchronized with the clock signal corresponding to the data transfer speed when receiving data, and reads 1-bit data from the output port 26 of the semiconductor integrated circuit 13. The judgment result can be acquired with just Therefore, the processing load for receiving data is reduced, and the CPU 12 having a low processing speed can be used.
[0063]
In addition, since data is transmitted from the semiconductor integrated circuit to the processor using the output port, a circuit on the semiconductor integrated circuit side for detecting whether or not the processor can receive data is not necessary.
The present invention is not limited to the above-described embodiment, and can be configured as follows.
(A) In the above-described embodiment, the three determination circuits of the reception electric field strength determination circuit 23, the intermediate frequency signal determination circuit 24, and the stereo determination circuit 25 are described, but the present invention is not limited to these determination circuits.
(B) The present invention is not limited to a semiconductor integrated circuit for FM / AM receivers, but can be applied to any semiconductor integrated circuit as long as it performs serial communication with a processor.
[0064]
【The invention's effect】
According to the present invention, the signal to be output from the output port of the receiving circuit can be arbitrarily designated from among a plurality of signals, and the processor can determine the timing for outputting the signal. In response, a desired signal can be captured. In addition, since any signal among a plurality of signals can be output from one output port, the number of output ports of the receiving circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a main part of a receiving circuit according to an embodiment;
FIGS. 2A and 2B are diagrams showing an example of a data configuration.
FIG. 3 is a detailed circuit diagram of a main part of a receiving circuit.
FIG. 4 is a timing chart of the receiving circuit.
FIG. 5 is a flowchart of a seek process performed by a CPU 12;
[Explanation of symbols]
11 Receiver circuit
12 CPU
13 Semiconductor integrated circuit
15 Conversion circuit
16 Clock signal generation circuit
17 Address decoder
18-21 Latch circuit
22 Decoder / Selector
23 Received field strength judgment circuit
24 Intermediate frequency judgment circuit
25 Stereo decision circuit
26 Output port

Claims (3)

A received electric field strength determination circuit for determining whether or not the received electric field strength is a predetermined value or more;
An intermediate frequency determination circuit for determining whether the frequency of the intermediate frequency signal is higher or lower than the reference frequency;
A conversion circuit that receives serial data output from an external processor and converts it into parallel data;
A data holding circuit for holding parallel data converted by the conversion circuit;
When the parallel data held in the data holding circuit is decoded and the decoding result is data requesting output of the determination result of the reception field strength determination circuit, one of the determination results of the reception field strength determination circuit When a bit signal is selected and output from one output port to the outside at a timing requested by the processor, and the decoding result is data requesting output of the determination result of the intermediate frequency determination circuit, A receiving circuit having an asynchronous serial communication function , comprising: a data output circuit that selects and outputs a 1-bit signal as a determination result of the intermediate frequency determination circuit to the outside from the output port . The intermediate frequency determination circuit determines whether the frequency of the intermediate frequency signal is higher or lower than the reference frequency or matches the reference frequency,
  The data output circuit, when the decoding result is data requesting output of a determination result of whether or not the frequency of the intermediate frequency signal is higher than a reference frequency or lower than a reference frequency, A 1-bit signal indicating whether the frequency of the intermediate frequency signal output from the frequency determination circuit is higher than a reference frequency or lower than a reference frequency is selected, and at the timing requested by the processor When the decoding result is data requesting output of a determination result as to whether or not the frequency of the intermediate frequency signal matches a reference frequency, it is output from the intermediate frequency determination circuit. A 1-bit signal indicating whether the frequency of the intermediate frequency signal matches a reference frequency is output from the output port to the outside Receiver circuit of claim 1 wherein the. Having a stereo determination circuit for determining whether it is stereo reception or monaural reception;
  In the data output circuit, the decoding result is data requesting output of any determination result among the determination result of the stereo determination circuit, the determination result of the reception electric field strength determination circuit, and the determination result of the intermediate frequency determination circuit. The receiving circuit according to claim 1, wherein a 1-bit signal of a corresponding determination result is selected and output from the output port to the outside depending on whether or not.

Images