JP4011098B2 - Circuit delay time calculation method and delay time calculation device - Google Patents

Description

  The present invention relates to a circuit delay time calculation method and a delay time calculation device, and more particularly to an accurate calculation of an arithmetic element gate unit in consideration of a saturation phenomenon of gate delay in a predetermined arithmetic element gate unit. The present invention relates to a delay time calculation method and a delay time calculation device for a circuit capable of calculating a long delay time.

A semiconductor integrated circuit such as an LSI in which a plurality of logic circuits are integrated has been increasingly scaled up and speeded up due to recent development of miniaturization technology.
As described above, as the speed and miniaturization of a semiconductor integrated circuit system progresses, timing control between LSI chips as its constituent elements becomes important, and strict accuracy is required for the timing control. Yes.

  Therefore, for example, when designing each LSI, it is necessary to verify the timing using a highly accurate logic simulator before entering the mask process.

  Generally, the configuration of a unit logic cell used in the semiconductor integrated circuit is equivalent to a plurality of parasitic capacitances in the arithmetic element gate portion I and the arithmetic element gate portion I as shown in FIG. The unit wiring groups h1 to hn including the line portion H are expressed as being configured by the line portion H configured to be connected to each other in series or partially in a branched shape.

The delay time of the arithmetic element gate unit in the unit logic cell having such a configuration is, for example, an input slew rate, wiring resistance, delay difference due to a line, temperature, power supply voltage, setting environment conditions such as a process, etc. Therefore, it is becoming difficult to perform accurate simulation.
As described above, due to the recent advancement of wiring miniaturization technology and the increase in scale of LSI chips, the influence of the wiring resistance of the line portion H connected to the arithmetic element gate portion becomes large, and the level cannot be ignored. Has reached.

In other words, the delay time of the wiring section is generally proportional to the resistance and the capacitance, respectively. Therefore, when the wiring width inside the LSI chip is reduced due to the miniaturization of the wiring, the resistance per unit length of the wiring is reduced. As a result, the delay time becomes longer.
On the other hand, with the advancement of wiring miniaturization technology, the LSI chip in the arithmetic element gate portion becomes smaller, so the delay time is increased, thereby increasing the proportion of the wiring delay, and the delay time of the wiring portion. The effect of

Further, as the LSI chip size increases, the internal wiring length of the LSI increases, so that the wiring resistance increases and the wiring capacity also increases.
Further, in recent years, since it has become common to drive a semiconductor integrated circuit at a high frequency, it is necessary to obtain an accurate delay time when manufacturing the semiconductor integrated circuit, and therefore, a highly accurate logic simulator. Need to develop.

Here, if an example of how to obtain the delay time in consideration of the wiring resistance in the logic cell represented by the above-described equivalent circuit will be briefly described, the delay of the arithmetic element gate portion I in FIG. If the time is Tgate and the total delay time of the line portion H is Tline, the total delay time TPD of the logic cell is
TPD = Tgate + Tline
Represented as:

Here, the delay time Tgate of the arithmetic element gate I is affected by the wiring resistance, the condition of other input pins, the input slew rate, etc., but as will be described later, the arithmetic element gate I This delay time is influenced by the wiring resistance and shows a saturation phenomenon.
In other words, the delay time of the arithmetic element gate portion I exhibits a phenomenon that the unit wiring portion connected to the output terminal of the gate portion is saturated and does not increase any more when the wiring length of the unit wiring portion is increased to some extent.

FIG. 5 shows the increment Tout due to the wiring load of the arithmetic element gate part I in the logic cell part as illustrated in FIG. 4 as a change when the wiring length is changed depending on the number of unit wiring parts connected. It is a thing.
Note that the vertical and horizontal axes in FIG. 5 are logarithmic scales.
In FIG. 5, graphs (1) and (2) show the increment Tout due to the load on the arithmetic element gate portion in the state where the above-described miniaturization is not performed. ) Shows a case where the load is only a capacitor and the impedance of the gate of the arithmetic element is large and it is driven at a low speed. In this case, the increment Tout due to the load increases substantially linearly. The increment Tout due to the overall wiring load is large.

Graph (2) shows the load composed of capacitance and resistance. As the wiring length becomes longer, the increment Tout due to the wiring load slightly decreases. There seems to be no substantial difference.
Graph (6) shows a wiring delay Tline due to an increase in wiring resistance in the state where the above-mentioned miniaturization is not performed in the prior art. Since the wiring resistance is also small, Tline due to wiring load is shown. However, the Tline level due to the overall wiring load is low, and therefore the influence of the wiring delay due to the wiring resistance load on the delay time of the arithmetic element gate part I is low. Few.

That is, in the prior art, the delay time is performed centering on the capacitor, and there is virtually no difference even if this is replaced with a resistor + capacitor.
On the other hand, graphs (3) and (4) determine the delay time of the arithmetic element gate portion I in the logic cell to which the above-described miniaturization technique is applied, and graph (3) shows the load. In this example, only the capacitor and the impedance of the arithmetic element gate are small and the gate is driven at a high speed, but in this case, the level of the increment Tout due to the load is smaller than that in the graph (1). However, it increases almost linearly.

Graph (4) shows a case where the load is composed of a capacitor and a resistor, and the impedance of the arithmetic element gate is small and driven at a high speed, but as the wiring length increases. It can be seen that the increment Tout due to the wiring load of the arithmetic element gate portion I does not increase beyond a certain value and is saturated.
Graph (5) shows the wiring delay Tline due to the increase of the wiring resistance with respect to the delay time of the arithmetic element gate portion I in the logic cell to which the above-described miniaturization technique is applied. Since the wiring resistance is large, the Tline due to the wiring load rises linearly on a substantially logarithmic case, and the delay time of the Tline due to the overall wiring load is also large. The influence of Tline due to the load of wiring resistance on the time increases.

In other words, in a semiconductor integrated circuit such as an LSI to which miniaturization technology is applied, the increment Tout due to the load of the arithmetic element gate section I cannot be evaluated only by the capacitance, and an accurate delay time is set. It is understood that it is impossible to calculate.
The object of the present invention is to improve the above-mentioned drawbacks of the prior art, and to calculate the delay time of the arithmetic element gate portion in the logic cell of the semiconductor integrated circuit including LSI etc. Therefore, there is provided a delay time calculation method and a delay time calculation device for a circuit to appropriately reflect the effect of the above in the calculation of the delay time and to execute an accurate simulation by calculating the accurate delay time.

  In order to achieve the above-described object, the present invention basically employs a technical configuration as described below. That is, when calculating the delay time of the arithmetic element gate unit in a circuit composed of a predetermined arithmetic element gate unit and one or a plurality of unit wirings or unit wiring groups, The resistance value is Rd, and the circuit configuration constituted by the unit wiring group is equivalently expressed by a single pi (π) model, and the equivalent resistance value R of the total resistance value of the unit wiring group and the equivalent resistance value R And C1 and C2, and the relationship between the delay time t in the arithmetic element gate portion and the output voltage V (t) of the arithmetic element gate portion is expressed by the arithmetic element gate portion. Is a function of the resistance value Rd, the equivalent resistance value R of the total resistance value of the unit wiring group when the unit wiring group is equivalently represented by a single pi (π) model, and the capacitance groups C1 and C2. The specified delay time judgment When measuring each delay time (Tgate) of the arithmetic element gate unit for each connection number of the unit wirings using an arithmetic expression, a V (t) value obtained by the delay time determination arithmetic expression is determined in advance. The variable resistance value Rdx of the arithmetic element gate unit having the predetermined number of unit wiring groups at the time when the predetermined determination level is reached is corrected in advance by the resistance value Rd of the arithmetic element gate unit. The correction resistance value Rdx ′ is obtained by multiplying by the correction value, and then the delay time (Tgate) of the calculation element gate unit is calculated from the delay time determination calculation formula using the resistance value Rdx ′. This is a method for calculating the delay time of a circuit, and calculates the delay time of the arithmetic element gate part in a circuit composed of a predetermined arithmetic element gate part and one or a plurality of unit wirings or unit wiring groups. In this case, the resistance value of the arithmetic element gate portion is Rd, and the circuit configuration constituted by the unit wiring group is equivalently expressed by a single pi (π) model, and the equivalent resistance of the total resistance value of the unit wiring group Capacitance groups connected to both ends of the value R and the equivalent resistance value R are denoted as C1 and C2, and the delay time t in the arithmetic element gate part and the output voltage V (t) of the arithmetic element gate part , The resistance value Rd of the arithmetic element gate part, the equivalent resistance value R of the total resistance value of the unit wiring group when the unit wiring group is equivalently represented by a single pi (π) model, and When measuring each delay time (Tgate) of the operation element gate unit for each connection number of the unit wirings using a predetermined delay time determination arithmetic expression expressed as a function of the capacitance groups C1 and C2, the delay By time judgment formula (T) V (t) value calculation means for calculating the value, identification means for detecting that the V (t) value in the delay time determination calculation formula has reached a predetermined determination level, After the identification means identifies that the V (t) value has reached a predetermined determination level, the variable means Rdx of the arithmetic element gate unit having the predetermined number of unit wiring groups is calculated. Variable resistance value calculating means, corrected resistance value calculating means for determining a corrected resistance value Rdx ′ by multiplying the resistance value Rd of the calculation element gate portion by a predetermined correction coefficient, and the corrected resistance value calculating means The delay time of a circuit constituted by delay time calculation means for calculating the delay time (Tgate) of the calculation element gate unit from the delay time determination calculation formula using the corrected resistance value Rdx ′ obtained by Arithmetic unit.

  Since the circuit delay time calculation method and the delay time calculation device according to the present invention have the above-described technical configuration, in the calculation of the delay time of the arithmetic element gate unit generally used conventionally. In addition, since the resistance of the arithmetic element gate portion is configured to be corrected using a common coefficient set in advance according to the wiring length, the correction coefficient is calculated once by an appropriate simulation. Therefore, it is possible to calculate an accurate delay time that takes into account the saturation effect based on the wiring length of the arithmetic element gate section, even for different types of logic cells. A high-performance semiconductor integrated circuit based on delay time management can be manufactured.

Hereinafter, specific configurations of a circuit delay time calculation method and a delay time calculation apparatus according to the present invention will be described in detail with reference to the drawings.
First, in the present invention, the equivalent circuit of the logic cell shown in FIG. 4 is transformed into an equivalent circuit diagram as shown in FIG. 6 to calculate the delay time.

  That is, the arithmetic element gate portion I ′ in FIG. 4 is represented as a resistor Rd, and a plurality of unit wirings h1 to hn connected to the arithmetic element gate portion I are connected in series or to each other. The line portions H ′ connected to each other while being formed constitute an equivalent circuit in which a resistor R, capacitors C1 and C2, a resistor G, and a diode D are connected as illustrated.

Here, the equivalent circuit portion formed by the resistor R and the two capacitors C1 and C2 constituting the line portion H ′ is referred to as a single pi (π) model portion.
When a step waveform, which is a predetermined signal waveform, is input as an input signal to the logic cell portion shown in FIG. 6, the delay time t of the arithmetic element gate portion I ′ is the output voltage V of the node portion N in FIG. The calculation is performed using the following delay time determination arithmetic expression (the arithmetic expression (1) of [Equation 1]) that defines the relationship with (t).

In the above equation (1), α1 and α2 are constants.
By analytically solving the time when the value of the output voltage V (t) in the above equation 1 becomes a predetermined output determination level, the resistance value Rdx of the arithmetic element gate portion I taking the above-described saturation effect into consideration is obtained. It is possible to determine appropriately and to obtain the delay time t accurately.
In the present invention, the output judgment level of the output voltage V (t) can be set to 1/2 V (t), for example.

Here, in order to confirm the validity of the logic cell model based on the equivalent circuit as shown in FIG. 6, the examination as shown in FIGS. 7 and 8 was performed.
That is, as shown in FIG. 7A, when the actual arithmetic element gate unit I is used as the arithmetic element gate unit I of the logical cell, and as shown in FIG. In the case where the element gate portion I is replaced with the resistor Rd, the output voltage of the arithmetic element gate portion I when the input signal having the same waveform is input to both circuits is measured at point a in the figure.

7A and 7B, the line portion H of the logic cell was calculated using an equivalent circuit as shown in FIG.
The result is shown in FIG.
FIG. 8 is a graph showing the relationship between the delay time Tout (ns) and the wiring length (mm) in the arithmetic element gate part I of both circuits. Graph 1 shows the resistance in FIG. 7B. The change of the delay time Tout when Rd is 658Ω is shown, and the graph 2 shows the change of the delay time Tout when the arithmetic element gate I in FIG. 7A is an inverter (V1N). Is.

As understood from FIG. 8, the delay time when the actual arithmetic element gate portion is used and the delay time when the arithmetic element gate portion is replaced with the resistor Rd show different values, and the wiring length is It can be seen that the longer the error, the greater the error.
Table 1 is a table in which the error is obtained according to the change in the wiring length.

Therefore, since the resistor Rd can be seen as a function that varies depending on the wiring length, when the delay time of the arithmetic element gate unit is accurately obtained, it is only necessary to replace one resistor Rd. It can be seen that it is difficult to approximate the delay operation.
Subsequently, in order to further pursue the cause of the error described above, simulations as shown in FIGS. 9 to 13 were performed.

That is, the line portion H in FIGS. 7A and 7B is replaced with one variable capacitor, and the input signal having the same waveform is input to both circuits while changing the capacitance. The output voltage V (t) of the arithmetic element gate portion I was measured at point a in the figure.
FIG. 10 and FIG. 11 are graphs showing the results in relation to the elapsed time Time (ns).

  FIG. 10 shows a waveform when the output voltage V (t) rises. The solid line 1 is a graph when the resistance Rd is set to 1388Ω in FIG. 9B, and the dotted line 2 is a diagram. 9A is a graph in the case where the arithmetic element gate portion I in FIG. 9A is a CMOS inverter (V1N), and shows the results when the capacitance is measured in four stages.

As can be determined from the graphs shown in FIG. 10, there is a difference in the output voltage waveform between the case where the actual arithmetic element gate portion is used and the case where the arithmetic element gate portion is replaced with the resistor Rd as described above. It turns out that it exists.
That is, the output voltage waveform 1 in the case where the arithmetic element gate portion is replaced with the resistor Rd has a lower slope than the output voltage waveform 2 measured using the actual arithmetic element gate portion, and thus the driving speed is also slow. As a result, the equivalent capacitance of the load wiring connected to the arithmetic element gate portion appears to be larger than that in the case of using the actual arithmetic element gate portion. In the output voltage waveform 2 measured using the gate portion, the slope of the graph is large, and as a result, the driving speed is increased, so that the equivalent of the load wiring connected to the arithmetic element gate portion is equivalent. The capacitance will appear smaller than when a resistor is used, and therefore the delay time is also shortened.
However, as can be seen from FIG. 10, the time Time (ns) at which the output voltage value V (t) in the simulation becomes 1/2 V (t) is the same in both graphs, and the tendency is Even when the capacitance is changed, the values are the same. Therefore, when a delay time is determined when the output voltage value V (t) is ½ V (t), both values are substantially the same. Therefore, it can be understood that there is no problem even if the calculation element gate section is replaced with the resistor Rd when only the capacitive load is used for calculating the delay time in the calculation element gate section.

Such a situation is shown in FIG. 11 which shows the result of performing the same measurement with respect to an example in which the output voltage waveform is lowered using the same circuit configuration as that used in the simulation performed in FIG. However, the same result as in FIG. 10 is obtained.
From the above considerations, it is understood that when calculating the delay time of the arithmetic element gate part, when calculating the exact delay time reflecting the effect of the saturation effect, the arithmetic element gate part is replaced with a resistor. However, as is apparent from FIGS. 10 and 11, since it can be seen that there is a considerable variation depending on the resistance value and the capacitance value, it is also necessary to change the resistance value depending on the type of the arithmetic element gate portion used in the logic cell. There is.

Therefore, by correcting the resistance value of the arithmetic element gate part to be used with a predetermined correction coefficient, the delay time of the arithmetic element gate part can be universally applied regardless of the type of the arithmetic element gate part. Can also be processed.
Therefore, first, the delay time Tgate of the arithmetic element gate portion I ′ in the present invention is calculated, and the initial resistance value Rdo of the resistor Rd in which the arithmetic element gate portion I ′ used in the logic cell is replaced is calculated. Need to ask.

  Therefore, in order to obtain the delay time Tgate of the arithmetic element gate portion I ′ in the present invention, a predetermined simulation is performed to measure the delay time Tgate, and from the delay time Tgate, the arithmetic element gate portion I ′ By subtracting the inherent delay time T0, the increment Tout due to the wiring load of the arithmetic element gate portion I ′ is obtained by the following equation.

Tout = Tgate-T0
On the other hand, in the present invention, when the slope value KCL of the graph is obtained, it is obtained by calculation by changing the capacitance in an equivalent circuit as shown in FIG. 9A, for example.
That is, in this specific example, when the slope value KCL of the graph is obtained, it is obtained not by changing the wiring length but by changing the capacitance value.

Then, the initial resistance value Rdo of the arithmetic element gate portion I ′ is obtained by dividing the KCL value by the logarithmic value ln2.
Rdo = KCL / ln2
Next, since the increment Tout due to the wiring load of the arithmetic element gate portion I ′ is obtained from the simulation result, the increment Tout is substituted for the value of t in the delay time determination arithmetic expression (1). Then, the resistance value Rd at the time when the output voltage value V (t) becomes 1/2 V (t) is obtained by calculation, and the value is set as the variable resistance value Rdx.

Since the resistance value Rdx differs depending on the type, shape, and circuit configuration of the arithmetic element gate portion used, it is referred to as a variable resistance value.
In the present invention, the variable resistance value Rdx is measured for a plurality of types of arithmetic element gate portions having different configurations and functions, and the results are shown in FIG.
That is, FIG. 12 shows the ratio between the resistance R shown in the equivalent circuit of the line resistance shown in FIG. 6 and the initial resistance value Rdo for the variable resistance value Rdx measured for each arithmetic element gate section I. It is the graph which displayed R / Rdo as a parameter, and the graph V1N (dn) and the graph V1N (up) in the figure respectively show the variable resistance value Rdx of the circuit where the output waveform falls by the 1-input inverter and the circuit where it rises. The graphs R4N (dn) and R4N (up) show the variable resistance values Rdx of the circuit in which the output waveform drops and the circuit in which the output waveform rises in the 4-input NOR circuit, respectively.

  Graphs N4N (dn) and N4N (up) show variable resistance values Rdx of the circuit in which the output waveform drops and the circuit in which the output waveform rises in the 4-input NAND circuit, respectively, and graph V2B (dn) and graph. V2B (up) indicates the variable resistance value Rdx of the circuit where the output waveform drops and the circuit where the output waveform rises in the power inverter, respectively.

  Further, the graph R2N (dn) and the graph R2N (up) show the variable resistance value Rdx of the circuit in which the output waveform drops and the circuit in which the output waveform rises in the 2-input NOR circuit, respectively, and the graph N2N (dn) and graph N3N (dn) indicates the variable resistance value Rdx in the circuit in which the output waveform drops in the 2-input NAND circuit and the circuit in which the output waveform drops in the 3-input NAND circuit.

  As can be seen from FIG. 12, the variable resistance values Rdx of the respective arithmetic element gate portions are different from each other, and with the data as it is, the calculation of the delay time must be executed individually for each arithmetic element gate portion. The calculation time must be long, but in the present invention, as shown in FIG. 13, a ratio obtained by dividing the variable resistance value Rdx by the initial resistance value Rdo is introduced. As a result, it was found that Rdx / Rdo = KRd in all the arithmetic element gate portions described above showed substantially the same value as the parameter R / Rdo described above.

That is, in the present invention, Rdx / Rdo = KRd (hereinafter referred to as the second coefficient) which is a ratio of the above-described parameter R / Rdo (hereinafter referred to as the first coefficient), the variable resistance value Rdx, and the initial resistance value Rdo. It is understood that it changes according to a predetermined relationship.
That is, in the calculation of the delay time in the present invention, the variable resistance value Rdx of each arithmetic element gate section changes as a magnification of a predetermined coefficient KRd (= Rdx / Rdo). Specifically, it is shown in FIG.

That is, the second coefficient KRd according to the present invention changes in a graph as illustrated in accordance with the change in the first coefficient R / Rdo.
Accordingly, when the resistance in the arithmetic element gate section whose delay time is to be measured is Rd, the resistance value Rd is multiplied by the second coefficient KRd as a correction value to thereby calculate the delay of the arithmetic element gate section. A correction resistance value (correction value of the variable resistance value Rdx) Rdx ′ can be obtained, and an accurate delay time of the arithmetic element gate unit can be obtained using the correction resistance value Rdx ′.

That is, the resistance Rd of each cell is different for each cell, and the variable resistance value Rdx of each cell is also different for each cell.
Therefore, it is necessary to create a table showing the relationship between the variable resistance value Rdx and the parameter R / Rdo for each cell. As described above, the variable resistance value Rdx and the parameter R / Rdo of each cell Since the relationship is the same in each cell, the variable resistance value Rdx of each cell can be easily calculated if one table showing such relationship is prepared.

Hereinafter, an example of a specific procedure and configuration of the above-described circuit delay time calculation method and its calculation device according to the present invention will be described with reference to the drawings.
That is, a calculation procedure in a specific example of the circuit delay time calculation method according to the present invention will be described. As shown in FIG. 6, a predetermined calculation element gate portion I ′ and one or a plurality of unit wirings are shown. Alternatively, the delay time t of the arithmetic element gate portion I ′ in the circuit constituted by the line portion H ′ constituted by the unit wiring groups h1 to hn is expressed by the above-described delay time determination arithmetic expression (1). When the calculation is performed, the resistance value of the calculation element gate portion I ′ is Rd, and the circuit configuration H ′ in which the unit wiring groups h1 to hn are arranged in series or in a branched manner is indicated by P in FIG. When equivalently expressed by such a single pi (π) model, the equivalent resistance value R of the total resistance value of the unit wiring groups h1 to hn and the capacitance group connected to both ends of the equivalent resistance value R are represented by C1 and C2 and each of these values is expressed in the delay time determination formula (1). Substituting and measuring each delay time (Tgate) of the arithmetic element gate unit, and at that time, the V (t) value obtained by the delay time determination arithmetic expression is a predetermined predetermined determination. The calculation is performed by correcting the variable resistance value Rdx of the arithmetic element gate portion I ′ at the time of reaching the level by multiplying the resistance value Rd of the arithmetic element gate portion by a predetermined correction coefficient KRd. After the corrected resistance value Rdx ′ of the element gate portion is obtained, the delay time Tgate in the same or different arithmetic element gate portion I ′ is calculated from the delay time determination calculation formula (1) using the resistance value Rdx ′. This is a delay time calculation method for a circuit obtained by calculation.

Therefore, the correction coefficient KRd used in the present invention has a predetermined value corresponding to the number of unit wiring groups h1 to hn connected to the arithmetic element gate portion I. Things are desirable.
Further, the correction coefficient KRd used in the present invention is stored in an appropriate storage means, and the correction coefficient KRd is connected to the arithmetic element gate section in the appropriate storage means. Corresponding to the number of unit wiring groups being stored, it is preferable that the data is stored in a correction table format, such as a lookup table format.

Further, the correction coefficient KRd according to the present invention is, for example, as described above, between the specific resistance Rdo possessed by the arithmetic element gate portion I and the variable resistance value Rdx of the arithmetic element gate portion I ′. It is set as a function.
In addition, the variable resistance value Rdx of the arithmetic element gate portion I ′ according to the present invention corresponds to the number of unit wiring groups h1 to hn connected to the arithmetic element gate portion I ′. These are individually measured according to a predetermined simulation program.

An example of a specific procedure of the delay time calculation method for the circuit in the present invention will be described with reference to the flowchart of FIG.
First, FIG. 1A is a flowchart showing a flow (library creation flow) for creating the correction table described above in the present invention.
A step of selecting a predetermined arithmetic element gate section I ′ (step (S1))
A step of counting the number of unit wirings connected to the arithmetic element gate section 1 ′ (step (S2))
In the single pi (π) model that equivalently represents the wiring load capacity in a line in which a plurality of the unit wirings are connected, the capacity far from the arithmetic element gate portion is defined as a first capacity C1. Further, when the capacity closer to the arithmetic element gate portion is the second capacity C2, and the total capacity of the route is Ctotal, C1 = 5 / 6Ctotal and C2 = 1 / 6Ctotal are determined. (Step (S3))
When the relationship between the delay time t and the output voltage V (t) of the arithmetic element gate portion is equivalently expressed by the resistance value Rd of the arithmetic element gate portion and the unit wiring group by a single pi (π) model. A simulation is executed using the delay time determination formula (1) expressed as a function of the equivalent resistance value R of the total resistance value of the unit wiring group and the capacitance groups C1 and C2, and the unit wiring is connected. A step of measuring each delay time (Tgate) of the arithmetic element gate section I ′ for each number (step (S4))
Next, by subtracting the inherent delay time To of the arithmetic element gate section from the delay time (Tgate) of the arithmetic element gate section for each number of connected unit wirings, the load on the arithmetic element gate section depends on the load. A step of obtaining a delay time increment Tout (step (S5))
As described above, the step of obtaining the capacitance load dependency coefficient KCL from the slope of the graph created by obtaining the relationship between the delay time Tgate of the cell (arithmetic element gate portion) and the capacitance value CL (step (S6))
The equivalent resistance R in the line H ′ to which a plurality of the unit wirings are connected is determined from the total value Rtotal of the resistances of the unit wirings arranged in the line R = 12/25 · Rtotal
A step of calculating using the relational expression (step (S7))
A step of dividing the slope value KCL by the logarithmic value ln2 to calculate an initial specific resistance value Rdo of the arithmetic element gate section I (step (S8))
Rdo = KCL / ln2
Substituting the delay time increment Tout, the equivalent resistance R, and the capacitors C1 and C2 of the arithmetic element gate section obtained above into the delay time determination arithmetic expression (1), the delay time determination arithmetic expression (1) Rd at the time when the value of the output voltage V (t) becomes a predetermined determination level, eg, 1 / 2V (t), is obtained, and this calculation changes depending on the line length. A step of setting the variable resistance value Rdx of the element gate portion I ′ (step (S9))
A step of calculating the value of the first coefficient R / Rdo using the equivalent resistance R and the specific resistance Rdo obtained in the steps (S7) and (S8), and obtaining the value (step (S10)).
A step of calculating the value of the second coefficient KRd (= Rdx / Rdo) by using the variable resistance value Rdx and the specific resistance Rdo obtained by the above-described steps (step (S11))
A step of storing the value of the first coefficient R / Rdo and the value of the second coefficient KRd (= Rdx / Rdo) in a predetermined storage means (step (S12))
After that, the correction table is completed.

Next, a procedure for actually calculating a delay time of a predetermined arithmetic element gate unit using the correction table thus completed will be described with reference to the flowchart of FIG.
That is, as a procedure for calculating the delay time of a predetermined arithmetic element unit, for example, an arbitrary arithmetic element gate unit arbitrarily selected and one or a plurality of unit wiring groups connected to the arithmetic element gate unit The gate resistance Rd is calculated according to each of the steps described above, and the value of the second coefficient KRd (= Rdx / Rdo) corresponding to the value of the first coefficient R / Rdo is calculated. Detecting from information stored in the storage means, (step (S13))
Using the value of the second coefficient KRd (= Rdx / Rdo) detected by the above process, the variable resistance value Rdx ′ of the arithmetic element gate unit is
Rdx ′ = Rd × KRd
(Step (S14))
The value of the variable resistance value Rdx ′ of the arithmetic element gate portion I ′ obtained by the process is substituted for the resistance value Rd in the delay time determination calculation formula (1), and the delay time determination calculation formula A step of obtaining a time Tout when the V (t) value in (1) reaches a predetermined determination level (step (S15))
Using Tout obtained in the above step and the delay time T0 of the arithmetic element gate portion when the arithmetic element gate portion is in a no-load state, the delay time Tgate of the arithmetic element gate portion I ′ is
Tgate = Tout + T0
(Step (S16))
This is a delay time calculation method for a circuit constituted by:

  In the present invention, when executing the above simulation, the arithmetic element gate portion I for measuring the delay time shown in FIG. 2 is dependent on the load when Tsin = 0, that is, when the input is a step waveform. It would be better to use something that has a straight line. When the simulation is executed, as described above, as shown in FIG. 2, the delay is caused when the plurality of unit wiring groups h1 to hn constituting the line portion H are sequentially connected. Each time Tgate is measured, and a list as shown in Table 2 is created.

  That is, the measured value of the delay time Tgate when the unit wiring h1 is connected to the arithmetic element gate portion I is described in the column of wire length (wiring length) 1, and then the unit wiring h1 and The measured value of the delay time Tgate when h2 is connected to the arithmetic element gate portion I in series or in a branched manner is described in the column of the wire length 3, and the delay time Tgate is similarly described below. The measured value of the delay time Tgate when all the unit wiring groups from the unit wirings h1 to hn are connected in series to the arithmetic element gate section I until the measured value of It is described in the column of n.

  Thereafter, the inherent delay time T0 of the arithmetic element gate portion I is subtracted from the measured value of the delay time Tgate to obtain an increment Tout due to the wiring load of the arithmetic element gate portion I. In each column of Table 2, Describe.

  Next, the equivalent resistance value R and the values of the capacitance groups C1 and C2 in the line H that have already been obtained are substituted into the delay time determination arithmetic expression (1), and a simulation similar to the above is executed. Further, the variable resistance value Rdx in the arithmetic element gate section I is calculated by the above-described method, and the result is calculated together with the equivalent resistance value R and the values of the capacitance groups C1 and C2, respectively. Enter in the column.

After that, in each column, after calculating the value of R / Rdo as the first coefficient and the value of KRd (= Rdx / Rdo) as the second coefficient, enter the results. Finish creating the correction table.
The correction table data is stored in a suitable storage means.
Next, when calculating the delay time t of the arithmetic element gate section I in another logic cell, the arithmetic element gate section I regardless of whether the load is a capacitive load or not. It is desirable to use a resistor that matches the characteristics of the gate.

When performing such a measurement, the resistor G shown in the equivalent circuit of FIG. 6 has no current flow because the gate is insulated when the arithmetic element gate portion is a CMOS. The resistance G can be calculated as 0.
Next, with respect to the arithmetic element gate portion, an increment Tout due to the wiring load of the arithmetic element gate portion is obtained by the above-described method, and the result is substituted into the delay time determination arithmetic expression (1), so that the V (t) value is For example, when the resistance value Rd of the arithmetic element gate portion in the case of ½ V (t) is obtained by analysis, the second coefficient KRd to be multiplied by the resistance value Rd is the first coefficient R / Based on the value of Rdo, it is detected from the correction table stored in the storage means, and from the coefficient KRd and the resistance value Rd, the correction resistance value Rdx ′ of the arithmetic element gate unit is obtained by the following equation. .

Rdx ′ = Rd × KRd
Finally, the corrected resistance value Rdx ′ relating to the arithmetic element gate portion is substituted into Rd in the delay time determination arithmetic expression (1), and the V (t) value is, for example, 1 / 2V (t). In this case, the delay time t is obtained by analysis, and is set as a delay time Tout which is an increase in delay due to the load of the arithmetic element gate portion. The total delay time Tgate of the arithmetic element gate portion is obtained as follows.

Tgate = To + Tout
A specific example of a circuit delay time calculation apparatus for realizing the above-described circuit delay time calculation method is shown in FIG.
FIG. 3A shows an example of an apparatus for realizing the operation for creating the correction table as described above, and FIG. 3B is created by FIG. 3A. An example of an apparatus for calculating a delay time for each cell using a correction table is shown.

  That is, FIG. 3A calculates the delay time of the arithmetic element gate portion in a circuit composed of a predetermined arithmetic element gate portion and one or a plurality of unit wirings or unit wiring groups. In this case, the resistance value of the arithmetic element gate portion is Rd, and the circuit configuration in which the unit wiring groups are arranged in series or in a branched manner is equivalently expressed by a single pi (π) model, and the total of the unit wiring groups is The equivalent resistance value R of the resistance value and the capacitance group connected to both ends of the equivalent resistance value R are represented as C1 and C2, and the delay time t in the arithmetic element gate part and the output voltage of the arithmetic element gate part The relationship between V (t), the resistance value Rd of the arithmetic element gate section, and the equivalent of the total resistance value of the unit wiring group when the unit wiring group is equivalently represented by a single pi (π) model. Resistance value R and capacitance groups C1 and C2 When measuring each delay time (Tgate) of the arithmetic element gate portion I for each connection number of the unit wirings using a predetermined delay time determination arithmetic expression expressed by a function of An input means 9 for inputting basic data, and a V (t) value calculation for calculating a V (t) value using the delay time determination calculation formula (1) using various basic data input to the input means. Means 10 for identifying that the V (t) value in the delay time judgment calculation formula has reached a predetermined judgment level, the identification means 11 for detecting that the V (t) value Is determined to have reached a predetermined determination level, and the variable resistance value Rdx, which is the above-described parameters in the arithmetic element gate unit having the predetermined number of unit wiring groups, Coefficient R / Rdo and second coefficient Variable resistance value calculating means 12 for calculating the value of Rd (= Rdx / Rdo), each variable resistance value Rdx, the first coefficient R / Rdo, and the value of the second coefficient KRd (= Rdx / Rdo) are stored. The correction coefficient storage means 15 creates a predetermined correction table.

The operation of such an apparatus is executed only when a correction table is created.
On the other hand, FIG. 3B shows an example of an apparatus for calculating the delay time for each cell using the correction table.
That is, in FIG. 3B, the same input means 9 as described above and the correction coefficient storage means 15 are connected to each other, and from the information input to the input means 9, for each cell. A corrected resistance value calculating means 13 for determining a corrected resistance value Rdx ′ by calculating a resistance value Rd and multiplying the resistance value Rd by a correction coefficient KRd set by the correction table. The delay time calculation means 14 calculates the delay time (Tgate) of the calculation element gate section I from the delay time determination calculation formula (1) using the corrected resistance value Rdx ′ obtained by the No. 13 It is a delay time calculation device of the circuit.

That is, in the apparatus shown in FIG. 3B, the calculation operation is repeatedly executed by the number of cells constituting a predetermined circuit.
Further, the correction coefficient storage means 15 constitutes a correction table 16 in which predetermined values are stored corresponding to the number of unit wiring groups connected to the arithmetic element gate section I. Things are desirable.

In the circuit delay time arithmetic unit according to the present invention, the resistance value R, the capacitance values C1, C2, the intrinsic delay time TO, the intrinsic resistance value R0, etc. of the selected arithmetic element gate section are obtained. It is also possible to provide input means for storing in an appropriate storage means (not shown).
Further, although not shown in FIG. 3, in order to control the delay time arithmetic unit of such a circuit, a ROM incorporating a predetermined simulation program and the delay time determination arithmetic expression (1) and the ROM And a control means comprising a CPU for controlling each means.

FIG. 1 is a flowchart for explaining an operation procedure in a specific example of a circuit delay time calculation method according to the present invention. FIG. 1 (A) is a flowchart showing an example of a procedure for creating a correction table. FIG. 1B is a flowchart showing an example of a procedure for calculating the delay time of each cell using the correction table. FIG. 2 is an equivalent model of the circuit configuration of the logic cell when the circuit delay time calculation method according to the present invention is executed. FIG. 3 is a diagram for explaining a configuration of a specific example of a circuit delay time calculation apparatus according to the present invention, and FIG. 3A is a block diagram showing an example of an apparatus for creating a correction table. FIG. 3B is a block diagram showing an example of an apparatus for calculating the delay time of each cell using the correction table. FIG. 4 is a block diagram showing a configuration example of a logic cell that is a target for measuring delay time. FIG. 5 is a graph showing an example of measuring the delay time of a logic cell in the prior art. FIG. 6 is a circuit diagram equivalently showing the logic cell in FIG. 7A and 7B show a case where the delay time of the arithmetic element gate portion I ′ is calculated using the arithmetic element gate portion itself, and that the arithmetic element gate portion I ′ is determined by the resistance value Rd. It is a figure explaining the difference with the case where the substituted delay time is calculated | required. FIG. 8 is a graph showing a delay time increment Tout, which is a measurement result of FIGS. 7A and 7B. FIG. 9A and FIG. 9B are diagrams for explaining the difference in output voltage when the load connected to the arithmetic element gate unit I ′ is composed of only a capacitive load. FIG. 10 is an output waveform diagram (waveform rise) showing the measurement results in FIGS. 9 (A) and 9 (B). FIG. 11 is an output waveform diagram (waveform drop) showing the measurement results in FIGS. 9 (A) and 9 (B). FIG. 12 is a graph showing the results of individually obtaining variable resistance values Rdx defined in the present invention for a plurality of types of arithmetic element gate portions. FIG. 13 is a graph obtained by normalizing the graph of FIG. 12 and plotting the second coefficient KRd (= Rdx / Rdo) using the first coefficient R / Rdo as a parameter. FIG. 14 is a graph for explaining a method of detecting the second coefficient KRd (= Rdx / Rdo) from the first coefficient R / Rdo in the present invention.

Explanation of symbols

10 V (t) value calculating means 11 Discriminating means 12 Variable resistance value calculating means 13 Modified resistance value calculating means 14 Delay time calculating means 15 Correction coefficient storage means 16 Correction table I, I 'arithmetic element gate part H, H' line part

Claims (7)

In a semiconductor integrated circuit including a plurality of logic cells each including a predetermined arithmetic element gate section and a line including a unit wiring group in which a plurality of unit wirings are connected to the arithmetic element gate section, the arithmetic element gate In the circuit delay time calculation method for calculating the delay time of the part,
A resistance value when the arithmetic element gate portion is replaced with a resistance is represented by Rd, and the unit wiring group is equivalently represented by a single pi (π) model,
The equivalent resistance value of the equivalent resistance of the unit wiring group is represented by R, and the capacitance group connected to both ends of the equivalent resistance value (R) is represented by C1 and C2.
The relationship between the delay time (t) in the arithmetic element gate part and the output voltage (V (t)) of the arithmetic element gate part is expressed as follows: the resistance value (Rd) of the arithmetic element gate part and the unit wiring group are single Predetermined delay time judgment expression expressed as a function of the equivalent resistance value (R) of the equivalent resistance of the unit wiring group and the capacitance group (C1 and C2) when equivalently expressed by a pi (π) model When determining the respective delay times (Tgate) of the arithmetic element gate portion for each connection number of the unit wiring groups,
Calculating an initial specific resistance value (Rdo) as an initial value of the resistance value (Rd) of the arithmetic element gate portion;
Calculating a variable resistance value (Rdx) of the arithmetic element gate portion at a time when the value of the output voltage V (t) calculated by the delay time determination arithmetic expression reaches a predetermined determination level determined in advance; ,
Storing a correction coefficient calculated using the initial specific resistance value (Rdo), the variable resistance value (Rdx), and the equivalent resistance value (R) in a predetermined storage unit;
Connected to the arbitrarily selected arithmetic element gate portion for a logic cell composed of an arbitrarily selected arithmetic element gate portion and a line including a unit wiring group connected to the arithmetic element gate portion A correction coefficient corresponding to the ratio between the equivalent resistance value (R) of the equivalent resistance of the unit wiring group and the initial specific resistance value (Rdo) of the arithmetic element gate section is read from the storage means, and the arithmetic element gate Multiplying the resistance value (Rd) of the portion by the correction coefficient to calculate a corrected variable resistance value (Rdx ′);
Further, using the corrected delay time determination equation obtained by substituting the corrected variable resistance value (Rdx ′) into the resistance value (Rd) in the delay time determination equation, the arithmetic element gate unit And calculating the delay time (Tgate) of the circuit.   The correction coefficient is stored in a predetermined correction table format corresponding to the number of the unit wiring groups connected to the arithmetic element gate section in the storage means. The delay time calculation method of the circuit according to claim 1.   3. The circuit delay time calculation method according to claim 2, wherein the correction table is a lookup table.   The correction coefficient is set as a function of an initial specific resistance value (Rdo) of the arithmetic element gate unit and a variable resistance value (Rdx) of the arithmetic element gate unit. The delay time calculation method for a circuit according to any one of claims 1 to 3.   The variable resistance value (Rdx) of the arithmetic element gate unit is individually measured according to a simulation program determined in advance corresponding to the number of unit wiring groups connected to the arithmetic element gate unit. The circuit delay time calculation method according to claim 1, wherein: In a semiconductor integrated circuit including a plurality of logic cells each including a predetermined arithmetic element gate section and a line including a unit wiring group in which a plurality of unit wirings are connected to the arithmetic element gate section, the arithmetic element gate In the circuit delay time calculation device for calculating the delay time of the unit,
A resistance value when the arithmetic element gate portion is replaced with a resistance is represented by Rd, and the unit wiring group is equivalently represented by a single pi (π) model,
The equivalent resistance value of the equivalent resistance of the unit wiring group is represented by R, and the capacitance group connected to both ends of the equivalent resistance value (R) is represented by C1 and C2.
The relationship between the delay time (t) in the arithmetic element gate part and the output voltage (V (t)) of the arithmetic element gate part is expressed as follows: the resistance value (Rd) of the arithmetic element gate part and the unit wiring group are single Predetermined delay time judgment expression expressed as a function of the equivalent resistance value (R) of the equivalent resistance of the unit wiring group and the capacitance group (C1 and C2) when equivalently expressed by a pi (π) model When determining the respective delay times (Tgate) of the arithmetic element gate portion for each connection number of the unit wiring groups,
Means for calculating an initial specific resistance value (Rdo) as an initial value of the resistance value (Rd) of the arithmetic element gate portion;
Means for calculating a variable resistance value (Rdx) of the arithmetic element gate portion at a time when the value of the output voltage V (t) calculated by the delay time determination arithmetic expression reaches a predetermined determination level determined in advance; ,
Correction coefficient storage means for storing a correction coefficient calculated using the initial specific resistance value (Rdo), the variable resistance value (Rdx), and the equivalent resistance value (R);
Connected to the arbitrarily selected arithmetic element gate portion for a logic cell composed of an arbitrarily selected arithmetic element gate portion and a line including a unit wiring group connected to the arithmetic element gate portion A correction coefficient corresponding to a ratio between an equivalent resistance value (R) of the equivalent resistance of the unit wiring group and the initial specific resistance value (Rdo) of the arithmetic element gate portion is read from the correction coefficient storage means, and the calculation is performed. Corrected variable resistance value calculating means for calculating a corrected variable resistance value (Rdx ′) by multiplying the resistance value (Rd) of the element gate portion by the correction coefficient;
A corrected delay time determination formula obtained by substituting the corrected variable resistance value (Rdx ′) obtained by the corrected variable resistance value calculation means into the resistance value (Rd) in the delay time determination formula And a means for calculating and calculating a delay time (Tgate) of the arithmetic element gate section.   The correction coefficient storage unit includes a correction table in which predetermined values are respectively stored corresponding to the number of unit wiring groups connected to the arithmetic element gate unit. 6. A delay time calculation device for a circuit according to item 6.

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