JP4007854B2 - Sampling clock generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sampling clock generator applied to an optical scanning sampling system that scans a sample with light to acquire information on the sample.
[0002]
[Prior art]
Optical scanning type that scans the sample with light and generates a sampling clock synchronized with the scanning, and obtains sample information by sampling reflected light, fluorescence or transmitted light from the sample detected by a photodetector For example, a scanning confocal laser microscope is known as a sampling system.
[0003]
In the scanning confocal laser microscope, a galvano scanner or a resonant scanner is mainly used for optical scanning. In the resonant scanner, the mirror vibrates in a sinusoidal shape due to its operating principle. On the other hand, the galvano scanner may be driven in a sine wave shape to increase the screen update speed.
[0004]
When the angle of the mirror changes in a sine wave shape with time, the light irradiation position on the sample by optical scanning changes in a sine wave shape with time. In this way, when the light irradiation position on the sample by optical scanning changes in a sinusoidal shape with time, for example, the detection signal of the photodetector that detects reflected light, fluorescence or transmitted light from the sample is used as the system timing. When sampling is performed at equal time intervals (constant time intervals) by a crystal oscillator or the like that manages the sampling, the sampling positions on the sample are not evenly spaced as shown in FIG. For this reason, images with significant distortion are acquired at both ends and the center of the screen.
[0005]
In such a case, in order to obtain a distortion-free image, as shown in FIG. 14B, a time interval (hereinafter referred to as “unequal time interval”) in which the time for sampling in accordance with scanning is not constant. It is conceivable that the positional relationship (pixel positional relationship) on the sample is equally spaced in the finally obtained image.
[0006]
As described above, as a method for generating the sampling clock at unequal time intervals in accordance with the sinusoidal scanning, there are the following proposals.
[0007]
U.S. Pat. No. 527,131 (Japanese Patent No. 3121037) stores a sinusoidal velocity signal pattern in a ROM, outputs the ROM pattern in synchronization with one period of the scanner, and outputs it as a control signal by a multiplying D / A converter. A VCO output is obtained as a sampling clock. The ROM pattern is sequentially addressed by the sampling clock, the gain is adjusted by the multiplying D / A converter so that one cycle of the output matches the scanner cycle, and the VCO is read from the sampling clock generated by the VCO through the FV converter. The deviation is fed back.
[0008]
In Japanese Patent Laid-Open No. 7-154544, a multiplied clock synchronized with a PLL in one period of the scanner is generated, thereby addressing a ROM in which a speed pattern is stored. The ROM output is converted into a control signal by a multiplier and a D / A converter, and a sampling clock is obtained by a VF converter. The gain adjustment performed by the multiplier for the ROM pattern output is performed so that the ROM pattern (speed signal) is integrated to be converted into position information to match the effective image length.
[0009]
In Japanese Patent Application Laid-Open No. 2001-21829, a multiplication clock synchronized with a PLL is generated in one period of the scanner in the same manner as described above, thereby addressing a ROM in which a speed pattern is stored. The gain is adjusted by the multiplication type D / A converter so that one period of the ROM output coincides with the scanner period, and a sampling clock is obtained by giving it to the VCO as a control signal.
[0010]
On the other hand, the position of the galvano scanner can be controlled, and when the galvano scanner is driven by a sawtooth wave, as shown in FIG. 14C, the scanning position changes at regular intervals over time. . Therefore, for example, even if the detection signal of the photodetector that detects reflected light, fluorescence, or transmitted light of the sample is sampled at a constant time interval by a crystal oscillator that manages the timing of the system, the sampling position on the sample is not changed. Since the intervals are equal, an image having a significant distortion in the screen is not immediately acquired.
[0011]
Therefore, the sawtooth wave that drives the scanner stores the target position waveform in a memory, etc., and sequentially converts the data from digital to analog by a crystal oscillator or the like that manages the system timing, and supplies it to the drive circuit. A sampling method is common.
[0012]
[Problems to be solved by the invention]
As described above, in the case of sine wave drive, in all cases, a speed pattern is stored in the ROM in advance, and sampling clocks with unequal time intervals are obtained by the voltage controlled oscillation means while operating in synchronization with one period of the scanner. ing.
[0013]
Such a method is based on the premise that the scanner operates in an ideal sine wave shape, and pattern data is generated from mathematical considerations. However, when the scanner is actually mounted in the apparatus and used, various error factors are superimposed, and the linearity of the finally obtained image is not always in the best state. Although it is possible to cancel this distortion by correcting the data, a part of the data of several thousand points is corrected, and a long trial and error is required. Even if data is generated by a program in this work, a great deal of effort is required not only for the clock generator but also for the jig development.
[0014]
U.S. Pat. No. 527,131 (Japanese Patent No. 3121037) attempts to improve accuracy by feedback control based on comparison with the ROM pattern in the VCO portion. However, since the delay time of the ROM side circuit and the delay time of the FV converter side circuit do not match, there is a possibility that the frequency change of the sampling clock may be distorted.
[0015]
Similarly, in Japanese Patent Laid-Open No. 7-154544, the relationship between the lowest frequency and the highest frequency given to the VCO is mathematically defined as a sine wave as a ROM pattern. There is a possibility that it becomes a limit in absorbing the error factor. Therefore, there is a possibility that distortion cannot be completely removed at both ends of the image.
[0016]
In Japanese Patent Laid-Open No. 2001-21829, although the PLL is applied in the latter stage by the signal input synchronized with the operation of the scanner, since only the management of the scanner cycle is performed in the first place, the optical zoom can be changed by changing the scanner amplitude. If applied, the phase of the synchronizing signal for the scanner may shift, and the operating point of the entire circuit may be shifted. The reason is considered as follows. Since the comparator detects the zero cross of the sine wave signal of the motion detection coil, if the scanner swing angle is reduced by zooming, the signal amplitude of the motion detection coil is also reduced and the zero cross detection position is delayed. That is, when zooming is applied, a phenomenon occurs in which the field of view moves to the right (image is left). Since it is assumed that the speed pattern stored in the ROM completely matches the scanner operation without any phase delay, if a phase shift occurs due to zooming, the degree of image distortion will change.
[0017]
On the other hand, in the sawtooth wave drive of the galvano scanner, the servo is applied to the drive waveform input to manage the position (posture) of the scanner, but the adjustment of the drive circuit is optimized according to the frequency response of the scanner. There is a limit to following a sudden input change at the turning point. For this reason, considering the time for settling, the efficiency of the range that can be imaged for one cycle of the scanner while linearly driving deteriorates as the scanning speed increases. Increasing the scanning speed in the area where the scanner responds reduces the range that can be imaged and increases the ineffective period. If you are observing fluorescence with a scanning confocal laser microscope, The ratio of giving fluorescence fading to an unnecessary area other than the observation target range increases, which is not a preferable state.
[0018]
[Problems to be solved by the invention]
An object of the present invention is to perform sampling without image degradation in an optical scanning sampling system, so that sampling can be performed faithfully to the operation of the scanning means, linearity of the image can be automatically corrected, and phase shift due to zoom can be corrected. It is an object of the present invention to provide a sampling clock generator capable of effectively allocating a scanning range of a scanning means that does not occur to an image period with an arbitrary number of effective pixels.
[0019]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention has taken the following measures.
[0020]
A sampling clock generator according to an aspect of the present invention scans light from a sample and samples light from the sample detected by a photodetector based on a sampling clock synchronized with the scanning. In a sampling clock generator applied to an optical scanning sampling system for acquiring information, scanning means for reflecting or refracting light from a light source while vibrating and irradiating the sample with light, and speed information of the scanning means Speed information generating means for obtaining the phase, a phase shift means for absorbing a time delay from irradiation of the scanning light to the sample until generation of a sampling clock, and absolute value speed information by converting the speed information into an absolute value Generating means, first variable gain means for adjusting the absolute velocity information to a predetermined amplitude, and the scanning status of the scanning means A second variable gain means for correcting the amplitude by a continuous amount; an offset adjustment means for correcting the level; a voltage controlled oscillation means for generating a sampling clock having a frequency corresponding to the corrected absolute value speed information; And a sampling means corresponding to the scanning of the scanning means and a synchronizing means for managing the imaging period of the sample.
[0021]
According to one aspect of the present invention, the speed information obtained from the scanning unit is converted into an absolute value and supplied to the voltage controlled oscillation unit to obtain a sampling clock. At this time, the amplitude of the speed information is adjusted so that a predetermined number of sampling clocks are included in one cycle of the scanning means. However, since the shape of the speed information is used as it is for the clock frequency control, Sampling position deviation does not occur by always following the operation pattern. On the other hand, frequency adjustment for applying image linearity correction is also possible, and a sampling clock free from image distortion can be obtained.
[0022]
A preferred embodiment of the sampling clock generator described above is as follows. In addition, each following embodiment may be applied independently and may be applied in combination as appropriate.
(1) The control signal output to the voltage controlled oscillating means is based on a speed waveform of the scanning means generated by the speed information generating means. Since the shape of the speed information is used as it is for the clock frequency control, the operation pattern of the scanning means is always followed accurately and no sampling position deviation occurs.
[0023]
(2) The correction related to the scanning state of the scanning unit given to the first and second variable gain units and the offset adjusting unit is performed by using the velocity information having a constant amplitude regardless of the scanning amplitude of the scanning unit. A predetermined number of sampling clocks that are output from the voltage controlled oscillating means, and the absolute value so as to reduce the phase difference between this count cycle and the scanning cycle from the scanning means. The amplitude of the speed information is finely adjusted, and the level of the absolute value speed information to be given to the voltage controlled oscillation means is determined separately from the amplitude adjustment. Since speed information with a constant amplitude can be output regardless of the scanning amplitude of the scanner (that is, optical zoom), there is no time operating point deviation from the scanner in the subsequent circuit operation for cycle management. On the other hand, the absolute value speed information gain is finely adjusted so that the scanner period and the sampling clock counting period coincide with each other. However, since the minimum frequency given to the voltage controlled oscillation means can be adjusted separately, only the period can be adjusted. Therefore, it is possible to perform image linearity correction and obtain a sampling clock without image distortion.
[0024]
(3) A scanning position detecting unit that detects a scanning position on the sample by the scanning unit and a linearity correcting unit that detects and corrects the linearity of the image. Sampling clocks are obtained by converting velocity information obtained from the scanning means into absolute values and supplying them to the voltage controlled oscillation means. At this time, the amplitude of the speed information is adjusted so that a predetermined number of sampling clocks are included in one cycle of the scanning means. However, since the shape of the speed information is used as it is for the clock frequency control, Sampling position deviation does not occur by always following the operation pattern. On the other hand, a frequency adjustment is also performed while performing image linearity correction, and a sampling clock free from image distortion can be obtained.
[0025]
(4) The linearity correction unit acquires a scanning position signal representing the scanning position of the scanning unit obtained by the scanning position detection unit at the timing of the sampling clock generated by the voltage controlled oscillation unit, and n The level of the absolute value speed information in the second gain variable means is determined so that the change amount of the scanning position for each pixel becomes constant. Since the minimum frequency given to the voltage-controlled oscillation means can always be adjusted while confirming the actual displacement amount of the scanning means at sampling points separated by an arbitrary amount, the sampling clock is generated while image linearity correction is performed.
[0026]
(5) The speed information generation means further includes selection means for generating at least one speed information of the scanning means and selecting the generated at least one speed information. An appropriate combination of accuracy and cost can be realized in the speed information input to the circuit for generating the sampling clock.
[0027]
(6) The synchronization means determines an imaging effective start point and period based on the sampling clock output from the voltage controlled oscillation means. Since the number of sampling clocks included in one period of the scanning unit is determined from the number of clocks from the scanning start point of the scanning unit to the start point of the image period and the number of effective pixels of the image, the number of sampling clocks included in one cycle of the scanning unit is determined. Any number of effective pixels can be efficiently allocated as an image period.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0029]
(First embodiment)
FIG. 1 is a block diagram of a scanning confocal laser microscope to which a sampling clock generator according to a first embodiment of the present invention is applied. The microscope body 1 of the scanning confocal laser microscope to which the sampling clock generator according to this embodiment is applied is configured as follows.
[0030]
Laser light as a spot light for scanning the focal plane (surface) of the sample 11 is emitted from the laser light source 6. The laser light emitted from the laser light source 6 is guided to the mirror 7, and the laser light reflected by the mirror 7 passes through the half mirror 8 and is guided to the two-dimensional scanning mechanism 5. The two-dimensional scanning mechanism 5 is a mechanism for two-dimensionally scanning the laser light from the laser light source 6 obtained through the mirror 7 and has the following configuration. The two-dimensional scanning mechanism 5 performs XY scanning of the laser beam under the control of the two-dimensional scanning drive control circuit 4. For example, the two-dimensional scanning mechanism 5 includes a resonance scanner for scanning in the X-axis direction and a galvano scanner for scanning in the Y-axis direction, and swings the mirrors of these scanners in the X-axis direction and the Y-axis direction, respectively ( The optical path of the laser beam with respect to the objective lens 10 can be swung in the XY directions.
[0031]
The revolver 9 holds a plurality of objective lenses 10 having different magnifications. By switching the revolver 9, the objective lens 10 having a desired magnification is arranged in the observation optical path of the microscope. be able to. The revolver 9 can be moved in the optical axis direction (vertical direction) by the Z-axis drive control circuit 16. Laser light from the two-dimensional scanning mechanism 5 irradiates the sample 11 on the stage 12 through the objective lens 10 disposed on the optical axis while performing two-dimensional scanning. The stage 12 is used for mounting the sample 11.
[0032]
The reflected light from the sample 11 reaches the half mirror 8 via the objective lens 10 and the two-dimensional scanning mechanism 5 through a path opposite to the incident light. The reflected light incident on the half mirror 8 is reflected by the half mirror 8 and guided to the detection system. The detection system includes a lens 13, a pinhole plate 14, and a photodetector 15. The lens 13 condenses the reflected light from the two-dimensional scanning mechanism 5 obtained through the half mirror 8. The pinhole plate 14 has a pinhole having a required diameter, and is arranged so that the pinhole comes to the focal position of the lens 13 in front of the light receiving surface of the photodetector 15. The light detector 15 is a light detection element that converts light obtained through the pinhole into an electric signal corresponding to the light amount.
[0033]
Note that the photodetector 15, the two-dimensional scanning drive control circuit 4, and the Z-axis drive control circuit 16 are each connected to a microscope input / output circuit 17. The microscope input / output circuit 17 exchanges data (signals) between the microscope main body 1 of the confocal scanning laser microscope and an external device (computer 2 in this embodiment). That is, the microscope input / output circuit 17 sends the signal photoelectrically converted by the photodetector 15 to the computer 2 together with the timing signal from the two-dimensional scanning drive control circuit 4, and also two-dimensionally scans various control signals from the computer 2. It has a function of sending to the drive control circuit 4, the Z-axis drive control circuit 16, and other microscope internal functions not shown.
[0034]
The computer 2 includes a control circuit 18 and an image input circuit 19. The control circuit 18 controls the computer 2 to appropriately execute a command input by an operator using an input unit (not shown). The image input circuit 19 inputs a signal photoelectrically converted by the photodetector 15 and a timing signal from the two-dimensional scanning drive control circuit 4. The computer 2 can obtain the surface information of the sample 11 by displaying an image detected by the photodetector 15 on the monitor 3 based on these input signals.
[0035]
The sampling clock generator in the first embodiment is the same as the scanning confocal laser microscope described above, except for the two-dimensional scanning mechanism 5 and a part of the two-dimensional scanning drive control circuit 4 (resonant scanner for X-axis direction scanning and timing signal). For example, a configuration as shown in FIG. 2 is provided.
[0036]
The resonance scanner 21 vibrates the mirror in a sine wave shape by a signal from the drive circuit 22. The drive circuit 22 self-oscillates based on a mirror speed signal by a speed pickup coil built in the resonance scanner 21, and its drive amplitude is controlled by feedback control.
[0037]
The speed input selection circuit 23 is free according to the type of output signal from the drive circuit 22 (for example, the drive circuit 22 may output a position signal or a synchronization signal instead of outputting a speed signal). This is a circuit for selecting an input to the sampling clock generator according to the present embodiment, and this speed input selection circuit 23 allows the sampling clock generator to be used regardless of the scanning means and the drive circuit. For example, when a position signal is output from the drive circuit 22, the signal may be converted into a speed signal. In the present embodiment, for example, a pickup coil signal (sense signal: Sens) and a signal (SYNC) indicating the direction thereof are given from the drive circuit 22. The relationship between these signals is shown in FIG. FIG. 3B is a diagram illustrating a circuit example of the speed input selection circuit 23. The speed input selection circuit 23 shown in FIG. 3B includes a band pass filter 33 (BPF) and a multiplexer 34. The band pass filter 33 has a center frequency at the resonance frequency of the resonance scanner 21. Thereby, when the SYNC signal passes, a sinusoidal signal is generated. The signal selected by the multiplexer 34 is output as a velocity signal (Velocity). Then, the phase shift circuit 60 absorbs the time (that is, time delay) from the irradiation of the scanning light to the sample to the generation of the sampling clock. Thereafter, the amplitude is adjusted to a predetermined amplitude by the AGC circuit 24 and input to the absolute value circuit 25 and the comparator 26.
[0038]
The comparator 26 generates a CYCLE signal in which the H level and the L level are switched at the zero cross position of the Velocity signal (a position where + and − are switched). The Velocity signal that has passed through the absolute value circuit 25 is gain-adjusted by the variable gain amplifier 27, the offset voltage given by the bias circuit 28 is added by the adder 61, and then the voltage-controlled oscillator 29 (hereinafter “VCO”) as the Control signal. It is given). The VCO 29 outputs a sampling clock (hereinafter referred to as “SCLK”). The synchronization circuit 30 receives SCLK from the VCO and generates an image valid period signal (hereinafter referred to as “DE”) and a timing signal (hereinafter referred to as “CLR”).
[0039]
The phase comparator 31 receives the CYCLE signal and the CLR, compares the phases thereof, and outputs an output signal corresponding to the phase difference to a low-pass filter 32 (hereinafter referred to as “LPF”). The signal that has passed through the low-pass filter 32 becomes a gain control signal (gain) of the variable gain amplifier 27.
[0040]
The operation of the sampling clock generator according to the first embodiment configured as described above will be described with reference to FIGS.
[0041]
First, when the resonant scanner 21 starts operating by the drive circuit 22, the mirror position becomes a sinusoidal vibration locus as shown in FIG. In this case, the mirror position (FIG. 4 (a)), the Sens signal (FIG. 4 (b)), and the SYNC signal (FIG. 4 (c)) are in the relationship shown in the figure. Here, it is assumed that the speed signal selection circuit 23 selects the Sens signal by setting means (not shown) in order to increase the sampling accuracy. The Sens signal is output as a Velocity signal by the multiplexer 34 (FIG. 4D).
[0042]
Subsequently, the Velocity signal output from the speed input selection circuit 23 is input to the phase shift circuit 60. Since there is a time delay of the circuit in the generation of the sampling clock, it is not output immediately corresponding to the position instructed by the resonant scanner 21, and the actually sampled image is shifted from the originally desired position. End up. Since unequally spaced sampling clocks are output, this shift causes image distortion. Therefore, the phase shift circuit 60 absorbs this time delay and adjusts the phase of the Velocity signal so that the light irradiation position and the sampling clock generation are aligned. The Velocity signal whose phase has been adjusted in this way is input to the AGC circuit 24, and is adjusted so that the amplitude change of the Velocity signal associated with the optical zoom of the resonant scanner 21 is canceled and the signal always has a constant amplitude. . Next, the Velocity signal is converted to a signal having only a positive amplitude as shown in FIG. 4E by passing through the absolute value circuit 25, while the Velocity signal input to the comparator 26 is Compared with the zero level at 26 (that is, whether the Velocity signal is positive or negative), the CYCLE signal shown in FIG. Since the Velocity signal is adjusted to have a constant amplitude by the AGC circuit 24, the tilt angle across the zero cross point due to zooming does not change, so that no phase shift occurs in the CYCLE signal.
[0043]
The Velocity signal converted to an absolute value by the absolute value circuit 25 is gain-adjusted by the variable gain amplifier 27, and a predetermined offset voltage output from the bias circuit 28 is added by the adder 61, and then the Control signal (FIG. 4 (g) )) To the VCO 29. The VCO output becomes SCLK (FIG. 4 (h)).
[0044]
In this case, gain adjustment by the variable gain amplifier 27 is performed by feedback control as described in detail below.
As shown in FIG. 5, the effective period N of the image _EN Is 1024 pixels and the imaging efficiency for scanning is 95%, the total number of clocks is 2156 for one period of the resonant scanner 21, and the front invalid period N _L Is 27 pixels, rear invalid period N _T (= N _L ) Is 27 pixels. When this is set in the synchronization circuit 30 by an input means (not shown), the synchronization circuit 30 outputs DE and CLR while counting SCLK output from the VCO 29 by the predetermined number (= 2156).
[0045]
The phase comparator 31 compares the phases of the CYCLE signal (FIG. 4 (f)) and CLR (FIG. 4 (i)), and outputs an error signal corresponding to the phase difference (FIG. 4 (j)). The error signal is smoothed by the LPF 32 to obtain a gain signal (FIG. 4 (k)), and the gain of the variable gain amplifier 27 is adjusted.
[0046]
The DC level of the Velocity signal output from the bias circuit 28 is adjusted to a level that ultimately provides the best image linearity. This level determines the lowest frequency of the output of the VCO 29. In the VCO 29, the frequency of SCLK rises and falls according to the shape of the Velocity signal with reference to this frequency. For example, when the gain is high and the voltage difference of the Velocity signal is large, the frequency of SCLK becomes high. For this reason, 2156 SCLK counting times are faster than one scanning period of the resonant scanner 21. On the contrary, when the gain is low and the voltage difference of the Velocity signal is small, the frequency of SCLK is low. For this reason, the counting time of 2156 SCLKs is delayed. As described above, the phase comparator 31 always controls the gain signal so that there is no deviation between the CYCLE signal and the CLR.
[0047]
Therefore, the amplitude of the Velocity signal given to the VCO 29 is adjusted by the control as described above so that the time when 2156 SCLKs that accelerate / decelerate according to the shape of the Velocity signal coincide with one period of the resonant scanner 21 is matched. Will be. Finally, SCLK, which is the output of the VCO 29, becomes a clock with a frequency change reflecting the velocity waveform of the resonant scanner 21, and a sampling clock is generated at a position and time at which the amount of change in the mirror position is equally spaced.
[0048]
As described above, since the frequency change of SCLK output from the VCO 29 is generated from the velocity waveform itself of the resonant scanner 21, the acceleration / deceleration change within the cycle is also directly reflected. For this reason, according to the present embodiment, it is possible to absorb fluctuations that cannot be obtained with an approximate waveform. That is, in the configuration according to the present embodiment, it means that no sampling position deviation occurs. Further, the AGC circuit 24 does not cause a phase shift of the CYCLE signal as a reference for phase comparison with the operation of the resonance scanner 21 by zooming, so that a stable sampling clock is always obtained regardless of zooming.
[0049]
In the first embodiment described above, the reciprocal sampling has been described as an example. However, if the half cycle side of the effective pixel period signal in the synchronization circuit 30 is masked, one-side sampling is naturally possible. In addition, the image period and the number of effective pixels are also variable. In particular, conditions can be set without considering the mathematical approximation of the scanner operation.
(Second Embodiment)
FIG. 6 shows a schematic configuration of the sampling clock generator according to the second embodiment. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. In the second embodiment, in order to directly detect the mirror position of the resonant scanner 21, the laser beam output from the laser light source 35 and reflected by the mirror 21 is a position detection element 37 (hereinafter referred to as "PSD"). Detected). The laser light source 35 is, for example, the same as the laser light source 6 in FIG. 1, and is an optically branched laser beam in the scanning confocal laser microscope after the X scanning resonance scanner. Alternatively, a semiconductor laser or the like provided separately for directly detecting the mirror position of the resonant scanner 21 may be used. The output of the PSD 37 is amplified by an amplifier 38 and output as a sinusoidal position signal corresponding to the mirror position of the resonant scanner 21. Similarly to the first embodiment, the phase shift circuit 60 absorbs a delay from the irradiation of the scanning light sample to the generation of the sampling clock.
[0050]
The speed input selection circuit 36 can freely select the input to the sampling clock generator of the present invention as in the first embodiment. The speed input selection circuit 36 does not depend on the scanning means or the drive circuit, and the second input of the present invention. The sampling clock according to the embodiment is provided so as to be applicable to a scanning confocal laser microscope. In the present embodiment, a Position signal indicating the mirror position of the resonance scanner 21, a pickup coil signal (Sens) output from the drive circuit 22, and a signal (SYNC) indicating the direction thereof are given. The relationship between these signals is shown in FIG. FIG. 7B shows an example of the configuration of the speed input selection circuit 36. The SYNC signal passes through a bandpass filter 43 having a center frequency at the resonance frequency of the resonance scanner 21, and the Position signal passes through a differentiation circuit 44. . The band pass filter 43 and the differentiating circuit 44 each generate a sine wave signal, and the signal selected by the multiplexer 45 is output as a velocity signal (Velocity).
[0051]
When the operation of the phase comparator 42 is stabilized, the phase comparator 42 outputs a LOCK signal as a notification signal to the linearity correction circuit 41.
[0052]
On the other hand, the Position signal of the resonant scanner 21 is adjusted to an appropriate amplitude by the AGC circuit 39, converted to digital data by the A / D converter 40, and given to the linearity correction circuit 41. The linearity correction circuit 41 generates an A / D conversion timing signal Convert from the SCLK, DE, and LOCK signals and outputs them to the A / D converter 40. The linearity correction circuit 41 generates an OFFSET signal for offsetting the Control signal applied to the VCO 29. For example, as shown in FIG. 8, the linearity correction circuit 41 includes a frequency divider 46, a memory 47, a CPU 48, a D / A converter 49, a switch 50, and a fixed bias 51. Here, it is assumed that the initial value of the D / A converter 49 is set to the same value as the level of the fixed bias 51. The offset amount of the Control signal given to the VCO 29 is switched from a fixed value to an OFFSET signal generated by the D / A converter 49 by the switch 50. The switch 50 operates according to the LOCK signal from the phase comparator 42.
[0053]
In the configuration as described above, the second embodiment will be described on the assumption that the position signal is selected by the setting means (not shown) in the speed input selection circuit 36 in order to maximize the sampling accuracy. The Position signal is converted into a Velocity signal by the differentiating circuit 44 shown in FIG.
[0054]
Subsequent basic operations for generating SCLK are the same as those in the first embodiment, and a stable sampling clock can be obtained. However, when the resonant scanner 21 is mounted on a scanning confocal laser microscope or the like, various error factors are superimposed, and the linearity of the finally obtained image is not always in the best state. This is because, even if the time required for generating a predetermined number of clocks matches with one period of the resonant scanner 21, non-linearity as shown in FIG. 9 may remain particularly at the position in the screen in the X direction. is there. That is, when the reference scale is observed, the actual speed ratio of the laser beam scanning on the scale at both ends and the center of the screen and the speed ratio at the ends and the center of the Velocity signal are determined by the optical system and A state that does not completely match may occur due to circuit distortion or the like.
[0055]
For example, FIG. 9A shows a case where the dimensions at both ends of the screen appear to be wider than the center, and the clock is too fast at both ends and too slow at the center with respect to scanning. FIG. 9B shows the opposite case where the dimensions of both ends of the screen appear to be smaller than the center. The clock is too slow at both ends and too fast at the center. is there.
[0056]
Hereinafter, the correction action for the above-described distortion in the second embodiment will be described. When the phase comparison enters the steady state in the phase comparator 42 and the generation timing of SCLK coincides with the operation of the resonant scanner 21, the linearity correction circuit 41 that receives the notification (LOCK signal) from the phase comparator 42 corrects the correction. Start operation. That is, a sine-wave Position signal corresponding to the mirror position of the resonant scanner 21 is adjusted to an appropriate amplitude by the AGC circuit 39, converted to digital data by the A / D converter 40, and given to the linearity correction circuit 41. . This conversion timing is set to the timing of SCLK every n pixels during the image effective period. Here, n = 4. When n = 4 is set by a setting means (not shown), the frequency divider 46 divides SCLK in DE, and sends a conversion pulse to the A / D converter 40 as a Convert signal once for four pixels. Position signal (mirror position of the resonant scanner 21) data at that moment is output from the A / D converter 40 and stored in the memory 47. The position data of the resonant scanner 21 obtained by sampling in the A / D converter 40 should be data that increases (or decreases) by a constant value when considered from the original SCLK generation purpose. This is because the scanning positions of the scanner change at unequal time intervals in time, so that SCLKs having unequal time intervals are generated so as to be sampled at the equal interval positions.
[0057]
When the number of effective pixels in one line is 1024 pixels, the CPU 48 obtains 256 position data from the memory 47 by scanning the resonance scanner 21 for one line. The amount of change between the sampled position data reflects the linearity of sampling as shown in FIGS. 9A and 9B when viewed in the order of acquisition.
[0058]
Here, for example, consider the case where the sampling state is such that the dimensions at both ends of the screen appear to expand as shown in FIG. In this case, a position data group in which the change amount of the position data is small at both ends and large at the center should be obtained. This is because, for example, the DC component of the control signal of the VCO 29 given by the fixed bias 51 before the switch 50 is switched after receiving the LOCK signal from the phase comparator 42 is large, and the SCLK frequency is generally increased. Means it is working. Still, since one period of the resonant scanner 21 and a predetermined number of times (2156 if the same as in the first embodiment) are generated, the SCLK is output, the gain in the variable gain amplifier 27 is adjusted so that the period is consistent. The setting is set to be low, and it is stable in a state where the frequency modulation ratio of SCLK is small. This is a state where the clock is too fast at both ends with respect to the scan and too slow at the center.
[0059]
Subsequently, the CPU 48 determines linearity from the obtained data group, and sets a correction value related thereto in the D / A converter 49, thereby generating an OFFSET signal for offsetting the control signal of the VCO 29. In this case, the CPU 48 must lower the offset of the control signal of the VCO 29 for the reason described above. The CPU 48 sets a correction value that is lower than the level of the fixed bias 51 in the D / A converter 49. As a result, the level of the control signal of the VCO 29 is lowered. When the level of the control signal of the VCO 29 is lowered, the operating point of the VCO 29 is changed, and the SCLK frequency is lowered as a whole and output. In this case, the clocks at both ends of the image are delayed. Since the number of clocks in one cycle is reduced as it is, the gain given to the Velocity signal is increased by the function of the gain loop so that 2156 SCLKs are counted, and the clock frequency ratio in the central portion is increased. In the present embodiment, the sampling at the linearity correction circuit 41 matches the actual speed ratio of the scanning laser beam at both ends and the center of the screen with the frequency ratio at the ends and center of the screen in the sampling clock. As shown in FIG. 9C, the linearity is finally improved. However, since the operating point of the gain loop is changed by changing the offset of the Velocity signal, the linearity correction loop time constant needs to be sufficiently lower than the gain loop time constant.
[0060]
In addition, when the linearity shows a distribution as shown in FIG. 9B, the linearity is improved as shown in FIG. 9C by correcting the offset in the direction opposite to the above description. To do.
[0061]
As described above, according to the second embodiment, as in the first embodiment, the sampling position is not shifted, and a stable sampling clock is always obtained regardless of the zoom. Since the scanning position of the resonance scanner 21 is detected at the timing of the sampling clock and the frequency modulation ratio of the sampling clock generated by the VCO 29 is adjusted from the rate of change, the linearity of the obtained image can be corrected. Yes. Here, the example in which the position data is acquired every four pixels has been described, but of course, there is no problem if the position data is acquired every other number of pixels.
[0062]
Similarly to the first embodiment, if the half cycle side of the effective pixel period signal in the synchronizing circuit 30 is masked, one-side sampling is of course possible, and the image period and the number of effective pixels are also variable. Conditions can be set without considering mathematical approximation.
[0063]
(Third embodiment)
FIG. 10 shows a schematic configuration of a sampling clock generator according to the third embodiment. 10, the same parts as those in FIG. 1 or FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 10, a galvano scanner 52 is used as a scanner for scanning in the X-axis direction. Since the galvano scanner 52 normally has a sensor for position detection therein, its Position signal can be obtained directly. The drive circuit 53 controls the operation of the galvano scanner 52 so as to follow the position instruction input by feedback control using a position sensor built in the galvano scanner 52. Similarly to the first embodiment, the phase shift circuit 60 absorbs a delay from the irradiation of the scanning light sample to the generation of the sampling clock.
[0064]
The differentiating circuit 54 differentiates the Position signal and converts it into a Velocity signal. The Velocity signal is input to the AGC circuit 24, adjusted to a predetermined amplitude, and input to the absolute value circuit 25 and the comparator 26. The comparator 26 generates a CYCLE signal in which the H level and the L level are switched at the zero cross position of the Velocity signal. The Velocity signal converted into an absolute value by the absolute value circuit 25 is gain-adjusted by the variable gain amplifier 27, the offset voltage output from the linearity correction circuit 41 is added by the adder 61, and then given to the VCO 29 as a Control signal. It is done. The VCO output becomes the sampling clock (SCLK).
[0065]
The synchronization circuit 55 receives SCLK and generates an image valid period signal (DE) and a timing signal (CLR).
[0066]
The phase comparator 42 compares the phases of the CYCLE signal and CLR and outputs a signal corresponding to the phase difference. The output signal from the phase comparator 42 passes through the low pass filter 32 and becomes a gain control signal (gain) of the variable gain amplifier 27. When the operation of the phase comparator 42 is stabilized, the phase comparator 42 generates a LOCK signal as a notification signal to the linearity correction circuit 41.
[0067]
On the other hand, the Position signal of the galvano scanner 52 is adjusted to an appropriate amplitude by the AGC circuit 39, converted to digital data by the A / D converter 40, and given to the linearity correction circuit 41. As in the second embodiment, the linearity correction circuit 41 generates an A / D conversion timing signal Convert from the SCLK, DE, and LOCK signals, and outputs them to the A / D converter 40. The linearity correction circuit 41 generates an OFFSET signal for offsetting the Control signal applied to the VCO 29. The configuration of the linearity correction circuit 41 may be the same as that of the second embodiment.
[0068]
Next, the operation of the present invention configured as described above will be described. When a sawtooth wave is applied to the drive circuit 53 of the galvano scanner 52, the galvano scanner 52 starts to operate, and the galvano scanner 52 operates according to the sawtooth wave vibration locus of FIG. Therefore, the change in position is equally spaced with respect to time, and a Velocity signal as shown in FIG. 11B is obtained.
[0069]
Subsequently, the Velocity signal is input to the AGC circuit 24, and is adjusted so that the amplitude change of the Velocity signal accompanying the optical zoom of the galvano scanner 52 is canceled and the signal always has a constant amplitude. Next, the Velocity signal is converted into a signal having only a positive amplitude as shown in FIG. 11C by passing through the absolute value circuit 25. On the other hand, the Velocity signal input to the comparator 26 is compared with the zero level by the comparator 26 (that is, whether the Velocity signal is positive or negative), and becomes the CYCLE signal shown in FIG. Since this CYCLE signal has been adjusted to have a constant amplitude by the AGC circuit 24, the tilt angle across the zero cross point does not change due to zooming, so no phase shift occurs in the CYCLE signal.
[0070]
The Velocity signal that has passed through the absolute value circuit 25 is gain-adjusted by the variable gain amplifier 27, an appropriate offset voltage is added by the linearity correction circuit 41, and then supplied to the VCO 29 as a Control signal (FIG. 11 (e)). The output of the VCO becomes SCLK (FIG. 11 (f)).
[0071]
In the third embodiment, since the position signal is sawtooth wave drive, the Velocity signal shows a certain level during the scanning period, and shows a higher level in the retrace period where the operation is steep. However, since the band of the galvano scanner 52 is limited, it cannot respond at the turning point of the waveform, and a curved portion is generated in the Velocity signal corresponding to both ends of the image. In consideration of the individual band variation of the galvano scanner 52 and the like, the conventional general sampling circuit avoids this curved portion and forms an image. Therefore, the ratio of the imaging period to the scanning range is inevitably limited. However, in this embodiment, since the timing of SCLK is adjusted by the VCO 29, there is no need to worry about it.
[0072]
The gain adjustment by the variable gain amplifier 27 is performed by feedback control as described in detail below.
As shown in FIG. 12, the effective period N of the image _EN Is 1024 pixels, and the imaging efficiency for scanning is 95% (conventionally 80% or less). Assuming that the sawtooth waveform is formed so that the speed of the blanking period is four times the scanning speed in the image acquisition direction, the total number of clocks is 1348 for one cycle of the galvano scanner 52, and the front invalid period N _L Is 27 pixels, rear invalid period N _T (= N _L ) Is 27 pixels, blanking period N _R Becomes 270 pixels. When this is set in the synchronization circuit 55 by an input means (not shown), the synchronization circuit 55 outputs DE and CLR while counting SCLK obtained by the VCO 29 by the predetermined number. The phase comparator 42 compares the CYCLE signal (FIG. 11 (d)) and CLR (FIG. 11 (g)) and outputs an error signal corresponding to the difference. (FIG. 11 (h)) By smoothing this with the LPF 32, a gain signal (FIG. 11 (i)) is obtained, and the gain of the variable gain amplifier 27 is adjusted. As a result, the amplitude of the Velocity signal applied to the VCO 29 is adjusted so that the time when 1348 SCLKs that accelerate / decelerate according to the shape of the Velocity signal coincide with one cycle of the galvano scanner 52. .
[0073]
By the way, as described in the second embodiment, when the offset amount given by the fixed bias 51 is not appropriate immediately after the gain loop is stabilized, the linearity of the image is not perfect. Since the Velocity signal is at a substantially constant level over the period of the galvano scanner 52, unlike the case of the second embodiment, the distribution of linearity is the both ends of the image as shown in FIGS. 13 (a) and 13 (b). It is conceivable that only a part of the curve, that is, the curve portion of the Velocity signal, deteriorates slightly. However, such a problem is automatically solved by the linearity correction circuit 41 as shown in FIG. 13C, as in the second embodiment.
[0074]
As described above, in this embodiment, the frequency change of SCLK generated by the VCO 29 is made from the velocity waveform itself of the galvano scanner 52 and directly reflects the acceleration / deceleration change within the period. Sampling position deviation does not occur. In addition, it can be efficiently used up to the vicinity of the turning point of the waveform that cannot be imaged conventionally. In other words, it means that laser irradiation of the sample in a useless range can be suppressed. Further, because of the operation of the AGC circuit 24 described above, the CYCLE signal that is a reference for phase comparison does not cause a phase shift from the operation of the galvano scanner 52 by zooming, so that a stable sampling clock is always obtained regardless of zooming.
[0075]
Furthermore, the actual scanning position of the galvano scanner 52 is detected at the timing of the sampling clock, and the frequency modulation ratio of the sampling clock generated by the VCO 29 is adjusted from the rate of change, so that the linearity of the obtained image is also improved. It can be corrected.
[0076]
In addition, by using a triangular wave, it is possible to perform both-side sampling, and the image period and the number of effective pixels are also variable. In particular, conditions can be set without considering the mathematical approximation of the operation of the scanner.
[0077]
The present invention is not limited to the above-described embodiments. Of course, various modifications can be made without departing from the scope of the present invention.
[0078]
【The invention's effect】
According to each embodiment of the present invention, a sample is generated by causing the sample to scan with light, generating a sampling clock synchronized with the scan, and sampling the reflected light, fluorescence, or transmitted light of the sample detected by the photodetector. In the sampling clock generator applied to the optical scanning sampling system that acquires the above information, for example, the following effects can be obtained, although not all the effects obtained in the present embodiment.
(1) The operation pattern of the scanning means is always followed and no sampling position deviation occurs.
(2) No phase shift due to optical zoom in the scanning means occurs.
(3) Any number of effective pixels can be efficiently allocated to the image period with respect to the scanning range of the scanner.
(4) No image distortion occurs.
(5) An appropriate combination of accuracy and cost can be selected for the speed information given to the sampling clock generation circuit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a scanning confocal laser microscope equipped with a first embodiment of the present invention.
FIG. 2 is a configuration diagram of the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of a speed input selection circuit used in the first embodiment.
FIG. 4 is a timing chart for explaining the operation of the first embodiment.
FIG. 5 is a diagram showing a correspondence between scanning and an imaging period according to the first embodiment.
FIG. 6 is a configuration diagram of a second embodiment of the present invention.
FIG. 7 is an explanatory diagram of a speed input selection circuit used in the second embodiment.
FIG. 8 is a configuration diagram of a linearity correction circuit used in the second embodiment.
FIG. 9 is a diagram illustrating nonlinearity remaining in an image in the second embodiment.
FIG. 10 is a configuration diagram of a third embodiment of the present invention.
FIG. 11 is a timing chart for explaining the operation of the third embodiment.
FIG. 12 is a diagram illustrating a correspondence between scanning and an imaging period according to the third embodiment.
FIG. 13 is a diagram illustrating nonlinearity remaining in an image according to the third embodiment.
FIG. 14 is an explanatory diagram of the scanning position and the timing of the sampling clock.
[Explanation of symbols]
1 ... Microscope body
2 ... Computer
3 ... Monitor
4 ... Two-dimensional scanning drive control circuit
5 ... Two-dimensional scanning mechanism
6 ... Laser light source
7 ... Mirror
8 ... Half mirror
9 ... Revolver
10 ... Objective lens
11 ... Sample
12 ... Stage
13 ... Lens
14 ... Pinhole plate
15 ... Photodetector
16 ... Z-axis drive control circuit
17 ... Microscope input / output circuit
18 ... Control circuit
19. Image input circuit
21 ... Resonant scanner
22 ... Drive circuit
23 ... Speed input selection circuit
24 ... AGC circuit
25. Absolute value circuit
26 ... Comparator
27 ... Variable gain amplifier
28 ... Bias circuit
29 ... Voltage controlled oscillator (VCO)
30 ... Synchronous circuit
31 ... Phase comparator
32 ... Low-pass filter (LPF)
33 ... Bandpass filter
34 ... Multiplexer
35 ... Laser light source
36 ... Speed input selection circuit
37 ... Position detecting element (PSD)
38 ... Amplifier
39 ... AGC circuit
40 ... A / D converter
41. Linearity correction circuit
42 ... Phase comparator
43 ... Band pass filter
44. Differentiation circuit
45. Multiplexer
46 ... frequency divider
47 ... Memory
48 ... CPU
49 ... D / A converter
50 ... Switch
51: Fixed bias
52 ... Galvano scanner
53 ... Drive circuit
54. Differentiation circuit
55. Synchronous circuit
60: Phase shift circuit
61 ... Adder

Claims (7)

Applied to an optical scanning type sampling system that scans light with a sample and obtains information of the sample by sampling light from the sample detected by a photodetector based on a sampling clock synchronized with the scanning In the sampling clock generator,
Scanning means for reflecting or refracting light from a light source while oscillating, and irradiating the sample with light;
Speed information generating means for obtaining speed information of the scanning means;
A phase shift means for absorbing a time delay between irradiation of the scanning light to the sample and generation of a sampling clock;
First variable gain means for correcting its amplitude by an amount related to the scanning status of the scanning means;
Means for generating absolute value speed information by converting the speed information into an absolute value;
Second variable gain means for adjusting the absolute value speed information to a predetermined amplitude;
Offset adjusting means for correcting the level;
Voltage-controlled oscillation means for generating a sampling clock having a frequency corresponding to the corrected absolute value speed information;
A sampling clock generator comprising: a sampling clock corresponding to scanning of the scanning means; and a synchronizing means for managing an imaging period of the sample. 2. The sampling clock generator according to claim 1, wherein the control signal output to the voltage controlled oscillation means is based on a velocity waveform of the scanning means generated by the velocity information generating means. Sampling clock generator. The sampling clock generator according to claim 1,
The correction related to the scanning status of the scanning means given to the first and second variable gain means and the offset adjusting means is:
The speed information having a constant amplitude is output regardless of the scanning amplitude of the scanning means,
A predetermined number of sampling clocks that are output from the voltage controlled oscillation means are counted, and the amplitude of the absolute velocity information is finely adjusted so as to reduce the phase difference between this count cycle and the scanning cycle from the scanning means. Yes,
A sampling clock generator for determining the level of the absolute speed information to be given to the voltage controlled oscillation means separately from the amplitude adjustment. The sampling clock generator according to claim 1,
Scanning position detecting means for detecting a scanning position on the sample by the scanning means;
A sampling clock generator further comprising linearity correction means for detecting and correcting linearity of an image. 5. The sampling clock generator according to claim 4, wherein the linearity correction means generates a scanning position signal representing a scanning position of the scanning means obtained by the scanning position detection means by the voltage controlled oscillation means. Sampling clock generator characterized in that it obtains at the timing of the sampling clock and determines the level of the absolute value speed information in the offset adjusting means so that the amount of change in scanning position for every n pixels is constant. . 6. The sampling clock generator according to claim 1, wherein the speed information generation unit generates at least one speed information of the scanning unit,
A sampling clock generator, further comprising selection means for selecting the generated at least one speed information. The sampling clock generator according to any one of claims 1 to 6, wherein the synchronization unit determines an imaging effective start point and a period based on the sampling clock output from the voltage controlled oscillation unit. A sampling clock generator characterized by being determined.

Images