JP3994593B2 - Thin film element transfer method - Google Patents

Thin film element transfer method Download PDF

Info

Publication number
JP3994593B2
JP3994593B2 JP23174399A JP23174399A JP3994593B2 JP 3994593 B2 JP3994593 B2 JP 3994593B2 JP 23174399 A JP23174399 A JP 23174399A JP 23174399 A JP23174399 A JP 23174399A JP 3994593 B2 JP3994593 B2 JP 3994593B2
Authority
JP
Japan
Prior art keywords
thin film
sacrificial layer
substrate
film element
transferring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23174399A
Other languages
Japanese (ja)
Other versions
JP2001057432A (en
Inventor
清一郎 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23174399A priority Critical patent/JP3994593B2/en
Publication of JP2001057432A publication Critical patent/JP2001057432A/en
Application granted granted Critical
Publication of JP3994593B2 publication Critical patent/JP3994593B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Description

【0001】
【発明の属する技術分野】
本発明は、液晶表示装置の表示画素または液晶駆動回路の構成素子として利用される薄膜トランジスタ等の薄膜素子を、転写によって他の基板に貼り付ける薄膜素子の転写方法に関する。
【0002】
【従来の技術】
多結晶シリコン( poly−Si)等の半導体膜は薄膜トランジスタ(以下本願明細書中ではTFTと称する)や太陽電池に広く利用されている。とりわけpoly−SiTFTは高移動度化が可能でありながらガラス基板のように透明で絶縁性の基板上に作成できるという特徴を生かして、液晶表示装置(LCD)や液晶プロジェクターなどの光変調素子あるいは液晶駆動用内蔵ドライバーの構成素子として広く用いられ、新しい市場の創出に成功している。
【0003】
ガラス基板上に高性能なTFTを作成する方法としては高温プロセスと呼ばれる製造方法がすでに実用化されている。TFTの製造方法として工程最高温度が1000℃程度の高温を用いるプロセスを一般的に高温プロセスと呼んでいる。高温プロセスの特徴は、シリコンの固相成長により比較的良質のpoly−Siを作成する事ができることと、熱酸化により良質のゲート絶縁膜(一般的に二酸化珪素)および清浄なpoly−Siとゲート絶縁膜の界面を形成できることである。高温プロセスではこれらの特徴により、高移動度でしかも信頼性の高い高性能TFTを安定的に製造することができる。しかし、高温プロセスを用いるためにはTFTを作成する基板が1000℃以上の高温の熱工程に耐え得る必要がある。この条件を満たす透明な基板は現在のところ石英ガラスしかない。このため昨今のpoly−Si TFTは総て高価で小さい石英ガラス基板上に作成されており、コストの問題上大型化には向かないとされている。また、固相成長法では十数時間という長時間の熱処理が必要であり、生産性が極めて低いとの課題がある。また、この方法では基板全体が長時間加熱されている事に起因して基板の熱変形が大きな問題と化し実質的に安価な大型ガラス基板を使用し得ないとの課題が生じており、これもまた低コスト化の妨げとなっている。
【0004】
一方、高温プロセスが持つ上記欠点を解消し、尚且つ高移動度のpoly−Si TFTを実現しようとしているのが低温プロセスと呼ばれる技術である。比較的安価な耐熱性ガラス基板を使うために、工程最高温度としておおむね600℃以下のpoly−Si TFT製造プロセスを一般的に低温プロセスと呼ぶ。低温プロセスでは発振時間が極短時間のパルスレーザーを用いてシリコン膜の結晶化をおこなう技術が広く使われている。レーザー結晶化とは、ガラス基板上のアモルファスシリコン膜に高出力のパルスレーザー光を照射することによって瞬時に溶融させ、これが凝固する過程で結晶化する性質を利用する技術である。最近ではガラス基板上のアモルファスシリコン膜にエキシマレーザービームをくり返し照射しながらスキャンすることによって大面積のpoly−Si膜を作成する技術が広く使われるようになった。また、ゲート絶縁膜としてはプラズマCVDをもちいた成膜方法で比較的高品質の二酸化珪素(SiO2)膜が成膜可能となり実用化への見通しが得られるほどになった。これらの技術によって、現在では一辺が数十センチほどもある大型のガラス基板上にpoly−Si TFTが作成可能となっている。
【0005】
以上のようにして作製したTFTは、低温プロセスといえどもプロセス温度として400℃程度の温度が必要なため、たとえば樹脂基板やプラスティック基板などの耐熱性の低い基板上に作製することは現状では不可能である。従って、TFTはガラスなどの基板上に作製し、しかる後にこれらの素子を任意の基板に転写することができると任意の基板上に薄膜トランジスタを形成することができるようになる。レーザーを利用して素子を転写する方法に関しては様々な技術が報告されているが、例えばJapanese Journal of Applied Physics Vol.38 (1999)pp.L217はごく最近報告された転写技術の一つである。これは図3に示すように窒化ガリウム102の表面にレーザー照射106をし、レーザーを吸収した最表面の熱励起による分解(窒素ガス108が発生)を利用して、素子を基板から分離する方法である。しかしながら、熱分解を促すために基板をホットプレート101で600℃に加熱する必要があり耐熱性の低い転写先基板を使うことができない。また、窒化ガリウムという特殊な材料を用いなければならないためこの犠牲層の上にTFTなどのシリコン系素子を作製するのはプロセスの制約上、困難であるといわざるを得ない。
【0006】
【発明が解決しようとする課題】
そこで本発明は上述の諸課題を鑑み、基板温度を上げること無くTFT等のシリコン薄膜素子を任意の基板上に転写する薄膜素子の転写方法を提供するものである。
【0007】
【課題を解決するための手段】
本発明の薄膜素子の転写方法は、第1の基板上の犠牲層上に作製した薄膜素子を第2の基板上に転写する薄膜素子の転写方法において、アモルファスシリコン膜またはゲルマニウム膜からなる前記犠牲層に電圧を印加した状態で該犠牲層に光照射した後、前記第1の基板と前記第2の基板とを接着剤を介して接着させ、その後該犠牲層を剥離することにより該犠牲層上の前記薄膜素子を前記第2の基板上に転写することを特徴とする。
【0008】
上記課題を解決する為に請求項2記載の発明は請求項1記載の薄膜素子の転写方法で、前記光照射をおこなったのち前記第1の基板と前記第2の基板を接着させ素子の転写をおこなうことを特徴とする。
【0009】
上記課題を解決する為に請求項3記載の発明は、請求項1または2記載の薄膜素子の転写方法で、前記犠牲層の厚みは10から500nmの範囲であることを特徴とする。
【0010】
上記課題を解決する為に請求項4記載の発明は、請求項1、2、または3記載の薄膜素子の転写方法で、前記犠牲層に印加する電圧は、該犠牲層を流れる電流密度が10000A/cm2以上となるように設定することを特徴とする。
【0011】
上記課題を解決する為に請求項5記載の発明は、請求項1、2、3または4記載の薄膜素子の転写方法で、前記犠牲層の剥離状態を、光照射後の犠牲層の抵抗値変化によって測定し、光照射を繰り返す最適条件をモニターすることを特徴とする。
【0012】
上記課題を解決する為に請求項6記載の発明は、請求項1、2、3、4、または5記載の薄膜素子の転写方法で、前記犠牲層に電圧を印加する電極は、第1の基板上の所望の転写領域を挟む位置に対向して設置されてなることを特徴とする。
【0013】
上記課題を解決する為に請求項7記載の発明は、請求項6記載の薄膜素子の転写方法において前記光照射は犠牲層に電圧を印加する対向した電極を両端とする領域に対しておこなうことを特徴とする。
【0015】
上記課題を解決する為に請求項8記載の発明は請求項1、2、3、4、5、6または7記載の薄膜素子の転写方法において、前記光照射はエキシマレーザーによって行われることを特徴とする。
【0016】
上記課題を解決する為に請求項9記載の発明は請求項1、2、3、4、5、6、7または8記載の薄膜素子の転写方法において、前記薄膜素子は薄膜トランジスタであることを特徴とする。
【0017】
【発明の実施の形態】
以下、本発明による実施の形態の一例を図1に基づいて詳述する。
【0018】
第1の基板207としては、石英ガラスや高融点ガラス、プラスティック基板など、転写時に照射するレーザー208に対して透明で、素子作製プロセスに耐えるものが望ましい。この基板207の上に犠牲層206を形成する。犠牲層はレーザー光208を効率的に吸収する材料が望ましい。たとえば、アモルファスシリコンやゲルマニウム、その他光分解型の有機物なども有効である。この上にバッファ層205を形成する。これは素子転写時の熱あるいは光の影響が上の素子に及ぶのを防止する役割を果たすもので、二酸化珪素、窒化シリコン、金属酸化物などが有効である。この上に転写したい素子を形成する。この素子は例えば薄膜トランジスタや、半導体レーザー、フォトダイオード、太陽電池などの半導体デバイスをはじめ、有機EL素子、液晶表示装置等任意の素子を形成して良い。しかる後に犠牲層206に電気的に接続する電極204を形成する。この電極204を介して犠牲層206にバイアス電圧を印加する。次にバイアス電圧を印加した状態でレーザー光208を照射する。ここでレーザー光源としては二酸化炭素レーザー、エキシマレーザーをはじめとする高出力のガスレーザー、YAGレーザー、半導体レーザーなどの固体レーザーが利用できるが、特にパルスレーザーは犠牲層を瞬時に溶融させながら、素子に熱的ダメージを与えないので有効である。レーザー光208の照射によって犠牲層206は温度上昇し、融点を超えると溶融する。溶融すると犠牲層206はより電気を流しやすくなるので、溶融と同時に犠牲層206を電流が流れる。この電流の値が十分大きいと、ジュール発熱によって犠牲層206の温度は更に上昇する。この電流値を適当に設定すると、犠牲層206は急激な温度上昇によって構造的な乱れが極めて大きくなり、ついには薄膜としての密着力を失う。このために、この犠牲層206を境にして上部の素子部分は容易に基板207から剥離することができるようになる。
【0019】
【実施例】
本発明の実施例として、TFT素子を転写する方法を図2にそって説明する。本実施例で用いられる基板及び下地保護膜に関しては前述の説明に準ずるが、ここでは基板の一例として4インチφの石英基板307を用いる。まず基板307上に犠牲層であるアモルファスシリコン306を100nm成膜する。本実施例では高真空型LPCVD装置を用いて、原料ガスで有るジシラン(Si)を200SCCM流し、425℃の堆積温度で堆積する。次に絶縁性物質である下地保護膜305を形成する。ここでは基板温度を150゜CとしてECR−PECVD法にて200nm程度の膜厚を有する酸化硅素膜を堆積する。次に薄膜トランジスタの能動層となる真性シリコン膜等の半導体膜300を堆積する。半導体膜300の厚みは50nm程度で有る。この半導体層は前記アモルファスシリコン306とまったく同様の方法により形成する。次にTFTのチャネル部分となるレーザー結晶化を行うのであるが、これに先立って非晶質シリコン膜を弗酸溶液に浸し、半導体膜300上の自然酸化膜をエッチングする。次にレーザー光の照射をおこなう。本実施例ではキセノン・クロライド(XeCl)のエキシマ・レーザー(波長:308nm)を照射する。レーザーパルスの強度半値幅(時間に対する半値幅)は25nsである。基板307をレーザー結晶化チャンバーにセットした後、真空排気をおこなう。基板307を加熱した状態でレーザー照射することでp−Si膜の結晶性を向上することができるので、真空排気後基板温度を250度℃まで上昇させる。一回のレーザー照射面積は10mm角の正方形状で、照射面でのエネルギー密度は160mJ/cmである。このレーザー光を90%ずつ重ねつつ(つまり照射するごとに1mmづつ)相対的にずらしながら照射を繰り返す(図1参照)。こうして4インチφの基板307全体のアモルファスシリコンを結晶化する。同様な照射方法を用いて2回目のレーザー照射を行う。2回目のエネルギー密度は180mJ/cmで有る。これをくり返し、3回目、4回目と約20mJ/cmづつ照射エネルギー密度を上昇させながら最終的にはのエネルギー密度440mJ/cmの照射をおこないレーザー照射を終了する。ここで450mJ/cmの照射レーザーエネルギー密度を超えた高いエネルギーを照射すると、p−Siのグレインが微結晶化を起こすため、これ以上のエネルギー照射を避けた。次にゲート絶縁膜成膜チャンバーでCVD法やPVD法などでゲート絶縁膜を形成する。本実施例では平行平板型rf放電PECVD法で基板温度を350℃として120nmの酸化硅素膜を堆積する。原料ガスとしてはTEOS(Si−(O−CH−CH)と酸素(O)の混合ガスをもちいた。引き続いてゲート電極301となる薄膜をPVD法或いはCVD法などで堆積する。通常はゲート電極とゲート配線は同一材料にて同一工程で作られる為、この材質は電気抵抗が低く、350℃程度の熱工程に対して安定である事が望まれる。本実施例では膜厚が600nmのタンタル薄膜をスパッタ法により形成する。ゲート電極となる薄膜を堆積後パターニングを行い、引き続いて半導体膜300に不純物イオン注入を行ってソース・ドレイン領域302及びチャンネル領域を形成する。この時ゲート電極301がイオン注入のマスクとなっているため、チャンネルはゲート電極301下のみに形成される自己整合構造となる。次に層間絶縁膜をCVD法或いはPVD法で形成する。本実施例ではTEOS(Si−(O−CH−CH)と酸素(O)、水(HO)を原料気体とし、希釈気体としてアルゴンを用いて基板表面温度300℃で500nmの膜厚に成膜する。イオン注入と層間絶縁膜形成後、350℃程度以下の適当な熱環境下にて数十分から数時間の熱処理を施して注入イオンの活性化及び層間絶縁膜の焼き締めを行う。この熱処理温度は注入イオンを確実に活性化する為にも250℃程度以上が好ましい。又層間絶縁膜を効能的に焼き締めるには300℃以上の温度が好ましい。層間絶縁膜形成後ソース・ドレイン領域302上および犠牲層306上にコンタクトホールを開孔し、ソース・ドレイン取り出し電極303とバイアス印加電極304配線をPVD法やCVD法などで形成して薄膜トランジスタおよび転写構造が完成する。
【0020】
上記構造の犠牲層および薄膜トランジスタ素子を形成した後、この素子を第二の基板に転写するプロセスをおこなう。犠牲層306に接続したバイアス印加電極304に50Vのバイアスを印加する。この状態で基板307側からエキシマレーザー308を照射する。ここでレーザー光はギャップ状のバイアス印加電極304が照射領域の両端に位置するように照射する。これによって照射領域全体に一様な電流が流せるので剥離工程での歩留まりを上げることができる。犠牲層であるアモルファスシリコン306は300mJ/cm2程度のエネルギー密度で照射したエキシマレーザー光をすべて吸収し溶融する。アモルファスシリコンは固体では極めて抵抗が高いが、一旦溶融すると金属的な性質を示し80μΩcmという大変低い抵抗体に成る。このためバイアス印加電極304を通して溶融状態のシリコンに極めて大きな電流密度で電流が流れる。このときの電流密度はおおむね10000A/cm2となるようにバイアス電圧を調節すると後の剥離が容易となる。この大電流のため溶融シリコン膜はジュール発熱するので、溶融シリコンの温度をバイアス電圧によって制御することができる。レーザー照射のみでは犠牲層306の温度コントロールができないため、剥離し易さをコントロールするのは極めて困難であったが、電流制御で温度コントロールをする本発明の方法によって剥離しやすさを容易に制御できるように成った。また、レーザー照射をおこなった後犠牲層306の抵抗値を測定することで犠牲層306の構造を反映した電気特性が評価できる。したがって、犠牲層306の抵抗値の変化をモニターしながらレーザー照射回数やエネルギーおよびバイアス電圧を適当な値に調整することで間違いなく転写可能な犠牲層306の状態を再現することができる。このようにして十分に剥離可能な状態になった第1の基板に、転写先となる第2の基板311を接着剤310によって接着する。接着剤が十分に固化した後、第1の基板307と第2の基板311をお互いに逆方向に引っ張ることによって、素子は犠牲層306を境にして容易に第2の基板311に転写される。
【0021】
【発明の効果】
以上のように、TFT作製プロセスと整合性の良い犠牲層をつくるには、TFTの能動層であるアモルファスシリコン膜を用いることが重要である。これによって、素子形成プロセスは従来とまったく同じで、犠牲層を作製することができるし、不純物による素子への悪影響もまったく与えずに済む。また、犠牲層を溶融させるレーザーとしてTFT作製プロセスで用いるエキシマレーザーが利用できるため、装置コストを低く抑えることが可能となる。
【0022】
以上のように本発明の薄膜素子の転写方法を用いることによって、制御性および再現性のよい素子転写が可能となる。
【図面の簡単な説明】
【図1】本発明をTFTに用いた場合の転写方法を説明するための図。
【図2】本発明の薄膜素子転写方法を説明するための図。
【図3】従来の薄膜転写方法を説明するための図。
【符号の説明】
207...基板
205...下地絶縁膜
300...半導体膜
106、308...レーザー光
306...犠牲層
301...ゲート電極
302...ソース、ドレイン領域
303...ソース、ドレイン電極
304...バイアス印加電極
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film element transfer method in which a thin film element such as a thin film transistor used as a display pixel of a liquid crystal display device or a constituent element of a liquid crystal driving circuit is attached to another substrate by transfer.
[0002]
[Prior art]
Semiconductor films such as polycrystalline silicon (poly-Si) are widely used for thin film transistors (hereinafter referred to as TFTs in the present specification) and solar cells. In particular, poly-Si TFTs can be made on a transparent and insulating substrate such as a glass substrate while being capable of high mobility, so that light modulation elements such as liquid crystal display devices (LCD) and liquid crystal projectors can be used. Widely used as a component of built-in drivers for liquid crystal drive, it has succeeded in creating a new market.
[0003]
As a method for producing a high-performance TFT on a glass substrate, a manufacturing method called a high-temperature process has already been put into practical use. A process using a high temperature with a maximum process temperature of about 1000 ° C. as a TFT manufacturing method is generally called a high temperature process. The characteristics of the high-temperature process are that a relatively high-quality poly-Si can be produced by solid phase growth of silicon, a high-quality gate insulating film (generally silicon dioxide) and a clean poly-Si and gate by thermal oxidation. That is, the interface of the insulating film can be formed. Due to these characteristics, a high-performance TFT having high mobility and high reliability can be stably manufactured in a high-temperature process. However, in order to use a high temperature process, it is necessary that the substrate on which the TFT is formed can withstand a high temperature heat process of 1000 ° C. or higher. The only transparent substrate that satisfies this condition is currently quartz glass. For this reason, poly-Si TFTs of recent years are all manufactured on a small and expensive quartz glass substrate, and are not suitable for enlargement due to cost problems. In addition, the solid phase growth method requires a heat treatment for a long time of ten and several hours, and there is a problem that productivity is extremely low. In addition, this method has caused a problem that the thermal deformation of the substrate becomes a big problem due to the whole substrate being heated for a long time, and it is impossible to use a substantially inexpensive large glass substrate. This also hinders cost reduction.
[0004]
On the other hand, a technique called a low-temperature process is intended to solve the above-mentioned drawbacks of a high-temperature process and to realize a poly-Si TFT with high mobility. In order to use a relatively inexpensive heat-resistant glass substrate, a poly-Si TFT manufacturing process having a maximum process temperature of approximately 600 ° C. or lower is generally called a low-temperature process. In a low temperature process, a technique for crystallizing a silicon film using a pulse laser having an extremely short oscillation time is widely used. Laser crystallization is a technology that utilizes the property of crystallizing in the process of solidifying instantaneously by irradiating an amorphous silicon film on a glass substrate with high-power pulsed laser light. Recently, a technique for forming a poly-Si film having a large area by scanning an amorphous silicon film on a glass substrate while repeatedly irradiating it with an excimer laser beam has been widely used. In addition, a relatively high quality silicon dioxide (SiO 2) film can be formed by a film forming method using plasma CVD as the gate insulating film, and the prospect for practical use is obtained. With these technologies, poly-Si TFTs can be created on a large glass substrate that is currently several tens of centimeters on a side.
[0005]
Since the TFT manufactured as described above requires a process temperature of about 400 ° C. even in a low temperature process, it is not currently possible to manufacture it on a substrate having low heat resistance such as a resin substrate or a plastic substrate. Is possible. Therefore, if the TFT is manufactured on a substrate such as glass and then these elements can be transferred to an arbitrary substrate, the thin film transistor can be formed on the arbitrary substrate. Various techniques have been reported for transferring elements using lasers. For example, Japanese Journal of Applied Physics Vol.38 (1999) pp.L217 is one of the most recently reported transfer techniques. . As shown in FIG. 3, a laser irradiation 106 is performed on the surface of gallium nitride 102, and the element is separated from the substrate by utilizing thermal excitation decomposition (generation of nitrogen gas 108) of the outermost surface that has absorbed the laser. It is. However, it is necessary to heat the substrate to 600 ° C. with the hot plate 101 in order to promote thermal decomposition, and a transfer destination substrate having low heat resistance cannot be used. In addition, since a special material called gallium nitride must be used, it can be said that it is difficult to manufacture a silicon-based device such as a TFT on the sacrificial layer due to process limitations.
[0006]
[Problems to be solved by the invention]
In view of the above-described problems, the present invention provides a thin film element transfer method for transferring a silicon thin film element such as a TFT onto an arbitrary substrate without increasing the substrate temperature.
[0007]
[Means for Solving the Problems]
The thin film element transfer method of the present invention is a thin film element transfer method in which a thin film element fabricated on a sacrificial layer on a first substrate is transferred onto a second substrate, wherein the sacrifice made of an amorphous silicon film or a germanium film. The sacrificial layer is irradiated with light in a state where a voltage is applied to the layer, and then the first substrate and the second substrate are bonded to each other through an adhesive, and then the sacrificial layer is peeled off to remove the sacrificial layer. The thin film element above is transferred onto the second substrate.
[0008]
In order to solve the above-mentioned problems, a second aspect of the invention is the thin film element transfer method according to the first aspect, wherein after the light irradiation, the first substrate and the second substrate are bonded to transfer the element. It is characterized by performing.
[0009]
In order to solve the above-mentioned problems, a third aspect of the present invention is the thin film element transfer method according to the first or second aspect, wherein the thickness of the sacrificial layer is in the range of 10 to 500 nm.
[0010]
In order to solve the above-mentioned problem, the invention according to claim 4 is the thin film element transfer method according to claim 1, 2, or 3, wherein the voltage applied to the sacrificial layer is such that the current density flowing through the sacrificial layer is 10,000 A. It is characterized in that it is set to be / cm 2 or more.
[0011]
In order to solve the above problem, the invention according to claim 5 is the thin film element transfer method according to claim 1, 2, 3 or 4, wherein the sacrificial layer is peeled off in accordance with the resistance value of the sacrificial layer after light irradiation. It is characterized by monitoring the optimum condition by measuring the change and repeating the light irradiation.
[0012]
In order to solve the above-mentioned problem, the invention according to claim 6 is the thin film element transfer method according to claim 1, wherein the electrode for applying a voltage to the sacrificial layer is the first electrode. It is provided so as to be opposed to a position on the substrate across a desired transfer region.
[0013]
In order to solve the above-mentioned problems, according to a seventh aspect of the present invention, in the thin film element transfer method according to the sixth aspect, the light irradiation is performed on a region having opposite electrodes that apply a voltage to the sacrificial layer at both ends. It is characterized by.
[0015]
In order to solve the above-mentioned problems, the invention according to claim 8 is the thin film element transfer method according to claim 1, 2, 3, 4, 5, 6 or 7, wherein the light irradiation is performed by an excimer laser. And
[0016]
In order to solve the above problems, the invention according to claim 9 is the thin film element transfer method according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein the thin film element is a thin film transistor. And
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment according to the present invention will be described in detail with reference to FIG.
[0018]
As the first substrate 207, quartz glass, high melting point glass, plastic substrate, or the like that is transparent to the laser 208 irradiated at the time of transfer and can withstand the element manufacturing process is desirable. A sacrificial layer 206 is formed on the substrate 207. The sacrificial layer is preferably made of a material that efficiently absorbs the laser beam 208. For example, amorphous silicon, germanium, and other photolytic organic substances are also effective. A buffer layer 205 is formed thereon. This plays a role of preventing the influence of heat or light upon element transfer from reaching the upper element, and silicon dioxide, silicon nitride, metal oxide, etc. are effective. An element to be transferred is formed thereon. As this element, for example, a semiconductor device such as a thin film transistor, a semiconductor laser, a photodiode, or a solar cell, an arbitrary element such as an organic EL element or a liquid crystal display device may be formed. Thereafter, an electrode 204 that is electrically connected to the sacrificial layer 206 is formed. A bias voltage is applied to the sacrificial layer 206 through the electrode 204. Next, the laser beam 208 is irradiated with a bias voltage applied. Here, solid-state lasers such as high-power gas lasers such as carbon dioxide lasers and excimer lasers, YAG lasers, and semiconductor lasers can be used as laser light sources. This is effective because it does not cause thermal damage. The temperature of the sacrificial layer 206 is increased by the irradiation of the laser beam 208 and melts when the melting point is exceeded. When melted, the sacrificial layer 206 is more likely to conduct electricity, so that current flows through the sacrificial layer 206 simultaneously with melting. If the value of this current is sufficiently large, the temperature of the sacrificial layer 206 further increases due to Joule heat generation. If this current value is set appropriately, the sacrificial layer 206 will have an extremely large structural disturbance due to a rapid temperature rise, and will eventually lose its adhesion as a thin film. Therefore, the upper element portion can be easily separated from the substrate 207 with the sacrificial layer 206 as a boundary.
[0019]
【Example】
As an embodiment of the present invention, a method for transferring a TFT element will be described with reference to FIG. Although the substrate and the base protective film used in this embodiment conform to the above description, a 4-inch φ quartz substrate 307 is used here as an example of the substrate. First, an amorphous silicon 306 as a sacrificial layer is formed to a thickness of 100 nm on the substrate 307. In this embodiment, using a high vacuum type LPCVD apparatus, 200 SCCM of disilane (Si 2 H 6 ), which is a raw material gas, is flowed and deposited at a deposition temperature of 425 ° C. Next, a base protective film 305 that is an insulating material is formed. Here, a silicon oxide film having a thickness of about 200 nm is deposited by ECR-PECVD at a substrate temperature of 150.degree. Next, a semiconductor film 300 such as an intrinsic silicon film which becomes an active layer of the thin film transistor is deposited. The thickness of the semiconductor film 300 is about 50 nm. This semiconductor layer is formed by the same method as that for the amorphous silicon 306. Next, laser crystallization which becomes the channel portion of the TFT is performed. Prior to this, the amorphous silicon film is immersed in a hydrofluoric acid solution, and the natural oxide film on the semiconductor film 300 is etched. Next, laser light is irradiated. In this embodiment, an excimer laser (wavelength: 308 nm) of xenon chloride (XeCl) is irradiated. The intensity half width (half width with respect to time) of the laser pulse is 25 ns. After setting the substrate 307 in the laser crystallization chamber, vacuum evacuation is performed. Since the crystallinity of the p-Si film can be improved by irradiating the laser with the substrate 307 heated, the substrate temperature is raised to 250 ° C. after evacuation. The area of laser irradiation at one time is a 10 mm square, and the energy density on the irradiated surface is 160 mJ / cm 2 . Irradiation is repeated while the laser beams are overlapped by 90% (that is, 1 mm for each irradiation) and relatively shifted (see FIG. 1). In this way, the amorphous silicon of the entire 4-inch φ substrate 307 is crystallized. A second laser irradiation is performed using the same irradiation method. The energy density for the second time is 180 mJ / cm 2 . This is repeated, and finally the irradiation with the energy density of 440 mJ / cm 2 is performed while increasing the irradiation energy density by about 20 mJ / cm 2 for the third time and the fourth time, and the laser irradiation is finished. Here, when high energy exceeding the irradiation laser energy density of 450 mJ / cm 2 was irradiated, since the grains of p-Si caused microcrystallization, further energy irradiation was avoided. Next, a gate insulating film is formed by a CVD method, a PVD method, or the like in a gate insulating film deposition chamber. In this embodiment, a 120 nm silicon oxide film is deposited at a substrate temperature of 350 ° C. by a parallel plate type rf discharge PECVD method. As the source gas, a mixed gas of TEOS (Si— (O—CH 2 —CH 3 ) 4 ) and oxygen (O 2 ) was used. Subsequently, a thin film to be the gate electrode 301 is deposited by a PVD method or a CVD method. Usually, since the gate electrode and the gate wiring are made of the same material and in the same process, it is desirable that this material has a low electric resistance and is stable to a heat process of about 350 ° C. In this embodiment, a tantalum thin film having a thickness of 600 nm is formed by sputtering. After depositing a thin film to be a gate electrode, patterning is performed, and subsequently, impurity ions are implanted into the semiconductor film 300 to form a source / drain region 302 and a channel region. At this time, since the gate electrode 301 serves as an ion implantation mask, the channel has a self-aligned structure formed only under the gate electrode 301. Next, an interlayer insulating film is formed by a CVD method or a PVD method. In this example, TEOS (Si— (O—CH 2 —CH 3 ) 4 ), oxygen (O 2 ), and water (H 2 O) are used as source gases, and argon is used as a dilution gas at a substrate surface temperature of 300 ° C. The film is formed to a thickness of 500 nm. After the ion implantation and the formation of the interlayer insulating film, heat treatment is performed for several tens of minutes to several hours in an appropriate thermal environment of about 350 ° C. or less to activate the implanted ions and to bake the interlayer insulating film. The heat treatment temperature is preferably about 250 ° C. or higher in order to reliably activate the implanted ions. Also, a temperature of 300 ° C. or higher is preferable for effectively baking the interlayer insulating film. After the interlayer insulating film is formed, contact holes are formed on the source / drain regions 302 and the sacrificial layer 306, and source / drain extraction electrodes 303 and bias application electrodes 304 are formed by PVD, CVD, etc. The structure is complete.
[0020]
After the sacrificial layer and the thin film transistor element having the above structure are formed, a process of transferring the element to the second substrate is performed. A bias of 50 V is applied to the bias application electrode 304 connected to the sacrificial layer 306. In this state, excimer laser 308 is irradiated from the substrate 307 side. Here, the laser beam is irradiated so that the gap-shaped bias application electrode 304 is positioned at both ends of the irradiation region. As a result, a uniform current can flow through the entire irradiation region, so that the yield in the peeling process can be increased. Amorphous silicon 306 as a sacrificial layer absorbs and melts all excimer laser light irradiated at an energy density of about 300 mJ / cm 2. Amorphous silicon has extremely high resistance in a solid state, but once melted, it exhibits metallic properties and becomes a very low resistance of 80 μΩcm. For this reason, a current flows through the bias application electrode 304 to the molten silicon at a very large current density. If the bias voltage is adjusted so that the current density at this time is approximately 10000 A / cm @ 2, the subsequent peeling is facilitated. Since the molten silicon film generates Joule heat due to this large current, the temperature of the molten silicon can be controlled by the bias voltage. Since the temperature of the sacrificial layer 306 cannot be controlled only by laser irradiation, it was extremely difficult to control the ease of peeling, but the ease of peeling was easily controlled by the method of the present invention in which the temperature is controlled by current control. I was able to do it. Further, by measuring the resistance value of the sacrificial layer 306 after laser irradiation, the electrical characteristics reflecting the structure of the sacrificial layer 306 can be evaluated. Therefore, the state of the sacrificial layer 306 that can be transferred is surely reproduced by adjusting the number of times of laser irradiation, energy, and bias voltage to appropriate values while monitoring the change in the resistance value of the sacrificial layer 306. A second substrate 311 serving as a transfer destination is bonded to the first substrate that is sufficiently peelable in this manner by an adhesive 310. After the adhesive is sufficiently solidified, the element is easily transferred to the second substrate 311 with the sacrificial layer 306 as a boundary by pulling the first substrate 307 and the second substrate 311 in opposite directions. .
[0021]
【The invention's effect】
As described above, in order to produce a sacrificial layer having good consistency with the TFT manufacturing process, it is important to use an amorphous silicon film which is an active layer of the TFT. As a result, the element formation process is exactly the same as in the prior art, a sacrificial layer can be formed, and there is no need to adversely affect the element due to impurities. In addition, since an excimer laser used in the TFT manufacturing process can be used as a laser for melting the sacrificial layer, the cost of the apparatus can be reduced.
[0022]
As described above, by using the thin film element transfer method of the present invention, element transfer with good controllability and reproducibility becomes possible.
[Brief description of the drawings]
FIG. 1 is a view for explaining a transfer method when the present invention is used in a TFT.
FIG. 2 is a view for explaining a thin film element transfer method of the present invention.
FIG. 3 is a view for explaining a conventional thin film transfer method.
[Explanation of symbols]
207. . . Substrate 205. . . Underlying insulating film 300. . . Semiconductor films 106, 308. . . Laser beam 306. . . Sacrificial layer 301. . . Gate electrode 302. . . Source / drain region 303. . . Source and drain electrodes 304. . . Bias application electrode

Claims (8)

第1の基板上の犠牲層上に作製した薄膜素子を第2の基板上に転写する薄膜素子の転写方法において、アモルファスシリコン膜またはゲルマニウム膜からなる前記犠牲層に電圧を印加した状態で該犠牲層に光照射した後、前記第1の基板と前記第2の基板とを接着剤を介して接着させ、その後該犠牲層を剥離することにより該犠牲層上の前記薄膜素子を前記第2の基板上に転写することを特徴とする薄膜素子の転写方法。In a thin film element transfer method for transferring a thin film element fabricated on a sacrificial layer on a first substrate onto a second substrate, the sacrificial layer is applied in a state where a voltage is applied to the sacrificial layer made of an amorphous silicon film or a germanium film. After the layer is irradiated with light , the first substrate and the second substrate are bonded to each other through an adhesive, and then the sacrificial layer is peeled off, thereby removing the thin film element on the sacrificial layer from the second layer. A method for transferring a thin film element, wherein the transfer is performed on a substrate. 前記犠牲層の厚みは10から500nmの範囲であることを特徴とする請求項1記載の薄膜素子の転写方法。  2. The method for transferring a thin film element according to claim 1, wherein the thickness of the sacrificial layer is in the range of 10 to 500 nm. 前記犠牲層に印加する電圧は、該犠牲層を流れる電流密度が10000A/cm2以上となるように設定することを特徴とする請求項1または記載の薄膜素子の転写方法。Voltage transfer process of a thin film element according to claim 1 or 2, wherein the current density flowing through the sacrificial layer is set to be 10000 A / cm 2 or more to be applied to the sacrificial layer. 前記犠牲層の剥離状態を、光照射後の犠牲層の抵抗値変化によって測定し、光照射を繰り返す最適条件をモニターすることを特徴とする請求項1、2または記載の薄膜素子の転写方法。Peeling state of the sacrificial layer, determined by the resistance value change of the sacrificial layer after light irradiation, a method of transferring a thin film element according to claim 1, 2 or 3 wherein monitoring the optimum conditions to repeat the light irradiation . 前記犠牲層に電圧を印加する電極は、第1の基板上の所望の転写領域を挟む位置に対向して設置されてなることを特徴とする請求項1、2、3または記載の薄膜素子の転写方法。Electrodes, thin-film element according to claim 1, 2, 3 or 4, wherein the composed installed to face the positions sandwiching the desired transfer regions on the first substrate for applying a voltage to the sacrificial layer Transfer method. 前記光照射は犠牲層に電圧を印加する対向した電極を両端とする領域に対しておこなうことを特徴とする請求項記載の薄膜素子の転写方法。6. The method for transferring a thin film element according to claim 5, wherein the light irradiation is performed on a region having opposing electrodes for applying a voltage to the sacrificial layer at both ends. 前記光照射はエキシマレーザーによって行われることを特徴とする請求項1、2、3、4、5または記載の薄膜素子の転写方法。Method for transferring a thin film device according to claim 2, 3, 4, 5 or 6, wherein the light irradiation is characterized by being performed by an excimer laser. 前記薄膜素子は薄膜トランジスタであることを特徴とする請求項1、2、3、4、5、6または記載の薄膜素子の転写方法。Method for transferring a thin film device according to claim 3, 4, 5, 6 or 7, wherein said thin film device is a thin film transistor.
JP23174399A 1999-08-18 1999-08-18 Thin film element transfer method Expired - Fee Related JP3994593B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23174399A JP3994593B2 (en) 1999-08-18 1999-08-18 Thin film element transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23174399A JP3994593B2 (en) 1999-08-18 1999-08-18 Thin film element transfer method

Publications (2)

Publication Number Publication Date
JP2001057432A JP2001057432A (en) 2001-02-27
JP3994593B2 true JP3994593B2 (en) 2007-10-24

Family

ID=16928355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23174399A Expired - Fee Related JP3994593B2 (en) 1999-08-18 1999-08-18 Thin film element transfer method

Country Status (1)

Country Link
JP (1) JP3994593B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60325669D1 (en) 2002-05-17 2009-02-26 Semiconductor Energy Lab Method for transferring an object and method for producing a semiconductor device
JP2004047975A (en) * 2002-05-17 2004-02-12 Semiconductor Energy Lab Co Ltd Method of transferring laminate and method of manufacturing semiconductor device
JP4757469B2 (en) * 2002-05-17 2011-08-24 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP2009228602A (en) * 2008-03-24 2009-10-08 Yanmar Co Ltd Engine
JP5790095B2 (en) 2011-04-01 2015-10-07 ソニー株式会社 Thin film element, manufacturing method thereof, and manufacturing method of image display device
WO2013035298A1 (en) * 2011-09-08 2013-03-14 シャープ株式会社 Display device and method for manufacturing same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3809712B2 (en) * 1996-08-27 2006-08-16 セイコーエプソン株式会社 Thin film device transfer method
JP3809681B2 (en) * 1996-08-27 2006-08-16 セイコーエプソン株式会社 Peeling method

Also Published As

Publication number Publication date
JP2001057432A (en) 2001-02-27

Similar Documents

Publication Publication Date Title
US5946562A (en) Polysilicon thin film transistors with laser-induced solid phase crystallized polysilicon channel
JPH07221017A (en) Semiconductor device and manufacturing method
JPH07249779A (en) Fabrication of semiconductor device
JPH04124813A (en) Manufacture of thin-film semiconductor and apparatus therefor
JP4174862B2 (en) Thin film transistor manufacturing method and semiconductor device manufacturing method
JP3190517B2 (en) Manufacturing method of semiconductor
JP4856252B2 (en) Thin film transistor manufacturing method
JPH0794756A (en) Method of fabricating semiconductor device
JP3994593B2 (en) Thin film element transfer method
JP4165305B2 (en) Crystalline semiconductor material manufacturing method and semiconductor device manufacturing method
KR100761345B1 (en) Method of manufacturing a crystalloid silicone
JP3202687B2 (en) Method for manufacturing semiconductor device
JP4200530B2 (en) Thin film transistor manufacturing method
JP3202688B2 (en) Method for manufacturing semiconductor device
JP3408242B2 (en) Method for manufacturing semiconductor device
JP3393863B2 (en) Method for manufacturing semiconductor device
JPH09232584A (en) Method of manufacturing semiconductor device
JP3393857B2 (en) Method for manufacturing semiconductor device
JP4016525B2 (en) Semiconductor manufacturing method
JPH0864526A (en) Modifying method of material by photo-irradiation and manufacture of semiconductor device
JP3906128B2 (en) Method for manufacturing semiconductor device
JP3680256B2 (en) Method for manufacturing semiconductor device
JPH10200118A (en) Manufacture of thin film transistor
JP3618604B2 (en) Semiconductor device manufacturing method
JP4181743B2 (en) Method for manufacturing thin film semiconductor device

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041101

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070116

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070319

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070424

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070619

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070710

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070723

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100810

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 3994593

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100810

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110810

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120810

Year of fee payment: 5

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120810

Year of fee payment: 5

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120810

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130810

Year of fee payment: 6

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S631 Written request for registration of reclamation of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313631

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S631 Written request for registration of reclamation of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313631

S633 Written request for registration of reclamation of name

Free format text: JAPANESE INTERMEDIATE CODE: R313633

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130810

Year of fee payment: 6

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130810

Year of fee payment: 6

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130810

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees