JP3968529B2 - Differential amplifier, two-stage amplifier, and analog / digital converter - Google Patents

Description

  The present invention relates to a differential amplifier, a two-stage amplifier, and an analog / digital converter.

  Conventionally, with the widespread use of digital equipment, analog / digital converters that convert analog signals into digital signals have been widely used.

  In this analog / digital converter, an analog signal is converted into a digital signal by comparing an input analog signal with a plurality of stages of reference voltages, and thus a plurality of amplifiers are used.

  For this reason, an analog / digital converter uses an amplifier having good characteristics, and in particular, a two-stage amplifier having an offset compression function is used in order to reduce an offset voltage which is important as an amplifier characteristic. Yes.

  In this two-stage amplifier, a variable gain differential amplifier is connected in series to a constant gain differential amplifier, and the offset voltage of the previous differential amplifier is apparently compressed by increasing or decreasing the gain of the subsequent differential amplifier. I have to.

  As the differential amplifier 101 used in the subsequent stage, as shown in FIG. 11, a load circuit 103 is connected to the differential amplifier circuit 102, and a changeover switch 104 is connected to the load circuit 103. Thus, the gain of the differential amplifier circuit 102 is switched by switching between the entire load having the entire load circuit 103 as the load of the differential amplifier circuit 102 and the partial load having a part of the load circuit 103 as the load of the differential amplifier circuit 102 There is a known configuration that can increase or decrease.

  The differential amplifier 101 includes a P-channel transistor T101 and P-channel transistors T102 and T103 that are differentially connected to form a differential amplifier circuit 102, and an N-channel transistor connected to the differential amplifier circuit 102. The transistors T104 and T105 constitute a load circuit 103, and switching transistors T106 and T107 as a changeover switch 104 are connected between the drain terminals and the gate terminals of the transistors T104 and T105 constituting the load circuit 103. Yes.

  In the differential amplifier 101, when the switching transistors T106 and T107 are in a disconnected state, the entire load circuit 103 becomes a load (overall load), and in that case, a current source load by the transistors T104 and T105. When the output impedance increases and the gain of the differential amplifier 101 increases. On the other hand, when the switching transistors T106 and T107 are connected, a part of the load circuit 103 becomes a load (partial load). As a result, a diode load is formed by the transistors T104 and T105, the output impedance is reduced, and the gain of the differential amplifier 101 is reduced.

When the offset voltage of the amplifier connected to the front side of the differential amplifier 101 is Vos, the gain at the partial load is Gr, the gain at the full load is Gc, and the input voltage is Vin, the output voltage Vout at the partial load is obtained. Is
Vout = Gr ・ Vos
The output voltage Vout at the time of the entire load is
Vout = Gc ・ Vin
Therefore, when switching from partial load to full load,
Gr ・ Vos = Gc ・ Vin
Therefore, the input voltage Vin is
Vin = Vos · Gr / Gc
It can be expressed as

  That is, in the two-stage amplifier using the differential amplifier 101 configured as described above, the offset voltage is compressed to Gr / Gc times, and the input conversion offset can be expressed as Vos · Gr / Gc.

When the transconductance of the transistors T102 and T103 constituting the differential amplifier circuit 102 is gm1, the transconductance of the transistors T104 and T105 constituting the load circuit 103 is gm2, the load capacity is C, and the operation time is t, the partial load The gain Gr at time is
Gr = gm1 / gm2
The gain Gc at the total load is
Gc = gm1 / Ct
Therefore, the input conversion offset is
Vin = Vos · C / (gm2 · t)
It can be expressed as

Therefore, in the differential amplifier circuit 102 configured as described above, in order to further reduce the input conversion offset, it is only necessary to reduce the load capacitance C or increase the transconductance gm2 and the operation time t of the transistors T104 and T105. Become.
Japanese Unexamined Patent Publication No. 3-70382

  In the differential amplifier circuit 102 configured as described above, the load capacitance C and the operation time t are determined by the circuit configuration, specifications, and the like. Therefore, in order to further reduce the input conversion offset of the differential amplifier circuit 102, the transistors T104, It was necessary to increase the transconductance gm2 of T105.

  However, in order to increase the transconductance gm2 of the transistors T104 and T105, the size of the transistors T104 and T105 must be increased or a large current must be passed through the transistors T104 and T105. In this case, the parasitic capacitances of the transistors T104 and T105 may increase, and the operation speed of the differential amplifier circuit 102 may be reduced. On the other hand, if a large current is applied to the transistors T104 and T105, the difference may occur. There is a possibility that the power consumption of the dynamic amplification circuit 102 increases.

Therefore, in the present invention according to claim 1, the present invention includes a differential amplifier circuit, a load circuit connected to the differential amplifier circuit, and a changeover switch connected to the load circuit, and the load is switched by the changeover switch. The gain of the differential amplifier circuit is changed by switching between an entire load that uses the entire circuit as a load of the differential amplifier circuit and a partial load that uses a part of the load circuit as a load of the differential amplifier circuit. In the configured differential amplifier circuit, the load circuit is configured to amplify an input signal of the differential amplifier circuit through a capacitor when the entire load is applied.

Further, in the present invention according to claim 2, in the two-stage amplifier having an offset compression function of compressing the offset voltage by connecting at least two differential amplifiers in series and increasing or decreasing the gain of the subsequent differential amplifier, The differential amplifier at the latter stage includes a differential amplifier circuit, a load circuit connected to the differential amplifier circuit, and a changeover switch connected to the load circuit, and the entire load circuit is constituted by the changeover switch. The gain of the differential amplifier circuit is changed by switching the entire load as the load of the differential amplifier circuit and the partial load as a load of the differential amplifier circuit as a part of the load circuit, and The load circuit is configured to amplify an input signal of the differential amplifier circuit through a capacitor when the entire load is applied.

According to a third aspect of the present invention, there is provided an analog / digital converter configured to amplify the difference between the voltage of the analog signal and a plurality of different reference voltages by a plurality of amplifying means and convert the difference into a digital signal. The means is a differential amplifier having an offset compression function for compressing an offset voltage, and the differential amplifier is connected to a differential amplifier circuit, a load circuit connected to the differential amplifier circuit, and the load circuit A changeover switch, and the changeover switch is used to switch between an overall load having the entire load circuit as a load of the differential amplifier circuit and a partial load having a portion of the load circuit as a load of the differential amplifier circuit. in configured to vary the gain of the differential amplifier circuit, moreover, the load circuit, the input signal of the differential amplifier circuit during the entire load through a capacitor It was be configured to amplify the force.

And in this invention, it has a differential amplifier circuit, a load circuit connected to the differential amplifier circuit, and a changeover switch connected to the load circuit, and the whole of the load circuit is formed by the changeover switch. A differential amplifier configured to change the gain of the differential amplifier circuit by switching between an entire load serving as a load of the differential amplifier circuit and a partial load using a part of the load circuit as a load of the differential amplifier circuit In the circuit, since the load circuit is configured to amplify the input signal of the differential amplifier circuit through a capacitor when the load is fully loaded, the gain of the differential amplifier circuit at the time of the entire load is increased. Can be made.

  Therefore, in the differential amplifier circuit according to the present invention, the gain ratio of the differential amplifier circuit can be increased without reducing the operation speed and without increasing the power consumption.

Therefore, when a two-stage amplifier having an offset compression function is configured using this differential amplifier circuit, a two-stage amplifier excellent in an offset compression function with reduced input conversion offset can be obtained.

  Further, when the analog / digital converter is configured using the differential amplifier circuit, the characteristics of the analog / digital converter can be improved.

  The analog / digital converter according to the present invention will be described below with reference to the drawings. In the following description, an analog signal is converted into the upper 2 bits of the digital signal, and then the lower 2 bits of the digital signal are converted, taking a total of 4 bits as a subranging type analog / digital converter. The specific embodiment of the invention is not limited to this.

  As shown in FIG. 1, the analog / digital converter 1 according to the present invention includes a sample hold means 2 for sampling and holding an analog signal, a reference voltage generation means 3 for generating a plurality of different reference voltages, an analog signal Comparing means 4 for comparing the voltage with a plurality of different reference voltages, and logic processing means 5 for outputting a digital signal corresponding to the analog signal by logically processing the output of the comparing means 4.

The sample hold means 2 holds the voltage of the analog signal applied to the input terminal T _in for a predetermined period at a predetermined timing and outputs it to the hold signal line 6.

The reference voltage generating means 3 has 16 identical resistance values between a high potential side reference power supply terminal T _rt that becomes a high potential side reference potential and a low potential side reference power supply terminal _Trb that becomes a low potential side reference potential. Are connected in series, and a plurality of reference voltages are generated by dividing the voltage between the reference potential on the high potential side and the reference potential on the low potential side by the 16 resistors R1 to R16, A predetermined reference voltage is output from the upper bit side reference voltage signal lines 7 and 8 or the lower bit side reference voltage signal lines 9 and 10.

Specifically, the reference voltage generating means 3, 4 between the high potential side reference power supply terminal T _rt and 4 th resistor R4 and 5 th resistor R5, and the low-potential reference power source terminal T _rb The upper bit side reference voltage signal lines 7 and 8 for outputting the upper bit side reference voltage are connected between the eye resistor R13 and the fifth resistor R12, respectively, while the high potential side reference power supply terminals _Trt to 1 A reference voltage on the lower bit side is connected between the third resistor R1 and the second resistor R2, and between the third resistor R3 and the fourth resistor R4 from the high potential side reference power supply terminal _Trt. The lower bit side reference voltage signal lines 9 and 10 to be output are connected to each other via switches SW1 and SW2 linked to each other, and the lower bit side reference voltage signal lines 9 and 10 are connected to the high potential side reference power supply terminal T _rt. 7 th resistor R7 and 8 th resistor between R8, and from the high potential side reference power supply terminal T _rt and 5 th resistor R5 6 th resistor from R6 Switch SW3 interlocking coupled between, SW4 is connected via, between the high potential side reference power supply terminal T _rt and ninth resistor R9 and 10th resistor R10, and the high potential reference power are connected via a switch SW5, SW6 which interlock coupled between the terminal T _rt 11 th resistor R11 and the twelfth resistor R12, further, from the high potential side reference power supply terminal T _rt for 15 th through between the resistor R15 and the sixteenth resistor R16, and a switch SW7, SW8 the interlocking coupled between the high potential side reference power source terminal T _rt 13 th resistor R13 and the 14 th resistor R14 It is connected.

  When converting the analog signal into the higher bit side digital signal, the reference voltage generation means 3 disconnects all the switches SW1 to SW8 and applies the reference voltage from the higher bit side reference voltage signal lines 7 and 8. On the other hand, when an analog signal is converted into a lower bit digital signal, only one pair of switches SW1 to SW8 is connected based on the upper bit conversion result, and the lower bit reference voltage signal line The reference voltage is output from 9,10.

  The comparison means 4 includes an upper bit side comparison means 11 that compares the voltage of the analog signal and the reference voltage on the upper bit side, and a lower bit side comparison means 12 that compares the voltage of the analog signal and the reference voltage on the lower bit side. It is composed. Here, since the upper bit side comparison means 11 and the lower bit side comparison means 12 have the same configuration, the upper bit side comparison means 11 will be described below.

  The upper bit side comparison means 11 comprises amplification means 13 for amplifying the difference between the voltage of the analog signal and the reference voltage, and comparison holding means 14 for comparing and holding the output of the amplification means 13.

  The amplification means 13 is connected to two two-stage amplifiers 17 in which two differential amplifiers 15 and 16 are connected in series, and differential amplifiers 15 and 15 preceding the adjacent two-stage amplifiers 17 and 17. And a complementary amplifier 18 that differentially amplifies the outputs of the differential amplifiers 15 and 15 at the preceding stage. Note that the two-stage amplifier 17 is not limited to the case where the two differential amplifiers 15 and 16 are connected in series, and may be configured such that three or more differential amplifiers are connected in series.

  Each of the two-stage amplifiers 17 has a variable gain differential amplifier 16 connected in series after the constant gain differential amplifier 15 as schematically shown in FIGS.

  The differential amplifier 15 in the previous stage connects the hold signal line 6 to the non-inverting input terminal 19 and connects the upper bit side reference voltage signal line 7 (8) to the inverting input terminal 20 via the switch SW9. The non-inverting input terminal 19 and the inverting input terminal 20 are short-circuited via the switch SW10. Here, the switches SW9 and SW10 are intermittently controlled by the clock signal CLK.

  The differential amplifier 16 in the subsequent stage has a load circuit 22 connected to the differential amplifier circuit 21 and a load switching means 23 connected to the load circuit 22. The load switching means 23 allows the entire load circuit 22 to be differentially connected. The gain of the differential amplifier circuit 21 can be increased or decreased by switching the entire load as the load of the amplifier circuit 21 and the partial load using a part of the load circuit 22 as the load of the differential amplifier circuit 21.

  Each of the two-stage amplifiers 17 has an offset compression function that apparently compresses the offset voltage of the preceding-stage differential amplifier 15 by increasing or decreasing the gain of the subsequent-stage differential amplifier 16 using the load switching means 23. ing.

  Hereinafter, a specific structure of each two-stage amplifier 17 will be described with reference to FIG.

  The differential amplifier 15 in the previous stage differentially connects a pair of N-channel transistors T11 and T12. The transistors T11 and T12 have a non-inverting input terminal 19 and an inverting input terminal 20 connected to their gate terminals. The current sources I1 and I2 are connected between the drain terminal and the power supply VCC, and the current source I3 is connected between the source terminal and the ground GND.

  The differential amplifier 15 in the previous stage connects the drain terminals of P-channel transistors T21 and T22 to the drain terminals of the transistors T11 and T12, and applies a predetermined bias voltage Vb1 to the gate terminals of the transistors T21 and T22. The output of the differential amplifier 15 in the previous stage is taken out from the source terminals of the transistors T21 and T22.

  Between the differential amplifier 15 at the front stage and the differential amplifier 16 at the rear stage, amplitude limiting means 24 for limiting the output amplitude of the differential amplifier 15 at the front stage is provided.

  The amplitude limiting means 24 is configured by connecting load resistors R21, R22 to the source terminals of the transistors T21, T22, and connecting a resistor R30 between the load resistors R21, R22 and the ground GND. Here, the output amplitude of the differential amplifier 15 at the front stage is limited by the load resistors R21 and R22, and the DC operating point of the input signal of the differential amplifier 16 at the rear stage is adjusted to the optimum voltage by the resistor R30.

  As shown in FIGS. 4 and 5, the differential amplifier 16 at the rear stage connects a drain terminal of an N-channel transistor T31 serving as a current source to a power supply VCC, and forms a differential pair with the source terminal of the transistor T31. N-channel transistors T32 and T33 are connected to form a differential amplifier circuit 21. Transistors T21 and T22 serving as outputs of the differential amplifier 15 in the previous stage are connected to the gate terminals of the transistors T32 and T33 of the differential amplifier circuit 21. On the other hand, the non-inverted output terminal 25 and the normal output terminal 26 are connected to the source terminals of the transistors T32 and T33 to extract the output.

  Capacitance cutting may be performed by connecting a capacitor between the gate terminals of the transistors T32 and T33 and the source terminals of the transistors T21 and T22. In this case, it is necessary to apply a voltage at a predetermined DC operating point to the gate terminals of the transistors T32 and T33 at a predetermined timing.

  The differential amplifier 16 in the subsequent stage connects the drain terminals of the transistors T34 and T35 as the load circuit 22 to the source terminals of the transistors T32 and T33 of the differential amplifier circuit 21, and the ground terminals to the source terminals of the transistors T34 and T35. GND is connected.

  Further, the differential amplifier 16 in the subsequent stage has switching transistors T36 and T37 as load switching means 23 connected between the drain terminals and gate terminals of the transistors T34 and T35 of the load circuit 22, and the switching transistors T36, A clock signal CLK is applied to the gate terminal of T37.

  Further, the differential amplifier 16 in the subsequent stage connects capacitors C1 and C2 as voltage holding means 27 for holding the voltage of the input signal of the differential amplifier circuit 21 to the gate terminals of the transistors T34 and T35 of the load circuit 22. The gate terminals of transistors T32 and T33, which are input terminals of the differential amplifier circuit 21, are connected to the capacitors C1 and C2.

  In the differential amplifier 16 in the subsequent stage, when the switching transistors T36 and T37 are disconnected, the entire load circuit 22 becomes a load (overall load). In this case, the current source load by the transistors T34 and T35 As a result, the output impedance increases, thereby increasing the gain of the differential amplifier 16 in the subsequent stage. On the other hand, when the switching transistors T36 and T37 are connected, a part of the load circuit 22 is a load (partial load). In this case, a diode load is formed by the transistors T34 and T35, and the output impedance is reduced. As a result, the gain of the differential amplifier 16 in the subsequent stage is reduced. Note that since a voltage is held in the capacitors C1 and C2 connected to the gate terminals of the transistors T34 and T35, a DC potential is held.

  In addition, since the input signal of the differential amplifier 16 (differential amplifier circuit 21) is applied to the gate terminals of the transistors T34 and T35 of the load circuit 22 via the capacitors C1 and C2, the load circuit 22 includes the transistor T34. , The input signal of the differential amplifier circuit 22 is amplified by the transistors T34 and T35 at the time of the entire load using T35 as a current source load.

  Therefore, the differential amplifier 16 in the subsequent stage can further increase the gain at the entire load when the switching transistors T36 and T37 are in the disconnected state, and accordingly, the differential at the full load can be increased. The gain of the amplifier circuit 21 can be increased.

  Next, the operation of the two-stage amplifier 17 will be described.

  The two-stage amplifier 17 applies the voltage of the analog signal to the non-inverting input terminal 19 and the inverting input terminal 20 of the differential amplifier 15 in the previous stage by turning off the switch SW9 and connecting the switch SW10 by the clock signal CLK. The switch SW9 is connected and the switch SW10 is disconnected by the clock signal CLK, and the analog signal voltage is applied to the non-inverting input terminal 19 of the differential amplifier 15 in the previous stage, while the inverting input terminal The comparison mode in which the reference voltage is applied to 20 is alternately repeated.

  In the reset mode, the load switching means 23 (switching transistors T36 and T37) are connected, the load of the differential amplifier 16 at the rear stage is a diode load, and the gain of the differential amplifier 16 at the rear stage is reduced. In the comparison mode, the load switching means 23 (switching transistors T36 and T37) are disconnected, the load of the subsequent differential amplifier 16 is used as a current source load, and the gain of the subsequent differential amplifier 16 is increased. . That is, the two-stage amplifier 17 is configured so that the gain of the differential amplifier 16 at the subsequent stage is larger in the comparison mode than in the reset mode.

  In this way, by increasing or decreasing the gain of the differential amplifier 16 at the subsequent stage, the two-stage amplifier 17 apparently compresses the offset voltage of the differential amplifier 15 at the previous stage.

That is, the offset voltage of the differential amplifier 15 in the previous stage is Vos, the gain in the reset mode (diode load) is Gr, the gain in the comparison mode (current source load) is Gc, the output voltage is Vout, and the input during comparison When the voltage is Vin, the output voltage Vout in the reset mode is
Vout = Gr ・ Vos
On the other hand, the output voltage Vout at the time of comparison is
Vout = Gc ・ Vin
Because
Gr ・ Vos = Gc ・ Vin
And
Vin = Vos · Gr / Gc
It becomes.

  That is, in the two-stage amplifier 17 using the differential amplifier 16 having the above configuration, the offset voltage is compressed to Gr / Gc times, and the input conversion offset can be expressed as Vos · Gr / Gc.

When the transconductance of the transistors T32 and T33 constituting the differential amplifier circuit 16 is gm1, the transconductance of the transistors T34 and T35 constituting the load circuit 22 is gm2, the load capacitance is C, and the comparison time is t, the reset mode The gain Gr at the time is the same as in the conventional circuit,
Gr = gm1 / gm2
However, the gain Gc at the total load is different from that in the conventional circuit, while the comparison time t is short,
Gc = (gm1 + gm2) / Ct
Therefore, the input conversion offset is
Vin = Vos · C / ((gm2 + gm2 / gm1) · t)
It can be expressed as

In the conventional circuit, the input conversion offset is
Vin = Vos · C / (gm2 · t)
Therefore, the differential amplifier 16 having the above configuration increases the effect of offset compression by the denominator gm2 / gm1.

  Next, the operation of the analog / digital converter 1 will be described with reference to FIG.

  The analog / digital converter 1 operates in synchronization with the clock signal CLK.

  The sample hold means 2 tracks (samples) the analog signal for a predetermined period (T) in synchronization with the rise of the clock signal CLK, and then only for a predetermined period (H) until the next rise of the clock signal CLK. Hold the analog signal.

  The amplifying means 13 on the upper bit side switches from the reset mode to the comparison mode after a predetermined time (t1) from the rise of the clock signal CLK, and amplifies the voltage difference between the analog signal voltage held by the sample hold means 2 and the reference voltage. Then, the comparison mode is switched to the reset mode again in synchronization with the falling edge of the clock signal CLK.

  The upper bit side comparison and holding means 14 is reset in synchronization with the rising edge of the clock signal CLK, and holds the output of the amplifying means 13 in synchronization with the falling edge of the clock signal CLK.

  The output held by the upper bit side comparison and holding means 14 is logically processed by the logic processing means 5 to generate the upper bit side digital signal and the reference voltage generating means 3 generates the lower bit side reference voltage. To do.

  On the other hand, the amplifying means 13 on the lower bit side switches from the reset mode to the comparison mode after a predetermined time (t2) from the rise of the clock signal CLK, and the voltage difference between the analog signal voltage held by the sample hold means 2 and the reference voltage. Is switched again from the comparison mode to the reset mode in synchronization with the rise of the clock signal CLK.

  Further, the comparison holding means 14 on the lower bit side is reset in synchronization with the fall of the clock signal CLK, and holds the output of the amplification means 13 in synchronization with the rise of the clock signal CLK.

  The output held by the lower bit side comparison holding means 14 is logically processed by the logic processing means 5 to generate a lower bit side digital signal, and a digital signal corresponding to the analog signal is generated one clock after the clock signal CLK. Output from the logic processing means 5.

  In the analog / digital converter 1, the circuit shown in FIG. 5 is used as the differential amplifier 16 following the two-stage amplifier 17. However, the present invention is not limited to this and is shown in FIGS. A circuit may be used. 6 to 9, components having the same functions as those of the circuit shown in FIG.

  The differential amplifier circuit 16a shown in FIG. 6 is a circuit when cascode-connected transistors T38, T34, T39, and T35 are used as the load circuit 22. A predetermined bias voltage is applied to the gate terminals of the transistors T38 and T39.

  The differential amplifier circuit 16b shown in FIG. 7 uses cascode-connected transistors T32, T40, T33, T41 as the differential amplifier circuit 21, and cascode-connected transistors T38, T34, T39, T35 as the load circuit 22. Circuit. A predetermined bias voltage is applied to the gate terminals of the transistors T38, T39, T40, and T41.

  The differential amplifier circuit 16c shown in FIG. 8 uses transistors T38, T34, T39, T35 connected in cascode as the load circuit 22, and a capacitor C3 for holding a voltage between the gate terminals of the transistors T34, T35 and the ground GND. , C4 is connected. A predetermined bias voltage is applied to the gate terminals of the transistors T38 and T39.

  The differential amplifier circuit 16d shown in FIG. 9 uses cascode-connected transistors T32, T40, T33, T41 as the differential amplifier circuit 21, and uses cascode-connected transistors T38, T34, T39, T35 as the load circuit 22. Further, this is a circuit when amplifiers AMP1 and AMP2 for amplifying an input signal are connected between capacitors C1 and C2 and an input terminal. A predetermined bias voltage is applied to the gate terminals of the transistors T38, T39, T40, and T41. A buffer may be used instead of the amplifiers AMP1 and AMP2.

  In the above embodiment, a 4-bit sub-ranging type analog / digital converter that performs conversion by dividing into 2 bits every 2 bits has been described as an example. However, the present invention is not limited to this, and conversion is performed in multiple stages. It is also possible to use a configuration that performs the above-mentioned, and it is not limited to a single input type, and may be a differential input type. Also, the specific circuit is not limited to the one with only the positive power supply, and may use a positive / negative power supply or only a negative power supply, and the specific elements constituting the circuit are appropriately selected. It's okay.

Explanatory drawing which shows the analog / digital converter which concerns on this invention. The schematic diagram which shows an amplification means (at the time of reset mode). The schematic diagram which shows an amplification means (at the time of a comparison mode). The circuit diagram which shows an amplification means. The circuit diagram which shows a differential amplifier circuit. The circuit diagram which shows another differential amplifier circuit. The circuit diagram which shows another differential amplifier circuit. The circuit diagram which shows another differential amplifier circuit. The circuit diagram which shows another differential amplifier circuit. The timing chart which shows the operation | movement of an analog / digital converter. The circuit diagram which shows the conventional differential amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Analog / digital converter 2 Sample hold means 3 Reference voltage generation means 4 Comparison means 5 Logic processing means 6 Hold signal line
7,8 Upper bit side reference voltage signal line
9,10 Lower bit reference voltage signal line
11 Upper bit side comparison means
12 Lower bit side comparison means
13 Amplification means
14 Comparison holding means
15,16 differential amplifier
17 Two-stage amplifier
18 Complementary amplifier
21 Differential amplifier circuit
22 Load circuit
23 Load switching means
24 Amplitude limiting means
27 Voltage holding means

Claims (3)

A differential amplifier circuit;
A load circuit connected to the differential amplifier circuit;
A changeover switch connected to the load circuit,
By switching the whole load circuit as a load of the differential amplifier circuit and a partial load using a part of the load circuit as a load of the differential amplifier circuit by the changeover switch, the differential amplifier circuit In a differential amplifier configured to change gain,
The differential amplifier is configured to amplify an input signal of the differential amplifier circuit through a capacitor when the load circuit is fully loaded. In a two-stage amplifier having an offset compression function of compressing an offset voltage by connecting at least two differential amplifiers in series and increasing / decreasing a gain of a subsequent differential amplifier,
The latter differential amplifier is
A differential amplifier circuit;
A load circuit connected to the differential amplifier circuit;
A changeover switch connected to the load circuit,
By switching the whole load circuit as a load of the differential amplifier circuit and the partial load using a part of the load circuit as a load of the differential amplifier circuit by the changeover switch, the differential amplifier circuit Configure to change the gain,
In addition, the load circuit is configured to amplify the input signal of the differential amplifier circuit through a capacitor when the load is fully loaded. In an analog / digital converter configured to amplify a difference between a voltage of an analog signal and a plurality of different reference voltages by a plurality of amplifying means and convert the difference into a digital signal, respectively,
Each amplifying means is a differential amplifier having an offset compression function for compressing an offset voltage,
The differential amplifier is
A differential amplifier circuit;
A load circuit connected to the differential amplifier circuit;
A changeover switch connected to the load circuit,
By switching the whole load circuit as a load of the differential amplifier circuit and the partial load using a part of the load circuit as a load of the differential amplifier circuit by the changeover switch, the differential amplifier circuit Configure to change the gain,
In addition, the load circuit is configured to amplify the input signal of the differential amplifier circuit via a capacitor when the load is fully loaded.

Images