JP3964575B2 - Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arrangement method - Google Patents

Description

（但し、ｌを図１４中の配線の長さとする）
一方、図１４（ａ）に示す第９の実施形態の配線形状の配線遅延Ｄ_ｄは、以下の式で得られる。
【０１２０】

尚、図１４（ａ）のＰ５とＰ６との間の距離は微小であるため、（２）の計算上無視することができる。
【０１２１】
従って、図１４（ｂ）のＨ型よりも図１４（ａ）の第９の実施形態の形状の方が、以下の分だけＲＣ遅延を小さくすることができる。
【０１２２】

このＲＣ遅延の低減は、配線分岐が信号伝播の上流寄りになることにより得られる効果である。また、このディレイの減少効果は、下流側に負荷容量がついていると、さらに大きくなる。さらに、使用する斜め方向配線の配線抵抗の方が、一般的にＸ−Ｙ方向配線の配線抵抗より小さいため、この点もディレイの減少効果を増す要因となる。
【０１２３】
尚、クロック端子が不均一に分布する場合には、ディレイのバランスポイントを図１４（ａ）のライン上にとることができない場合がある。こうした場合、図１５に示すように配線形状を修正する。この図１５の配線形状により、バランスポイントを的確に設定することができる。この図１５の配線形状は、図１４（ｃ）の全体のクロックツリーの中で、部分的に用いればよい。
【０１２４】
また、図１６（ｂ）に示すように、ツリーの途中に挿入したバッファ３１０の出力端子付近において、他のバッファとディレイを揃えるために迂回経路３１１を設けることがある。こうした場合に、図１６（ａ）に示すような斜め方向配線を使用することで、ビアホール数を削減することができる。従って、この図１６（ａ）の構成は、ビアホール抵抗の低減や、エレクトロマイグレーション耐性の面で有利な効果が得られる。
【０１２５】
尚、図１７（ａ）、（ｂ）、（ｃ）に、４５°及び１３５°方向の斜め配線格子を自動配線で行う場合の具体的な配線方法として迷路法を使う配線設計の例を示す。
【０１２６】
図１７（ａ）、（ｂ）、（ｃ）中の３２０，３２１は互いに接続すべき端子ペアの始点と終点である。３３０はチップコア領域内の配線禁止領域である。始点３２０から終点３２１まで図１７（ａ）、（ｂ）、（ｃ）中の太線で示される経路で配線が配置される。図１７（ａ）に示す例は、Ｘ−Ｙ方向配線と斜め方向配線を併用した場合の配線を示す。図１７（ｂ）の例は、斜め方向配線だけで配線した例を示す。また図１７（ｃ）示す例は、Ｘ−Ｙ方向配線と１３５°方向の斜め配線を使った場合の配線を示している。
【０１２７】
上記のように、第９の実施形態によれば、ツリー経路の構築において、斜め方向配線を活用した単位配線形状を組み合わせた構成を用いる。このため、配線ＲＣ遅延が低減され、最適なクロックツリーを構築することができる。
【０１２８】
第１０の実施形態
第１０の実施形態は、上記の実施形態の斜め配線格子を利用した多層配線構造において、図３のＸ−Ｙ方向の配線格子を、互いに直交する３層の配線層により構成することで、セルロウ方向の配線リソースを増加させる実施形態である。
【０１２９】
図１８は、本発明の第１０の実施形態に係る半導体集積回路の配線格子構造を示すレイアウト図である。図１９は、図１８に示すような配線格子構造に基づいて配線を実施した場合の配線構造を図１８のＸ軸方向から観察した断面図である。
【０１３０】
図１８において、Ｘ−Ｙ方向の配線格子は、３層の配線により構成されている。具体的には、図１８に示すように、第１層６０１、第２層６０２、第３層６０３の配線と、第４層６０４、第５層の配線６０５とは、互いに直交する配線格子を構成している。ここで、第１０の実施形態は、第１層配線６０１と平行する第３層配線６０３を提供する。すなわち、第１層および第３層配線に対して、第４層配線と第５層配線はそれぞれ４５°、１３５°で交差するようにグリッドが配置されている。
【０１３１】
図１８中の６０１は、第１層の配線グリッドであり、その上層に直交して第２層の配線グリッド６０２が形成されている。この第２の配線グリッド６０２の上層に直交して第３の配線グリッド６０３が形成されている。さらに、第１層配線グリッド６０１および第３層配線グリッド６０３に対して４５°斜め方向の第４層配線グリッド６０４と、第１層配線グリッド６０１および第３層配線グリッド６０３に対して１３５°斜め方向の第５層配線グリッド６０５とが順次配置されている。
【０１３２】
第１０の実施形態は、第１の実施形態と同様、斜め方向に配置された第４層配線６０４の間と第５層配線６０５の間の配線ピッチを、それぞれ第１層配線６０１の間及び第２層配線６０２の間、第２層配線６０２及び第３層配線６０３との間の配線ピッチ（λ）の√２倍（√２・λ）に設定する。また、図１９に示すように、斜め方向に配置された第４層配線６０４の間と第５層配線６０５の間の配線幅を、それぞれ第１層配線６０１の間及び第２層配線６０２の間、第２層配線６０２及び第３層配線６０３との間の配線ピッチ（ｔ）の√２倍（√２・ｔ）に設定する。尚、第１層配線６０１、第２層配線６０２、第３層配線６０３は、配線設計におけるデザインルールにより定まる最小の配線幅、高さ、配線ピッチで定義されているのが望ましい。
【０１３３】
図１８に戻り、第１層配線６０１と第３層配線６０３はセルロウ方向と平行の方向に形成される。このため、第１の実施形態と比較して、さらにセルロウ方向の配線リソースを増加させることができる。尚、第１０の実施形態は、配線チャネルを設けない点において、第３の実施形態と相違する。
【０１３４】
従来のＸ−Ｙ方向に直交する配線格子による多層構造においては、複数の層の配線を平行に形成した場合、配線の平行配置によるクロストークノイズを生じていた。第１０の実施形態は、斜め配線格子と配線の平行配置を組み合わせることにより、クロストークノイズの発生を抑制しつつセルロウ方向の配線リソースを確保することができる。
【０１３５】
上記のように、第１０の実施形態によれば、セルロウと平行な方向に第１層配線および第３層配線を形成し、この上層に上記の斜め配線格子を形成する。このため、セルロウ方向の配線リソースを確保することができる。
【０１３６】
尚、第１０の実施形態の変形例として、第４層配線６０４と第５層配線６０５とが成す斜め配線格子のさらに上層に、１層あるいは複数の層の配線格子を形成してもよい。このさらに上層の配線格子は、第５層配線６０５に対して、互いに直交する第６層配線および第７層配線がなす２つの配線格子ペアが４５度の角度で形成され、以降、この構成を繰り返して構成される。すなわち、上記の第１層配線、第２層配線および第３層配線がなす基準配線格子と、第４層配線および第５層配線がなす斜め配線格子に加え、さらに互いに直交する第ｐ−１層と第ｐ層の２つの配線格子ペアが、第ｐ−２層の配線に対して４５度の角度をなして形成されるｑ層の配線構造が提供される。（但し、ｑ＞＝５）
ここで、互いに直交する第ｐ−１層と第ｐ層の配線は、第ｐ−２層配線の配線ピッチの√２倍に設定する。また、第ｐ−１層と第ｐ層の配線の配線幅を、それぞれ第ｐ−２層配線の配線ピッチの√２倍に設定する。尚、第１層配線、第２層配線、第３層配線は、配線設計におけるデザインルールにより定まる最小の配線幅、高さ、配線ピッチで定義されているのが望ましい。
【０１３７】
この変形例によれば、回路の集積度を向上させるとともに、配線ＲＣ遅延を低減させることができる。
【０１３８】
第１１の実施形態
第１１の実施形態は、上記の実施形態の斜め配線格子を利用した多層配線構造において、斜め配線格子をなす配線層の配線を、比較的長い配線であるグローバル配線に用いることにより、回路スピードを向上させる実施形態である。
【０１３９】
図２０は、第１１の実施形態における配線の配置を説明する図である。図２１は、第１１の実施形態におけるグローバル配線を説明する図である。尚、以下では理解の便宜のため、第１０の実施形態と同様、Ｘ−Ｙ方向の配線格子が第１層配線、第２層配線および第３層配線により形成され、斜め配線格子が第４層配線および第５層配線により形成される場合を例として説明するが、これが第１の実施形態に示される第１層配線および第２層配線によりＸ−Ｙ方向の配線格子が形成される場合にも適用できることはいうまでもない。
【０１４０】
図２０に示すように、第１１の実施形態は、斜め配線格子をなす第４層配線及び第５層配線の上層配線は、グローバル配線のために用いられる。グローバル配線においては、一般に求められる遅延特性がクリティカルであって、この遅延特性がチップ全体の回路スピードを左右するため、特に配線ＲＣ遅延が問題となる。ここで、上記の実施形態は、上層配線のＲＣ遅延が下層配線（Ｘ−Ｙ方向の配線）に対して１／２となる。このため、この上層配線である斜め配線格子の配線をグローバル配線に用いることによって、回路の動作スピードを向上させることができる。一方、下層配線（Ｘ−Ｙ方向の配線）は、ローカルな配線に用いられることが望ましい。
【０１４１】
尚、ここで、グローバル配線とは、チップ全体にわたるクロックネット（クロック配線）、バス、電源補強線などに用いられる配線である。例えば、０．２５μｍのデザインルールの場合、配線距離が約２．５ｍｍ以上の配線をグローバル配線とすると、この場合、配線ＲＣ遅延は約１．４ｎｓｅｃ程度となる。一方、ローカル配線とは、これより配線距離の短い配線をいう。
【０１４２】
尚、このローカル配線に用いられるＸ−Ｙ方向の配線（下層配線）の配線ピッチは、斜め方向配線（上層配線）の配線ピッチより狭くなる。この場合、図２１に示すように、例えば、クロックバッファセルやバス用のバッファセルなど、ドライブ力の強いセル６１０は、各層の配線（６０１〜６０４）を都度介するのではなく、グローバル配線と直接接続することが望ましい。このため、第１１の実施形態は、ドライブ力の強いセルの出力端子の形状を直接第４層以上の斜め配線格子の配線と接続可能な形状とする。図２２に示すように、これらドライブ力の強いセルの出力端子７０４は、上層の斜め配線格子の直交するアクセスポイントに定義される。
【０１４３】
これらのセルの出力端子形状を、グローバル配線に直接接続できる形状とすることにより、これらのセルについての配線長が短縮され、配線設計も容易となる。また、直接上層の第４層以上の斜め配線格子の配線と接続するので、ビアホールの数を低減することができ、ビアホールに起因する抵抗を低減することができる。
【０１４４】
上記のように、第１１の実施形態によれば、斜め配線格子をなす配線層の配線を、比較的長い配線であるグローバル配線に用いる。このため、回路特性に大きく影響する配線の配線ＲＣ遅延が低減されて、回路スピードが向上される。 第１２の実施形態
第１２の実施形態は、上記の実施形態の斜め配線格子を利用した多層配線構造において、ＰＬＬ（Phase Locked Loop）回路からのクロック供給用のクロック配線の構造を、ＰＬＬからチップセンターへ斜め配線格子を用いて配線し、このチップセンターから各フリップフロップへの配線をツリー構造により定義することにより、ＲＣ積をバランスさせる実施形態である。
【０１４５】
図２３（ａ）は、従来のＰＬＬからのクロック供給配線の配線手法を示す図である。ＰＬＬ８０３は、センシティブなアナログセルであるため、回路特性上、チップの端部に配置する必要がある。このため、Ｘ−Ｙ方向の配線８０１を用いる従来手法では、配線長が長くなっていた。図２３（ｂ）は、第１２の実施形態の、ＰＬＬからのクロック供給配線の配線手法を示す図である。第１２の実施形態は、ＰＬＬ８０２からチップセンター８０４へのクロック供給配線８０２を斜め配線格子を用いて行う。このため、配線長が短縮されるとともに、配線ＲＣ遅延が低減される。図２４に示すように、このチップセンターから各フリップフロップがなすクラスターへの配線がバッファセルを介してなされる。図２５は、第１２の実施形態のクロックツリーを示す図である。各バッファセルからは、図２４に示すように、ＲＣ積をバランスさせるように、クロック配線経路が構成される。すなわち、チップセンターからはＸ−Ｙ方向および斜め方向の遅延をバランスさせるように、クロック配線経路が階層的に構成される。この階層的クロックツリーは、図２６に示すように、上記の第９の実施形態と同様に構成されてよい。尚、ＰＬＬは、ＤＬＬに置き換えられてもよい。
【０１４６】
尚、これらのクロック配線経路には、上層の斜め配線格子を優先的に用い、かつ配線幅を広く設定する方がよい。すなわち、斜め配線格子の配線ピッチが下層のＸ−Ｙ配線格子の√２倍であれば、斜め配線格子に太い配線幅を用いることが容易であり、これによって配線抵抗Ｒの低下に伴う配線ＲＣ遅延の増加を抑えることができる。
【０１４７】
上記のように、第１２の実施形態によれば、ＰＬＬからチップセンターへのクロック供給配線に斜め配線格子を用い、このチップセンターからチップ上の各フリップフロップへのクロック供給配線をＸ−Ｙ方向および斜め方向の遅延をバランスさせるように、クロック配線経路が階層的に構成される。このため、クロック供給のための配線長が短縮されるとともに配線ＲＣ遅延が低減される。
【０１４８】
第１３の実施形態
第１３の実施形態は、上記の実施形態の斜め配線格子を利用した多層配線構造において、チップ上にＳＲＡＭが配置される場合に、斜め配線格子を用いてこのＳＲＡＭ上を通過配線させた実施形態である。尚、第１３の実施形態において、ＳＲＡＭをＤＲＡＭに置き換えて構成してもよい。
【０１４９】
図２７は、第１３の実施形態におけるメモリ上の通過配線を説明する図である。下層のＸ−Ｙ方向の配線層１、２は、例えばワード線およびビット線に用いられ、ＳＲＡＭ９０１内部に形成される。一方、通過配線３、４は、上層の斜め配線格子を用いて配線される。すなわち、ＳＲＡＭ９０１内部のＸ−Ｙ方向の配線１、２と、斜め配線格子を用いた通過配線２、３とは従来のように平行とならない。このため、従来と比較して、カップリングノイズが低減される。
【０１５０】
上記のように、第１３の実施形態によれば、メモリ上を通過する通過配線を斜め配線格子を用いてメモリ内の配線に対して４５度または１３５度の交差角を成して形成する。このため、メモリ内配線と通過配線とのカップリングノイズが低減される。
【０１５１】
尚、本発明は、上述した実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更することが可能である。
【０１５２】
【発明の効果】
以上説明したように、本発明によれば、Ｘ−Ｙ方向に直交する配線格子に加えて、斜め方向に直交する配線格子を設けた多層配線構造を用いる半導体集積回路において、斜め配線層を活用することによって、回路の遅延特性とノイズ耐性が向上すると共に配線設計の容易化および製造コストの低減化が実現される。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体集積回路装置の配線格子構造を示すレイアウト図である。
【図２】図１に示すような配線格子構造に基づいて配線を実施した場合の配線構造の一例を示す平面図である。
【図３】図２のＡ−Ａ断面図である。
【図４】本発明の第２の実施形態に係る半導体集積回路装置のリピータセル挿入手法を説明する図である。
【図５】配線遅延を説明する図である。
【図６】本発明の第３の実施形態に係る半導体集積回路装置の構成を示すレイアウト図である。
【図７】本発明の第４の実施形態に係る半導体集積回路装置のビアホールの形状を示す部分平面図である。
【図８】本発明の第５の実施形態に係る半導体集積回路装置におけるセルまたはメガセルを示す図である。
【図９】第５の実施形態における配線の障害物の例を示す図である。
【図１０】第５の実施形態における配線の障害物領域と配線との関係を説明する図である。
【図１１】本発明の第６の実施形態に係る半導体集積回路装置の要部構成を示す図である。
【図１２】本発明の第７の実施形態に係る半導体集積回路装置の要部構成を示す図である。
【図１３】本発明の第８の実施形態に係る半導体集積回路のセルの配置方法を示す図である。
【図１４】本発明の第９の実施形態に係る半導体集積回路のクロックツリーの基本構成を説明する図である。
【図１５】第９の実施形態に係るクロックツリーの構成の変形例を説明する図である。
【図１６】迂回経路を設けた場合のツリー要部の構成を説明する図である。
【図１７】斜め配線格子を自動配線で行う場合の具体的な配線方法を示した図である。
【図１８】本発明の第１０の実施形態に係る半導体集積回路の配線格子構造を示すレイアウト図である。
【図１９】図１８の配線格子構造をＸ軸方向から観察した場合の断面図である。
【図２０】本発明の第１１の実施形態に係る半導体集積回路のグローバル配線およびローカル配線による配線格子構造を説明する図である。
【図２１】第１１の実施形態において、ドライブ力の強いセルから斜め配線格子の配線への直接接続を説明する図である。
【図２２】図２１のドライブ力が強いセルの出力端子の定義位置を説明する図である。
【図２３】従来のＰＬＬから各フリップフロップへのクロック供給配線の配線構造および本発明の第１２の実施形態に係るＰＬＬから各フリップフロップへのクロック供給配線の配線構造を説明する図である。
【図２４】第１２の実施形態に係るＰＬＬから各フリップフロップへのクロック供給配線の配線構造を説明する図である。
【図２５】第１２の実施形態のクロックツリー構造を説明する図である。
【図２６】第１２の実施形態のクロックツリー構造を説明する図である。
【図２７】本発明の第１３の実施形態に係る半導体集積回路の配線格子構造を示すレイアウト図である。
【図２８】斜め方向の配線を利用した従来の半導体集積回路装置の配線格子構造を示すレイアウト図である。
【図２９】従来技術の格子点のずれの問題点を説明する図である。
【符号の説明】
１、６０１ 第１層配線
２、６０２ 第２層配線
３、６０３ 第３層配線
４、６０４ 第４層配線
１０ 半導体基板
１１ 層間絶縁膜
１２、１３、１４ ビアホール
２０ リピータセル
２１、２２、１０１、２０１ セル
８０ セルロウ
８５ 配線チャネル
１０２ 有効領域
１０３ トランジスタ領域
１９１ 電源供給用配線
２５０、２６０ カットライン
６０５ 第５層配線
６１０ ドライブ力の強いセル
８０１、８０２ クロック配線
８０３ ＰＬＬ
８０４ チップセンター
８０５ バッファセル
８０６ フリップフロップ
８０７ クラスタ
９０１ ＳＲＡＭ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure, a semiconductor integrated circuit wiring method, and a cell arrangement method. In particular, in a semiconductor integrated circuit in which a wiring layer of an oblique wiring grid is formed above a wiring layer of a wiring grid in the XY direction, a semiconductor integrated circuit and a semiconductor that realize a reduction in circuit delay and an improvement in noise resistance The present invention relates to integrated circuit wiring technology.
[0002]
[Prior art]
Conventional multi-layer wiring structures of LSIs using the standard cell system or the gate array system have employed a system in which orthogonal wiring layers are stacked on top. That is, the n-1th layer and the nth layer are orthogonal to each other, such that the first layer and the second layer are orthogonal to each other, and the second layer and the third layer are orthogonal to each other. In such a multilayer wiring structure in which the layers are orthogonal to each other, when two points in the diagonal direction are connected, points separated by the Euclidean distance are connected. For this reason, a wiring having a length longer than the distance of √2 times the linear distance is required. Therefore, the orthogonal multilayer wiring structure has an overhead in terms of integration and delay characteristics.
[0003]
However, when designing LSI wiring on a computer, the method of wiring in an orthogonal coordinate system is simple in terms of algorithm. For this reason, wiring design has been performed on the computer ignoring the overhead.
[0004]
However, as the miniaturization of the circuit structure progresses, the delay component due to the wiring structure has come to influence the performance of the entire circuit. For this reason, it has become impossible to ignore the overhead due to the long wiring length.
[0005]
Specifically, first, the delay component due to the wiring resistance occupies most of the critical path delay. As described above, the influence of the wiring length on the circuit performance is increasing.
[0006]
Second, the breakdown of the load capacitance caused by the wiring is dominated by the coupling capacitance between adjacent wirings rather than the capacitance of the substrate. For this reason, how to reduce the capacitance between adjacent wirings has become an important factor for improving circuit performance.
[0007]
Thirdly, malfunction due to coupling noise due to the coupling capacitance between the wirings has become serious. Especially in the conventional wiring structure in which all the wirings are orthogonal to each other, when the wirings that run in parallel in the same layer affect each other, even if the wiring is replaced with another wiring layer, it is You will run in parallel. For this reason, it is difficult to reduce the coupling capacitance between wirings running in parallel in the same layer.
[0008]
In connection with the orthogonal multilayer wiring structure, a wiring technique has been proposed in which the wiring length is shortened by using wiring in an oblique direction (45 ° or 135 °) in addition to the orthogonal wiring structure. For example, Japanese Patent Laid-Open No. 5-102305 "Automatic Layout Method for Semiconductor Integrated Circuit" discloses this oblique wiring technique. This prior art will be described.
[0009]
FIG. 28 is a layout diagram showing a wiring grid structure of a conventional semiconductor integrated circuit device using the diagonal wiring.
[0010]
In this wiring structure, a wiring grid in an oblique direction is formed as another layer on a layer constituting orthogonal coordinates. Reference numeral 401 in FIG. 28 denotes a first-layer wiring grid (grid), and a second-layer wiring grid 402 is formed orthogonal to the upper layer. Further, in these upper layers, a third layer wiring grid 403 inclined at 45 ° with respect to the first layer 401 and a fourth layer wiring grid 404 inclined at 135 ° with respect to the first layer 401 are formed. .
[0011]
However, this prior art multilayer wiring technique using wiring in an oblique direction has the following problems.
[0012]
(1) In the conventional multilayer wiring structure, since the wiring grid in the oblique direction is simply provided, there is a problem that the grid points are shifted. That is, as shown in FIG. 29, the lattice points of the first layer 401 and the second layer 402 are 501. On the other hand, the lattice points of the third layer 403 and the fourth layer 404 are 502. Here, when connecting holes (via holes) are placed from the fourth layer 404 to the third layer 403, they are placed at the lattice points 502. On the other hand, when a via hole is placed from the third layer 403 to the second layer 402, it is placed at the lattice point 501. However, if these lattice points 502 and 501 are close to each other, a via hole cannot be placed. For this reason, it is necessary to provide a via hole at another position. As described above, the lattice points are shifted between the upper layer diagonal wiring grid (third layer 403 and fourth layer 404) and the lower layer XY wiring grid (first layer 401 and second layer 402). The wiring design was complicated.
[0013]
(2) The resistance of the upper diagonal wiring layer is the same as that of the lower wiring layer. For this reason, even if an oblique wiring layer is used as an upper layer, RC delay caused by wiring is not reduced. Here, the RC delay is a delay due to the resistance component R and the capacitance component C. For this reason, a wiring structure suitable for global wiring for connecting long distances cannot be constructed even if an upper-layer diagonal wiring grid is used.
[0014]
(3) The wiring pitch of the upper diagonal wiring layer is generally not wider than the minimum design rule. For this reason, even if an oblique wiring layer is disposed on the upper layer, the adjacent wiring capacity is not reduced. With respect to this point, a second technique for obliquely laying out the wiring of the layer with the strictest restriction on the arrangement and wiring interval according to the design rule with respect to the wiring grid on the CAD is disclosed in Japanese Patent Laid-Open No. 7-86414 “Semiconductor Device”. ing. However, this conventional technique does not reduce the wiring resistance because the wiring width is not wide at the same time. Further, since the coupling capacitance with the adjacent wiring is not reduced, the RC delay of the wiring cannot be reduced.
[0015]
(4) In the prior art, the shape of the via hole is defined as a rectangular shape. However, when connecting wires other than the orthogonal wires, that is, when connecting wires that cross diagonally, a rectangular via hole shape cannot secure a necessary and sufficient cut area. Therefore, the resistance to the electromigration phenomenon causing the disconnection failure of the wiring is insufficient.
[0016]
(5) The relationship between the definition of a cell row formed by arranging logic cells in a row and the definition of an oblique wiring grid was not clear. For this reason, for example, when a total of four wiring layers, that is, two orthogonal wiring layers and two oblique wiring layers, are defined, it is clear that the wiring resources located in parallel with the cell row are insufficient. In this regard, Japanese Patent Laid-Open No. 5-243379 “Semiconductor Integrated Circuit Device” discloses a technique for solving the above-described shortage of wiring resources by defining two wiring layers in an oblique direction on three orthogonal wiring layers. Is disclosed. However, this technique requires five wiring layers, which causes a problem of increasing costs.
[0017]
(6) Crosstalk noise that causes malfunction of the circuit cannot be reduced in the same wiring layer. In the conventional wiring structure including the diagonal wiring grid, the upper and lower wiring layers do not overlap in the same wiring direction. For this reason, since the coupling capacitance between the wirings of the upper and lower wiring layers is reduced, the problem of crosstalk noise between the upper and lower wirings is solved. However, since different wirings are arranged in parallel in the same wiring layer, the coupling capacitance between adjacent wirings cannot be reduced. That is, the conventional oblique wiring grid technology cannot remove crosstalk noise generated between two parallel wirings in the same wiring layer.
[0018]
(7) The conventional oblique wiring grid is insufficient for wiring for power supply. For example, when a pad is formed in the core region of a chip constituting the combinational circuit, a part of the pad can be used for power supply. (It should be noted that the peripheral region where the chip I / O is arranged with respect to the core region is referred to as an I / O region.) In this case, the upper diagonal wiring grid layer is used as auxiliary wiring for power supply. Can do. In such a configuration, the conventional oblique wiring grid structure has a structure having a wiring pitch or a wiring width that is unsuitable for forming a wide wiring. For this reason, the structure is not suitable for effectively using the upper diagonal wiring grid layer for power supply.
[0019]
(8) Since the wiring length of the wiring for supplying a clock from the PLL (Phase Locked Loop) to the flip-flop in the chip is long, the delay is increased.
[0020]
In order not to deteriorate the characteristics of the analog circuit built in the chip, the PLL is usually arranged at a corner of the chip and wired from the corner to each flip-flop. For this reason, it is necessary to draw a wiring having a length close to the half circumference of the chip at the shortest. Therefore, as the delay increases, the number of buffer stages increases, which adversely affects the clock duty ratio.
[0021]
(9) In the case of a memory circuit such as an SRAM, wiring that passes over these memory circuits causes coupling noise between the wiring in the memory and the passing wiring, thereby degrading performance. For this reason, the passing wiring on the memory circuit has been conventionally designed to be avoided. There is one conventional technique for shielding the passing wiring on the memory circuit. However, this technique requires one more layer to shield the wiring. Therefore, the circuit configuration is complicated. There is another conventional technique that uses a passing wiring on a memory circuit for a small amplitude signal. However, this technology has limited the integrated circuits to be applied.
[0022]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems of the prior art.
[0023]
The purpose of the circuit is to utilize the diagonal wiring layer in a semiconductor integrated circuit using a multilayer wiring structure provided with a wiring grid orthogonal to the diagonal direction in addition to the wiring grid orthogonal to the XY direction. It is an object of the present invention to provide a semiconductor integrated circuit and a semiconductor integrated circuit wiring method capable of improving delay characteristics and noise resistance and facilitating wiring design and reducing manufacturing costs.
[0024]
[Means for Solving the Problems]
A feature of the present invention is that a semiconductor region in which a plurality of unit elements are formed and an n (n ≧ 2) layer wiring that is formed in an upper layer of the semiconductor region are m ( m ≧ 2) a reference wiring layer that forms a reference wiring grid in the XY direction by wiring of the layer, and an m + 1 layer wiring and an m + 2 layer wiring that are positioned above the reference wiring layer and orthogonal to each other, An oblique wiring layer forming an oblique wiring grid that intersects the reference wiring grid at an angle of 45 degrees or 135 degrees, and the oblique wiring layer is a wiring between the m + 1 layer wiring and the m + 2 layer wiring. The pitch is set to √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer, and the wiring widths of the (m + 1) th layer wiring and the (m + 2) th layer wiring are set to be equal to those of the reference wiring layer. √2 times the wiring width of each layer In that it provides a semiconductor integrated circuit device characterized in that it is a constant.
[0025]
Another feature of the present invention is that the wiring thickness of the oblique wiring layer is set to √2 times the wiring thickness of the reference wiring grid.
[0026]
Another feature of the present invention is that the reference wiring layer and the oblique wiring layer constitute a wiring channel region, and the wiring channel region is parallel to a cell row in which logic cells composed of the unit elements are arranged in a row. It is in a point provided in a different direction.
[0027]
Another feature of the present invention is that the wiring of the reference wiring layer and the wiring of the oblique wiring layer are provided with via holes for wiring connection at intersections thereof, and the via hole has a hexagonal cross section, It is in the point which is either a square shape or a parallelogram shape.
[0028]
Another feature of the present invention is that the plurality of unit elements constitute a cell, and the cell is defined by a shape along a wiring direction of the oblique wiring grid, and an obstacle region where wiring is not performed is provided. It is in having.
[0029]
Another feature of the present invention is that a part of the wiring of the oblique wiring layer is configured as a power supply wiring for supplying power.
[0030]
Another feature of the present invention is that the plurality of unit elements constitute a cell including the plurality of unit elements, and the cell is supplied with a clock signal through a tree-type wiring path, and the tree-type wiring The route includes a first connection by a route formed so as to approach each other on the wiring of the oblique wiring layer from the first and second points, and on the wiring of the oblique wiring layer from the third and fourth points. Are formed by combining unit wiring shapes configured by connecting the second connection through the paths formed so as to approach each other by the wiring of the reference wiring layer.
[0031]
Another feature of the present invention is that the semiconductor integrated circuit device further includes a p-1 (p ≧ 2) layer wiring and a p layer wiring, which are positioned above the diagonal wiring layer and orthogonal to each other. An upper wiring layer that forms an upper wiring grid that intersects the diagonal wiring grid or the p-2 layer wiring at an angle of 45 degrees or 135 degrees, and the upper wiring layer is a wiring between the wirings of the respective layers; The pitch is set to √2 times between the wirings of each of the diagonal wiring layers or the wiring pitch of the p-2th layer wiring, and the wiring width of the wiring of each layer is set to the diagonal wiring layer. In other words, it is set to √2 times the wiring width of each layer or the wiring width of the p-2th layer wiring.
[0032]
Another feature of the present invention resides in that the diagonal wiring layer is provided with global wirings extending over the entire chip.
[0033]
Another feature of the present invention is that local wiring other than the global wiring is wired in the reference wiring layer.
[0034]
Another feature of the present invention is that the plurality of unit elements constitute a cell, and the cell has an output terminal shape that can be directly connected to the wiring of the oblique wiring layer when the cell is to be directly connected to the global wiring. It is in having.
[0035]
According to another aspect of the present invention, the semiconductor integrated circuit device further includes a flip-flop circuit and a PLL (Phase Locked Loop) disposed at a corner of the chip. The flip-flop circuit is a tree type. The tree-type wiring path is connected from the PLL to the vicinity of the center of the chip using the wiring of the diagonal wiring layer, and from the vicinity of the center of the chip to the flip-flop circuit. The point is that the RC products are hierarchically connected through the buffer cells so as to balance them.
[0036]
Another feature of the present invention is that the semiconductor integrated circuit device further includes an SRAM circuit that uses the wiring of the reference wiring layer as an internal wiring, and the oblique wiring layer passes over the SRAM circuit. It is in the point where the wiring to perform is wired.
[0037]
Another feature of the present invention is that the reference wiring layer is composed of three layers, and the first layer wiring and the third layer wiring of the reference wiring layer are arranged in a row of logic cells composed of the unit elements. The wiring is in a direction parallel to the cellulosic.
[0038]
Another feature of the present invention is that the reference wiring layer is composed of two layers.
[0039]
Another feature of the present invention is a semiconductor integrated circuit wiring method for wiring elements of a semiconductor integrated circuit, wherein an nth (n ≧ 2) layer wiring is orthogonal to an n−1th layer wiring. The step of forming the reference wiring layer in the XY direction by the wiring of m ≧ 2) layer and 45 degrees or 135 degrees with respect to the reference wiring grid by the (m + 1) th layer wiring and the (m + 2) th layer wiring orthogonal to each other. The wiring pitch between the (m + 1) th layer wiring and the (m + 2) th layer wiring of the diagonal wiring layers intersecting at an angle is set to √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer. And the step of forming the wiring width of the (m + 1) th layer wiring and the (m + 2) th layer wiring so as to be set to √2 times the wiring width of each layer of the reference wiring layer. Provided semiconductor integrated circuit wiring method There to that point.
[0040]
According to another aspect of the present invention, the semiconductor integrated circuit wiring method further includes the step of extracting a wiring net that causes a delay exceeding a predetermined delay time from the wiring net formed by the reference wiring layer, and the extraction And a step of inserting a buffer cell for signal amplification at a position on the wiring net that can be connected to the wiring of the oblique wiring layer.
[0041]
In another aspect of the present invention, the semiconductor integrated circuit wiring method further includes the step of defining a cell composed of the plurality of unit elements, and an obstacle region in which the wiring is not performed in the cell, And a step of defining the shape along the wiring direction of the oblique wiring layer.
[0042]
Another feature of the present invention resides in that the obstacle region defining step arranges the m + 1st layer wiring or the m + 2th layer wiring in the vicinity of the corner.
[0043]
Another feature of the present invention is that the semiconductor integrated circuit wiring method further includes any one of the m layers of the reference wiring layer, wherein two of the parallel wirings belonging to the same layer are included. The method includes a step of replacing a predetermined portion in the middle of one of the two wirings with the wiring of the oblique wiring layer when one wiring gives noise to the other wiring.
[0044]
Another feature of the present invention is that the semiconductor integrated circuit wiring method further includes a step of inserting a buffer cell into a wiring path of the oblique wiring layer used for the replacement.
[0045]
Another feature of the present invention is a cell placement method for placing cells on a semiconductor integrated circuit, wherein the nth (n ≧ 2) layer wiring is m (m) orthogonal to the n−1th layer wiring. ≧ 2) An angle of 45 degrees or 135 degrees with respect to the reference wiring layer by the step of forming the reference wiring layer in the XY direction by the wiring of the layer, and the m + 1 layer wiring and the m + 2 layer wiring orthogonal to each other. The wiring pitch between the (m + 1) th layer wiring and the (m + 2) th layer wiring is set to be √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer. A step of forming a cell composed of a plurality of unit elements using an XY cut line corresponding to the wiring direction of the reference wiring layer and an oblique cut line corresponding to the wiring direction of the diagonal wiring layer; Arranged based on the predetermined cutting method It is to provide an cell placement method characterized by comprising the steps that.
[0046]
Another feature of the present invention is that the semiconductor integrated circuit wiring method further sets a first path formed so as to approach each other on the wiring of the oblique wiring layer from the first and second points. Setting a second path formed so as to approach each other on the wiring of the diagonal wiring grid from the third and fourth points, and the first path and the second path Forming a unit wiring shape constituted by connecting the wirings of the reference wiring layer and a tree-type wiring path for supplying a clock signal to a cell composed of the plurality of unit elements by combining the unit wiring shapes Forming a step.
[0047]
Another feature of the present invention is a semiconductor integrated circuit wiring method for wiring elements of a semiconductor integrated circuit, wherein an nth (n ≧ 2) layer wiring is orthogonal to an n−1th layer wiring. The step of forming the reference wiring layer in the XY direction by the wiring of m ≧ 2) and the m + 1 layer wiring and the m + 2 layer wiring orthogonal to each other at 45 degrees or 135 degrees with respect to the reference wiring layer The wiring pitch between the (m + 1) th layer wiring and the (m + 2) th layer wiring of the diagonal wiring layers intersecting at an angle is set to √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer. Forming a step, connecting from the PLL (Phase Locked Loop) arranged at the corner of the chip to the vicinity of the center of the chip using the wiring of the oblique wiring layer, and from the vicinity of the center of the chip to the flip-flop in the chip In that it provides a semiconductor integrated circuit wiring method characterized by including the step of hierarchically connected as to balance the RC product via the buffer cell to the circuit.
[0048]
Another feature of the present invention is a semiconductor integrated circuit wiring method for wiring elements of a semiconductor integrated circuit, wherein an nth (n ≧ 2) layer wiring is orthogonal to an n−1th layer wiring. The step of forming the reference wiring layer in the XY direction by the wiring of m ≧ 2) and the m + 1 layer wiring and the m + 2 layer wiring orthogonal to each other at 45 degrees or 135 degrees with respect to the reference wiring layer The wiring pitch between the (m + 1) th layer wiring and the (m + 2) th layer wiring of the diagonal wiring layers intersecting at an angle is set to √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer. Forming an SRAM circuit using the wiring of the reference wiring layer as an internal wiring thereof, and forming a wiring passing through the SRAM circuit on the oblique wiring layer. Characteristic semiconductor It is to provide an integrated circuit wiring method.
[0049]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a semiconductor integrated circuit and a semiconductor integrated circuit wiring method according to the present invention will be described in detail with reference to the drawings.
[0050]
First embodiment
In the first embodiment, the third layer wiring intersects the reference wiring grid at an angle of 45 degrees or 135 degrees on the upper layer of the first and second reference wiring grids orthogonal to each other and orthogonal to each other. And an oblique wiring grid formed by the fourth layer wiring, and the wiring pitch and wiring width between the third layer wiring and the fourth layer wiring of the oblique wiring grid are set to √ with respect to the wiring pitch of the reference wiring grid. This is an embodiment in which the wiring length is shortened, the RC delay is reduced, and the noise resistance is improved by setting twice.
[0051]
FIG. 1 is a layout diagram showing a wiring grid structure of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 is a plan view showing an example of a wiring structure when wiring is performed based on the wiring grid structure as shown in FIG. 3 is a cross-sectional view taken along the line AA in FIG.
[0052]
As shown in FIG. 1, the wiring structure of the first embodiment is similar to the prior art of FIG. 28. The wirings of the first layer and the second layer and the wirings of the third layer and the fourth layer are orthogonal to each other. Has a grid. That is, the grid is arranged so that the third layer and the fourth layer intersect at 45 ° and 135 ° with respect to the first layer, respectively.
[0053]
Reference numeral 1 in FIG. 1 denotes a first-layer wiring grid, and a second-layer wiring grid 2 is formed orthogonal to the upper layer. Further, a third layer wiring grid 3 inclined at 45 ° with respect to the first layer wiring grid 1 and a fourth layer wiring grid 4 inclined at 135 ° with respect to the first layer wiring grid 1 are sequentially arranged. Yes.
[0054]
Here, in the first embodiment, the wiring pitch between the third layer wirings 3 and the fourth layer wirings 4 arranged in the oblique direction is set between the first layer wirings 1 and the second layer wirings 2, respectively. Set wider than between. Specifically, the wiring pitch between the third layer wiring 3 and the fourth layer wiring 4 is √2 times the wiring pitch (λ) between the first layer wiring 1 and the second layer wiring 2. It is set to (√2 · λ).
[0055]
Thereby, it is avoided that the lattice point is shifted between the upper layer XY wiring grid (third layer 4 and fourth layer 4) and the lower layer diagonal wiring grid (first layer 1 and second layer 2). can do. For this reason, wiring design can be facilitated. That is, a via hole between the second layer and the third layer can be placed at the intersection of the first layer and the second layer grid, and an adjacent lattice can be used for the wiring of the first layer or the second layer. .
[0056]
Furthermore, in the first embodiment, the wiring widths of the third layer wiring 3 and the fourth layer wiring 4 arranged in the oblique direction with the wiring pitch (√2 · λ) are set as the first layer wiring 1 and the second layer wiring. Set wider than 2. Specifically, as shown in FIG. 2, the wiring width of the third layer wiring 3 and the fourth layer wiring 4 is √2 times the wiring width (d) of the first layer wiring 1 and the second layer wiring 2, respectively. It is set to (√2 · d). As described above, since the wiring pitch of the third layer and the fourth layer is √2 times, the wiring interval indicated by p in FIG. 2 does not violate the design rule. For this reason, the wiring width can be widened without violating the design rule.
[0057]
In the example shown in FIG. 3, the first layer wiring 1 is first arranged in the vertical direction, and the second layer wiring 2 is arranged in a direction orthogonal thereto. On the other hand, the third layer wiring 3 and the fourth layer wiring 4 are arranged obliquely. In the figure, 12 is a via hole placed between the first layer wiring 1 and the second layer wiring 2, and 13 is a via hole placed between the second layer wiring 2 and the third layer wiring 3. Further, 14 is a via hole placed between the third layer wiring 3 and the fourth layer wiring 4.
[0058]
In the first embodiment, on the premise of the characteristics of the wiring pitch and the wiring width described above, the wiring thicknesses of the third layer wiring 3 and the fourth layer wiring 4 arranged in the oblique direction are set to be the same as those of the first layer wiring 1 and It is set thicker than the two-layer wiring 2. Specifically, as shown in FIG. 3, the wiring thickness of the third layer wiring 3 and the fourth layer wiring 4 is √2 of the wiring width (t) of the first layer wiring 1 and the second layer wiring 2, respectively. Double (√2 · t) is set. In FIG. 3, 10 is a semiconductor substrate on which a transistor is formed, and 11 is an interlayer insulating film. By using the structure in which the wiring width and the wiring film thickness of the third layer and the fourth layer are set to √2 times that of the first layer and the second layer, the wiring cross-sectional areas of the third layer wiring and the fourth layer wiring are As shown by the following formula, the wiring cross-sectional area of the first layer wiring and the second layer wiring is twice as large.
[0059]
√2 × √2 = 2
For this reason, the wiring resistance per unit length is ½ of the wiring of the first layer and the second layer. On the other hand, the area facing the adjacent wiring is √2 times, but the distance between adjacent wirings is also √2 times. Therefore, the capacitance between adjacent wirings in the third layer wiring and the fourth layer wiring is the first layer wiring and the second wiring. This is the same as the capacitance between adjacent wirings in the single layer wiring. Since the wiring resistance is 1/2 and the capacitance between adjacent wirings is the same, the wiring RC delay per unit length is ½ of the wiring of the first layer and the second layer. Note that the wiring RC delay is a delay due to a resistance component and a capacitance component of the wiring.
[0060]
As described above, according to the first embodiment, the wiring pitch between the third layer wirings and the fourth layer wirings is √2 times the wiring pitch between the first layer wirings and the second layer wirings. Set to. For this reason, it is possible to avoid the shift of the lattice points between the layers of the upper diagonal wiring grid and the lower reference wiring grid, and the wiring design can be facilitated.
[0061]
In addition, since the wiring width is set to √2 times, the wiring RC delay can be reduced. Further, since the wiring film thickness is set to √2 times, the wiring RC delay can be further reduced, and a great effect can be obtained from the viewpoint of increasing the operation speed of the circuit with a relatively long wiring.
[0062]
Second embodiment
In the second embodiment, the repeater cell (buffer cell) is further inserted into the wiring in the multilayer wiring structure using the oblique wiring grid of the first embodiment to prevent the occurrence of a timing error due to wiring delay. It is a form.
[0063]
FIGS. 4A, 4B, 4C, and 4D are diagrams illustrating a procedure for inserting a repeater cell according to the second embodiment. 5A and 5B are diagrams for explaining the wiring delay. With reference to FIG. 4 and FIG. 5, the repeater cell insertion procedure of the second embodiment will be described in detail.
[0064]
First, only the first layer and the second layer are used, and all nets are wired by wiring only in the XY direction. Next, a delay analysis is performed using a simulator to extract a net causing a timing error. The following processing is performed on the extracted net.
[0065]
That is, a repeater cell is inserted into the net where a timing error has occurred. The repeater cell is inserted at a position where the repeater cell can be connected to the diagonal wiring by using the third layer and the fourth layer. By using the third layer or the fourth layer, the wiring length can be shortened.
[0066]
For example, assume that a timing error has occurred in the net as shown in FIG. In this net, three types of FIGS. 4A, 4 </ b> B, and 4 </ b> C are conceivable as the insertion position of the repeater cell 20 between the cell 21 and the cell 22 and the wiring direction. In the example of FIG. 4A, first, the X-direction wiring 23 is used, and after the repeater cell 20 is inserted, the diagonal wiring 25 is used. In the example of FIG. 4B, the repeater cell 20 is first inserted, the wiring 34 in the oblique direction is used, and then the wiring 35 in the X direction is used. In the example of FIG. 4C, the repeater cell 20 is first inserted, the wiring 45 in the X direction is used, and then the wiring 46 in the oblique direction is used.
[0067]
4 (a), 4 (b), and 4 (c), the difference between the insertion positions of the repeater cells is the delay between the cell 21 that outputs a signal and the repeater cell 20 and between the repeater cell 20 and the cell 22 that inputs a signal. This causes a distribution difference. Comparing the example of FIG. 4A and FIG. 4B, the delay between the cell 21 and the repeater cell 20 is smaller in FIG. 4B than in the example of FIG. On the other hand, the delay between the repeater cell 20 and the cell 22 is smaller in FIG. 4A than in the example of FIG. Which example can reduce the actual delay depends on the transistor sizes of the cell 21 and the repeater cell 20. Therefore, in general, it is necessary to analyze the delays in all possible combinations and determine how to use the final repeater insertion position and wiring direction. However, the delay in the example of FIG. 4C is clearly larger than in the other examples.
[0068]
Regarding the wiring width, according to Elmore's wiring delay calculation formula, the wiring delay becomes shorter as the wiring width is gradually reduced from the cell that outputs the signal. That is, as shown in FIG. 5 (a), when the thick wiring width 63 is first used and then the thin wiring width 64 is used, the thin wiring 73 is used first as shown in FIG. 5 (b). The wiring delay is shorter than when the thick wiring width 74 is used.
[0069]
Since the diagonal wiring is √2 times thicker than the wiring along the X and Y axes, the diagonal wiring is used first, and then the X or Y wiring is used. First, the wiring delay is shorter than when the wiring in the X or Y direction is used and then the wiring in the oblique direction is used. That is, it is understood that the wiring delay is shorter in the example of FIG. 4B than in the example of FIG.
[0070]
Accordingly, the rules for inserting repeater cells when using diagonal wiring are defined as follows.
[0071]
(1) An oblique wiring is connected to a wiring close to the signal output terminal.
(2) An oblique wiring is connected to the signal output terminal.
(3) The diagonal wiring is frequently used for the wiring near the signal output terminal of the repeater cell.
(4) A diagonal wiring is connected to the signal output terminal of the repeater cell.
(5) The repeater cell is arranged at a position where the diagonal wiring can be connected to the signal output terminal.
[0072]
According to the above rules, the structure of the repeater cell is also defined as follows.
[0073]
(1) The signal input terminal is formed so as to be easily connected to the wiring along the XY direction. That is, a signal input terminal is formed on the first layer.
(2) Further, the signal output terminal is formed so as to be easily connected to the wiring in the oblique direction. That is, a signal output terminal is formed on the third layer.
[0074]
As described above, according to the second embodiment, in order to prevent the occurrence of a timing error due to a wiring delay, an oblique wiring grid is used when inserting a repeater cell that relays and amplifies a signal on a wiring net. The repeater cell is inserted at a position where it can be connected to the diagonal wiring grid. For this reason, a repeater cell can be inserted under optimum conditions to shorten the wiring length and further reduce the wiring delay.
[0075]
Third embodiment
The third embodiment is an embodiment that solves the shortage of wiring resources in the cell row direction by providing a wiring channel in a direction parallel to the cell row in the multilayer wiring structure using the oblique wiring grid of the above embodiment.
[0076]
FIG. 6 is a layout diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention.
[0077]
The semiconductor integrated circuit of FIG. 6 has a plurality of cell rows 80 formed by arranging logic cells in a column. A multilayer wiring having the diagonal wiring grid shown in FIG. 1 is formed on the plurality of cell rows 80.
[0078]
Specifically, in FIG. 6, 1 is the first layer metal wiring, 2 is the second layer metal wiring, 3 is the third layer metal wiring, and 4 is the fourth layer metal wiring. Wiring. In the configuration of FIG. 6, wiring channels 85 each formed of metal wirings 1, 2, 3, and 4 are formed in a direction parallel to the cell rows 80. That is, the wiring channel 85 is provided in a direction parallel to the cell row 80. For this reason, a wiring resource in the cell row direction that requires more wiring resources can be secured with a small number of wiring hierarchies.
[0079]
As described above, according to the third embodiment, a shortage of wiring resources in the cell row direction that requires more wiring resources can be resolved and wiring resources can be secured with a small number of wiring hierarchies.
[0080]
Fourth embodiment
The fourth embodiment is an embodiment in which the shape of the multilayer wiring structure using the diagonal wiring grid of the above-described embodiment is improved so that the cut area of the via hole connecting the diagonally intersecting wiring is not insufficient. It is.
[0081]
7A, 7B, 7C, and 7D are partial plan views showing the shapes of via holes of the semiconductor integrated circuit according to the fourth embodiment.
[0082]
The semiconductor integrated circuit according to the fourth embodiment includes an X-Y direction wiring (first layer or second layer) in the multilayer wiring structure having the diagonal wiring grid shown in FIG. When connecting a diagonal wiring (third layer or fourth layer) having an angle of 135 °, as shown in FIGS. 7A, 7B, 7C, and 7D, the longitudinal section is Use octagonal, parallelogram, or hexagonal via holes. By using the via holes having these cross-sectional shapes, a via hole cut having a necessary and sufficient cross-sectional area can be created between the intersecting wiring layers.
[0083]
In the example of FIG. 7A, an octagonal via hole 90A is formed at the intersection of the XY wiring 91 and the diagonal wiring 92. In the example of FIG. 7B, a parallelogram via hole 90B is formed at the intersection of the XY wiring 91 and the diagonal wiring 92.
[0084]
In the example shown in FIG. 7B, the via holes may be abnormally approached. In order to avoid this, a hexagonal shape shown in FIGS. 7C and 7D is provided. In the example of FIG. 7C, a hexagonal via hole 90 </ b> C is formed at the intersection of the XY wiring 91 and the diagonal wiring 92. In the example of FIG. 7D, a hexagonal via hole 90D is formed at the intersection of the XY wiring 91 and the diagonal wiring 92.
[0085]
As described above, according to the fourth embodiment, the cross-sectional shape of the via hole that connects the wirings that intersect diagonally is an octagon, a parallelogram, or a hexagon. For this reason, a sufficient cut area of the via hole connecting the wirings crossing obliquely is ensured. Fifth embodiment
The fifth embodiment is an embodiment in which the obstacle region of the wiring is optimally defined in the multilayer wiring structure using the oblique wiring grid of the above-described embodiment.
[0086]
FIGS. 8A and 8B are diagrams showing cells or megacells in a semiconductor integrated circuit according to the fifth embodiment of the present invention.
[0087]
Reference numeral 101 shown in FIG. 8A denotes a cell in which a plurality of unit elements are formed or a megacell in which a plurality of these cells are assembled. This cell or megacell 101 is divided into an effective region 102 and a transistor region 103 with a 45 ° line 101a at the four corners as a boundary. In the transistor region 103, transistors and lower layer cells 103a are arranged. On the other hand, the effective area 102 is provided for effective use of the four corners of the cell, for example, for the purpose of alleviating wiring congestion occurring in the vicinity of the four corners of the cell (described later), and no transistor or lower layer cell is disposed. In the following description, the cell is assumed to include the above megacell.
[0088]
Further, as shown in FIG. 8B, it is preferable to use the 45 ° or 135 ° oblique wiring 113 described above in the vicinity of the four corner lines 101a as the wiring arranged in the transistor region 103 of the cell 101.
[0089]
Thus, when designing the cell or megacell, the above-mentioned effective area is provided and the four corners are not used, so that the obstacle of the wiring is defined along the 45 ° or 135 ° oblique wiring. be able to. Next, this point will be described.
[0090]
FIGS. 9A and 9B are diagrams illustrating examples of wiring obstacles according to the fifth embodiment. In the example shown in FIG. 9A, the obstacle area in the cell 101 is defined by a set of small rectangles 122. Here, the obstacle area is an area for defining an obstacle of wiring in wiring design.
[0091]
In the example shown in FIG. 9B, the obstacle area in the cell 101 is defined by a polygon or a set thereof. That is, in the example of FIG. 9B, when there are two obstacle areas, they are defined by trapezoids 132 and 133, respectively.
[0092]
In the example shown in FIG. 9A, there is a problem that the amount of data in CAD design increases, but in the example shown in FIG. 9B, an obstacle region can be defined with a small amount of data.
[0093]
FIGS. 10A and 10B are diagrams illustrating the effects of the fifth embodiment.
[0094]
In the normal XY wiring grid model, as shown in FIG. 10A, the obstacle region 142 inside the cell or megacell 141 is defined as a set of orthogonal rectangles. When orthogonal wiring is performed using these cells or megacells 141, there is a problem that the degree of congestion of the wirings 143 near the four corners 144 increases, thereby reducing the degree of integration of the chip.
[0095]
On the other hand, when wiring is performed using the cell and the megacell 101 created by the method of the fifth embodiment described above, the obstacle region 152 has four corners of the cell or megacell as shown in FIG. Defined with a configuration that is not used. The obstacle region 152 can be defined by a shape along the oblique wiring. For this reason, the congestion degree of the wiring 153 in the vicinity of the four corners 154 is reduced, and the integration degree of the chip is improved.
[0096]
As described above, according to the fifth embodiment, in the design of the cell or megacell, the obstacle region is defined by the shape along the oblique wiring in a configuration that does not use the four corners of the cell or megacell. For this reason, the four corners of the cell can be used effectively. In addition, the degree of wiring congestion in the vicinity of the four corners is alleviated, and the degree of chip integration is improved.
[0097]
Sixth embodiment
The sixth embodiment is an embodiment that suppresses crosstalk noise that occurs when there are wirings arranged in parallel in the same layer in the multilayer wiring structure using the diagonal wiring grid of the above embodiment.
[0098]
FIGS. 11A, 11B, and 11C are diagrams showing the main part of the configuration of the semiconductor integrated circuit according to the sixth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the element which is common in FIG. 6, and the description is abbreviate | omitted.
[0099]
Consider a case where there are wirings 161 and 162 arranged in parallel in the same layer as shown in FIG. In the sixth embodiment, as shown in FIG. 11B, an oblique direction wiring 173 that forms an angle of 45 ° or 135 ° with an intermediate portion of one of the wirings (for example, the wiring 162). , 174, the wiring layer is changed. By replacing this wiring, the distance at which two wirings in the same layer are parallel is shortened, and the occurrence of crosstalk noise can be suppressed.
[0100]
Further, of the parallel wirings 161 and 162, assuming that, for example, the wiring that generates noise is the wiring 161 and the wiring that receives noise is the wiring 162, when the wiring 162 is changed by the diagonal wirings 173 and 174 described above, One or a plurality of buffer cells 183 are inserted on the diagonal wirings 173 and 174.
[0101]
In this manner, noise propagation can be completely prevented by inserting buffer cells into the diagonal wiring path. For example, the plane running distance may be limited so that the voltage level of crosstalk noise generated between two wirings arranged in parallel in the same layer does not exceed the logical threshold value of the buffer cell 183 inserted for noise cancellation. Thus, it is possible to completely suppress noise.
[0102]
As described above, according to the sixth embodiment, the wiring layer is changed so that the middle part of one of the wirings arranged in parallel in the same layer is replaced with the diagonal wiring. In addition, a buffer cell is inserted into the path of the diagonal wiring used for replacement. For this reason, the distance at which two wirings in the same layer are parallel is shortened, and the occurrence of crosstalk noise between the wirings is suppressed.
[0103]
Seventh embodiment
The seventh embodiment is an embodiment in which the wiring resources of the diagonal wiring grid are used for power supply in the multilayer wiring structure using the diagonal wiring grid of the above-described embodiment.
[0104]
FIG. 12 is a diagram showing a main configuration of a semiconductor integrated circuit according to the seventh embodiment of the present invention. Elements common to those in FIG. 6 are denoted by the same reference numerals and description thereof is omitted.
[0105]
As shown in FIG. 12, a part of the third layer wiring 3 and the fourth layer wiring 4 located above the first layer wiring 1 and the second layer wiring 2 are replaced with a power supply wiring 191 for power supply. Use. Thereby, a part of the wiring resources of the general signal lines in the oblique direction can be used for power supply, and the power shortage in the cell row 80 can be compensated.
[0106]
As described above, according to the seventh embodiment, a part of the wiring resource of the general signal destination in the oblique direction is used as the power supply wiring. For this reason, it is possible to make up for the power shortage caused by cellulosic.
[0107]
Eighth embodiment
The eighth embodiment is an embodiment in which the arrangement of cells is optimized in the multilayer wiring structure using the oblique wiring grid of the above-described embodiment.
[0108]
FIGS. 13A and 13B are diagrams showing a cell arrangement method of a semiconductor integrated circuit according to the eighth embodiment of the present invention.
[0109]
Normally, in the LSI design by CAD, the cell placement method is performed in consideration of the ease of wiring so as to shorten the wiring length. At that time, the following method using the top-down method is used for the operation of arranging which cell and where.
[0110]
In this conventional method, as shown in FIG. 13B, first, a set of cells to be arranged is divided into two by vertical and horizontal cut lines 260. Next, the cells 201 and 210 are arranged so that the number of wires crossing the cut line 260 is reduced. Thereafter, the image is further divided into two parts using a cut line in the same manner, and the two parts are repeated until all the regions become the minimum unit. The above conventional method is referred to as a mini-cut method.
[0111]
Here, as shown in FIG. 13B, the conventional cut line 260 has vertical and horizontal straight lines corresponding to the wiring grid in the XY direction. However, when the above-described diagonal wiring is provided, as described in the fifth embodiment, for example, a wiring obstacle having an angle of 45 ° appears. For this reason, the optimum cell position cannot be obtained only by the vertical and horizontal cut lines 260.
[0112]
Therefore, in the eighth embodiment, as shown in FIG. 13A, in addition to a conventional cut line orthogonal to the vertical and horizontal directions, an oblique cut line 250 is used. The cells 201 and 210 are arranged so that the number of wires crossing the oblique cut line 250 is minimized. As a result, the position of the cell can be determined so that optimum wiring can be performed in the vertical and horizontal directions and in the oblique direction, and the integration density of the LSI can be increased.
[0113]
As described above, according to the eighth embodiment, when designing the cell arrangement in the LSI design, the cell arrangement is performed by the mini-cut method using the oblique cut lines. For this reason, the position of the cell can be optimized so that the optimum wiring can be performed in the multilayer wiring structure using the diagonal wiring grid. Therefore, the degree of integration of LSI can be improved.
[0114]
Ninth embodiment
In the ninth embodiment, in the multilayer wiring structure using the diagonal wiring grid of the above-described embodiment, the clock tree configuration in the clock design for clock supply when the diagonal wiring is used is optimized to reduce the wiring RC delay. It is embodiment which reduces the dispersion | variation in this.
[0115]
14A, 14B, 14C, and 14D are views for explaining the basic configuration of the clock tree of the semiconductor integrated circuit device according to the ninth embodiment of the present invention.
[0116]
In order to provide a delay of the clock signal for each path path, a tree-type wiring shape is generally used. In this case, if the multilayer wiring structure has a wiring grid only in the XY direction, as shown in FIG. 14D, the H-shaped wiring shape shown in FIG. 14B is repeated.
[0117]
In the construction of such a tree wiring path, the ninth embodiment employs a repeating structure having a shape utilizing diagonal wiring as shown in FIG. 14A, as shown in FIG. 14C. That is, as shown in FIG. 14A, paths are connected from four points P1, P2, P3, and P4 so as to approach each other using an oblique wiring grid. The shape shown in FIG. 14A is obtained by connecting the wirings in either the vertical or horizontal wiring layer at points P5 and P6 where two points P1, P2 and P3, P4 are formed. However, the points P5 and P6 at which the path branches are positions where delays on the downstream side of signal propagation are aligned.
[0118]
Comparing the conventional H-shaped wiring shape shown in FIG. 14B with the wiring shape of the ninth embodiment shown in FIG. 14A, the wiring length is only a few percent, but in the wiring RC delay. There is a significant difference. It is assumed that the wiring resistance r and the wiring capacity c per unit length of each wiring layer are equal, and that the terminal is not loaded with a capacitive load. Here, the wiring delay D of the conventional H-shaped wiring shape shown in FIG. _H Is obtained by the following equation.
[0119]

(However, l is the length of the wiring in FIG. 14)
On the other hand, the wiring delay D of the wiring shape of the ninth embodiment shown in FIG. _d Is obtained by the following equation.
[0120]

Since the distance between P5 and P6 in FIG. 14A is very small, it can be ignored in the calculation of (2).
[0121]
Therefore, the shape of the ninth embodiment of FIG. 14A can reduce the RC delay by the following amount compared to the H type of FIG. 14B.
[0122]

This reduction in RC delay is an effect obtained when the wiring branch is closer to the upstream side of signal propagation. In addition, the effect of reducing the delay is further increased if a load capacity is provided on the downstream side. Furthermore, since the wiring resistance of the diagonal wiring to be used is generally smaller than the wiring resistance of the XY wiring, this point is also a factor of increasing the delay reduction effect.
[0123]
If the clock terminals are unevenly distributed, the delay balance point may not be on the line shown in FIG. In such a case, the wiring shape is corrected as shown in FIG. The balance point can be accurately set by the wiring shape of FIG. The wiring shape of FIG. 15 may be partially used in the entire clock tree of FIG.
[0124]
Further, as shown in FIG. 16B, a bypass path 311 may be provided in the vicinity of the output terminal of the buffer 310 inserted in the middle of the tree in order to align the delay with other buffers. In such a case, the number of via holes can be reduced by using diagonal wiring as shown in FIG. Therefore, the configuration of FIG. 16A can provide advantageous effects in terms of reducing via hole resistance and electromigration resistance.
[0125]
FIGS. 17A, 17B, and 17C show examples of wiring designs using the maze method as a specific wiring method when diagonal wiring grids in the 45 ° and 135 ° directions are formed by automatic wiring. .
[0126]
Reference numerals 320 and 321 in FIGS. 17A, 17B, and 17C denote the start point and end point of the terminal pair to be connected to each other. Reference numeral 330 denotes a wiring prohibited area in the chip core area. Wirings are arranged from the start point 320 to the end point 321 along a route indicated by a thick line in FIGS. 17A, 17B, and 17C. The example shown in FIG. 17A shows a wiring when an XY wiring and an oblique wiring are used in combination. The example of FIG. 17B shows an example in which wiring is performed using only diagonal wiring. In addition, the example shown in FIG. 17C shows wiring when XY wiring and 135 ° oblique wiring are used.
[0127]
As described above, according to the ninth embodiment, in the construction of the tree path, a configuration in which unit wiring shapes using diagonal wiring are combined is used. For this reason, the wiring RC delay is reduced, and an optimal clock tree can be constructed.
[0128]
Tenth embodiment
In the tenth embodiment, in the multilayer wiring structure using the oblique wiring grid of the above-described embodiment, the wiring grid in the XY direction in FIG. 3 is configured by three wiring layers orthogonal to each other. This is an embodiment in which the wiring resources in the direction are increased.
[0129]
FIG. 18 is a layout diagram showing a wiring grid structure of a semiconductor integrated circuit according to the tenth embodiment of the present invention. 19 is a cross-sectional view of the wiring structure when wiring is performed based on the wiring grid structure as shown in FIG. 18 as observed from the X-axis direction of FIG.
[0130]
In FIG. 18, the wiring grid in the XY direction is composed of three layers of wiring. Specifically, as shown in FIG. 18, the wirings of the first layer 601, the second layer 602, and the third layer 603 and the wirings 605 of the fourth layer 604 and the fifth layer are interconnected at right angles. It is composed. Here, the tenth embodiment provides a third layer wiring 603 parallel to the first layer wiring 601. That is, the grid is arranged so that the fourth layer wiring and the fifth layer wiring intersect at 45 ° and 135 ° with respect to the first layer and the third layer wiring, respectively.
[0131]
Reference numeral 601 in FIG. 18 denotes a first-layer wiring grid, and a second-layer wiring grid 602 is formed orthogonal to the upper layer. A third wiring grid 603 is formed orthogonal to the upper layer of the second wiring grid 602. Further, a fourth layer wiring grid 604 inclined by 45 ° with respect to the first layer wiring grid 601 and the third layer wiring grid 603 and a 135 ° inclination with respect to the first layer wiring grid 601 and the third layer wiring grid 603. A fifth-layer wiring grid 605 in the direction is sequentially arranged.
[0132]
In the tenth embodiment, as in the first embodiment, the wiring pitch between the fourth layer wiring 604 and the fifth layer wiring 605 arranged in the oblique direction is set between the first layer wiring 601 and the fifth layer wiring 605, respectively. The wiring pitch (λ) between the second layer wiring 602 and between the second layer wiring 602 and the third layer wiring 603 is set to √2 times (√2 · λ). Further, as shown in FIG. 19, the wiring width between the fourth layer wiring 604 and the fifth layer wiring 605 arranged in the oblique direction is set between the first layer wiring 601 and the second layer wiring 602. In the meantime, it is set to √2 times (√2 · t) of the wiring pitch (t) between the second layer wiring 602 and the third layer wiring 603. Note that the first layer wiring 601, the second layer wiring 602, and the third layer wiring 603 are preferably defined by the minimum wiring width, height, and wiring pitch determined by the design rule in the wiring design.
[0133]
Returning to FIG. 18, the first layer wiring 601 and the third layer wiring 603 are formed in a direction parallel to the cell row direction. Therefore, it is possible to further increase the wiring resources in the cell row direction as compared with the first embodiment. Note that the tenth embodiment differs from the third embodiment in that no wiring channel is provided.
[0134]
In a conventional multi-layer structure with a wiring grid orthogonal to the XY direction, when wirings of a plurality of layers are formed in parallel, crosstalk noise is generated due to the parallel arrangement of the wirings. In the tenth embodiment, by combining the oblique wiring grid and the parallel arrangement of the wiring, it is possible to secure the wiring resources in the cell row direction while suppressing the occurrence of crosstalk noise.
[0135]
As described above, according to the tenth embodiment, the first layer wiring and the third layer wiring are formed in a direction parallel to the cell row, and the above-described oblique wiring grid is formed in the upper layer. For this reason, wiring resources in the cell row direction can be secured.
[0136]
As a modification of the tenth embodiment, a single-layer or multiple-layer wiring grid may be formed in an upper layer of the diagonal wiring grid formed by the fourth layer wiring 604 and the fifth layer wiring 605. In this upper layer wiring grid, two wiring grid pairs formed by a sixth layer wiring and a seventh layer wiring orthogonal to each other with respect to the fifth layer wiring 605 are formed at an angle of 45 degrees. It is composed repeatedly. That is, in addition to the reference wiring grid formed by the first layer wiring, the second layer wiring, and the third layer wiring, and the oblique wiring grid formed by the fourth layer wiring and the fifth layer wiring, the p-1 There is provided a q-layer wiring structure in which two wiring lattice pairs of the layer and the p-th layer are formed at an angle of 45 degrees with respect to the wiring of the p-th layer. (However, q> = 5)
Here, the p-1 layer wiring and the p layer wiring orthogonal to each other are set to √2 times the wiring pitch of the p-2 layer wiring. Further, the wiring widths of the p-1 layer wiring and the p layer wiring are respectively set to √2 times the wiring pitch of the p-2 layer wiring. The first layer wiring, the second layer wiring, and the third layer wiring are preferably defined by the minimum wiring width, height, and wiring pitch determined by the design rule in the wiring design.
[0137]
According to this modification, the circuit integration degree can be improved and the wiring RC delay can be reduced.
[0138]
Eleventh embodiment
In the multilayer wiring structure using the diagonal wiring grid of the above-described embodiment, the eleventh embodiment uses the wiring of the wiring layer forming the diagonal wiring grid for the global wiring that is a relatively long wiring, thereby reducing the circuit speed. It is an embodiment to improve.
[0139]
FIG. 20 is a diagram for explaining the arrangement of wirings in the eleventh embodiment. FIG. 21 is a diagram for explaining global wiring in the eleventh embodiment. In the following, for convenience of understanding, as in the tenth embodiment, the wiring grid in the XY direction is formed by the first layer wiring, the second layer wiring, and the third layer wiring, and the diagonal wiring grid is the fourth. The case where the wiring is formed by the layer wiring and the fifth layer wiring will be described as an example, but this is the case where the wiring grid in the XY direction is formed by the first layer wiring and the second layer wiring shown in the first embodiment. Needless to say, this can also be applied.
[0140]
As shown in FIG. 20, in the eleventh embodiment, the upper layer wiring of the fourth layer wiring and the fifth layer wiring forming an oblique wiring grid is used for global wiring. In global wiring, generally required delay characteristics are critical, and this delay characteristics influence the circuit speed of the entire chip, so wiring RC delay is particularly a problem. Here, in the above embodiment, the RC delay of the upper layer wiring is halved with respect to the lower layer wiring (wiring in the XY direction). For this reason, the operation speed of the circuit can be improved by using the wiring of the diagonal wiring grid as the upper layer wiring for the global wiring. On the other hand, the lower layer wiring (wiring in the XY direction) is preferably used for local wiring.
[0141]
Here, the global wiring is wiring used for a clock net (clock wiring), a bus, a power supply reinforcing line, and the like over the entire chip. For example, in the case of a design rule of 0.25 μm, if a wiring having a wiring distance of about 2.5 mm or more is a global wiring, in this case, the wiring RC delay is about 1.4 nsec. On the other hand, local wiring refers to wiring with a shorter wiring distance.
[0142]
Note that the wiring pitch of the XY wiring (lower layer wiring) used for the local wiring is narrower than the wiring pitch of the diagonal wiring (upper layer wiring). In this case, as shown in FIG. 21, for example, a cell 610 having a strong driving force, such as a clock buffer cell or a bus buffer cell, is not directly connected to the wiring (601 to 604) of each layer but directly to the global wiring. It is desirable to connect. For this reason, in the eleventh embodiment, the shape of the output terminal of the cell having a strong driving force is directly connectable to the wiring of the diagonal wiring grid of the fourth layer or higher. As shown in FIG. 22, the output terminals 704 of the cells having a strong driving force are defined as access points orthogonal to each other in the upper diagonal wiring grid.
[0143]
By making the output terminal shape of these cells a shape that can be directly connected to the global wiring, the wiring length for these cells is shortened, and the wiring design is facilitated. In addition, since it is directly connected to the wiring of the upper-layer oblique wiring grid of the fourth layer or more, the number of via holes can be reduced, and the resistance caused by the via holes can be reduced.
[0144]
As described above, according to the eleventh embodiment, the wiring in the wiring layer forming the diagonal wiring grid is used for the global wiring that is a relatively long wiring. For this reason, the wiring RC delay of the wiring greatly affecting the circuit characteristics is reduced, and the circuit speed is improved. 12th embodiment
In the twelfth embodiment, in the multilayer wiring structure using the diagonal wiring grid of the above-described embodiment, the clock wiring structure for supplying a clock from a PLL (Phase Locked Loop) circuit is changed from the PLL to the chip center. In this embodiment, the RC product is balanced by defining the wiring from the chip center to each flip-flop with a tree structure.
[0145]
FIG. 23A is a diagram showing a wiring method of clock supply wiring from a conventional PLL. Since the PLL 803 is a sensitive analog cell, it needs to be arranged at the end of the chip because of circuit characteristics. For this reason, in the conventional method using the wiring 801 in the XY direction, the wiring length is long. FIG. 23B is a diagram illustrating a wiring method of clock supply wiring from the PLL according to the twelfth embodiment. In the twelfth embodiment, the clock supply wiring 802 from the PLL 802 to the chip center 804 is performed using an oblique wiring grid. For this reason, the wiring length is shortened and the wiring RC delay is reduced. As shown in FIG. 24, wiring from the chip center to a cluster formed by each flip-flop is made through a buffer cell. FIG. 25 is a diagram illustrating a clock tree according to the twelfth embodiment. As shown in FIG. 24, a clock wiring path is configured from each buffer cell so as to balance the RC product. That is, the clock wiring path is hierarchically configured so as to balance the delay in the XY direction and the oblique direction from the chip center. As shown in FIG. 26, this hierarchical clock tree may be configured in the same manner as in the ninth embodiment. Note that the PLL may be replaced with a DLL.
[0146]
For these clock wiring paths, it is preferable to use an upper-level diagonal wiring grid preferentially and to set a wide wiring width. That is, if the wiring pitch of the diagonal wiring grid is √2 times that of the underlying XY wiring grid, it is easy to use a thick wiring width for the diagonal wiring grid, and thereby the wiring RC accompanying the decrease in the wiring resistance R. An increase in delay can be suppressed.
[0147]
As described above, according to the twelfth embodiment, an oblique wiring grid is used for the clock supply wiring from the PLL to the chip center, and the clock supply wiring from the chip center to each flip-flop on the chip is arranged in the XY direction. The clock wiring paths are hierarchically configured so as to balance the delays in the diagonal direction. For this reason, the wiring length for clock supply is shortened and the wiring RC delay is reduced.
[0148]
Thirteenth embodiment
In the thirteenth embodiment, when the SRAM is arranged on the chip in the multilayer wiring structure using the diagonal wiring grid of the above embodiment, the wiring is passed over the SRAM using the diagonal wiring grid. It is. In the thirteenth embodiment, the SRAM may be replaced with a DRAM.
[0149]
FIG. 27 is a diagram for explaining the passage wiring on the memory in the thirteenth embodiment. The lower wiring layers 1 and 2 in the XY direction are used for word lines and bit lines, for example, and are formed inside the SRAM 901. On the other hand, the passing wirings 3 and 4 are wired using an upper-level diagonal wiring grid. That is, the wirings 1 and 2 in the XY direction inside the SRAM 901 and the passing wirings 2 and 3 using the diagonal wiring grid are not parallel as in the prior art. For this reason, the coupling noise is reduced as compared with the prior art.
[0150]
As described above, according to the thirteenth embodiment, the passing wiring passing over the memory is formed at an intersection angle of 45 degrees or 135 degrees with respect to the wiring in the memory by using an oblique wiring grid. For this reason, the coupling noise between the in-memory wiring and the passing wiring is reduced.
[0151]
In addition, this invention is not limited to embodiment mentioned above, In the range which does not deviate from the summary, it can change variously.
[0152]
【The invention's effect】
As described above, according to the present invention, an oblique wiring layer is utilized in a semiconductor integrated circuit using a multilayer wiring structure provided with a wiring grid orthogonal to the diagonal direction in addition to the wiring grid orthogonal to the XY direction. As a result, the delay characteristics and noise resistance of the circuit are improved, and the wiring design is simplified and the manufacturing cost is reduced.
[Brief description of the drawings]
FIG. 1 is a layout diagram showing a wiring grid structure of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a plan view showing an example of a wiring structure when wiring is performed based on the wiring grid structure as shown in FIG.
3 is a cross-sectional view taken along the line AA in FIG.
FIG. 4 is a diagram for explaining a repeater cell insertion method of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 5 is a diagram for explaining wiring delay;
FIG. 6 is a layout diagram showing a configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 7 is a partial plan view showing the shape of a via hole of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 8 is a diagram showing a cell or a mega cell in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of a wiring obstacle according to a fifth embodiment;
FIG. 10 is a diagram for explaining a relationship between wiring obstacle areas and wiring in a fifth embodiment;
FIG. 11 is a diagram showing a main configuration of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.
FIG. 12 is a diagram showing a main configuration of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.
FIG. 13 is a diagram showing a cell arrangement method of a semiconductor integrated circuit according to an eighth embodiment of the present invention.
FIG. 14 is a diagram illustrating a basic configuration of a clock tree of a semiconductor integrated circuit according to a ninth embodiment of the present invention.
FIG. 15 is a diagram illustrating a modification of the configuration of the clock tree according to the ninth embodiment.
FIG. 16 is a diagram illustrating a configuration of a main part of a tree when a detour route is provided.
FIG. 17 is a diagram showing a specific wiring method when an oblique wiring grid is performed by automatic wiring.
FIG. 18 is a layout diagram showing a wiring grid structure of a semiconductor integrated circuit according to a tenth embodiment of the present invention.
19 is a cross-sectional view of the wiring grid structure of FIG. 18 when observed from the X-axis direction.
FIG. 20 is a diagram illustrating a wiring grid structure using global wiring and local wiring of a semiconductor integrated circuit according to an eleventh embodiment of the present invention.
FIG. 21 is a diagram for explaining a direct connection from a cell having a strong driving force to a wiring of an oblique wiring grid in the eleventh embodiment.
22 is a diagram for explaining a definition position of an output terminal of a cell having a strong driving force in FIG. 21. FIG.
FIG. 23 is a diagram illustrating a wiring structure of a clock supply wiring from a conventional PLL to each flip-flop and a wiring structure of a clock supply wiring from the PLL to each flip-flop according to the twelfth embodiment of the present invention;
FIG. 24 is a diagram illustrating a wiring structure of clock supply wiring from a PLL to each flip-flop according to a twelfth embodiment.
FIG. 25 is a diagram illustrating a clock tree structure according to a twelfth embodiment.
FIG. 26 is a diagram illustrating a clock tree structure according to a twelfth embodiment.
FIG. 27 is a layout diagram showing a wiring grid structure of a semiconductor integrated circuit according to a thirteenth embodiment of the present invention.
FIG. 28 is a layout diagram showing a wiring grid structure of a conventional semiconductor integrated circuit device using wiring in an oblique direction.
FIG. 29 is a diagram for explaining a problem of grid point shift in the prior art.
[Explanation of symbols]
1, 601 First layer wiring
2,602 Second layer wiring
3, 603 Third layer wiring
4,604 4th layer wiring
10 Semiconductor substrate
11 Interlayer insulation film
12, 13, 14 Via hole
20 repeater cells
21, 22, 101, 201 cells
80 cellulou
85 wiring channels
102 Effective area
103 transistor region
191 Power supply wiring
250, 260 cut line
605 5th layer wiring
610 A cell with strong driving force
801, 802 Clock wiring
803 PLL
804 chip center
805 buffer cell
806 flip-flop
807 clusters
901 SRAM

Claims (25)

A semiconductor region in which a plurality of unit elements are formed;
The n-th (n ≧ 2) layer wiring formed in the upper layer of the semiconductor region is formed by a m (m ≧ 2) layer wiring orthogonal to the n−1-th layer wiring to form a reference wiring grid in the XY direction. A reference wiring layer to be formed;
An oblique wiring layer that is located above the reference wiring layer and forms an oblique wiring grid that intersects the reference wiring grid at an angle of 45 degrees or 135 degrees by the (m + 1) th layer wiring and the (m + 2) th layer wiring orthogonal to each other. And
The diagonal wiring layer has a wiring pitch between the m + 1 layer wiring and the m + 2 layer wiring set to √2 times the wiring pitch between the wirings of each of the reference wiring layers, and The semiconductor integrated circuit device, wherein the wiring widths of the (m + 1) th layer wiring and the (m + 2) th layer wiring are set to √2 times the wiring width of each layer of the reference wiring layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the oblique wiring layer has a wiring film thickness set to √2 times the wiring film thickness of the reference wiring grid. The reference wiring layer and the oblique wiring layer constitute a wiring channel region,
The semiconductor integrated circuit device according to claim 1, wherein the wiring channel region is provided in a direction parallel to a cell row in which logic cells including the unit elements are arranged in a row. The wiring of the reference wiring layer and the wiring of the diagonal wiring layer are provided with via holes for wiring connection at these intersections,
The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the via hole has a cross-sectional shape of any one of a hexagon, an octagon, and a parallelogram. The plurality of unit elements constitute a cell,
5. The semiconductor integrated circuit device according to claim 1, wherein the cell has an obstacle region that is defined by a shape along a wiring direction of the oblique wiring grid and in which wiring is not performed. 6. The semiconductor integrated circuit device according to claim 1, wherein a part of the wiring of the oblique wiring layer is configured as a power supply wiring for supplying power. The plurality of unit elements constitutes a cell composed of the plurality of unit elements,
The cell is supplied with a clock signal through a tree-type wiring path,
The tree-type wiring route includes a first connection by a route formed so as to approach each other on the wiring of the oblique wiring layer from the first and second points, and the diagonal from the third and fourth points. It is configured by combining a unit wiring shape configured by connecting the second connection by the path formed so as to approach each other on the wiring of the wiring layer by the wiring of the reference wiring layer. The semiconductor integrated circuit device according to claim 1. The semiconductor integrated circuit device further includes:
45 degrees or 135 degrees with respect to the diagonal wiring grid or the p-2 layer wiring, depending on the p-1 (p ≧ 2) layer wiring and the p layer wiring, which are positioned above the diagonal wiring layer and orthogonal to each other. An upper wiring layer forming an upper wiring grid intersecting at an angle of
In the upper wiring layer, the wiring pitch between the wirings of each layer is set to √2 times between the wirings of each of the oblique wiring layers or the wiring pitch of the p-2th layer wiring, The wiring width of each of the wiring layers is set to √2 times the wiring width of each of the oblique wiring layers or the wiring width of the p-2th layer wiring. A semiconductor integrated circuit device according to any one of the above. 9. The semiconductor integrated circuit device according to claim 1, wherein a global wiring over the entire chip is wired in the oblique wiring layer. The semiconductor integrated circuit device according to claim 9, wherein a local wiring other than the global wiring is wired in the reference wiring layer. The plurality of unit elements constitute a cell,
11. The semiconductor integrated circuit device according to claim 9, wherein the cell has an output terminal shape that can be directly connected to the wiring of the oblique wiring layer when the cell is to be directly connected to the global wiring. The semiconductor integrated circuit device further includes:
A flip-flop circuit;
PLL (Phase Locked Loop) arranged at the corner of the chip,
The flip-flop circuit is supplied with a clock signal through a tree-type wiring path,
The tree-type wiring path is connected from the PLL to the vicinity of the center of the chip using the wiring of the oblique wiring layer, and balances the RC product from the vicinity of the center of the chip to the flip-flop circuit via the buffer cell. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit devices are connected in a hierarchical manner as described above. The semiconductor integrated circuit device further includes:
An SRAM circuit using the wiring of the reference wiring layer as its internal wiring;
The semiconductor integrated circuit according to any one of claims 1 to 12, wherein a wiring that passes over the SRAM circuit is wired in the oblique wiring layer. The reference wiring layer is composed of three layers,
The first-layer wiring and third-layer wiring of the reference wiring layer are wired in a direction parallel to a cell row in which logic cells composed of the unit elements are arranged in a row. Or a semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1, wherein the reference wiring layer includes two layers. A semiconductor integrated circuit wiring method for wiring elements of a semiconductor integrated circuit,
A step of forming a reference wiring layer composed of a reference wiring grid in the XY direction, with the n (n ≧ 2) layer wirings being m (m ≧ 2) layer wirings orthogonal to the (n−1) th layer wiring; ,
Wiring between the m + 1th layer wiring and the m + 2th layer wiring is performed by crossing the reference wiring layer at an angle of 45 degrees or 135 degrees with the m + 1 layer wiring and the m + 2 layer wiring orthogonal to each other. The pitch is set to √2 times the wiring pitch between the wirings of the respective layers of the reference wiring layer, and the wiring widths of the (m + 1) th layer wiring and the (m + 2) th layer wiring are set to be equal to those of the reference wiring layer. And a step of forming so as to be set to √2 times the wiring width of each layer. The semiconductor integrated circuit wiring method further includes:
Extracting a wiring net that causes a delay exceeding a predetermined delay time from the wiring net formed by the reference wiring layer;
17. The method of wiring a semiconductor integrated circuit according to claim 16, further comprising the step of inserting a buffer cell for signal amplification at a position on the extracted wiring net that can be connected to the wiring of the oblique wiring grid. The semiconductor integrated circuit wiring method further includes:
Defining a cell comprising a plurality of said unit elements;
18. The semiconductor device according to claim 16, further comprising: an obstacle defining step for defining an obstacle area in which no wiring is performed in the cell in a shape along a wiring direction of the oblique wiring layer. Integrated circuit wiring method. 19. The semiconductor integrated circuit wiring method according to claim 18, wherein in the obstacle defining step, the (m + 1) th layer wiring or the (m + 2) th layer wiring is disposed in the vicinity of the corner. The semiconductor integrated circuit wiring method further includes:
When any one of the m layers of the reference wiring layer and one of the two parallel wires belonging to the same layer causes noise to the other wire, the wiring of the two wires The method for wiring a semiconductor integrated circuit according to any one of claims 16 to 19, further comprising a step of replacing a predetermined portion in the middle of any one of the wirings with a wiring of the oblique wiring layer. The semiconductor integrated circuit wiring method further includes:
21. The semiconductor integrated circuit wiring method according to claim 20, further comprising a step of inserting a buffer cell into a wiring path of the oblique wiring layer used for the replacement. The semiconductor integrated circuit wiring method further includes:
A predetermined cutting method using a cell composed of a plurality of unit elements using an XY cut line corresponding to the wiring direction of the reference wiring layer and an oblique cut line corresponding to the wiring direction of the diagonal wiring layer. The cell placement method according to claim 16, further comprising a step of placing based on. The semiconductor integrated circuit wiring method further includes:
Setting a first path formed so as to approach each other on the wiring of the diagonal wiring layer from the first and second points;
Setting a second path formed so as to approach each other on the wiring of the diagonal wiring layer from the third and fourth points;
Forming a unit wiring shape configured by connecting the first path and the second path by wiring of the reference wiring layer;
The semiconductor integrated circuit according to any one of claims 16 to 21, further comprising: forming a tree-type wiring path that supplies a clock signal to a cell composed of the plurality of unit elements by combining the unit wiring shapes. Circuit wiring method. The semiconductor integrated circuit wiring method further includes:
Connecting from the PLL (Phase Locked Loop) arranged at the corner of the chip to the vicinity of the center of the chip using the wiring of the diagonal wiring layer;
17. The semiconductor integrated circuit according to claim 16, further comprising a step of hierarchically connecting the RC product in the chip from the vicinity of the chip center to the flip-flop circuit in the chip through a buffer cell so as to balance the RC product. Circuit wiring method. The semiconductor integrated circuit wiring method further includes:
Forming an SRAM circuit using the wiring of the reference wiring layer as an internal wiring;
17. The method of wiring a semiconductor integrated circuit according to claim 16, further comprising: forming a wiring that passes over the SRAM circuit on the diagonal wiring layer.

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