JP3961072B2 - Semiconductor device and timing adjustment method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to various DRAMs or a semiconductor device including the same as a part thereof and a timing adjustment method thereof.
[0002]
[Prior art]
FIG. 9 shows a schematic configuration of a conventional DRAM. In general, a signal in which the low level “L” is in the active state is indicated by *.
A combination of a chip select signal * CS, a row address strobe signal * RAS, a column address strobe signal * CAS and a write enable signal * WE supplied to the command decoder 1, and further logical values of other signals if necessary. In response, one or more commands are supplied from the command decoder 1 to the timing adjustment circuit 2, and the commands are activated and deactivated at a predetermined timing, and supplied to the DRAM core 3 as DRAM control signals. This timing is generated by delaying a command generation time or an edge time of the clock CLKi by a delay circuit. The clock CLKi is obtained by supplying the external CLK to the clock buffer circuit 4.
[0003]
The control signal PR is supplied from the timing adjustment circuit 2 to the precharge circuit 5 while the row address strobe signal * RAS is at the high level “H”, and the bit lines BL and * BL in the memory cell array 6 are set to the potential VDD / 2, for example. Precharged. The CAS data bus DB and the data I / O buffer circuit 13 are precharged while the column address strobe signal * CAS is 'H'.
[0004]
When the row address strobe signal * RAS transitions to a low level 'L', the following series of RAS operations are performed asynchronously with the clock CLKi. That is, the higher addresses A23 to A12 are held in the row address buffer register 7 by the signal from the timing adjustment circuit 2 and decoded by the row decoder 8. The selected word line WL is set to a high voltage by the signal RX from the timing adjustment circuit 2, and the charge of the cell 6a is read to the bit line BL. The sense amplifier row 9 is activated by the control signals SAP (for turning on / off the pMOS transistors in the sense amplifier row 9) and SAN (for turning on / off the nMOS transistors in the sense amplifier row 9) from the timing adjustment circuit 2, and the bit line A minute potential difference between BL and * BL is amplified. If the activation start point is too early, the minute potential difference between the bit lines BL and * BL is too small and the amplification direction may be reversed due to noise.
[0005]
When the column address strobe signal * CAS changes to 'L', a series of operations of the CAS system is started. If the write enable signal * WE is 'H' at the fall of the column address strobe signal * CAS, the read operation is started, and if it is 'L', the write operation is started. The lower addresses A11 to A0 are held in the column address buffer register 10 by the signal from the timing adjustment circuit 2, decoded by the column decoder 11, and one column gate in the column gate row 12 is selected, and the bit lines BL and * BL is connected to the data bus DB. In the read operation, the data on the bit lines BL and * BL is read through the data I / O buffer circuit 13, and in the write operation, the data on the data bus DB passes through the bit lines BL and * BL to the cell 6a. Is written to. Next, the word line WL is set to a low level, the control signals SAP and SAN are deactivated, and the sense amplifier array 9 is deactivated.
[0006]
In synchronous DRAMs such as synchronous DRAMs and Rambus DRAMs, the speed of CAS-type operations is increased by pipeline processing in synchronization with a clock. However, for the RAS system, even in the case of a synchronous DRAM, the timing adjustment circuit 2 activates and deactivates a signal by signal delay using a load such as a transistor, a capacitor, and a wiring, as in the case of an asynchronous DRAM. The timing is adjusted. This timing adjustment design is performed using simulation, and the timing adjustment is performed with high accuracy.However, it is necessary to consider variations in the manufacturing process, fluctuations in the power supply voltage, etc., which increases the design period and increases costs. Cause.
[0007]
For general-purpose DRAMs that are mass-produced in one type, the design period can be extended, so this is not a problem, but for short-time and small-volume production DRAM / logic mixed chips such as ASIC, there is a problem. . This problem becomes more serious as the operating clock frequency increases. As a method for shortening the design period of such a chip, a method is also proposed in which the RAS system is operated synchronously with the same clock as the operation clock of the logic circuit.
[0008]
[Problems to be solved by the invention]
However, when the clock frequency is 100 MHz, for example, the timing is designed in units of 10 ns, and timing adjustment can be performed only in units of 5 ns even if the rising and falling edges of the clock are used, and the demand for speeding up the operation of the DRAM cannot be satisfied. .
[0009]
In view of such problems, an object of the present invention is to provide a semiconductor device and a timing adjustment method thereof capable of performing timing design with relatively high adjustment accuracy in a short period of time.
[0010]
[Means for solving the problems and their effects]
In the first aspect of the present invention ,
A command decoder that issues a control command in response to a supplied DRAM control signal;
DRAM core,
A timing adjustment circuit that supplies the DRAM core as a DRAM control signal with the control command active for a predetermined period;
In the semiconductor device, the timing adjustment circuit generates different first to n clocks whose phases are shifted with respect to a supplied reference clock, and one of the first to n clocks is generated in a predetermined operation cycle. The DRAM control signal is generated by activating the control command during a period from a predetermined number to a predetermined number of the first to n clocks , and the timing adjustment circuit further includes:
A first counter for counting one of the first to n clocks;
A second counter for counting one of the first to n clocks;
A timing buffer that generates the DRAM control signal by activating the control command from when the count value of the first counter becomes the first value until the count value of the second counter becomes the second value Circuit,
Have
[0011]
According to this semiconductor device, timing adjustment is performed in an integral multiple of the delay stage in the first to n-th clock generation circuits (digitally). Therefore, manufacturing process variations and power supply voltage variations are sensitively considered in timing design. Therefore, it is possible to reduce the manufacturing cost by shortening the timing design period, and it is particularly effective when applied to an ASIC having a short delivery time and a small volume production. For example, when the reference clock is 100 MHz and n = 6, the timing adjustment can be designed in units of 10/6 = 1.7 nsec, and the timing adjustment for the activation and deactivation of the control command can be performed with relatively high accuracy. There is an effect that can be performed.
[0013]
The semiconductor device according to the second aspect of the present invention differs from the first aspect in the following points. That is, the timing adjustment circuit of the second aspect is
A common counter that counts one of the first to n clocks and the reference clock as a common clock;
A first logic gate that enables and outputs one of the first to n clocks only while the count value of the common counter is a first value;
A second logic gate that enables and outputs one of the first to n clocks only while the count value of the common counter is a second value;
A timing buffer circuit for generating the DRAM control signal by activating the control command from when the output of the first logic gate is activated until the output of the second logic gate is activated; .
[0014]
According to this semiconductor device, the output of the common counter can be used in common for a plurality of or all of the command adjustments, so that the configuration is simplified.
In a third aspect of the present invention, in the first or second aspect, the timing adjustment circuit has a logic gate that validates and outputs the generated DRAM control signal only during a period in which the control command is issued. .
[0015]
According to a fourth aspect of the present invention, in the second aspect, the logic gate supplies the common clock to the first counter only while the control command is issued.
According to this semiconductor device, the number of logic gate stages of the control command output unit can be reduced as compared with the case of the third aspect , and the clock is counted by the counter only during the period when the control command is issued. The power consumption can be reduced.
[0016]
In a fifth aspect of the present invention, in the second aspect, the command decoder enables the count value of the first counter to be the first value only while the control command is issued. A logic gate for supplying the timing buffer circuit;
In the sixth aspect of the present invention, in any of the first to fifth aspects, the counter is a loop counter.
[0017]
According to this semiconductor device, the configuration is simplified.
According to a seventh aspect of the present invention, in the sixth aspect, a multi-bit output of the counter is supplied to at least one of the counters, and one-bit output is selected and output according to a selection control input value. A selection circuit;
A timing setting unit for storing and outputting the selection control input value.
[0018]
According to an eighth aspect of the present invention, in the second aspect, one of the first to n clocks is selected according to a selection control input value and supplied as a clock to the first logic gate or the second logic gate. A selection circuit;
A timing setting unit for storing and outputting the selection control input value.
[0019]
In a ninth aspect of the present invention, in the seventh or eighth aspect, the timing setting unit is a register.
According to this semiconductor device, it is possible to easily set and change the timing setting unit.
[0020]
According to a tenth aspect of the present invention, there is provided an MPU for accessing the DRAM according to any one of the first to ninth aspects .
In the semiconductor device timing adjustment method according to the eleventh aspect of the present invention, the output of the timing setting section according to the seventh or eighth aspect is determined before shipment according to the conditions of the manufacturing process.
According to this semiconductor device timing adjustment method, it is possible to improve the manufacturing yield of the semiconductor device without changing the circuit design.
[0021]
In the semiconductor device timing adjustment method of the twelfth aspect of the present invention, the output of the timing setting unit of the seventh or eighth aspect is determined before shipment in accordance with the required operation speed.
This method of adjusting the timing of the semiconductor device also has the effect of improving the yield of manufacturing the semiconductor device without changing the circuit design.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 shows a schematic configuration of a semiconductor device 20 according to the first embodiment of the present invention. The same parts as those in FIG. 9 are denoted by the same reference numerals.
[0023]
The semiconductor device 20 includes an ASIC in which a DRAM including a command decoder 1, a DRAM core 3, a clock buffer circuit 4, and a timing adjustment circuit 22, a logic circuit 24 such as a CPU or a memory controller, and other logic circuits 25 are mounted together. It is.
The logic circuits 24 and 25 operate in synchronization with the clock CLKi. A chip select signal * CS, a row address strobe signal * RAS, a column address strobe signal * CAS and a write enable signal * WE are supplied from the logic circuit 24 to the command decoder 1, and for example, these logical values at the rising edge of the clock CLKi are supplied. A command corresponding to the combination is issued from the command decoder 1. This command is a command SANNC, SAPC, PRC or PXC corresponding to the above-described control signals SAN, SAP, PR or PX. Hereinafter, any one of these will be referred to as CNTC, and DRAM control corresponding to the command CNTC. The signal is denoted as CNT.
[0024]
The multi-phase clock generation circuit 26 delays the clock CLKi through, for example, 2m, 4m, 6m,..., 2 (n−1) m and 2 nm inverters, thereby changing the phase of the clock CLKi to θ˜nθ. Shifted clocks φ1 to φn are generated. Here, m is a natural number. The multi-phase clock generation circuit 26 may be a DLL circuit that matches the phase of the clock φn with the phase of the clock CLKi. In this case, automatic adjustment is performed so that nθ = 2π. Clocks φ1 to φ6 in the case of n = 6 and nθ = 2π are shown in FIG. 3 together with the clock CLKi. The clocks CLKi and φ1 to φ6 have the same period T.
[0025]
In FIG. 1, the timing adjustment circuit 22 counts the clocks φ1 to φn generated by the multiphase clock generation circuit 26 by the counter circuit 28, and determines the timings of activation and deactivation of the control signal CNT. The signal is supplied to the timing buffer circuit 27 to generate the control signal CNT at this timing and supplied to the DRAM core 3. The timing buffer circuit 271 that is a part of the timing buffer circuit 27 is controlled by counters 281 and 282 that are a part of the counter circuit 28.
[0026]
FIG. 2 shows a configuration example of a part of the timing adjustment circuit 22 in FIG.
The timing buffer circuit 271 includes a flip-flop 30 in which the output terminal and the input terminal of the inverter 32 are connected to the input terminal and the output terminal of the inverter 31, respectively. The input terminal of the flip-flop 30 is connected to the drains of the pMOS transistors 33A and 33B and the nMOS transistor 35, the sources of the pMOS transistors 33A and 33B are connected to the power supply line VDD, and the source of the nMOS transistor 35 is connected to the ground line. Yes. The output of the flip-flop 30 is supplied to one input terminal of the AND gate 36, and the control command CNTC is supplied to the other input terminal of the AND gate 36.
[0027]
Each of the loop counters 281 and 282 has a value different from the remaining bits by only one bit, and is initialized to “00... 1” by a reset pulse RST, for example, as illustrated. Clocks φ3 and φ4 are supplied to clock input terminals CK of the loop counters 281 and 282, respectively.
A negative reset pulse * RST is supplied to the gate of the pMOS transistor 33A, whereby the output of the flip-flop 30 is initialized to 'L'. The output of the first bit of the loop counter 281 is supplied to the gate of the nMOS transistor 35 as the activation timing signal CNT1. The loop counter 281 is initialized by the reset pulse RST, and then becomes “10... 0” by the first pulse φ3, whereby the nMOS transistor 35 is turned on and the output of the flip-flop 30 becomes “H”. 'become. The output of the second bit of the loop counter 282 is supplied to the gate of the pMOS transistor 33B as the deactivation timing signal CNT2. After being initialized by the reset pulse RST, the loop counter 282 becomes “01... 0” by two pulses of the clock φ4, thereby turning on the pMOS transistor 33B and the output of the flip-flop 30 being “ L '.
[0028]
For example, as shown in FIG. 3, the control command CNTC rises in synchronization with the fall of the row address strobe signal * RAS at the start of the memory operation cycle, whereby the AND gate 36 is opened and the output of the flip-flop 30 is It passes through the AND gate 36 and is taken out as a control signal CNT. The control command CNTC becomes 'L' when the control command PRC is issued from the command decoder 1, for example, until the next row address strobe signal * RAS falls.
[0029]
The timing adjustment of other commands is also performed by the same circuit as in FIG.
According to the first embodiment, the timing of activation and deactivation of the control command CNTC is adjusted by counting the clocks of a predetermined phase output from the multi-phase clock generation circuit 26 with the counter, that is, the timing Since the adjustment is performed (digitally) by an integral multiple of the delay stage in the multi-phase clock generation circuit 26, it is not necessary to sensitively consider variations in manufacturing processes and power supply voltage variations in timing design. For example, when the clock CLKi is 100 MHz and n = 6, the timing adjustment can be designed in units of 10/6 = 1.7 nsec, and the timing adjustment for command activation and deactivation can be performed with relatively high accuracy. It can be carried out.
[0030]
[Second Embodiment]
In the first embodiment, the bit length must be increased so that the contents of the loop counters 281 and 282 do not exceed one round in the RAS cycle from the fall of the row address strobe signal * RAS to the next fall. .
Therefore, in the counter circuit 28A of the second embodiment, as shown in FIG. 4, the clock CLKi is counted by the loop counter 281 and the predetermined bit output of the loop counter 281 and the clock φ3 are supplied to the AND gate 37 to activate the timing. The signal CNT1 is generated, and a predetermined bit output of the loop counter 281 and the clock φ4 are supplied to the AND gate 37 to generate the deactivation timing signal CNT2.
[0031]
In this way, the output of the loop counter 281 can be used in common for all other command adjustments, so that the configuration of the counter circuit 28A is simplified.
Other points are the same as in the case of FIG.
[Third Embodiment]
FIG. 5 shows a schematic configuration of the timing adjustment circuit 22 according to the third embodiment of the present invention.
[0032]
In this circuit, an AND gate 283 is used for the counter circuit 28B in place of the AND gate 36 in FIG. 4, the clock CLKi and the control command CNTC are supplied thereto, and the output of the AND gate 283 is counted by the loop counter 281. Yes.
According to this configuration, the output of the flip-flop 30 can be directly used as the control signal CNT, and there is no need to consider the delay caused by the AND gate 36 in FIG. Further, since the clock CLKi is counted by the loop counter 281 through the AND gate 283 only when the control command CNTC is “H”, the power consumption of the counter circuit 28B can be reduced.
[0033]
Also, the pMOS transistors 33A and 33B and the nMOS transistor 35 in FIG. 4 are replaced with the nMOS transistors 35A and 35B and the pMOS transistor 33, respectively, the power supply wiring is reversed, and the negative logic control signal * CNT is output from the flip-flop 30. ing.
Other points are the same as in the case of FIG.
[0034]
[Fourth Embodiment]
FIG. 6 shows a schematic configuration of a DRAM control circuit according to the fourth embodiment of the present invention.
In this circuit, an AND gate 1a is used for the command decoder 1A instead of the AND gate 36 of FIG. 4, and the output of the loop counter 281 and the control command CNTC are supplied to the AND gate 1a. In this case, the AND gate 1a and the command decoder 1 of FIG. 1 constitute a command decoder 1A.
[0035]
When the activation period of the control signal CNT is one cycle or less of the clock CLKi, the output of the AND gate 1a can be commonly used by the AND gate 37 and the AND gate 38 as shown.
The loop counter 281 only needs to count one of the clock CLKi and φ1 to φ6. In FIG. 6, the clock φ2 is counted, and the next clock CLKi is counted from the rising edge of the clock φ3 in the predetermined period. The control signal CNT is activated during the period up to the rising edge of the clock φ1 of the period.
[0036]
Also in the fourth embodiment, the output of the flip-flop 30 can be directly used as the control signal CNT, and there is no need to consider the delay caused by the AND gate 36 in FIG.
[Fifth Embodiment]
For applications that are sufficient even if the operation speed of the DRAM is low, the yield of the semiconductor device manufacturing can be improved by designing the timing adjustment circuit 22 so that the timing margin is widened. However, it is complicated to change the design according to the application.
[0037]
Therefore, in the fifth embodiment, as shown in FIG. 7, the counter circuit 28D includes selection circuits 284A, 284B, 285A, 285B and a timing setting unit 286. Then, each bit of the output of the loop counter 281 is supplied to the selection circuits 284A and 285A, and the clocks φ1 to φ6 are supplied to the selection circuits 284B and 285B. Any one input can be selected for each of the above.
[0038]
The timing setting unit 286 has a variable output setting by selectively fusing a fuse with a laser beam, for example. By performing this setting before the semiconductor chip package according to the application or according to the conditions of the manufacturing process, it is possible to improve the manufacturing yield of the semiconductor device without changing the circuit design.
The other points are the same as in FIG.
[0039]
[Sixth Embodiment]
FIG. 8 shows a part of a DRAM control circuit according to the sixth embodiment of the present invention.
This circuit applies the concept of FIG. 6 to the circuit of FIG. 7, and uses a timing setting register 286A as one type of the timing setting unit 286 of FIG.
According to the sixth embodiment, it is possible to easily set and change the timing setting register 286A.
[0040]
In FIG. 8, CNT1 and CNT2A output from the AND gates 261A and 261B of the command decoder 1B are activation coarse timing signals.
Note that the present invention includes various other modifications.
For example, a configuration using the timing adjustment circuit 22 only for the * RAS system may be used. In this case, the “cycle of the predetermined operation” in claim 1 or 2 is not a * RAS cycle but is a period in which * RAS is at a low level, and the reset signal RST is activated during a period in which * RAS is 'H'. The bit length of the loop counter can be shortened.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a part of the timing adjustment circuit 22 in FIG. 1;
FIG. 3 is a timing chart showing the operation of the circuit of FIGS. 1 and 2;
FIG. 4 is a diagram showing a part of a timing adjustment circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a part of a timing adjustment circuit according to a third embodiment of the present invention.
FIG. 6 is a diagram showing a part of a DRAM control circuit according to a fourth embodiment of the present invention.
FIG. 7 is a diagram showing a part of a timing adjustment circuit according to a fifth embodiment of the present invention.
FIG. 8 is a diagram showing a part of a DRAM control circuit according to a sixth embodiment of the present invention;
FIG. 9 is a block diagram showing a schematic configuration of a conventional DRAM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Command decoder 2, 22 Timing adjustment circuit 3 DRAM core 20 Semiconductor device 24, 25 Logic circuit 26 Multiphase clock generation circuit 27, 271, 271A, 271B Timing buffer circuit 28, 28A-28D Counter circuit 281, 282 Loop counter 284A, 284B, 285A, 285B selection circuit 286 timing setting unit 286A timing setting register 30 flip-flop

Claims (12)

A command decoder that issues a control command in response to a supplied DRAM control signal;
DRAM core,
A timing adjustment circuit that supplies the DRAM core as a DRAM control signal with the control command active for a predetermined period;
In the semiconductor device, the timing adjustment circuit generates different first to n clocks whose phases are shifted with respect to a supplied reference clock, and one of the first to n clocks is generated in a predetermined operation cycle. The DRAM control signal is generated by activating the control command during a period from a predetermined number to a predetermined number of the first to n clocks , and the timing adjustment circuit further includes:
A first counter for counting one of the first to n clocks;
A second counter for counting one of the first to n clocks;
A timing buffer that generates the DRAM control signal by activating the control command from when the count value of the first counter becomes the first value until the count value of the second counter becomes the second value Circuit,
Wherein a has a. A command decoder that issues a control command in response to a supplied DRAM control signal;
DRAM core,
A timing adjustment circuit that supplies the DRAM core as a DRAM control signal with the control command active for a predetermined period;
The timing adjustment circuit generates different first to n clocks whose phases are shifted with respect to a supplied reference clock, and one of the first to n clocks is generated in a predetermined operation cycle. The DRAM control signal is generated by activating the control command during a period from a predetermined number to a predetermined number of the first to n clocks, and the timing adjustment circuit further includes :
A common counter for counting one of the first 1~n clock and the reference clock as a common clock,
A first logic gate count of the common counter enable and output one of said first 1~n clock only during the first value,
A second logic gate count of the common counter output enable one of said first 1~n clock only during the second value,
And a timing buffer circuit for generating the DRAM control signal by the output of the second logic gate the output of said first logic gate becomes active is to be active during the above control commands until the activity,
Semi conductor arrangement you, comprising a. 3. The semiconductor device according to claim 1, wherein the timing adjustment circuit includes a logic gate that validates and outputs the generated DRAM control signal only during a period in which the control command is issued. 3. The semiconductor device according to claim 2 , further comprising a logic gate that supplies the common clock to the first counter only while the control command is issued. The command decoder has a logic gate that enables the count value of the first counter to be the first value and supplies the timing buffer circuit to the timing buffer circuit only while the control command is issued. The semiconductor device according to claim 2 . The semiconductor device according to any one of claims 1 to 5, characterized in that the counter is each a loop counter. For at least one of the counters, a selection circuit for supplying a multi-bit output of the counter and selecting and outputting a 1-bit output of the counter according to a selection control input value;
A timing setting unit for storing and outputting the selection control input value;
The semiconductor device according to claim 6, further comprising: A selection circuit that selects one of the first to n clocks according to a selection control input value and supplies the selected clock as a clock to the first logic gate or the second logic gate;
A timing setting unit for storing and outputting the selection control input value;
The semiconductor device according to claim 2, further comprising: 9. The semiconductor device according to claim 7 , wherein the timing setting unit is a register. The semiconductor device according to any one of claims 1 to 9, characterized in that it comprises an MPU that accesses the DRAM. A timing adjustment method for a semiconductor device, characterized in that the output of the timing setting unit according to claim 7 or 8 is determined before shipment in accordance with conditions of a manufacturing process. 9. A method of adjusting a timing of a semiconductor device, wherein the output of the timing setting unit according to claim 7 or 8 is determined before shipment in accordance with a required operation speed.

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