JP3960353B2 - Liquid crystal display - Google Patents

Description

The present invention relates to a liquid crystal display device, and is particularly suitable for application to a liquid crystal display device in which a conductive light-shielding layer is provided in an upper layer of a thin film transistor for driving a pixel electrode and a lower layer of the pixel electrode. .

Liquid crystal display devices are widely used as flat displays. Conventionally, an amorphous silicon (a-Si) TFT has been used as a thin film transistor (TFT) for driving a pixel electrode in this liquid crystal display device, but recently, a polycrystalline Si TFT has been frequently used.

Polycrystalline Si TFTs are not as light sensitive as a-Si TFTs, but in recent liquid crystal display devices, for example, projectors are used under a large amount of light, and light leakage current cannot be ignored even with polycrystalline Si TFTs. . As a result, image quality deterioration such as a decrease in contrast, crosstalk, and flicker is a problem.

In a liquid crystal display device, light from a light source is normally incident from the counter substrate side. However, as described in Japanese Patent Laid-Open No. 5-100250, for example, this light suppression for the incidence of light on a polycrystalline Si TFT has been conventionally performed. Reduction is achieved by installing the conductive light-shielding layer (black matrix) that has been placed on the counter substrate on the upper layer of the polycrystalline Si TFT of the TFT substrate that is closer to the polycrystalline Si TFT.

However, according to the knowledge of the present inventor, in the technique disclosed in the above Japanese Patent Laid-Open No. 5-100250, the thickness of the conductive light-shielding layer depends on the unevenness of the underlying insulating layer, so that It has been found that the light shielding performance at the step portion becomes insufficient due to the phenomenon of thinning, in other words, the phenomenon of deterioration of step coverage. For this reason, under high-intensity light irradiation, light leakage current is generated by light leaked from the stepped portion, and deterioration of image quality cannot be suppressed.

This problem will be described more specifically. FIG. 8 shows a TFT substrate of a conventional active matrix type liquid crystal display device. As shown in FIG. 8, the quartz glass substrate 10 in the light shielding region.
1 is provided with a light shielding layer 102, and an interlayer insulating film 103 is provided so as to cover the light shielding layer 102. A polycrystalline Si film 104 having a predetermined shape is provided on the interlayer insulating film 103, and a gate insulating film 105 is provided so as to cover the polycrystalline Si film 104. A gate wiring 106 is provided on the gate insulating film 105. Although not shown, a source region and a drain region (not shown) are formed in the polycrystalline Si film 104 in a self-aligned manner with respect to the gate wiring 106. The gate electrode composed of the gate wiring 106 and the source region and the drain region constitute a polycrystalline Si TFT for driving the pixel electrode. An electrode 107 is provided on the gate insulating film 105 in a predetermined portion above the drain region. With the structure in which the gate insulating film 105 is sandwiched between the electrode 107 and the drain region,
A holding capacitive element is configured.

An interlayer insulating film 108 is provided so as to cover the gate wiring 106 and the electrode 107.
Contact holes 109 are formed in predetermined portions of the interlayer insulating film 108 and the gate insulating film 105.
, 110 are provided. On the interlayer insulating film 108 in the light shielding region, an extraction electrode 111 is provided connected to the drain region of the polycrystalline Si TFT through the contact hole 109, and is connected to the source region of the polycrystalline Si TFT through the contact hole 110. A wiring 112 is provided. An interlayer insulating film 113 is provided so as to cover the extraction electrode 111 and the signal wiring 112. A SiN film 114 formed by a plasma CVD method is provided on a predetermined portion on the interlayer insulating film 113. This Si
The N film 114 mainly serves as a hydrogen supply source for improving the characteristics of the polycrystalline Si TFT by inactivating dangling bonds existing in the polycrystalline Si film 104 with hydrogen. Further, a contact hole 1 is formed in the interlayer insulating film 113 in a predetermined portion on the extraction electrode 111.
15 is provided. A conductive light-shielding layer 116 is provided on the interlayer insulating film 113 and connected to the extraction electrode 111 through the contact hole 115, and the SiN film 1
A conductive light-shielding layer 117 is provided on 14. By superimposing these conductive light shielding layers 116, 117, the extraction electrode 111, and the signal wiring 112, all of the regions other than the pixel opening region are shielded against incident light from above. Conductive light shielding layers 116 and 11
An interlayer insulating film 118 is provided so as to cover 7. A contact hole 119 is provided in the interlayer insulating film 118 in a predetermined portion on the conductive light shielding layer 116. On the interlayer insulating film 118, a transparent pixel electrode 120 connected to the conductive light shielding layer 116 through the contact hole 119 is provided. An alignment film 121 of liquid crystal (not shown) is provided so as to cover the pixel electrode 120.
JP-A-5-100250

However, in the conventional liquid crystal display device shown in FIG. 8 described above, the conductive light shielding layers 116 and 117 are formed on the interlayer insulating film 113 having large unevenness reflecting the stepped shape of the base. The step coverage of the conductive light shielding layers 116 and 117 is deteriorated. For this reason, the light shielding performance by the conductive light shielding layers 116 and 117 at the stepped portion becomes insufficient, and light leakage current is generated due to light leaked from the stepped portion under irradiation of high-intensity light, thereby suppressing deterioration in image quality. I couldn't.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of improving the light shielding performance by a conductive light shielding layer and suppressing image quality deterioration due to light leakage current, and a method for manufacturing the same.

In order to solve the above problems, the present invention provides:
In a liquid crystal display device in which a thin film transistor for driving a pixel electrode is provided on a substrate, and a conductive light-shielding layer is provided at a position above the thin film transistor and below the pixel electrode,

The conductive light shielding layer is provided on the flattened layer.

The invention also provides
In a method of manufacturing a liquid crystal display device, a thin film transistor for driving a pixel electrode is provided on a substrate, and a conductive light-shielding layer is provided above the thin film transistor and below the pixel electrode.
The conductive light shielding layer is formed on the flattened layer.

In the present invention, the surface of the flattened layer usually has a residual step level of at least 0.5 μm or less, preferably 0.3 μm or less (except for the contact portion in the display area). The difference in thickness is flattened. This planarized layer is typically SiO 2
_Although the insulating layer is mainly composed of ₂ , other insulating layers may be used.

As a method for forming the flattened layer, for example, various methods capable of obtaining a residual step level of 0.5 μm or less can be used. For example, a method using a plasma CVD method using tetraethoxysilane (TEOS) or the like as a raw material gas or a film forming method having good embeddability by an atmospheric pressure CVD method, phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG) Or the like, a flow method using spin-on glass (SOG), a method of etching back after forming an insulating film, a chemical mechanical polishing (CMP) after forming an insulating film ) Method. Of these methods,
The CMP method is preferable because it can provide excellent flatness and can suppress plasma damage to the thin film transistor. As an insulating layer planarized by this CMP method, in particular, a film formed by plasma CVD using TEOS, TEOS
It is possible to use a film by atmospheric pressure CVD using a film, a film by high density plasma CVD, a laminated film thereof, or the like.

The conductive light shielding layer has a sheet resistance of 10 from the viewpoint of suppressing the coupling capacity with the adjacent wiring.
It is preferably 0Ω / □ or less, and more preferably 10Ω / □ or less. The conductive light shielding layer has a wavelength of at least 4 from the viewpoint of suppressing the light leakage current of the thin film transistor.
The transmittance with respect to light in the region of 00 to 500 nm is preferably 10% or less, more preferably 5% or less, and further lower for increasing the light shielding effect. The thickness of the conductive light-shielding layer can basically be freely selected as long as both low sheet resistance and light-shielding properties can be achieved. In practice, however, the conductive light-shielding layer usually has an insulating layer on the conductive light-shielding layer. Since a transparent pixel electrode is further formed via the liquid crystal so as to sandwich the liquid crystal, a thickness in a range in which the step due to the conductive light shielding layer does not affect the alignment of the liquid crystal is desirable. Practically, the thickness of the conductive light shielding layer is preferably 50 to 500 nm, and more preferably 100 to 300 nm. Furthermore, the material of the conductive light shielding layer can be freely selected basically as long as both conductivity and light shielding properties can be achieved. Specifically, for example, Al, Cu, W, Mo, Pt, Pd, Ti, TiN
, Cr and the like, and alloys and silicides thereof.

In addition, the conductive light-shielding layer is provided, for example, in a pixel portion that is separated into a portion connected to the pixel electrode and a portion connected to the common potential. Further, the conductive light-shielding layer shields all of the areas other than the pixel opening area by overlapping the incident light from above with one or more other light-shielding layers.

In the present invention, the thin film transistor for driving the pixel electrode is typically a thin film transistor using polycrystalline silicon, that is, a polycrystalline Si TFT. This polycrystalline SiTF
T may be a so-called high-temperature polycrystalline Si TFT using a polycrystalline Si film by a high-temperature process or a so-called low-temperature polycrystalline Si TFT using a polycrystalline Si film by a low-temperature process. Further, the thin film transistor for driving the pixel electrode may be an a-Si TFT.
According to the present invention configured as described above, since the conductive light shielding layer is formed on the flattened layer, the step coverage of the conductive light shielding layer is improved, and the thickness uniformity is improved. Can be achieved. For this reason, sufficient light-shielding performance can be obtained by this conductive light-shielding layer, and the occurrence of light leakage current can be suppressed even under high-intensity light irradiation because the leakage light can be greatly reduced. .

According to the present invention, by forming the conductive light shielding layer on the planarized layer, the light shielding performance by the conductive light shielding layer can be improved, and the deterioration of the image quality due to the light leakage current can be suppressed.

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.

FIG. 1 shows an example of a TFT substrate of a liquid crystal display device according to the first embodiment of the present invention.
Shows an example of the overall configuration of the liquid crystal display device. This liquid crystal display device is an active matrix type liquid crystal display device.

As shown in FIGS. 1 and 2, in this liquid crystal display device, a light shielding layer 12 is provided on a quartz glass substrate 11 in a light shielding region. This light shielding layer 12 has a film thickness of 50 n, for example.
It consists of a laminated film in which a polycrystalline Si film doped with m phosphorus (P) and a WSi film having a thickness of 200 nm, for example, are sequentially laminated. An interlayer insulating film 13 made of, for example, an SiO ₂ film is provided so as to cover the light shielding layer 12. A polycrystalline Si film 1 having a predetermined shape is formed on the interlayer insulating film 13.
4 is provided, and a gate insulating film 15 made of, for example, a SiO ₂ film is provided so as to cover the polycrystalline Si film 14. A gate wiring 16 is provided on the gate insulating film 15. Although not shown, a source region and a drain region are formed in the polycrystalline Si film 14 in a self-aligned manner with respect to the gate wiring 16. The gate electrode made of the gate wiring 16 and the source region and the drain region constitute a polycrystalline Si TFT for driving the pixel electrode. An electrode 17 is provided on the gate insulating film 15 in the portion above the drain region. A holding capacitor element is configured by a structure in which the gate insulating film 15 is sandwiched between the electrode 17 and the drain region.

The gate wiring 16 and the electrode 17 are composed of a laminated film in which, for example, a polycrystalline Si film doped with P having a thickness of 100 nm and a WSi film having a thickness of 100 nm, for example, are sequentially laminated. An interlayer insulating film 18 is provided so as to cover the gate wiring 16 and the electrode 17. Contact holes 19 and 20 are provided in predetermined portions of the interlayer insulating film 18 and the gate insulating film 15. Polycrystalline S is formed on the interlayer insulating film 18 in the light shielding region through the contact hole 19.
A lead electrode 21 is provided connected to the drain region of the iTFT, and a signal wiring 22 is connected to the source region of the polycrystalline Si TFT through the contact hole 20. The lead electrode 21 and the signal wiring 22 have a film thickness of 50 nm, for example.
WSi film, for example, an Al film having a film thickness of 300 nm and a WSi film having a film thickness of 50 nm, for example, are sequentially stacked. An interlayer insulating film 23 made of, for example, a SiO ₂ film is provided so as to cover the extraction electrode 21 and the signal wiring 22. The interlayer insulating film 23 is made of a PSG film having a film thickness of 400 nm formed by, for example, an atmospheric pressure CVD method. A predetermined portion on this interlayer insulating film 23 is formed by plasma CVD, for example, with a film thickness of 200 nm.
The SiN film 24 is provided. The SiN film 24 mainly serves as a hydrogen supply source for improving the characteristics of the polycrystalline Si TFT by inactivating dangling bonds existing in the polycrystalline Si film 14 with hydrogen. An interlayer insulating film 25 is provided on the interlayer insulating film 23 and the SiN film 24. This interlayer insulating film 25 is made of, for example, a SiO ₂ film formed by a plasma CVD method using TEOS as a source gas. A contact hole 26 is provided in the interlayer insulating film 25 and the interlayer insulating film 23 in a predetermined portion on the extraction electrode 21.

The surface of the interlayer insulating film 25 is at least 0.5 μm except for the contact hole 26 portion.
It is flattened to a residual step level of m or less, preferably 0.3 μm or less. The thickness of the interlayer insulating film 25 is, for example, about 1.8 ± 0.5 μm at the opening region and about 0.3 μm at the portion on the extraction electrode 21.

Conductive light-shielding layers 27 and 28 are provided separately on the interlayer insulating film 25 having a flat surface. The conductive light shielding layer 27 is connected to the extraction electrode 21 through the contact hole 26. These conductive light shielding layers 15 and 16 are made of, for example, a Ti film having a thickness of 250 nm. By superimposing these conductive light shielding layers 27 and 28 with the extraction electrode 21 and the signal wiring 22, all of the regions other than the pixel opening region are shielded against incident light from above. The conductive light shielding layer 27 is connected to a pixel electrode described later, and the conductive light shielding layer 28 is connected to a predetermined common potential.

An interlayer insulating film 29 is provided so as to cover the conductive light shielding layers 27 and 28. The interlayer insulating film 29 is made of, for example, a SiO ₂ film having a thickness of 400 nm formed by a plasma CVD method using TEOS as a source gas. A contact hole 30 is provided in the interlayer insulating film 29 in a predetermined portion on the conductive light shielding layer 27. A transparent pixel electrode 31 is provided on the interlayer insulating film 29 so as to be connected to the conductive light shielding layer 27 through the contact hole 30. The pixel electrode 31 is made of, for example, ITO having a film thickness of 70 nm. A liquid crystal alignment film 32 is provided so as to cover the pixel electrode 31.

As shown in FIG. 2, a liquid crystal 36 is formed between the TFT substrate configured in this manner and a transparent electrode 34 as a counter electrode and a liquid crystal alignment film 35 sequentially stacked on one main surface of a glass substrate 33. Is enclosed.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment configured as described above will be described.

First, as shown in FIG. 3, a polycrystalline Si film doped with P and a WSi film are sequentially formed on a quartz glass substrate 11, and then the light shielding layer 12 is formed by patterning these films. Next, an interlayer insulating film 13 made of a SiO ₂ film is formed on the entire surface of the substrate by, eg, CVD. Next, after a polycrystalline Si film 14 is formed on the entire surface by, eg, CVD, this polycrystalline Si film 14
Is patterned. Next, after a gate insulating film 15 made of a SiO ₂ film is formed on the entire surface of the substrate by, for example, the CVD method, the gate insulating film 15 is patterned into a predetermined shape. next,
After sequentially forming a polycrystalline Si film doped with P and a WSi film on the entire surface of the substrate, these films are patterned to form a gate wiring 16 and a capacitor element electrode 17.

Next, an interlayer insulating film 18 made of, for example, a SiO ₂ film is formed on the entire surface of the substrate by, eg, CVD. Next, predetermined portions of the interlayer insulating film 18 and the gate insulating film 15 are removed by etching to form contact holes 19 and 20. Next, after sequentially forming a WSi film, an Al film and a WSi film on the entire surface of the substrate, these films are patterned to form the lead electrode 21 and the signal wiring 22. Next, an interlayer insulating film 23 made of a SiO ₂ film is formed on the entire surface of the substrate by, for example, atmospheric pressure CVD. Next, the SiN film 24 is formed on the entire surface of the substrate by, for example, plasma CVD.
After this, the SiN film 24 is patterned.

Next, for example, Si plasma is formed on the entire surface of the substrate by a plasma CVD method using TEOS as a source gas.
A flat interlayer insulating film 25 made of an O ₂ film is formed. The thickness of the interlayer insulating film 25 is, for example, 2500 nm.

Next, as shown in FIG. 4, the interlayer insulating film 25 is, for example, about 2200 nm thick by CMP.
Polish and flatten. The level difference level after planarization by this CMP method is at least 0.5.
It can be made 0.1 μm or less depending on conditions. An example of the CMP conditions is as follows.

Polishing load 470 gf / cm ²
Chuck rotation speed 60rpm
Table rotation speed 4rpm
Retainer height 840μm
Polishing rate 4 minutes at 500 nm / min. Dressing system in-situ dress Slurry SS-25 (Slurry in which silica particles are dispersed in KOH liquid)
Uses 1/2 pure water dilution

Next, as shown in FIG. 1, predetermined portions of the interlayer insulating film 25 and the interlayer insulating film 23 are removed by etching to form contact holes 26. Next, after a Ti film is formed on the entire surface of the substrate by, for example, a vacuum deposition method or a sputtering method, the Ti film is patterned to form the conductive light shielding layers 27 and 28. In this case, when the Ti film is formed, the surface of the underlying interlayer insulating film 25 is planarized in advance, so that this Ti film, and hence the conductive light shielding layers 27, 2
The step coverage of 8 is good and has a uniform thickness.

Next, an interlayer insulating film 29 made of a SiO ₂ film is formed on the entire surface of the substrate by, for example, a plasma CVD method using TEOS. Next, a predetermined portion of the interlayer insulating film 29 is removed by etching to form a contact hole 30. Next, after forming an ITO film on the entire surface of the substrate, this ITO
A pixel electrode 31 is formed by patterning the film by etching. Next, an alignment film 32 is formed on the entire surface of the substrate.

After manufacturing the TFT substrate as described above, the process proceeds according to a conventionally known method,
As shown in FIG. 2, a target liquid crystal display device is completed.

As described above, according to the first embodiment, the conductive light-shielding layers 27 and 28 are formed on the interlayer insulating film 25 whose surface is flattened by the CMP method. The step coverage of the conductive light shielding layers 27 and 28 is improved, and the thickness is uniform. For this reason, the light shielding performance by these conductive light shielding layers 27 and 28 is improved, the leakage light is suppressed, and the light leakage current is greatly reduced. Therefore, even when used under a large amount of light, it is caused by the light leakage current. It is possible to significantly reduce the bright spot generation rate and the amount of crosstalk, and to suppress deterioration in image quality.

  Next, an example of the second embodiment of the present invention will be described.

In the first embodiment, the interlayer insulating film 25 which is the base layer of the conductive light shielding layers 27 and 28 is made of a thick SiO ₂ film formed by a plasma CVD method using TEOS as a source gas.
Polished by MP method. By the way, generally, the stress of the SiO ₂ film formed on the Si substrate by the plasma CVD method is −1.0 to 2.0 × 10 ⁹ dyne / cm ² (compression).
On the other hand, when the SiO ₂ film is formed on the quartz glass substrate 11 under the same conditions as on the Si substrate, the stress is 1.0 to 2.0 × 10 ⁹ dyne / cm ² (tensile). . This S
The stress of the iO ₂ film causes a warp of the quartz glass substrate 11 (hereinafter simply referred to as a wafer) in the wafer state during the process, so that it is desirable to reduce the stress in order to prevent problems caused by the warp. Therefore, in the second embodiment, a warp mitigation measure for the wafer will be described.

In this second embodiment, as a measure for reducing the warpage of the wafer, a method of creating a high vacuum in the film forming chamber when forming the SiO ₂ film as the interlayer insulating film 25 by plasma CVD,
Examples include a method of reducing the flow rate of EOS and a method of increasing RF power.

For example, when a plasma CVD apparatus manufactured by AMJ is used to form a SiO ₂ film, the general film forming conditions are: pressure 8.2 Torr, temperature 400 ° C., O ₂ flow rate 600 sccm, TEOS flow rate 800 sccm, RF power 700 W, Whereas the spacing is 250 mils
When the SiO ₂ film as the interlayer insulating film 25 is formed on the quartz glass substrate 11 by the plasma CVD method, the pressure in the film forming chamber is set to 6.8 Torr or less, the RF power is set to 800 W or more, O ₂ / By performing any one of making the TEOS ratio 1 or more, the interlayer insulating film 25
The stress of the wafer can be relaxed, and the warpage of the wafer can be effectively prevented.

Since the other aspects of the second embodiment are the same as those of the first embodiment, description thereof will be omitted.

According to the second embodiment, the same advantages as those of the first embodiment can be obtained.
Since the warpage of the wafer can be greatly reduced, an advantage that a liquid crystal display device can be manufactured without causing a problem due to the warpage of the wafer can be obtained.

Next, an example of the third embodiment of the present invention will be described. In the third embodiment, a wafer warping mitigation measure by a method different from that of the second embodiment will be described.

In the third embodiment, as a warp mitigation measure for the wafer, after the process is advanced to the polishing of the interlayer insulating film 25 as in the first embodiment, as shown in FIGS.
A groove 37 reaching the quartz glass substrate 11 is formed in the scribe region of the quartz glass substrate 11 so that the interlayer insulating films 13, 18, 23, and 25 are divided for each chip. The width of the groove 37 is, for example, about 200 μm. The groove 37 may be formed by etching the interlayer insulating films 13, 18, 23, and 25 after polishing the interlayer insulating film 25. From the viewpoint of simplifying the process, the groove 37 It is advantageous to form the holes 19 and 20 in two steps by using the etching for forming the holes 19 and 20 and the etching for forming the contact holes 26. Specifically, the contact hole 19 is formed after the interlayer insulating film 18 is formed.
, 20 are also removed by etching in the interlayer insulating films 13 and 18 in the scribe region. Next, after the deposition and polishing of the interlayer insulating film 25 are performed, the interlayer insulating films 23 and 2 in the scribe region portion are etched at the time of etching for forming the contact hole 26.
5 is also removed by etching. Thereby, the groove 37 is formed. These etches are
A dry etching method such as a reactive ion etching (RIE) method, a wet etching method, or a combination thereof can be used.

After forming the groove 37 as described above, the conductive light shielding layer 27 is formed in the same manner as in the first embodiment.
, 28 are advanced to complete the target liquid crystal display device.

Since the third embodiment other than the above is the same as that of the first embodiment, description thereof will be omitted.

According to the third embodiment, the same advantages as in the first embodiment can be obtained,
The wafer warpage of by dividing the whole of the interlayer insulating film 13,18,23,25 including an interlayer insulating film 25 made of SiO ₂ film by a plasma CVD method in which large stress exists by the groove 37 in each chip The liquid crystal display device can be advantageously manufactured without causing problems due to warpage of the wafer.

Next explained is a liquid crystal display device according to one example of the fourth embodiment of the invention. FIG. 7 shows an example of the liquid crystal display device.

As shown in FIG. 7, in this liquid crystal display device, the extraction electrode 21 and the signal wiring 2
As an insulating layer between 2 and the conductive light shielding layers 27 and 28, only an interlayer insulating film 25 made of a SiO ₂ film formed by plasma CVD is formed. That is, the formed interlayer insulating film 18 and SiN film 24 are not formed in the liquid crystal display device according to the first embodiment.

Since the fourth embodiment is the same as the first embodiment except for the above, the description thereof is omitted.

  According to the fourth embodiment, the same advantages as those of the first embodiment can be obtained.

The embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible.

That is, the numerical values, structures, shapes, materials, processes, and the like given in the above-described embodiments are merely examples, and different numerical values, structures, shapes, materials, processes, and the like can be used as necessary. is there.

For example, in the above-described embodiment, the light shielding layer 12 is also formed in the lower layer of the polycrystalline Si TFT, but this light shielding layer 12 is for preventing light incidence from below the polycrystalline Si TFT. It can be omitted as necessary.

In the above-described embodiment, the pixel electrode 31 is connected to the extraction electrode 21 via the conductive light shielding layer 27. However, if a good contact can be obtained, the conductive light shielding layer 27 can be obtained.
The pixel electrode 31 may be directly connected to the extraction electrode 21 without forming the electrode.

Furthermore, the present invention is basically a liquid crystal display device in which a thin film transistor for driving a pixel electrode is provided on a substrate, and a conductive light-shielding layer is provided above the thin film transistor and below the pixel electrode. Can be applied to any liquid crystal display device.

It is sectional drawing which shows the TFT substrate of the liquid crystal display device by 1st Embodiment of this invention. 1 is a cross-sectional view showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing method of the liquid crystal display device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the liquid crystal display device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the 3rd Embodiment of this invention. It is a top view for demonstrating the 3rd Embodiment of this invention. It is sectional drawing which shows the TFT substrate of the liquid crystal display device by 4th Embodiment of this invention. It is sectional drawing which shows the TFT substrate of the conventional liquid crystal display device.

Explanation of symbols

11 ... quartz glass substrate, 12 ... light shielding layer, 13, 18, 23, 25, 29 ...
Interlayer insulating film, 14 ... polycrystalline Si film, 16 ... gate wiring, 19, 20, 26, 30
... Contact hole, 27, 28 ... Conductive light shielding layer, 31 ... Pixel electrode, 33
..Glass substrate, 34 ... transparent electrode, 36 ... liquid crystal, 37 ... groove

Claims (9)

In a liquid crystal display device in which a thin film transistor for driving a pixel electrode is provided on a substrate, and a conductive light shielding layer is provided in a position above the thin film transistor and below the pixel electrode,
The conductive light shielding layer is provided on the planarized layer;
A lead electrode and a signal wiring are provided at a position above the substrate and below the conductive light shielding layer ,
The conductive light shielding layer has a portion connected to the extraction electrode in the pixel portion, and an end thereof is provided on the flattened layer,
The liquid crystal display device, characterized in that it covering the region other than the pixel aperture region overlap each other with the conductive shielding layer and the other one or more light-shielding layers. The extraction electrode and the signal wiring partially cover an area other than the pixel opening area, and the conductive light shielding layer covers an area other than the pixel opening area not covered by the extraction electrode and the signal wiring. The liquid crystal display device according to claim 1. The conductive light shielding layer partially covers a region other than the pixel opening region, and the lead electrode and the signal wiring cover a region other than the pixel opening region that is not covered by the conductive light shielding layer. The liquid crystal display device according to claim 1. 2. The liquid crystal display device according to claim 1, wherein the conductive light shielding layer includes a portion connected to the pixel electrode or a portion connected to a common potential . 5. The liquid crystal display device according to claim 4, wherein the conductive light shielding layer has a portion connected to the extraction electrode through a contact hole formed in the planarized layer. 2. The portion of the conductive light shielding layer connected to the pixel electrode is connected to the extraction electrode through a contact hole formed in the planarized layer. Liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein the conductive light shielding layer , the extraction electrode, and the signal wiring overlap to cover the region of the thin film transistor. 8. The liquid crystal display device according to claim 7, wherein the conductive light shielding layer , the extraction electrode, and the signal wiring overlap to cover a channel region of the thin film transistor. In a projector using a liquid crystal display device in which a thin film transistor for driving a pixel electrode is provided on a substrate, and a conductive light-shielding layer is provided above the thin film transistor and below the pixel electrode,
The conductive light shielding layer is provided on the planarized layer;
A lead electrode and a signal wiring are provided at a position above the substrate and below the conductive light shielding layer ,
The conductive light shielding layer has a portion connected to the extraction electrode in the pixel portion, and an end thereof is provided on the flattened layer,
A projector characterized in that the conductive light shielding layer and one or more other light shielding layers overlap to cover an area other than the pixel opening area.

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