JP3958221B2

JP3958221B2 - Semiconductor device and manufacturing method thereof

Info

Publication number: JP3958221B2
Application number: JP2003012077A
Authority: JP
Inventors: 望下石坂; 久士船越; 健松本; 芳宏松島
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2003-01-21
Filing date: 2003-01-21
Publication date: 2007-08-15
Anticipated expiration: 2023-01-21
Also published as: JP2004228199A

Description

【０００１】
【発明の属する技術分野】
本発明は、ＣＯＧやＴＡＢ、ＣＯＦ等のベアチップ実装に使用される半導体素子の電極上に電解めっきバンプを形成した半導体装置およびその製造方法に関するものである。
【０００２】
【従来の技術】
近年、電子機器の小型化、高機能化及び半導体素子プロセスの微細化に伴い、ベアチップ接合に用いるバンプ電極を備えた半導体装置も微細化、狭端子ピッチ化が要望されている。狭ピッチのベアチップ実装やＣＯＧやＴＡＢ、ＣＯＦ接合などのバンプ電極形成には電解めっき法が主に用いられる。
【０００３】
バンプ高さのばらつきはベアチップ実装の実装歩留りに直接影響を及ぼす。電解めっき法によるバンプの高さばらつきはめっき電流密度の不均一性に起因するため、従来よりめっき電流密度の均一性を向上する提案がなされている。
【０００４】
めっき電流密度の均一性を向上する方法としては、被めっき物である半導体ウエーハ側にめっき電流密度の不均一を緩和する構造を設けるもの（例えば、特許文献１、特許文献２参照）や、電解めっきバンプの製造方法として電解めっき装置にめっき電流密度の集中の不均一を緩和する構造を設けるもの（例えば、特許文献３、特許文献４参照）などが提案されている。
【０００５】
以下、従来の電解めっきバンプを備えた半導体装置及びその製造方法について図面を参照しながら説明する。
【０００６】
図７（ａ）は電解めっきバンプを備えた従来の半導体装置を示す斜視図、図７（ｂ）は図７（ａ）のＢ−Ｂ'間の断面図である。
【０００７】
図７において、１は半導体素子、２は半導体素子１に形成された内部回路、３は内部回路２と電気的に接続し半導体装置１の表面に配列された半導体素子電極、４は半導体素子１の表面に形成されたパッシベーション膜、５はパッシベーション膜４に形成され半導体素子電極３上を開口する第１の開口部、６は第１の開口部５を経由して半導体素子電極３の表面に形成されたバリア層、７はバリア層６の表面に形成されためっきシード層、８はめっきシード層７上に形成された電解めっきバンプである。
【０００８】
次に上記の電解めっきバンプを備えた従来の半導体装置の製造方法について図８〜図１１を参照して説明する。
【０００９】
図８〜図１１において、１は半導体素子、２は内部回路、３は半導体素子電極、４はパッシベーション膜、５は第１の開口部、６はバリア層、７はめっきシード層、８は電解めっきバンプであり、これらは図７と同一のものである。
【００１０】
９は半導体素子１を格子状に配列した半導体ウエーハ、１０は半導体ウエーハ９上に配列された半導体素子１のチップ領域、１１は半導体ウエーハ９上のスクライブ領域である。
【００１１】
１２はめっきシード層７上に形成されためっきレジスト、１３はめっきレジスト１２の第２の開口部、１４は電解めっき電極、１５は電解めっき装置、１６は電解めっき液、１７は陽極、１８は定電流電源、１９はめっき電流、２０はめっきレジスト１２を開口して形成したダミーめっき領域である。
【００１２】
まず図８（ａ）、（ｂ）、（ｃ）に示すように半導体素子１が格子状に配列されチップ領域１０とスクライブ領域１１を有する半導体ウエーハ９を準備する。ここで図８（ａ）は半導体ウエーハ９の全体の平面図、図８（ｂ）は半導体ウエーハ９の部分拡大斜視図、図８（ｃ）は図８（ｂ）のチップ領域１０の一部の断面図を示す。
【００１３】
次に図９（ａ）に示すように半導体素子１のパッシベーション膜６上にバリア層６、めっきシード層７をスパッタリング法で形成した後、めっきレジスト１２を塗布しフォトリソ法により開口部１３を形成する。このとき、図９（ｂ）に示すように半導体ウエーハ９の周辺部分を開口して電解めっき電極１４を同時に形成する。この電解めっき電極１４は、半導体ウエーハ９の周辺部分でめっきレジスト１２が開口された部分に形成されているバリア層６およびめっきシード層７からなる。
【００１４】
次に図１０（ａ）に示すようにめっきレジスト１２を形成した半導体ウエーハ９をめっき装置１５の電解めっき液１６に浸漬し、めっきシード層７を陰極とし陽極１７に定電流電源１８から一定の電流を必要な時間だけ印加して電解めっきを行うと、めっきレジスト１２の第２の開口部１３に露出したシード層７にめっき金属が析出する。この電解めっき工程により図１０（ｂ）に示すようにめっきレジスト１２の第２の開口部１３に電解めっきバンプ８が形成される。
【００１５】
次にめっきレジスト１２を除去し、その後電解めっきバンプ８をマスクとしてめっきシード層７とバリア層６をエッチング除去し、スクライブ領域１１に沿って半導体素子１を個片化することにより図７に示す電解めっきバンプ８を備えた半導体装置を形成する。
【００１６】
一般に電解めっき法によりバンプを形成する場合、図１０（ａ）に示すように全バンプのめっきに必要なめっき電流を一括して定電流電源１８で供給するため、各電解めっきバンプ８のウエーハ上の位置によりめっき電流密度の不均一が生じ、電解めっきバンプ８の高さばらつきの原因となる。めっき電流密度の不均一性を低減する方法としては一般的には図９（ｂ）に示すようにめっき電極１４を複数個形成する方法や、ウエーハの周辺部を全てめっき電極として使用し、めっき電流密度の均一化を図る方法などがある。また、図１０（ａ）の陽極１７とウエーハ９との間に絶縁性の遮蔽板を挿入しめっき電流密度の均一化を図る方法なども従来より行われている。
【００１７】
更に、図１１（ａ）または（ｂ）に示すようにウエーハ９上でめっき電流密度が集中する箇所にダミーめっき領域２０を設けてめっき電流密度の均一化を図る方法なども提案されている。
【００１８】
以上のような方法により従来の電解めっきバンプを備える半導体装置を製造していた。
【００１９】
【特許文献１】
特開平０９−１３９３８７号公報
【特許文献２】
特開平０４−２５８１２８号公報
【特許文献３】
特許第２７４６１８号公報
【特許文献４】
特開平０３−２５４１２９号公報
【００２０】
【発明が解決しようとする課題】
しかしながら上記従来の半導体装置及びその製造方法は、いずれも半導体ウエーハ全体に対し一定のめっき電流で電解めっきを行うため、電解めっきバンプのウエーハ上の位置によりめっき電流密度の不均一が生じ、電解めっきバンプの高さばらつきが生じる。なお、上述のようにめっき電流密度の均一化を図る方法も提案されているが、いずれも半導体ウエーハ上の比較的広い面積に対してめっき電流密度の均一性を改善する方法であり、電解めっきバンプの高さばらつきを効果的に低減することができず、高さばらつきが生じるという欠点を有していた。
【００２１】
本発明は上記従来の課題を解決するもので、電解めっきバンプの高さばらつきを効果的に低減することができる半導体装置およびその製造方法を提供することを目的とする。
【００２２】
【課題を解決するための手段】
本発明の請求項１記載の半導体装置は、半導体ウエーハと、半導体ウエーハの主面上に形成された複数の半導体素子と、半導体素子上に配列された複数の電極と、半導体素子の表面を被覆保護するパッシベーション膜と、パッシベーション膜に形成され電極の上を開口する開口部と、電極の上に形成された電解めっきバンプとを備えた半導体装置であって、電解めっきバンプ形成時のめっき電流を一定に制御するために半導体ウエーハ内に形成された複数の定電流回路と、定電流回路に接続した電流入力電極と、定電流回路に接続した電流流出電極とを設けたことを特徴とする。
【００２３】
この請求項１の構成によれば、電解めっきバンプ形成時のめっき電流を一定に制御するために複数の定電流回路を設けているため、電解めっきバンプを形成する際には、半導体ウエーハ上で電解めっきバンプの形成される複数の電極のそれぞれがどれか１つの定電流回路と対応し、各定電流回路をそれと対応する１つまたは複数の電極に接続して電解めっきを行うことで、各定電流回路に接続された１つまたは複数の電極ごとにめっき電流を一定に制御することができるため、半導体ウエーハ面内でのめっき電流密度のばらつきを抑え、電解めっきバンプの高さばらつきを効果的に低減することができる。
【００２４】
また、請求項２記載の半導体装置は、請求項１記載の半導体装置において、定電流回路、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極は、個々の半導体素子ごとに設けられていることを特徴とする。
【００２５】
この請求項２の構成によれば、請求項１と同様の効果が得られ、この場合、定電流回路が半導体素子と同数設けられ、電解めっきバンプを形成する際には、各半導体素子ごとに電解めっきバンプの形成される電極が対応する１つの定電流回路と接続され、半導体素子ごとにめっき電流を一定に制御することができる。
【００２６】
また、請求項３記載の半導体装置は、請求項１記載の半導体装置において、定電流回路、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極は、個々の半導体素子に設けられた電解めっきバンプの個数より少ない複数の電解めっきバンプごとに設けられていることを特徴とする。
【００２７】
この請求項３の構成によれば、請求項１と同様の効果が得られ、この場合、定電流回路が半導体素子の個数より多く設けられ、電解めっきバンプを形成する際には、個々の半導体素子の電解めっきバンプの個数より少ない数の電解めっきバンプの形成される電極が、対応する１つの定電流回路と接続され、請求項２の場合より少ない数の電極ごとにめっき電流を一定に制御することができる。
【００２８】
また、請求項４記載の半導体装置は、請求項１記載の半導体装置において、定電流回路、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極は、個々の電解めっきバンプごとに設けられていることを特徴とする。
【００２９】
この請求項４の構成によれば、請求項１と同様の効果が得られ、この場合、定電流回路が電解めっきバンプと同数設けられ、電解めっきバンプを形成する際には、電解めっきバンプの形成される電極が対応する１つの定電流回路と接続され、電解めっきバンプの形成される電極ごとにめっき電流を一定に制御することができる。
【００３０】
また、請求項５記載の半導体装置は、請求項１、２、３または４記載の半導体装置において、定電流回路、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極は、個々の半導体素子どうしの間に形成されているスクライブ領域内に設けられていることを特徴とする。
【００３１】
この請求項５の構成によれば、請求項１、２、３または４と同様の効果が得られ、この場合、定電流回路、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極を、個々の半導体素子の面積を増大させること無く配置できるため、個々の半導体素子を小型化することができる。
【００３２】
また、請求項６記載の半導体装置は、請求項１、２、３、４または５記載の半導体装置において、定電流回路は、電解めっきバンプ形成時には半導体素子の電極と電気的に接続され、電解めっきバンプ形成後に電気的に遮断されたことを特徴とする。
【００３３】
この請求項６の構成によれば、請求項１、２、３、４または５と同様の効果が得られ、この場合、電解めっきバンプ形成後の半導体素子の電気的な動作に定電流回路が与える影響を無くすことができる。
【００３４】
また、請求項７記載の半導体装置は、請求項１、２、３、４、５または６記載の半導体装置において、半導体素子の電極と電解めっきバンプとの間に金属膜が設けられたことを特徴とする。
【００３５】
この請求項７の構成によれば、請求項１、２、３、４、５または６と同様の効果が得られ、この場合、金属膜を定電流回路を電解めっきバンプ形成時には半導体素子の電極と電気的に接続し、電解めっきバンプ形成後に電気的に遮断する電気配線として用いることで、半導体素子電極と電流入力電極との電気的な接続と遮断のためのスイッチ回路を半導体素子に内蔵することを不要にでき、半導体素子の面積が増大することが無い。更に金属膜の材質を適切に選択することで、半導体素子電極の金属の電解めっきバンプへの拡散を防止し、製品の信頼性を向上することが可能である。
【００３６】
本発明の請求項８記載の半導体装置の製造方法は、複数の定電流回路が内部に形成され、表面にパッシベーション膜が形成され、パッシベーション膜が開口された部分に、半導体素子電極、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極が形成された半導体ウエーハを準備する工程と、半導体素子電極上に開口部を持つめっきレジストを形成する工程と、電解めっき法を用いて開口部の半導体素子電極、電流入力電極、定電流回路、および電流流出電極を介してめっき電流を流すことにより、開口部の半導体素子電極上に電解めっきバンプを形成する電解めっき工程と、めっきレジストを除去する工程とを含んでいる。
【００３７】
この請求項８の製造方法によれば、半導体ウエーハに複数の定電流回路が形成され、半導体ウエーハ上で電解めっきバンプの形成される複数の半導体素子電極のそれぞれがどれか１つの定電流回路と対応し、各定電流回路をそれと対応する１つまたは複数の半導体素子電極に接続して電解めっきを行うことで、各定電流回路に接続された１つまたは複数の半導体素子電極ごとにめっき電流を一定に制御することができるため、半導体ウエーハ面内でのめっき電流密度のばらつきを抑え、形成される電解めっきバンプの高さばらつきを効果的に低減することができる。
【００３８】
本発明の請求項９記載の半導体装置の製造方法は、複数の定電流回路が内部に形成され、表面にパッシベーション膜が形成され、パッシベーション膜が開口された部分に、半導体素子電極、定電流回路に接続した電流入力電極および定電流回路に接続した電流流出電極が形成された半導体ウエーハを準備する工程と、半導体ウエーハの表面に金属膜を形成する工程と、金属膜上に所定のパターンのエッチングレジストを形成する工程と、エッチングレジストをマスクにして金属膜をエッチングすることにより、電流入力電極と電流流出電極とが定電流回路を介した経路によってのみ電気的に接続されるように少なくとも電流入力電極と電流流出電極との間の金属膜の一部を除去する第１のエッチング工程と、エッチングレジストを除去した後、半導体素子電極上の金属膜上に開口部を持つめっきレジストを形成する工程と、電解めっき法を用いて開口部の金属膜、電流入力電極、定電流回路、および電流流出電極を介してめっき電流を流すことにより、開口部の金属膜上に電解めっきバンプを形成する電解めっき工程と、めっきレジストを除去した後、電解めっきバンプをマスクとして金属膜をエッチングする第２のエッチング工程とを含んでいる。
【００３９】
この請求項９記載の製造方法によれば、請求項８記載の製造方法と同様の効果が得られる。
【００４０】
また、請求項１０記載の半導体装置の製造方法は、請求項９記載の半導体装置の製造方法において、第１のエッチング工程では半導体素子電極と電流入力電極との間が金属膜で電気的に接続されるように金属膜を残し、第２のエッチング工程により半導体素子電極と電流入力電極との間が電気的に遮断されるように金属膜を除去することを特徴とする。
【００４１】
この請求項１０記載の製造方法によれば、請求項９と同様の効果が得られ、この場合、半導体素子電極と電流入力電極との電気的な接続と遮断のためのスイッチ回路を半導体素子に内蔵することないため、半導体素子の面積が増大することが無い。また特別な製造工法を用いることなく、通常のエッチング工程により半導体素子電極と電流入力電極との電気的な接続と遮断が可能であるため、製造装置の価格が増大することが無く低コストの製品を実現することができる。
【００４２】
また、請求項１１記載の半導体装置の製造方法は、請求項９記載の半導体装置の製造方法において、第２のエッチング工程で、電解めっきバンプでマスクされていない電流入力電極および電流流出電極を溶解することなく金属膜のみを選択的にエッチングすることを特徴とする。
【００４３】
この請求項１１記載の製造方法によれば、請求項９と同様の効果が得られ、この場合、第２のエッチング工程では電流入力電極および電流流出電極が溶解されないため、金属膜のエッチングの工程管理が容易になり、製品の歩留を向上することが可能になる。
【００４４】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照しながら説明する。
【００４５】
図１（ａ）は本発明の実施の形態の半導体装置を示す斜視図、図１（ｂ）は図１（ａ）のＡ−Ａ'間の断面図である。
【００４６】
図１において、２１は半導体素子（半導体チップ）、２２は半導体素子２１に形成された内部回路、２３は内部回路２２と電気的に接続し半導体装置２１の表面に配列された半導体素子電極、２４は半導体素子２１の表面に形成されたパッシベーション膜、２６は第１の開口部を経由して半導体素子電極３の表面に形成されたバリア層、２７はバリア層２６の表面に形成されためっきシード層、２８はめっきシード層２７上に形成された電解めっきバンプである。３１は定電流回路、３２は定電流回路３１の電流入力電極、３３は定電流回路３１の電流流出電極、３４はパッシベーション膜２４に形成され半導体素子電極２３、定電流回路３１の電流入力電極３２、電流流出電極３３上を開口する第１の開口部である。
【００４７】
なお、定電流回路３１は、ここではエンハンスメント型のＭＯＳ型ＦＥＴのドレイン電流の定電流特性を利用した回路である。この他バイポーラ型トランジスタによるカレントミラー特性を利用する回路等、めっき時の電圧に依存せずかつ電流のばらつきが少なく一定の電流に制御できる回路であれば良い。
【００４８】
次に本発明の半導体装置の製造方法について図２〜図６を参照して説明する。
【００４９】
図２〜図６において、２１は半導体素子、２２は内部回路、２３は半導体素子電極、２４はパッシベーション膜、２６はバリア層、２７はめっきシード層、２８は電解めっきバンプ、３１は定電流回路、３２は電流入力電極、３３は電流流出電極、３４は第１の開口部であり、これらは上述した図１の半導体装置のものと同一である。
【００５０】
３９は半導体素子２１を格子状に配列した半導体ウエーハ、４０は半導体ウエーハ３９上に配列された半導体素子２１のチップ領域、４１は半導体ウエーハ３９上のスクライブ領域である。
【００５１】
４２はめっきシード層２７上に形成されたエッチングレジスト、４３はめっきシード層２７上に形成されためっきレジスト、４４はめっきレジスト４３の第２の開口部、４５は半導体素子電極２３と定電流回路３１の電流入力電極３２とを接続する第１の配線、４６は定電流回路３１の電流流出電極３３同士を接続する第２の配線、４７は電解めっき電極、４８は電解めっき装置、４９は電解めっき液、５０は陽極、５１はめっき電源、５２はめっき電流である。
【００５２】
まず図２（ａ）、（ｂ）、（ｃ）に示すように内部回路２２と定電流回路３１及び半導体素子電極２３と定電流回路３１の電流入力電極３２と電流流出電極３３及びパッシベーション膜２４を備える半導体素子２１が格子状に配列され、各半導体素子２１のチップ領域４０とスクライブ領域４１を有する半導体ウエーハ３９を準備する。ここで図２（ａ）は半導体ウエーハ３９の全体の平面図、図２（ｂ）は半導体ウエーハ３９の部分拡大斜視図、図２（ｃ）は図２（ｂ）のチップ領域４０の一部の断面図を示す。
【００５３】
次に図３（ａ）に示すように半導体素子２１の半導体素子電極２３、電流入力電極３２、電流流出電極３３、パッシベーション膜２４上に、バリア層２６、めっきシード層２７をスパッタリング法で形成する。
【００５４】
ここでは半導体素子電極２３、電流入力電極３２、電流流出電極３３の材料には一般的な半導体ウエーハの配線材料としてＡｌ、Ａｌ−ＳｉもしくはＡｌ−Ｓｉ−Ｃｕを用いる。また、パッシベーション膜２４としてはＳｉＮを用いる。
【００５５】
バリア層２６としては半導体素子電極２３、電流入力電極３２、電流流出電極３３及びパッシベーション膜２４との密着性及びエッチング液の選択性の観点からＴｉ−Ｗを用いる。
【００５６】
また、シード層２７の材質は電解めっき時の導電性の確保と電解めっき液４９（ここでは電解Ａｕめっき液を使用する）のめっき下地金属としての観点からＡｕを用いる。
【００５７】
次に図３（ｂ）に示すようにエッチングレジスト４２をフォトリソ法で形成し、図３（ｃ）に示すようにエッチングレジスト４２をマスクとして第１のエッチング工程を行いシード層２７とバリア層２６をパターニングする。
【００５８】
Ａｕからなるシード層２７のエッチング液としてはＴｉ−Ｗからなるバリア層２６を溶解しない溶液としてここではヨウ素とヨウ化カリウム及び酢酸からなる混合溶液を用いる。また、バリア層２６のエッチング液としてはパッシベーション膜２４及び半導体素子電極２３、電流入力電極３２、電流流出電極３３を溶解しない溶液としてここでは過酸化水素水を用いる。
【００５９】
次に図３（ｄ）に示すようにエッチングレジスト４２を剥離する。このときの半導体ウエーハ３９の部分拡大斜視図を図４（ａ）に示す。
【００６０】
ここで第１のエッチング工程により図３（ｄ）、図４（ａ）に示すように半導体素子電極２３と定電流回路３１の電流入力電極３２とを接続する第１の配線４５及び、定電流回路３１の電流流出電極３３同士を接続する第２の配線４６が形成される。第１の配線４５及び第２の配線４６はバリア層２６およびめっきシード層２７からなる。
【００６１】
また、第１のエッチング工程では、図４（ｂ）に示されるように、定電流回路３１の電流流出電極３３同士を接続する第２の配線４６を電解めっき電極４７に接続する配線部分と、電解めっき電極４７も同時に形成される。
【００６２】
次に図４（ｂ）、（ｃ）に示すようにめっきレジスト４３をフォトリソ法により形成し、第２の開口部４４を形成する。このとき、図４（ｂ）に示す電解めっき電極４７上も同時に開口する。この電解めっき電極４７は、半導体ウエーハ３９の周辺部分でめっきレジスト４３が開口された部分に形成されているバリア層２６およびめっきシード層２７からなる。
【００６３】
次に図５（ａ）に示すようにめっきレジスト４３を形成した半導体ウエーハ３９をめっき装置４８の電解めっき液４９に浸漬し、めっきシード層２７を陰極として電解めっきを行うと図５（ｂ）に示すようにめっきレジスト４３の第２の開口部４４に電解めっきバンプ２８が形成される。
【００６４】
電解めっき液４９としてここでは一般的な亜硫酸金めっき溶液を用いる。
【００６５】
このとき、個々の電解めっきバンプ２８のめっき電流５２はめっきレジスト４３の第２の開口部４４から第１の配線４５と電流入力端子３２を経由して定電流回路３１に流入するため、半導体ウエーハ３９内の電解めっきバンプ２８の配置や密度、電解めっき液４９の流量などのめっき条件に影響されることなく、めっき電流密度は個々の電解めっきバンプ毎に一定に制御される。
【００６６】
なお、ここでは電解めっきバンプ２８のめっき電流を定電流回路３１を用いて個別に制御したが、電解めっきバンプ２８の高さばらつきが許容できる範囲で複数の電解めっきバンプ２８のめっき電流をまとめて一つの定電流回路３１で制御しても良い。
【００６７】
次に図６（ａ）に示すようにめっきレジスト４３を除去し、その後図６（ｂ）に示すように電解めっきバンプ２８をマスクとしてめっきシード層２７とバリア層２６を第２のエッチング工程により除去する。
【００６８】
ここで、第１のエッチング工程と同様にシード層２７のエッチング液としてはヨウ素とヨウ化カリウム及び酢酸からなる混合溶液を用い、また、バリア層２６のエッチング液としては過酸化水素水を用いる。
【００６９】
次に半導体ウエーハ３９のスクライブ領域４１に沿って半導体素子２１を個片化することにより図６（ｃ）示すように電解めっきバンプ２８を備えた半導体装置を形成する。
【００７０】
以上のように本実施の形態によれば、各電解めっきバンプ２８ごとに定電流回路３１を設け、各々の電解めっきバンプ２８ごとにめっき電流を一定に制御することができるため、半導体ウエーハ面内でのめっき電流密度のばらつきを抑え、形成される電解めっきバンプ２８の高さばらつきを効果的に低減することができる。
【００７１】
また、先述したように、電解めっきバンプ２８の高さばらつきが許容できる範囲で複数の電解めっきバンプ２８のめっき電流をまとめて一つの定電流回路３１で制御しても良い。例えば、半導体素子２１ごとの複数の電解めっきバンプ２８のめっき電流をまとめて一つの定電流回路３１で制御しても良いし、あるいは、個々の半導体素子２１に設けられる電解めっきバンプ２８の個数より少ない複数の電解めっきバンプ２８のめっき電流をまとめて一つの定電流回路３１で制御しても良い。
【００７２】
なお、本実施の形態では、定電流回路３１、電流入力端子３２、電流流出端子３３を個々の半導体素子のチップ領域に形成したが、スクライブ領域に形成しても良いし、半導体ウエーハ３９上であればチップ領域及びスクライブ領域以外の領域に形成しても良い。
【００７３】
また、本実施の形態では、定電流回路３１と電解めっきバンプ２８とをバリア層２６およびめっきシード層２７からなる第１の配線４５で接続し、定電流回路３１と電解めっき電極４７とをバリア層２６およびめっきシード層２７からなる第２の配線４６で接続しているが、それぞれバリア層２６およびめっきシード層２７で接続する代わりに半導体素子内の配線で接続しても良い。この場合、めっき後に不要となる第１の配線４５および第２の配線４６を第２のエッチング工程で切断（除去）しているが、半導体素子内の電子的なスイッチによって切り離しても良い。
【００７４】
【発明の効果】
以上のように本発明によれば、半導体ウエーハに複数の定電流回路が設けられ、電解めっきバンプ形成時には、半導体ウエーハ上で電解めっきバンプの形成される複数の半導体素子電極のそれぞれがどれか１つの定電流回路と対応し、各定電流回路をそれと対応する１つまたは複数の半導体素子電極に接続して電解めっきを行うことで、各定電流回路に接続された１つまたは複数の半導体素子電極ごとにめっき電流を一定に制御することができるため、半導体ウエーハ面内でのめっき電流密度のばらつきを抑え、形成される電解めっきバンプの高さばらつきを効果的に低減することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態の半導体装置を示す図
【図２】本発明の実施の形態の半導体装置の製造方法を示す図
【図３】本発明の実施の形態の半導体装置の製造方法を示す図
【図４】本発明の実施の形態の半導体装置の製造方法を示す図
【図５】本発明の実施の形態の半導体装置の製造方法を示す図
【図６】本発明の実施の形態の半導体装置の製造方法を示す図
【図７】従来の半導体装置を示す図
【図８】従来の半導体装置の製造方法を示す図
【図９】従来の半導体装置の製造方法を示す図
【図１０】従来の半導体装置の製造方法を示す図
【図１１】従来の半導体装置の製造方法を示す図
【符号の説明】
１半導体素子
２内部回路
３半導体素子電極
４パッシベーション膜
５第１の開口部
６バリア層
７めっきシード層
８電解めっきバンプ
９半導体ウエーハ
１０チップ領域
１１スクライブ領域
１２めっきレジスト
１３第２の開口部
１４電解めっき電極
１５電解めっき装置
１６電解めっき液
１７陽極
１８定電流電源
１９めっき電流
２０ダミーめっき領域
２１半導体素子
２２内部回路
２３半導体素子電極
２４パッシベーション膜
２６バリア層
２７めっきシード層
２８電解めっきバンプ
３１定電流回路
３２電流入力電極
３３電流流出電極
３４第１の開口部
３９半導体ウエーハ
４０チップ領域
４１スクライブ領域
４２エッチングレジスト
４３めっきレジスト
４４第２の開口部
４５第１の配線
４６第２の配線
４７めっき電極
４８電解めっき装置
４９電解めっき液
５０陽極
５１めっき電源
５２めっき電流[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which electrolytic plating bumps are formed on electrodes of semiconductor elements used for bare chip mounting such as COG, TAB, and COF, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, along with miniaturization and high functionality of electronic devices and miniaturization of semiconductor element processes, semiconductor devices including bump electrodes used for bare chip bonding are also required to be miniaturized and narrow terminal pitches. Electrolytic plating is mainly used for narrow pitch bare chip mounting and bump electrode formation such as COG, TAB, and COF bonding.
[0003]
The variation in bump height directly affects the mounting yield of bare chip mounting. Since the variation in bump height due to the electrolytic plating method is caused by the nonuniformity of the plating current density, proposals for improving the uniformity of the plating current density have been made.
[0004]
As a method for improving the uniformity of the plating current density, a structure for mitigating the unevenness of the plating current density is provided on the side of the semiconductor wafer that is the object to be plated (for example, see Patent Document 1 and Patent Document 2), electrolysis As a method for producing a plating bump, an electrolytic plating apparatus provided with a structure that alleviates uneven concentration of plating current density (see, for example, Patent Document 3 and Patent Document 4) has been proposed.
[0005]
Hereinafter, a conventional semiconductor device including an electrolytic plating bump and a manufacturing method thereof will be described with reference to the drawings.
[0006]
FIG. 7A is a perspective view showing a conventional semiconductor device provided with an electrolytic plating bump, and FIG. 7B is a cross-sectional view taken along the line BB ′ in FIG.
[0007]
In FIG. 7, 1 is a semiconductor element, 2 is an internal circuit formed in the semiconductor element 1, 3 is a semiconductor element electrode electrically connected to the internal circuit 2 and arranged on the surface of the semiconductor device 1, and 4 is a semiconductor element 1. A passivation film 5 formed on the surface of the semiconductor element electrode 5 is formed on the passivation film 4 and opens on the semiconductor element electrode 3, and 6 is formed on the surface of the semiconductor element electrode 3 via the first opening 5. The formed barrier layer, 7 is a plating seed layer formed on the surface of the barrier layer 6, and 8 is an electrolytic plating bump formed on the plating seed layer 7.
[0008]
Next, a method for manufacturing a conventional semiconductor device having the above-described electrolytic plating bump will be described with reference to FIGS.
[0009]
8 to 11, 1 is a semiconductor element, 2 is an internal circuit, 3 is a semiconductor element electrode, 4 is a passivation film, 5 is a first opening, 6 is a barrier layer, 7 is a plating seed layer, and 8 is electrolysis. These are plating bumps, which are the same as in FIG.
[0010]
Reference numeral 9 denotes a semiconductor wafer in which the semiconductor elements 1 are arranged in a lattice pattern, 10 denotes a chip region of the semiconductor element 1 arranged on the semiconductor wafer 9, and 11 denotes a scribe region on the semiconductor wafer 9.
[0011]
12 is a plating resist formed on the plating seed layer 7, 13 is a second opening of the plating resist 12, 14 is an electroplating electrode, 15 is an electroplating apparatus, 16 is an electroplating solution, 17 is an anode, and 18 is A constant current power source, 19 is a plating current, and 20 is a dummy plating region formed by opening the plating resist 12.
[0012]
First, as shown in FIGS. 8A, 8 </ b> B, and 8 </ b> C, a semiconductor wafer 9 having semiconductor elements 1 arranged in a lattice and having a chip region 10 and a scribe region 11 is prepared. 8A is a plan view of the entire semiconductor wafer 9, FIG. 8B is a partially enlarged perspective view of the semiconductor wafer 9, and FIG. 8C is a part of the chip region 10 in FIG. 8B. FIG.
[0013]
Next, as shown in FIG. 9A, a barrier layer 6 and a plating seed layer 7 are formed on the passivation film 6 of the semiconductor element 1 by a sputtering method, and then a plating resist 12 is applied and an opening 13 is formed by a photolithography method. To do. At this time, as shown in FIG. 9B, the peripheral portion of the semiconductor wafer 9 is opened and the electrolytic plating electrode 14 is simultaneously formed. The electrolytic plating electrode 14 includes a barrier layer 6 and a plating seed layer 7 formed in a portion where the plating resist 12 is opened in the peripheral portion of the semiconductor wafer 9.
[0014]
Next, as shown in FIG. 10A, a semiconductor wafer 9 on which a plating resist 12 is formed is immersed in an electrolytic plating solution 16 of a plating apparatus 15 so that the plating seed layer 7 serves as a cathode and a constant current source 18 is connected to an anode 17 from a constant current power source 18. When electroplating is performed by applying a current for a necessary time, plating metal is deposited on the seed layer 7 exposed in the second opening 13 of the plating resist 12. By this electrolytic plating step, the electrolytic plating bump 8 is formed in the second opening 13 of the plating resist 12 as shown in FIG.
[0015]
Next, the plating resist 12 is removed, and then the plating seed layer 7 and the barrier layer 6 are removed by etching using the electrolytic plating bumps 8 as a mask, so that the semiconductor element 1 is separated into pieces along the scribe region 11 as shown in FIG. A semiconductor device provided with the electrolytic plating bumps 8 is formed.
[0016]
In general, when bumps are formed by an electrolytic plating method, as shown in FIG. 10 (a), the plating current necessary for plating all the bumps is supplied all at once by the constant current power supply 18, and therefore, on the wafer of each electrolytic plating bump 8. Depending on the position, the plating current density becomes non-uniform, which causes variations in the height of the electrolytic plating bumps 8. As a method for reducing the non-uniformity of the plating current density, generally, a method of forming a plurality of plating electrodes 14 as shown in FIG. 9B, or using all the peripheral portions of the wafer as plating electrodes, There is a method of making the current density uniform. In addition, a method of making the plating current density uniform by inserting an insulating shielding plate between the anode 17 and the wafer 9 in FIG.
[0017]
Furthermore, as shown in FIG. 11 (a) or (b), a method has been proposed in which a dummy plating region 20 is provided at a location where the plating current density is concentrated on the wafer 9 to make the plating current density uniform.
[0018]
The semiconductor device provided with the conventional electrolytic plating bump was manufactured by the above methods.
[0019]
[Patent Document 1]
JP 09-139387 A
[Patent Document 2]
JP 04-258128 A
[Patent Document 3]
Japanese Patent No. 274618
[Patent Document 4]
Japanese Patent Laid-Open No. 03-254129
[0020]
[Problems to be solved by the invention]
However, since the conventional semiconductor device and the manufacturing method thereof both perform electrolytic plating with a constant plating current on the entire semiconductor wafer, the plating current density is non-uniform depending on the position of the electrolytic plating bump on the wafer. Bump height variation occurs. As described above, methods for making the plating current density uniform have also been proposed. However, all of these are methods for improving the uniformity of the plating current density over a relatively large area on the semiconductor wafer. The bump height variation cannot be effectively reduced, and the height variation occurs.
[0021]
SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can effectively reduce variation in height of electrolytic plating bumps.
[0022]
[Means for Solving the Problems]
A semiconductor device according to claim 1 of the present invention covers a semiconductor wafer, a plurality of semiconductor elements formed on the main surface of the semiconductor wafer, a plurality of electrodes arranged on the semiconductor element, and a surface of the semiconductor element A semiconductor device comprising a passivation film to be protected, an opening formed on the passivation film and opening above the electrode, and an electrolytic plating bump formed on the electrode, wherein the plating current at the time of forming the electrolytic plating bump is A plurality of constant current circuits formed in the semiconductor wafer for constant control, a current input electrode connected to the constant current circuit, and a current outflow electrode connected to the constant current circuit are provided.
[0023]
According to the first aspect of the present invention, since a plurality of constant current circuits are provided in order to control the plating current at the time of forming the electrolytic plating bumps constant, when forming the electrolytic plating bumps, the semiconductor wafer is formed on the semiconductor wafer. Each of the plurality of electrodes on which the electroplating bumps are formed corresponds to any one constant current circuit, and each constant current circuit is connected to one or more corresponding electrodes to perform electroplating, Because the plating current can be controlled to be constant for each electrode or electrodes connected to the constant current circuit, variations in the plating current density within the semiconductor wafer surface are suppressed, and variations in the height of the electrolytic plating bumps are effective. Can be reduced.
[0024]
The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the constant current circuit, the current input electrode connected to the constant current circuit, and the current outflow electrode connected to the constant current circuit are provided for each individual semiconductor element. It is provided in.
[0025]
According to the configuration of the second aspect, the same effect as that of the first aspect can be obtained. In this case, the same number of constant current circuits as that of the semiconductor elements are provided. The electrode on which the electrolytic plating bump is formed is connected to a corresponding constant current circuit, and the plating current can be controlled to be constant for each semiconductor element.
[0026]
The semiconductor device according to claim 3 is the semiconductor device according to claim 1, wherein the constant current circuit, the current input electrode connected to the constant current circuit, and the current outflow electrode connected to the constant current circuit are connected to each semiconductor element. It is characterized in that it is provided for each of a plurality of electrolytic plating bumps which is smaller than the number of electrolytic plating bumps provided.
[0027]
According to the configuration of claim 3, the same effect as in claim 1 can be obtained. In this case, the constant current circuit is provided more than the number of semiconductor elements. An electrode on which a smaller number of electrolytic plating bumps than the number of electrolytic plating bumps of the element is formed is connected to one corresponding constant current circuit, and the plating current is controlled to be constant for each of the smaller number of electrodes than in the case of claim 2. can do.
[0028]
According to a fourth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the constant current circuit, the current input electrode connected to the constant current circuit, and the current outflow electrode connected to the constant current circuit are individually electroplated bumps. It is provided for each.
[0029]
According to the configuration of the fourth aspect, the same effect as in the first aspect can be obtained. In this case, the same number of constant current circuits as the electrolytic plating bumps are provided. The formed electrode is connected to a corresponding constant current circuit, and the plating current can be controlled to be constant for each electrode on which the electrolytic plating bump is formed.
[0030]
The semiconductor device according to claim 5 is the semiconductor device according to claim 1, 2, 3 or 4, wherein the constant current circuit, the current input electrode connected to the constant current circuit, and the current outflow electrode connected to the constant current circuit are The semiconductor device is characterized in that it is provided in a scribe region formed between individual semiconductor elements.
[0031]
According to the configuration of the fifth aspect, the same effect as in the first, second, third or fourth aspect can be obtained. In this case, the constant current circuit, the current input electrode connected to the constant current circuit, and the constant current circuit are connected. Since the current outflow electrode can be arranged without increasing the area of each semiconductor element, the size of each semiconductor element can be reduced.
[0032]
According to a sixth aspect of the present invention, in the semiconductor device of the first, second, third, fourth, or fifth aspect, the constant current circuit is electrically connected to the electrode of the semiconductor element when the electrolytic plating bump is formed. It is characterized by being electrically cut off after the formation of the plating bump.
[0033]
According to the configuration of the sixth aspect, the same effect as that of the first, second, third, fourth or fifth aspect can be obtained. In this case, the constant current circuit is used for the electrical operation of the semiconductor element after the formation of the electrolytic plating bump. It is possible to eliminate the influence.
[0034]
The semiconductor device according to claim 7 is the semiconductor device according to claim 1, wherein a metal film is provided between the electrode of the semiconductor element and the electrolytic plating bump. Features.
[0035]
According to the configuration of the seventh aspect, the same effect as that of the first, second, third, fourth, fifth or sixth aspect can be obtained. In this case, the electrode of the semiconductor element is formed when the constant current circuit is formed on the metal film and the electrolytic plating bump is formed. A switch circuit for electrical connection and disconnection between the semiconductor element electrode and the current input electrode is built in the semiconductor element by using as an electrical wiring that is electrically connected to and electrically disconnected after the formation of the electrolytic plating bump. This can be eliminated, and the area of the semiconductor element does not increase. Further, by appropriately selecting the material of the metal film, it is possible to prevent the diffusion of the metal of the semiconductor element electrode to the electrolytic plating bump, and to improve the reliability of the product.
[0036]
According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of constant current circuits are formed inside, a passivation film is formed on a surface, and a semiconductor element electrode and a constant current circuit are formed at a portion where the passivation film is opened. A step of preparing a semiconductor wafer on which a current input electrode connected to the substrate and a current outflow electrode connected to a constant current circuit are formed; a step of forming a plating resist having an opening on the semiconductor element electrode; and an electrolytic plating method An electroplating step of forming an electroplating bump on the semiconductor element electrode in the opening by flowing a plating current through the semiconductor element electrode in the opening, the current input electrode, the constant current circuit, and the current outflow electrode; And a step of removing the resist.
[0037]
According to the manufacturing method of claim 8, a plurality of constant current circuits are formed on the semiconductor wafer, and each of the plurality of semiconductor element electrodes on which the electrolytic plating bumps are formed on the semiconductor wafer is one of the constant current circuits. Correspondingly, by carrying out electrolytic plating by connecting each constant current circuit to one or more semiconductor element electrodes corresponding thereto, the plating current for each one or more semiconductor element electrodes connected to each constant current circuit Therefore, variation in plating current density in the semiconductor wafer surface can be suppressed, and variation in the height of the formed electrolytic plating bumps can be effectively reduced.
[0038]
According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of constant current circuits are formed therein, a passivation film is formed on a surface, and a semiconductor element electrode and a constant current circuit are formed at a portion where the passivation film is opened. A step of preparing a semiconductor wafer having a current input electrode connected to the substrate and a current outflow electrode connected to a constant current circuit; a step of forming a metal film on the surface of the semiconductor wafer; and etching a predetermined pattern on the metal film At least current input so that the current input electrode and the current outflow electrode are electrically connected only by a path through the constant current circuit by etching the metal film using the resist forming process and the etching resist as a mask. A first etching step for removing a part of the metal film between the electrode and the current outflow electrode, and after removing the etching resist A step of forming a plating resist having an opening on a metal film on a semiconductor element electrode, and a plating current through the metal film, the current input electrode, the constant current circuit, and the current outflow electrode using an electrolytic plating method An electroplating step for forming an electroplating bump on the metal film in the opening, and a second etching step for etching the metal film using the electroplating bump as a mask after removing the plating resist. Yes.
[0039]
According to the manufacturing method of the ninth aspect, the same effect as the manufacturing method of the eighth aspect can be obtained.
[0040]
The method for manufacturing a semiconductor device according to claim 10 is the method for manufacturing a semiconductor device according to claim 9, wherein in the first etching step, the semiconductor element electrode and the current input electrode are electrically connected by a metal film. The metal film is left as it is, and the metal film is removed by the second etching process so that the semiconductor element electrode and the current input electrode are electrically disconnected.
[0041]
According to the manufacturing method of the tenth aspect, the same effect as in the ninth aspect can be obtained. In this case, a switch circuit for electrically connecting and disconnecting the semiconductor element electrode and the current input electrode is provided in the semiconductor element. Since it is not built in, the area of the semiconductor element does not increase. In addition, it is possible to electrically connect and disconnect the semiconductor element electrode and the current input electrode by a normal etching process without using a special manufacturing method. Can be realized.
[0042]
The method for manufacturing a semiconductor device according to claim 11 is the method for manufacturing a semiconductor device according to claim 9, wherein in the second etching step, the current input electrode and the current outflow electrode not masked by the electrolytic plating bump are dissolved. It is characterized in that only the metal film is selectively etched without doing so.
[0043]
According to the manufacturing method of the eleventh aspect, the same effect as that of the ninth aspect can be obtained. In this case, the current input electrode and the current outflow electrode are not dissolved in the second etching step. Management becomes easy and the yield of products can be improved.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0045]
FIG. 1A is a perspective view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along a line AA ′ in FIG.
[0046]
In FIG. 1, 21 is a semiconductor element (semiconductor chip), 22 is an internal circuit formed in the semiconductor element 21, 23 is a semiconductor element electrode electrically connected to the internal circuit 22 and arranged on the surface of the semiconductor device 21, 24. Is a passivation film formed on the surface of the semiconductor element 21, 26 is a barrier layer formed on the surface of the semiconductor element electrode 3 via the first opening, and 27 is a plating seed formed on the surface of the barrier layer 26. Layers 28 are electrolytic plating bumps formed on the plating seed layer 27. Reference numeral 31 denotes a constant current circuit, 32 denotes a current input electrode of the constant current circuit 31, 33 denotes a current outflow electrode of the constant current circuit 31, 34 denotes a semiconductor element electrode 23 formed on the passivation film 24, and a current input electrode 32 of the constant current circuit 31 This is a first opening that opens on the current outflow electrode 33.
[0047]
Here, the constant current circuit 31 is a circuit using the constant current characteristic of the drain current of the enhancement type MOS FET. In addition, any circuit that does not depend on the voltage at the time of plating and that can be controlled to a constant current with little variation in current, such as a circuit that uses a current mirror characteristic of a bipolar transistor, may be used.
[0048]
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
[0049]
2 to 6, 21 is a semiconductor element, 22 is an internal circuit, 23 is a semiconductor element electrode, 24 is a passivation film, 26 is a barrier layer, 27 is a plating seed layer, 28 is an electrolytic plating bump, and 31 is a constant current circuit. 32 is a current input electrode, 33 is a current outflow electrode, and 34 is a first opening, which are the same as those of the semiconductor device of FIG.
[0050]
Reference numeral 39 denotes a semiconductor wafer in which the semiconductor elements 21 are arranged in a lattice pattern, reference numeral 40 denotes a chip region of the semiconductor elements 21 arranged on the semiconductor wafer 39, and reference numeral 41 denotes a scribe area on the semiconductor wafer 39.
[0051]
42 is an etching resist formed on the plating seed layer 27, 43 is a plating resist formed on the plating seed layer 27, 44 is a second opening of the plating resist 43, and 45 is a semiconductor element electrode 23 and a constant current circuit. 31 is a first wiring that connects the current input electrode 32, 46 is a second wiring that connects the current outflow electrodes 33 of the constant current circuit 31, 47 is an electroplating electrode, 48 is an electroplating apparatus, and 49 is an electrolysis device. A plating solution, 50 is an anode, 51 is a plating power source, and 52 is a plating current.
[0052]
First, as shown in FIGS. 2A, 2 </ b> B, and 2 </ b> C, the internal circuit 22, the constant current circuit 31, the semiconductor element electrode 23, the current input electrode 32, the current outflow electrode 33, and the passivation film 24 of the constant current circuit 31. A semiconductor wafer 39 having a chip region 40 and a scribe region 41 of each semiconductor element 21 is prepared. 2A is a plan view of the entire semiconductor wafer 39, FIG. 2B is a partially enlarged perspective view of the semiconductor wafer 39, and FIG. 2C is a part of the chip region 40 of FIG. 2B. FIG.
[0053]
Next, as shown in FIG. 3A, a barrier layer 26 and a plating seed layer 27 are formed on the semiconductor element electrode 23, the current input electrode 32, the current outflow electrode 33, and the passivation film 24 of the semiconductor element 21 by sputtering. .
[0054]
Here, as a material for the semiconductor element electrode 23, the current input electrode 32, and the current outflow electrode 33, Al, Al—Si, or Al—Si—Cu is used as a wiring material of a general semiconductor wafer. Further, SiN is used as the passivation film 24.
[0055]
As the barrier layer 26, Ti—W is used from the viewpoint of adhesion to the semiconductor element electrode 23, the current input electrode 32, the current outflow electrode 33, and the passivation film 24 and the selectivity of the etching solution.
[0056]
In addition, Au is used as the material of the seed layer 27 from the viewpoint of ensuring conductivity during electrolytic plating and as a plating base metal of the electrolytic plating solution 49 (here, electrolytic Au plating solution is used).
[0057]
Next, as shown in FIG. 3B, an etching resist 42 is formed by a photolithography method, and as shown in FIG. 3C, a first etching process is performed using the etching resist 42 as a mask to perform seed layer 27 and barrier layer 26. Is patterned.
[0058]
As the etching solution for the seed layer 27 made of Au, a mixed solution made of iodine, potassium iodide, and acetic acid is used here as a solution that does not dissolve the barrier layer 26 made of Ti—W. As the etchant for the barrier layer 26, hydrogen peroxide is used here as a solution that does not dissolve the passivation film 24, the semiconductor element electrode 23, the current input electrode 32, and the current outflow electrode 33.
[0059]
Next, as shown in FIG. 3D, the etching resist 42 is peeled off. FIG. 4A shows a partially enlarged perspective view of the semiconductor wafer 39 at this time.
[0060]
Here, as shown in FIG. 3 (d) and FIG. 4 (a), the first wiring 45 for connecting the semiconductor element electrode 23 and the current input electrode 32 of the constant current circuit 31 and the constant current are formed by the first etching step. A second wiring 46 that connects the current outflow electrodes 33 of the circuit 31 is formed. The first wiring 45 and the second wiring 46 include a barrier layer 26 and a plating seed layer 27.
[0061]
In the first etching step, as shown in FIG. 4B, a wiring portion that connects the second wiring 46 that connects the current outflow electrodes 33 of the constant current circuit 31 to the electrolytic plating electrode 47, and The electrolytic plating electrode 47 is also formed at the same time.
[0062]
Next, as shown in FIGS. 4B and 4C, a plating resist 43 is formed by photolithography, and a second opening 44 is formed. At this time, the electroplating electrode 47 shown in FIG. The electrolytic plating electrode 47 includes a barrier layer 26 and a plating seed layer 27 that are formed in a peripheral portion of the semiconductor wafer 39 in a portion where the plating resist 43 is opened.
[0063]
Next, as shown in FIG. 5A, when a semiconductor wafer 39 on which a plating resist 43 is formed is immersed in an electrolytic plating solution 49 of a plating apparatus 48 and electrolytic plating is performed using the plating seed layer 27 as a cathode, FIG. As shown in FIG. 5, the electrolytic plating bump 28 is formed in the second opening 44 of the plating resist 43.
[0064]
Here, a general gold sulfite plating solution is used as the electrolytic plating solution 49.
[0065]
At this time, since the plating current 52 of each electrolytic plating bump 28 flows from the second opening 44 of the plating resist 43 into the constant current circuit 31 via the first wiring 45 and the current input terminal 32, the semiconductor wafer The plating current density is controlled to be constant for each electroplating bump without being affected by the plating conditions such as the arrangement and density of the electroplating bump 28 in 39 and the flow rate of the electroplating solution 49.
[0066]
Here, the plating currents of the electrolytic plating bumps 28 are individually controlled using the constant current circuit 31. However, the plating currents of the plurality of electrolytic plating bumps 28 are collected within a range in which the height variation of the electrolytic plating bumps 28 is allowable. It may be controlled by one constant current circuit 31.
[0067]
Next, as shown in FIG. 6A, the plating resist 43 is removed, and then, as shown in FIG. 6B, the plating seed layer 27 and the barrier layer 26 are formed by the second etching process using the electrolytic plating bump 28 as a mask. Remove.
[0068]
Here, as in the first etching step, a mixed solution of iodine, potassium iodide, and acetic acid is used as the etchant for the seed layer 27, and hydrogen peroxide is used as the etchant for the barrier layer 26.
[0069]
Next, by separating the semiconductor element 21 along the scribe region 41 of the semiconductor wafer 39, a semiconductor device provided with the electrolytic plating bumps 28 is formed as shown in FIG.
[0070]
As described above, according to the present embodiment, the constant current circuit 31 is provided for each electrolytic plating bump 28, and the plating current can be controlled to be constant for each electrolytic plating bump 28. It is possible to suppress variations in the plating current density at, and to effectively reduce variations in the height of the electrolytic plating bumps 28 to be formed.
[0071]
Further, as described above, the plating currents of the plurality of electrolytic plating bumps 28 may be collectively controlled by one constant current circuit 31 within a range in which the variation in height of the electrolytic plating bumps 28 is allowable. For example, the plating currents of a plurality of electrolytic plating bumps 28 for each semiconductor element 21 may be collectively controlled by one constant current circuit 31, or may be determined based on the number of electrolytic plating bumps 28 provided on each semiconductor element 21. The plating currents of a small number of electrolytic plating bumps 28 may be collectively controlled by one constant current circuit 31.
[0072]
In the present embodiment, the constant current circuit 31, the current input terminal 32, and the current outflow terminal 33 are formed in the chip region of each semiconductor element, but may be formed in the scribe region or on the semiconductor wafer 39. If present, it may be formed in an area other than the chip area and the scribe area.
[0073]
In the present embodiment, the constant current circuit 31 and the electrolytic plating bump 28 are connected by the first wiring 45 including the barrier layer 26 and the plating seed layer 27, and the constant current circuit 31 and the electrolytic plating electrode 47 are connected to the barrier. Although the connection is made by the second wiring 46 composed of the layer 26 and the plating seed layer 27, they may be connected by wiring in the semiconductor element instead of being connected by the barrier layer 26 and the plating seed layer 27, respectively. In this case, the first wiring 45 and the second wiring 46 that are not required after plating are cut (removed) in the second etching step, but may be separated by an electronic switch in the semiconductor element.
[0074]
【The invention's effect】
As described above, according to the present invention, a plurality of constant current circuits are provided on a semiconductor wafer, and at the time of forming an electroplating bump, one of each of a plurality of semiconductor element electrodes on which the electroplating bump is formed on the semiconductor wafer. One or a plurality of semiconductor elements connected to each constant current circuit by performing electroplating by connecting each constant current circuit to one or a plurality of semiconductor element electrodes corresponding to each constant current circuit Since the plating current can be controlled to be constant for each electrode, variations in the plating current density in the semiconductor wafer surface can be suppressed, and variations in the height of the formed electrolytic plating bumps can be effectively reduced.
[Brief description of the drawings]
FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 3 is a view showing a method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 4 is a diagram showing a method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 5 is a diagram showing a method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 6 is a diagram showing a method for manufacturing the semiconductor device according to the embodiment of the present invention.
FIG. 7 shows a conventional semiconductor device.
FIG. 8 is a view showing a conventional method for manufacturing a semiconductor device.
FIG. 9 is a view showing a conventional method for manufacturing a semiconductor device.
FIG. 10 is a view showing a conventional method for manufacturing a semiconductor device.
FIG. 11 is a view showing a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
1 Semiconductor device
2 Internal circuit
3 Semiconductor device electrodes
4 Passivation film
5 First opening
6 Barrier layer
7 Plating seed layer
8 Electrolytic plating bump
9 Semiconductor wafer
10 chip area
11 Scribe area
12 Plating resist
13 Second opening
14 Electroplating electrode
15 Electrolytic plating equipment
16 Electrolytic plating solution
17 Anode
18 Constant current power supply
19 Plating current
20 Dummy plating area
21 Semiconductor elements
22 Internal circuit
23 Semiconductor device electrodes
24 Passivation film
26 Barrier layer
27 Plating seed layer
28 Electrolytic plating bump
31 Constant current circuit
32 Current input electrode
33 Current outflow electrode
34 First opening
39 Semiconductor wafer
40 chip area
41 Scribe area
42 Etching resist
43 Plating resist
44 Second opening
45 First wiring
46 Second wiring
47 Plating electrode
48 Electrolytic plating equipment
49 Electrolytic plating solution
50 anode
51 Plating power supply
52 Plating current

Claims

Semiconductor wafer, a plurality of semiconductor elements formed on the main surface of the semiconductor wafer, a plurality of electrodes arranged on the semiconductor element, a passivation film for covering and protecting the surface of the semiconductor element, and the passivation film A semiconductor device comprising an opening formed on the electrode and an electroplating bump formed on the electrode,
A plurality of constant current circuits formed in the semiconductor wafer, a current input electrode connected to the constant current circuit, and a connection to the constant current circuit in order to control the plating current at the time of forming the electrolytic plating bumps constant. A semiconductor device comprising a current outflow electrode.

2. The semiconductor device according to claim 1, wherein a constant current circuit, a current input electrode connected to the constant current circuit, and a current outflow electrode connected to the constant current circuit are provided for each individual semiconductor element.

A constant current circuit, a current input electrode connected to the constant current circuit, and a current outflow electrode connected to the constant current circuit are provided for each of a plurality of electrolytic plating bumps smaller than the number of electrolytic plating bumps provided for each semiconductor element. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed.

2. The semiconductor device according to claim 1, wherein a constant current circuit, a current input electrode connected to the constant current circuit, and a current outflow electrode connected to the constant current circuit are provided for each electrolytic plating bump. .

A constant current circuit, a current input electrode connected to the constant current circuit, and a current outflow electrode connected to the constant current circuit are provided in a scribe region formed between individual semiconductor elements. The semiconductor device according to any one of claims 1 to 4 .

Constant current circuit, at the time of electrolytic plating bump formation is connected electrode in electrical semiconductor device, according to any one of claims 1 to 5, characterized in that said electrically cut off after the electroless plating bump formation Semiconductor device.

The semiconductor device according to any one of claims 1 6, characterized in that the metal film is provided between the electrode and the electrolytic plating bumps of the semiconductor device.

A plurality of constant current circuits are formed inside, a passivation film is formed on the surface, a semiconductor element electrode, a current input electrode connected to the constant current circuit, and a connection to the constant current circuit are formed in the portion where the passivation film is opened A step of preparing a semiconductor wafer having a current outflow electrode formed thereon;
Forming a plating resist having an opening on the semiconductor element electrode;
By applying a plating current through the semiconductor element electrode, the current input electrode, the constant current circuit, and the current outflow electrode of the opening using an electrolytic plating method, on the semiconductor element electrode of the opening An electroplating process for forming an electroplating bump;
And a step of removing the plating resist.

A plurality of constant current circuits are formed inside, a passivation film is formed on the surface, a semiconductor element electrode, a current input electrode connected to the constant current circuit, and a connection to the constant current circuit are formed in the portion where the passivation film is opened A step of preparing a semiconductor wafer having a current outflow electrode formed thereon;
Forming a metal film on the surface of the semiconductor wafer;
Forming an etching resist having a predetermined pattern on the metal film;
By etching the metal film using the etching resist as a mask, the current input electrode and the current outflow electrode are at least electrically connected only by a path through the constant current circuit. A first etching step of removing a part of the metal film between the electrode and the current outflow electrode;
Forming a plating resist having an opening on the metal film on the semiconductor element electrode after removing the etching resist;
Electrolytic plating is performed on the metal film in the opening by flowing a plating current through the metal film in the opening, the current input electrode, the constant current circuit, and the current outflow electrode using an electrolytic plating method. An electroplating process for forming bumps;
And a second etching step of etching the metal film using the electrolytic plating bumps as a mask after removing the plating resist.

In the first etching step, the metal film is left so that the semiconductor element electrode and the current input electrode are electrically connected by a metal film, and in the second etching process, the semiconductor element electrode and the current input electrode are The method of manufacturing a semiconductor device according to claim 9, wherein the metal film is removed so that a gap is electrically cut off.

10. The method of manufacturing a semiconductor device according to claim 9, wherein in the second etching step, only the metal film is selectively etched without dissolving the current input electrode and the current outflow electrode not masked by the electrolytic plating bump. Method.