JP3956979B2 - Development tools for large-scale integrated circuits - Google Patents

Description

  The present invention relates to a large-scale integrated circuit development method and development tool, and in particular, performs floor planning, which is a part of circuit architecture examination and implementation design, and performs logic design / verification, logic synthesis and implementation design. The present invention relates to a large-scale integrated circuit development method for performing concurrent layout and timing verification, and a large-scale integrated circuit development tool for developing a large-scale integrated circuit by the large-scale integrated circuit development method.

  There is a strong demand for higher functionality, higher speed processing, and miniaturization of communication devices and information processing devices, and in order to realize them, it is essential to implement circuits using large-scale integrated circuits.

  In particular, in communication devices, a large-scale integrated circuit called an ASIC (Application Specific Integrated Circuit) for realizing a function unique to the communication device is often applied, and the ASIC is rapidly increasing in scale. It has entered the era of the so-called mega gate ASIC.

  Of course, the large scale of the integrated circuit makes the design difficult, so that the design number is inevitably prolonged in order to ensure the design quality.

  However, on the other hand, there is an increasing demand for shorter delivery times for communication devices. Therefore, even if a communication device manufacturer develops and applies an ASIC, a dedicated integrated circuit manufacturer develops and supplies an ASIC, or a software vendor develops an integrated circuit, it maintains market competitiveness. For this purpose, development with a short delivery time is essential.

  Moreover, the ASIC realizes functions unique to communication devices, and it is often impossible to apply a standard circuit configuration. Therefore, it is necessary to design with a new configuration every time a new communication device is developed. As the amount of work increases at a higher rate than the rate of ASIC expansion, the number of personnel required for development has also increased significantly. Even in such an ASIC development environment, the reliability of the developed product must be maintained.

  In this way, it is indispensable for both communication equipment manufacturers, integrated circuit manufacturers, and software vendors to develop ASICs while satisfying the contradictory demands of rapid delivery and maintaining the reliability of the developed products. Only the manufacturers that have solved this problem can overcome the tough competition.

  Currently, large-scale integrated circuits such as ASICs are mainly developed by a method that combines functional description language design and logic synthesis by VHDL, Verilog, etc., but the whole process of developing such large-scale integrated circuits Can be roughly divided into the following steps.

That is,
a. Circuit architecture study to examine circuit structure b. RTL (Register Transfer Level) design by function description language and logic design / verification for its verification c. Logic synthesis that synthesizes and optimizes a circuit d. This is the four steps of implementation design that performs floor planning, layout, timing adjustment and verification.

  FIG. 20 shows a flow of conventional large-scale integrated circuit development.

  Here, a solid line with a thick arrow in FIG. 20 indicates a flow of design in the forward direction, and a thin solid line with an arrow indicates reworking of the design.

  As clearly shown in FIG. 20, in the conventional large-scale integrated circuit development, the circuit architecture examination, logic design / verification, logic synthesis, and implementation design are serial in time series. If the process is not completed, the process does not move to the subsequent process. In this sense, the development process is simple if the development can be completed with only forward work in time.

  FIG. 21 shows the development procedure of the conventional large-scale integrated circuit in a little more detail. Here, a solid line with a thick arrow indicates the flow of development, and a broken line with a thin arrow indicates the flow of data.

  Hereinafter, the development procedure of the conventional large-scale integrated circuit will be described along the reference numerals assigned to the respective development stages in FIG.

  S151. Based on the required specifications and required examination items, the circuit structure is examined, the entire circuit is divided into functional blocks, and the required verification items are broken down into blocks.

  S152. The circuit is designed using a function description language for each block divided in the circuit architecture study in step S151 and an RTL (Registor Transfer Level) list is output, and the function confirmation item of the target block is divided in the circuit architecture study in step S151. Subdivide according to the verification items, and further add block-specific function confirmation items to the verification items.

  At this stage, a draft of the inter-block netlist, which is connection information between the terminals of the block and between the terminals of the block and the terminals of the chip of the large-scale integrated circuit, is generated.

  S153. Using the RTL list and the verification items, logic verification is performed in units of blocks.

  S154. It is determined whether or not there is a problem in the logic verification result. If it is determined that there is a problem (Yes), the process returns to the RTL design in step S152 to update the circuit design, and steps S152 and S153 are repeated until it is determined that there is no problem.

  S155. If it is determined in step S154 that there is no problem (No), it is determined whether RTL design and logic verification have been completed for all blocks. If it is determined that the determination result is not completed for all blocks (No), the process returns to the RTL design in step S152, and steps S152 and S153 are performed until it is determined that all blocks are completed.

  S156. If the determination result in step S156 is the end of all blocks (Yes), logical synthesis is performed using the RTL list that is the result of step S152, and the inter-block netlist that has been drafted in the RTL design of step S152 And the entire net list is generated by inserting the logic synthesis result into the inter-block net list.

  S157. It is determined whether there is a problem in the logic synthesis. If the result of this determination is that there is a problem (Yes), the design is updated by returning to the RTL design in step S152 or the circuit architecture consideration in step S151, and the logic synthesis is repeated until it is determined that there is no problem.

  S158. If the determination result in step S157 is no problem (No), chip floor planning is performed based on the net list that is the output of logic synthesis in step S156.

  S159. It is determined whether there is a problem with the result of the floor planning. If this judgment result is problematic (Yes), the process returns to the logic synthesis in step S156, the RTL design in step S152, or the circuit architecture examination in step S151, and the design is updated until the judgment result shows no problem.

  S160. If the determination result in step S158 is no problem (No), layout is performed and an SDF (Standard Delay File) is generated.

  S161. Timing verification is performed based on the SDF output from step 160.

  S162. It is determined whether or not there is a problem with the result of the timing verification. If this judgment result is problematic (Yes), the process returns to the floor planning in step S158, the logic synthesis in step S156, or the circuit architecture examination in step S151, and the design is updated until this judgment result is satisfactory.

  If the result of the determination is no problem (No), the design is terminated.

  Note that lowercase alphabet letters indicating the division of the design process are shown in FIG. That is, step S151 is the circuit architecture study a, steps S152 to S155 are the logic design / verification b, steps S156 and S157 are the logic synthesis c, and steps S158 and later are the implementation design d. It is.

  That is, in the development procedure of FIG. 21, as shown in the flow of the development process of FIG. 20, circuit architecture examination, logic design / verification, logic synthesis, and implementation design are performed serially.

  However, in the development of a large-scale integrated circuit, each design step rarely ends once, and specification changes, design errors, timing errors, etc. occur. For this reason, it often happens that the subsequent design process returns to the previous design process.

For example, if it is determined in step S154 in FIG. 21 that there is a problem in the logic verification result (Yes), the RTL design in step S152 is performed again.
However, this is an integrated process of logic design and logic verification, so the design process will not be confused.

  The problem is the return from the later process to the previous process.

  That is, after the logic synthesis in step S156, if it is determined in step S157 that there is a problem in the logic synthesis (Yes), the process returns to the RTL design in step S152 or the circuit architecture examination in step S151, and the floor in step S158. If it is determined in step S159 after planning that there is a problem in floor planning (Yes), the process returns to the logic synthesis in step S156, the RTL design in step S152, or the circuit architecture examination in step S151, and the timing verification in step S161. When it is determined that there is a problem in the timing verification (Yes) in the subsequent step S162, the process returns to the floor planning in step S157, the logic synthesis in step S155, or the circuit architecture examination in step S151. And such a return is repeated many times.

  In FIG. 20, a solid line with an arrow is drawn at a place where the above-mentioned reversal can occur.

  These backtracks do not simply repeat the completed trapping process again, but there are often contradictions in the cause of each backtracking, so if you go back between specific processes and update the design, it will also go back between other processes. It will be necessary, and it will lead to the situation that the work for development does not converge easily.

  In such a case, the efficiency of large-scale integrated circuit development is significantly reduced, and the development process is extremely long. As a result, even a communication device manufacturer, a large-scale integrated circuit manufacturer, or a software vendor cannot avoid the decline in competitiveness.

Up to now, the performance of CAD machines has been improved, that is, the processing capacity of CAD machines such as servers has been increased. The speed of CAD tools has been increased, that is, the processing speed of software installed in CAD tools has increased (for example, (Serial processing is changed to parallel processing to increase processing speed, etc.)
Efforts have been made to prevent a decrease in development efficiency and prolongation of the process by reducing errors due to repeated checks, etc., but with the further increase in scale of large-scale integrated circuits, the performance of CAD machines has increased, It has become almost impossible to prevent a decrease in development efficiency and prolongation of the process only by speeding up and reducing errors by repeated checks.

  In view of such problems, the present invention develops a large-scale integrated circuit by developing a large-scale integrated circuit that performs circuit architecture examination, logic design / verification, logic synthesis, and implementation design concurrently, and the large-scale integrated circuit development method. An object of the present invention is to provide a large-scale integrated circuit development tool for improving the efficiency of large-scale integrated circuit development and to improve the quality of the developed large-scale integrated circuit.

  FIG. 1 shows the flow of the development process of the large-scale integrated circuit of the present invention. Here, a solid line with a thick arrow in FIG. 1 indicates a forward process, and a thin solid line with an arrow and a thin broken line with an arrow indicate a backward step.

As clearly shown in FIG. 1, the features of the present invention are:
The floor planning, which is one step of the circuit architecture study and the implementation design, is performed in parallel, and the floor planning is finalized when the circuit architecture study is completed.
Design conditions and design data generated in the circuit architecture review process and floor planning process are used as data that is commonly used in subsequent logic design / verification (RTL design, logic verification), logic synthesis, and layout processes. This is to prevent contradiction in design conditions and design data between the processes.

  FIG. 2 is a principle procedure for development of a large-scale integrated circuit according to the present invention, and shows a flow of a development process of the large-scale integrated circuit according to the present invention in some detail. In FIG. 2, a solid line with a thick arrow indicates a development flow, and a thin broken line with an arrow indicates a data flow.

  In the following, the principle procedure for developing a large-scale integrated circuit according to the present invention will be described along the reference numerals assigned to the respective development stages in FIG.

  S1. Dividing a large-scale integrated circuit into functional blocks using the required specifications and required verification items as input, and estimating and setting the following items (a) to (h) for each block, and examining the circuit structure .

(A) Number of flip-flops for determining whether the block can be accommodated (b) Chip input / output port information and block input / output port information (c) Realization scale (d) For clock drive capability determination Number of flip-flop groups for each input clock type (e) Clock tree (f) Number and scale of read-only memory (ROM) and random access memory (RAM) used for chip area estimation (g) Operating speed (g) Functional verification items in block units As is clear from (b) through (c) above, a draft floor plan is being considered at this stage.

  S2. A block-to-block netlist is created by using the input / output port information of the chip and the input / output port information of each block that are output as a result of the circuit architecture study in step S1 as inputs. Specifically, an operation of connecting ports having the same name is performed, and connection information is listed.

  The inter-block netlist created here is a black box in the block and includes only the wiring information between the blocks and between the blocks and the chip. This data is common to both implementation design.

  S3. Using the estimation results or setting results from (a) to (h) in the circuit architecture examination in step S1 and the interblock netlist created in step S2, the block remains black box and blocks on the chip. Then, the feasibility of the inter-block wiring is verified by estimating the area where the inter-block wiring is possible.

  S4. It is determined whether or not there is a problem in the result of the floor planning in step S3, that is, whether or not there is a problem in the arrangement of all blocks and the wiring between blocks and between blocks and chips.

  If it is determined that there is a problem (Yes), the process returns to the circuit architecture examination in step S1, the block division is changed, and steps S2 and S3 are repeated. As described at the end of the description of step S1, since the draft of floor planning is considered in the circuit architecture consideration in step S1, there is substantially no return to step S1 here.

  In this way, by performing the floor planning at an early stage and confirming it, it is possible to avoid reverting to RTL design or circuit architecture examination due to a timing error that is first known by timing verification performed after layout.

  Since the circuit architecture examination, the inter-block netlist generation and the floor planning are performed in parallel, these can be determined simultaneously.

  S5. If it is determined in step S4 that there is no problem (No), the inter-block netlist generated in step S2 and the RTL source generated in step S6 described later are input, A synthesis constraint condition for performing logic synthesis such as fan-out is extracted.

  S6. On the other hand, circuit design (RTL design) is performed on the block units divided in step S1 using a function description language to generate an RTL source.

  By using this as logic synthesis data at an early stage, it is possible to avoid inconsistencies between logic design / verification and logic synthesis, and to ensure the quality and reliability of the RTL source at an early stage. Become.

  Then, after the RTL design, the function verification items of the target block are subdivided according to the verification items divided in step S1, and an operation check item unique to the target block is added to the verification item.

  As a result, it is possible to prevent omission of verification regarding the required specification, the function and operation of the target block.

  S7. Using the interblock netlist generated in step S2, the synthesis constraint condition generated in step S5, and the RTL source generated in step S6 as inputs, logical synthesis is performed in units of blocks, and the scale of realization of the block Is calculated and confirmed, and the netlist is generated by the building block method by inserting the design information of the block into the interblock netlist.

  S8. If it is determined that there is a problem in the realization scale of the block calculated in step S7 (Yes), the RTL design in step S6 is returned to update the design, and RTL design and logic verification are performed until it is determined that there is no problem. repeat.

  S9. On the other hand, the verification items generated from step S1 and step S6, the function of generating input signals for the logic verification target block and chip using the block division result in step S1, and the output signal and its expected value Generate a test bench with matching function.

  S10. The RTL source generated in step S6, the test bench generated in step S9, and the interblock netlist generated in step S2 are input, and the functions and operations are confirmed in units of blocks and chips.

  This is to statically verify whether or not the RTL source is as expected without considering the delay time.

  As the validity of the required specifications of the RTL source is confirmed in units of blocks by this process, it becomes possible to confirm the functions and operations of the confirmed combinations of blocks as necessary. That is, the function and operation of the large scale integrated circuit can be confirmed by the building block method.

  S11. It is determined whether or not there is a problem with the result of step S10. If it is determined that there is a problem (Yes), the RTL design in step S6 is updated, and the RTL design in step S6 and the logic verification in step S10 are repeated until it is determined that there is no problem.

  S12. On the other hand, if it is determined in step S8 that there is no problem in the result of logic synthesis (No), the netlist generated in step S7 is used as an input, and the arrangement and wiring between the blocks and the blocks according to the floor plan, that is, Perform layout.

  Then, an SDF (Standard Delay File) is generated after layout. Specifically, the delay between input and output including the delay due to wiring is calculated for each cell used in the block. This is used in timing verification described later and gate verification as necessary.

  S13. If it is determined in step S11 that there is no problem (No), the interblock netlist generated in step S2, the netlist generated in step S7, and the test bench generated in step S9 are input. Check the operation.

  This is to verify statically without considering the delay by using the netlist of the logic synthesis result.

  S14. It is determined whether or not there is a problem with the result of the gate verification in step S13. If it is determined that there is a problem (Yes), step S6, step S10, step S11 and step S13 are repeated.

  If it is determined that there is no problem (No) in this step, the logic is consistent between the logic design and the implementation design. Therefore, as long as there is no mismatch with the specification change or the logic synthesis result, there is no return to the RTL design.

  S15. If it is determined that there is no problem (No) in the gate verification result in step S14, the timing verification is performed using the netlist generated in step S7, the test bench generated in step S9, and the SDF generated in step S12 as inputs. To do.

  In this method, the SDF obtained after the layout is used to dynamically verify the delay time between the cell and the wiring.

  S16. It is determined whether or not there is a problem with the timing verification in step S15, and the validity of the floor plan and layout is confirmed.

  If it is determined that there is a problem (Yes), the process returns to the logic synthesis in step S7, and steps S7, S8, and S12 are repeated.

  If it is determined in step S16 that there is no problem (No), the design of the large scale integrated circuit is completed.

  Now, on the right shoulder of the rectangle indicating each design step in FIG. 2, the symbols a to d attached to the design process of the large scale integrated circuit described in the prior art are described, and each design step in FIG. The relationship with the general design process of the scale integrated circuit is clearly shown.

  That is, the circuit architecture study in step S1 corresponds to the circuit architecture study in a, the RTL design in step S6, the logic verification in S10 and the gate verification in S13 correspond to the logic design / verification in b, and the logic synthesis in step S7 is performed. Corresponding to logic synthesis of c, interblock netlist generation in step S2, floor planning in step S3, synthesis constraint extraction in step S5, layout in step S12, and timing verification in step S15 correspond to the implementation design in d.

  Since the interblock netlist generation in step S2 and the floor planning in step S3 correspond to the floor planning referred to as d, the circuit architecture study and the floor planning are performed in parallel as shown in FIG. If there is a problem in the result, the circuit architecture is reviewed and reconsidered.

  In this way, by performing the floor planning at an early stage and confirming it, it is possible to avoid the case where the RTL design or the circuit architecture study may be reverted due to a timing error which is conventionally known for the first time after the timing verification performed after the layout. That is, the quality and reliability of circuit architecture examination and floor planning can be improved.

  Furthermore, since circuit architecture examination, interblock netlist generation, and floor planning are performed in parallel, these can be determined simultaneously and used as common data for subsequent design processes. That is, since circuit architecture examination and floor planning can be determined at an early stage, inconsistencies in subsequent processes can be eliminated, and high design quality and reliability can be ensured in subsequent processes.

  Also, since the RTL design in step S6 corresponds to the logic design of b, and the logic verification in step S10 and the gate verification in step S13 correspond to the logic verification of b, these are performed in parallel as shown in FIG. Since the RTL source is generated and the logic synthesis in step S7 is performed in parallel with the RTL source as an input, the high-quality RTL source and the netlist are determined by the building block method.

  Then, the layout of step S12 is performed according to the result of the logic synthesis of step S7, and the SDF is generated, and the timing verification is performed using the netlist and the SDF as inputs. If there is a problem, the process returns to the logic synthesis in step S7, and the design is updated to improve the quality and reliability of the netlist.

  In addition, since the circuit architecture study and floor plan are fixed, there is no retroactive return to the circuit architecture study and floor planning, and RTL design, logic verification, logic synthesis, layout, and timing verification are performed in parallel. As a result, logic design / verification, logic synthesis, layout and timing verification can be converged at an early stage.

  As described above, the time required for developing a large-scale integrated circuit can be shortened, and the quality and reliability of the design result can be increased.

  The present invention provides a method for developing a large-scale integrated circuit that performs circuit architecture examination, logic design / verification, logic synthesis, and implementation design concurrently. As a result, the design efficiency and design quality of the large-scale integrated circuit can be improved. it can.

  Further, the development tool of the present invention makes it possible to perform circuit architecture examination, logic design / verification, logic synthesis, and implementation design concurrently in the development of a large-scale integrated circuit.

  Thus, the present invention can greatly contribute to the development of a large-scale integrated circuit.

<Example>
FIG. 3 is a detailed procedure for developing a large-scale integrated circuit according to the present invention, and shows the principle procedure for developing the large-scale integrated circuit described in FIG. 2 in more detail. In addition, the code | symbol corresponding to the code | symbol attached | subjected to each development stage in FIG.
That is, development stages with the same code number correspond to each other, and the lowercase alphabet after the code number in FIG. 3 is divided into a plurality of stages in the development stage shown in a single stage in FIG. Indicates that

  In the following, detailed procedures for developing a large-scale integrated circuit according to the present invention will be described along the reference numerals attached to the respective development stages in FIG. In FIG. 3, a solid line with a thick arrow indicates a flow of development, and a broken line with a thin arrow indicates a data flow.

  S1a. With the required specifications as input, function division, block division, and examination of the structure of the realization circuit, and estimation and setting of the following data or information necessary for implementation design are performed.

(B) Number of flip-flops for determining whether or not a block can be accommodated (b) Chip input / output port information and block input / output port information (c) Realization scale (d) For clock drive capability determination Number of flip-flop groups for each input clock type (e) Clock tree (f) Number and scale of read-only memory (ROM) and random access memory (RAM) used for chip area estimation (g) Operating speed The average operation speed is a factor that determines the width of the power supply bus, and the operation speed for each block gives an indication of an arrangement place in the floor planning and becomes a constraint condition for logic synthesis of the block.

(H) Functional verification items in block units As apparent from (b) to (h) above, a draft floor plan is being considered at this stage.

  S1b. A block design specification such as a functional description and a circuit structure incorporating the result of the study in step S1a is examined, and a document describing the design specification is created.

  S1c. The request verification item is input, and each item is subdivided as a chip verification item based on the result of block division examined in step S1a, and the function corresponding to the request verification item is clarified. In this step, a block-specific verification item that is not included in the request verification item is added.

  S1d. Using the chip verification item created in step S1c as an input, the block verification items are subdivided into blocks in the same manner as in step S1c.

  By layering the above three verification items, ie, requirement verification item, block verification item, and chip verification item, from the required specification to the function of the realized circuit is organically connected, so that it is possible to prevent omission of functional verification become able to.

  S2. A block-to-block netlist is created by inputting the input / output port information of the chip and the input / output port information of the block unit, that is, the pin data, which are output as a result of the circuit architecture examination in step S1. Specifically, an operation of connecting ports having the same name is performed, and connection information is listed.

  In the inter-block netlist created here, the blocks are black boxes and contain only wiring information between blocks and between blocks and chips. This data is common to both implementation design.

  S3. Using the estimation and setting results in the circuit architecture study in step S1 and the inter-block netlist created in step S2, the block can be laid out on the chip with the black box inside, allowing inter-block wiring A large area and verify the feasibility of inter-block wiring.

  S4. It is determined whether or not there is a problem with the result of the floor planning in step S3. If it is determined that there is a problem (Yes), the process returns to the circuit architecture examination in step S1, the block division is changed, and steps S1 to S3 are repeated until it is determined that there is no problem.

  However, since the draft of the floor plan is considered in step S1a, there is substantially very little return to step S1a because there is a problem with the floor planning in step S3.

  As described above, by performing the floor planning at an early stage and confirming it, it is possible to avoid the case where the RTL design or the circuit architecture examination may be reverted due to a timing error which is conventionally known for the first time in the timing verification performed after the layout.

  Since the circuit architecture study, the interblock netlist generation, and the floor planning are performed in parallel, these can be determined at the same time, and inconsistencies between them can be avoided.

  S5a. If it is determined in step S4 that there is no problem (No), the inter-block netlist generated in step S2 and the clock tree generated in step S1a are input, and the timing, fanout and block area in the block are input. That is, a synthesis constraint condition for logic synthesis is extracted.

  S6. On the other hand, circuit design (RTL design) is performed on the block units divided in step S1a using a function description language to generate an RTL source.

  By making this logic synthesis data at an early stage, it is possible to avoid inconsistencies between logic design / verification and logic synthesis, and to ensure the quality and reliability of the RTL source at an early stage. .

  Then, after the RTL design, the function verification items of the target block are subdivided according to the verification items divided in step S1, and an operation check item unique to the target block is added to the verification item. As a result, it is possible to prevent omission of verification regarding the required specification, the function and operation of the target block.

  S7a. Using the interblock netlist generated in step S2 and the RTL source generated in step S6 as input, logical synthesis is performed in units of blocks, and the realization scale of the block is calculated and confirmed, and the interblock netlist is calculated. The netlist is generated by the building block method by inserting the design information of the block into the block.

  Specifically, logic synthesis is performed with a development tool using electronic mail, and details thereof will be described later.

  S7b. Using the intra-block constraint extracted in step S5a as input, timing adjustment is performed on the block-unit netlist generated by the logical synthesis in step S7a to perform optimization synthesis of blocks.

  S12c. Next, block layout is performed in order from the block for which optimization synthesis has been completed.

  S12d. It is determined whether logic synthesis and optimization synthesis have been completed for all blocks. If it is determined that logic synthesis and optimization synthesis have not been completed for all blocks (No), the process returns to block automatic logic synthesis in step S7a, and steps until optimization synthesis are completed until all blocks are completed. repeat.

  S8. If it is determined that there is a problem in the realization scale of the blocks calculated up to step S7b (Yes), the process returns to the RTL design in step S6 to update the design, and the subsequent steps are repeated until it is determined that there is no problem. .

  S5b. If it is determined in step S8 that there is no problem (No), a timing condition that is a logical synthesis constraint condition between blocks is extracted.

  S7c. Using the chip constraint extracted in step S5b, the timing of the entire chip is optimized.

  Note that step S5a, step S5b, and step S7c do not need to be performed every time the RTL design for each block is completed. This is because there is no change in step S5a unless there is a significant increase / decrease in the block size, and in step S5b there is no change unless there is an increase / decrease in the input / output ports of the block. This is because there is no change unless the input / output ports of the block are increased or decreased or the number of flip-flops is increased or decreased.

S9a. On the other hand, using the block verification items generated from step S1d and step S6 and the block division result in step S1a as input, the function to generate an input signal for the block to be logically verified and the collation of the output signal and its expected value A test bench for each block having a function (in FIG. 3, it is indicated as a block TB).
) Is generated.

  S9b. Further, a chip test bench having a function of generating an input signal to the chip and a function of collating the output signal with its expected value by inputting the chip verification item generated in step S1c and the block division result in step S1a. (In FIG. 3, it is indicated as chip TB).

  S10a. Using the RTL source generated in step S6, the test bench generated in steps S9a and S9b, and the inter-block netlist generated in step S2, the functions and operations are confirmed in units of blocks.

  This is to statically verify whether or not the RTL source of the block is as expected without considering the delay time.

  By this process, the validity of the required specification of the RTL source is confirmed in units of blocks, so that it is possible to confirm the functions and operations for a combination of a plurality of confirmed blocks as necessary. That is, the function and operation of the large scale integrated circuit can be confirmed by the building block method.

  S11a. It is determined whether or not there is a problem with the result of step S10a. If it is determined that there is a problem (Yes), the process returns to the RTL design in step S6, the design is updated, and the block logic verification in step S10a is repeated until it is determined that there is no problem.

  S13. If it is determined in step S11a that there is no problem (No), the interblock netlist generated in step S2, the netlist generated in step S7a, and the test bench generated in step S9 are input. Check the operation.

  This is to verify statically without considering the delay by using the netlist of the logical synthesis result of the block.

  S14. It is determined whether or not there is a problem with the result of the gate verification in step S13. If it is determined that there is a problem (Yes), the process returns to step S6, and the processes between step S6, step S10, step S11, and step S13 are repeated until it is determined that there is no problem.

  If it is determined that there is no problem (No) in this step, the logic is consistent between the logic design and the implementation design.

  S10b. The chip test bench generated in step S9b and the RTL source generated in step S6 are input to perform logic verification as a chip.

  This verifies whether the logic design including the wiring of the chip is as expected, and is a static verification that does not consider the delay time.

  S11b. It is determined whether there is a problem in the chip logic verification in step S10b. If it is determined that there is a problem (Yes), the process returns to step S6, and the processes between step S6, step S10, step S11, step S13, and step S10b are repeated until it is determined that there is no problem.

  If it is determined that there is no problem (No) in this step, the logic is matched between the logic design and the implementation design as a chip. Therefore, as long as there is no mismatch with the specification change or logic synthesis, there is no return to the RTL design in step S6.

  S12a. On the other hand, the clock tree taking into consideration the restriction on the driving capability of the clock driver and the reduction of the clock skew, with the interblock netlist output in step S2 and the clock tree that is the clock connection information created in step S1a as inputs. Make wiring. At this time, the clock skew can be reduced by making the clock wiring the same length.

  The reason why clock skew does not occur at this stage is that the inter-block netlist and floor plan have been determined first.

  As described above, since the clock skew can be prevented from occurring between the blocks, the design between the blocks and the blocks can be made independent, and the layout within the blocks can be easily advanced.

  S12b. The layout of high-speed blocks that are difficult to adjust timing at high speed is performed and layout data is generated.

  S12e. In step S12c, the low-speed operation block is laid out. In step S12b, the high-speed operation block is laid out and stored in the layout data. Therefore, the block arrangement and wiring between the blocks are performed according to the floor plan. The chip layout result is stored in the layout data.

  Then, an SDF (SDF; Standard Delay File) is generated after layout.

  This is an accumulation of the input / output delay time of the cell including the influence of the wiring, and is used for timing verification described later, and is also used for gate verification in step S13 as necessary.

  In this way, the layout of blocks that operate at high speed and the layout of blocks that operate at low speed are performed in parallel to reduce the turnaround time of the layout design. As a result, this becomes possible.

  In other words, in the past, automatic placement and wiring is difficult for blocks that operate at high speed, so manual placement and wiring by the designer is prioritized, and blocks that operate at low speed operate at high speed. Placement / wiring is automatically performed after block placement / wiring is completed, but this cannot start placement / wiring of blocks that operate at low speed until the high-speed block placement / wiring is completed.

  However, according to the development method of the present invention, since the inter-block netlist and the floor plan are fixed at this stage, the block of the block that operates at a low speed can be operated without waiting for the result of the placement and wiring of the block that operates at a high speed. Can start placement and wiring.

  Again, with the conventional development method, the interblock netlist and floor plan cannot be determined before the layout stage, and often the interblock netlist and floorplan must be changed according to the results of layout and timing verification. However, while the turnaround time for large-scale integrated circuit development was long, the above-mentioned development method shortened the turnaround time for the layout, which in turn reduced the turnaround time for large-scale integrated circuit development. Easy to understand.

  S15. If it is determined in step S11b that there is no problem in the result of the chip logic verification (No) and the chip layout in step S12e is completed, the interblock netlist generated in step S2, the netlist generated in step S7, Timing verification is performed with the chip test bench generated in step S9b and the SDF generated in step S12e as inputs.

  In this method, the SDF obtained after the layout is used to dynamically verify the delay time between the cell and the wiring.

  S16. It is determined whether or not there is a problem with the timing verification in step S15, and the validity of the floor plan and layout is confirmed.

  If it is determined that there is a problem (Yes), the process returns to step S7a, and there is no problem between the logic synthesis of step S7a, step S7b, and step S7c and the layout of step S12a, step S12b, and step S12c. Repeat until judged.

  If it is determined in step S16 that there is no problem (No), the design of the large scale integrated circuit is completed.

  As a whole, the output of block netlist generation and floor planning, which is performed in parallel with the circuit architecture study, is used as the common data for logic design and verification, logic synthesis and implementation design, and logic design and verification, logic synthesis and implementation design are performed. Proceed at the same time.

  First, in logic design, RTL design and logic verification are carried out while checking the validity of the circuit architecture for the required specifications in units of blocks in accordance with an interblock netlist and floor plan that are conscious of implementation design.

  In logic synthesis, RTL source designed in block units is input as logic, and the result is inserted into the inter-block netlist to generate a netlist. Further, optimized synthesis of blocks and chips is performed. To do.

  On the other hand, in the implementation design, the layout in units of blocks and the layout of the chip are sequentially advanced on the basis of the floor plan and the net list between blocks completed before the start of the RTL design. At this time, the layout design of the high-speed block and the low-speed block is performed in parallel to reduce the turnaround time of the layout design.

  This concurrent design work shortens the feedback loop during the design process. In particular, the result of the timing verification that is the final process does not cause feedback to the circuit architecture examination that is the first process, so that it is possible to prevent confusion and congestion in the design work due to the feedback.

  Up to this point, explanation has been given through the entire process of large-scale integrated circuit development, but hereinafter, the explanation of the main process and development tools applied to logic synthesis will be explained individually.

  FIG. 4 is a detailed procedure for examining the circuit architecture.

  In the study of the circuit architecture, a plurality of constraints described in a block having a round shape on both sides arranged on the left side in the flowchart of FIG. 4 are given and examined until all the constraints are satisfied. Repeat the examination.

  Hereinafter, the detailed procedure of the circuit architecture study will be described along the reference numerals attached to the respective steps in FIG. In FIG. 4, a solid line with a thick arrow indicates a flow of development, a broken line with a thin arrow indicates a flow of data, and a thin solid line with an arrow indicates a reference of a constraint condition.

  S21. Clarify the positioning of the large-scale integrated circuit to be developed from the required specifications, and extract the required functions without omission.

  S22. The functional configuration (combination of functions) for satisfying the functions of the entire chip is studied, and the functions are largely divided for each function.

  S23. Using the operation speed, function, and number of nets between blocks as constraints, the result of chip function division in step S22 is further divided into blocks to divide the chip into blocks.

  At this time, regarding the operation speed, the high-speed operation unit and the low-speed operation unit are divided, the functions are divided into functions that can be shared and individual functions, and the number of nets between blocks is minimized. Divide into

  S24. The block size is estimated with the gate size in the block as a constraint.

  This gate size estimation is performed for the feasibility of logic synthesis in units of blocks, reduction of layout design turnaround time, and flexibility of floor planning (movability of blocks).

  S25. It is determined whether or not there is a problem in the result of the gate size estimation in step S24. If there is a problem (Yes), the process returns to the block division of step S23, and steps S23 and S24 are repeated until it is determined that there is no problem by changing the division.

  S26. If it is determined that there is no problem (No) in step S25, the number of nets between the blocks is set as a constraint for the possibility of wiring between the blocks, and the possibility of clock driving is determined. The flip-flop groups calculated in step S24 are grouped within a specified number to define ports of blocks including clock ports.

  In particular, the definition of a clock port will be described with reference to FIG. 5, which is a diagram for explaining the assignment of flip-flops to clock ports.

  FIG. 5A shows the estimation result of the flip-flop group obtained in step S24. In this case, the result that 20 flip-flops are necessary is obtained, and it is illustrated that one type of clock is supplied. Yes.

  Assuming that the driving capability of the flip-flop with one clock line is five, the group of 20 flip-flops is divided into four groups of five, and one clock wiring is arranged in one group. Just connect.

  The result of this is shown in FIG.

  S27. It is determined whether or not there is a problem with the result of step S26. If it is determined that there is a problem (Yes), the process returns to the block division of step S23, and steps S23, S24, and S26 are repeated.

  S28. If it is determined in step S27 that there is no problem (No), a clock tree is created based on the constraint condition of the clock buffer for each technology related to the clock driving capability. The clock tree created here is clock connection information.

  S29. It is determined whether or not there is a problem with the clock tree obtained in step S28. If it is determined that there is a problem (Yes), the process returns to the block division in step S23, and steps S23, S24, and S26 are repeated until it is determined that there is no problem, thereby completing the clock tree.

  By completing the clock tree at this stage, the clock distribution to the blocks can be determined prior to the logical design, and the occurrence of a contradiction regarding the clock between the logical design and the implementation design can be prevented.

  S30. If it is determined that there is no problem (No) in step S29, the result of block division in step S23, the result of gate estimation in step S24, the definition of the block port in step S26 and the clock tree created in step S28 are input. Floor planning.

  At this stage, a draft floor plan reviewed on the desk is completed.

  S31. It is determined whether or not there is a problem in the consistency of the floor plan obtained in step S30, that is, whether or not the block can be laid out on the chip in consideration of the inter-block wiring area. If it is determined that there is a problem in consistency (Yes), the process returns to step S23 and the following examination is repeated until it is determined that there is no problem.

  S32. If it is determined in step S31 that there is no problem (No), the terminal arrangement of the large-scale integrated circuit is defined in consideration of the restriction on the number of simultaneous switching determined by the technology.

  S33. It is determined whether there is a problem with the terminal arrangement defined in step S32. If it is determined that there is a problem with the terminal arrangement (Yes), that is, there is a constraint violation regarding the number of simultaneous switchings, the process returns to the floor planning of step S30, and a terminal arrangement that satisfies the technology restrictions is possible. Repeat the floor planning.

  If it is determined in this step that there is no problem (No), the circuit architecture is examined.

  FIG. 6 shows a procedure for generating physical interface information, that is, a procedure for generating an interblock netlist.

  Hereinafter, a procedure for generating physical interface information will be described along the reference numerals attached to the respective steps in FIG. In FIG. 6, a solid line with a thick arrow indicates a development flow, and a thin broken line with an arrow indicates a data flow.

  S41. This step is a step of studying the circuit architecture described in FIG. 2, FIG. 3, etc., and defines the port name, input / output information, and block port information of bit width.

  S42. The block port information generated in step S41 is used as an input to generate a block unit port list.

  This block unit port list is also used in the RTL design.

  S43. Using the block unit port list generated in step S42 and the terminal arrangement information of the large scale integrated circuit as inputs, the ports having the same name are connected to generate an interblock netlist.

  FIG. 7 is a diagram conceptually illustrating generation of an inter-block net.

  In FIG. 7, small circles indicate block ports (shown in FIG. 7A), and small triangles indicate ports of the large-scale integrated circuit (chip) shown (shown in FIG. 7B). Then, an inter-block net (shown in FIG. 7C) is generated by connecting the block ports, the block ports, and the chip ports. The interblock netlist is a list of connection information between block ports and connection information between block ports and chip ports.

  The inter-block netlist generated here is used as common data for logic verification, gate verification, and timing verification, that is, common data for logic design and implementation design.

  For this reason, even if the logic design and the implementation design are performed in parallel, for example, there is no inconsistency in the interface between the blocks, and the quality or reliability of the results of the logic design and the implementation design performed in parallel can be improved.

  Next, logic synthesis will be described. Before describing the development tool used for logic synthesis, the logic synthesis using the development tool will be described.

  FIG. 8 shows the configuration of a development tool for a large-scale integrated circuit according to the present invention.

  In FIG. 8, reference numeral 1 denotes a network for connecting components of the development tool. For example, Ethernet is applied as described in FIG. A monitoring server 2 is equipped with a program for constantly monitoring an RTL source as a result of RTL design. Design terminals 3a and 3b are operated by a designer who designs RTL. A mail server 4 distributes various mails transferred through the development tool. A file server 5 stores the RTL source. Reference numeral 6 denotes a synthesis server, which performs logic synthesis on a block for which RTL design is completed.

  The operation mode of the development tool in FIG. 8 includes an RTL monitoring mode and a logic synthesis mode. The outline is as follows.

  First, in the case of the RTL monitoring mode, when the RTL monitoring command is emailed to the monitoring server 2 from the design terminals 3a and 3b, the monitoring server 2 checks the command in the received mail, and if it is a command in a prescribed format. The monitoring program is activated to start RTL monitoring, the presence or version number of the newly created or updated RTL source is confirmed, and if there is a corresponding RTL source, the design terminal and the synthesis server are notified by e-mail. The design terminal can check the RTL source to be logically synthesized and its version number by this mail, and can logically synthesize an incorrect version number of the RTL source and can avoid omission of version number update.

Next, in the logic synthesis mode, the following operation is performed. That is, when the RTL design is newly completed for each block or the update of the RTL design is completed, a mail for requesting composition is transmitted from the monitoring server 2 to the composition server 6. The composition server 6 that has received the composition request mail executes logic composition when it confirms that the contents of the mail are correct. After completion of logic synthesis, the synthesis server 6 transmits the result of logic synthesis to the design terminal as a report. (To be precise, the synthesis results report is not sent directly to the design terminal, but instead is sent to the designer ’s own mailbox, where the designer goes to the mailbox, Here, the expression “send to the design terminal” will be used consistently.) This allows the design terminal to confirm the validity of the logic synthesis. If the validity of the logic synthesis cannot be confirmed, the RTL design is performed again, and the logic synthesis is repeated until the validity of the logic synthesis is confirmed. When the RTL source is mailed from the design terminal to the composition server, the RTL source is cut out from the received mail and stored in the file server. The stored RTL source is recognized as a new file by the monitoring server 2 constantly monitoring the RTL source, and can be logically synthesized by the above flow.

  FIG. 9 is a diagram for explaining functions of the RTL monitoring mode.

  In FIG. 9, reference numeral 1 denotes a network for connecting components of the development tool, and for example, Ethernet is applied as described in FIG. A monitoring server 2 is equipped with a program for constantly monitoring an RTL source as a result of RTL design. Design terminals 3a and 3b are operated by a designer who designs RTL. Reference numeral 4 denotes a mail server which controls transmission / reception of various mails transferred within the development tool. A file server 5 stores the RTL source of the design result.

  And when the new or updated RTL source is stored in the file server, the monitoring server supports the update of the RTL source in addition to notifying the design terminal via the mail server by e-mail. And a function for managing the version number of the RTL source.

  The design terminals 3a and 3b send an e-mail to the monitoring server 2 to start a monitoring program installed in the monitoring server 2.

  The mail managed by the mail server includes a mail for realizing the monitoring function of the monitoring server 2, a mail for transmitting a result of monitoring by the monitoring server 2 to the design terminal 3a or 3b, and a mail from the design terminal 3a or 3b. Monitoring start command mail.

  As described in detail with reference to FIG. 3, RTL design and logic verification are performed in parallel on a block-by-block basis, and if there is a design error in the RTL source, it is updated and verified as needed. Therefore, a new or updated RTL source If the version number and the version number are not managed reliably, logic synthesis may be performed by an incorrect version number of the RTL source or execution of logic synthesis may be leaked for a specific block, resulting in logic design. And inconsistent design may occur.

  Therefore, in order to avoid this inconsistency by arranging and monitoring a server for monitoring the RTL source, the designer is conscious of whether or not logic synthesis is performed on the latest RTL source. Even if not, logic synthesis can be executed for the correct RTL source.

  FIG. 10 is a schematic procedure of RTL source monitoring.

  Hereinafter, the procedure of RTL monitoring will be described along the reference numerals attached to the respective steps in FIG. Note that the solid line with thick arrows in FIG. 10 indicates the flow of RTL source monitoring in the monitoring server, the solid line with thin arrows indicates the relationship of processing with other components, and the broken line with thin arrows indicates the flow of data. ing.

  First, an RTL monitoring start command mail is transmitted from the design terminal 3a or 3b.

  S51. The monitoring server is waiting to receive mail.

  S52. If no mail is received (No), the process returns to step S51 to continue waiting for mail reception.

  S53. In step S52, if a mail is received (Yes), the received command is checked.

  S54. If it is determined that the command is not in a predetermined format (No), the process returns to step S51 to enter mail reception standby.

  S55. If it is determined in step S54 that the command is in a predetermined format (Yes), the monitoring program is activated to generate RTL monitoring data including the storage address of the RTL source, the project name, and the name of the large-scale integrated circuit. .

  S56. Check if there is a newly designed RTL source or an updated RTL source.

  S57. As a result of the check in step S56, if it is determined that there is no new or updated RTL source (No), the process returns to step S56 to continue the check.

  S58. If it is determined in step S57 that there is a new or updated RTL source (Yes) as a result of the check in step S56, the RTL monitoring data is transmitted to the design terminals 3a and 3b and the synthesis server 6 by e-mail. The RTL monitoring procedure ends.

  Thereby, the design terminal side can confirm that the corresponding RTL source exists and its version number.

  In addition, when a newly designed or updated RTL source, that is, the latest RTL source exists, the monitoring server requests the synthesis server to perform logic synthesis, so that the latest RTL source can be executed without omission.

  FIG. 11 shows a procedure for generating RTL monitoring data performed by the monitoring server after receiving the RTL monitoring start command mail from the design terminal 3a or 3b in the general procedure for RTL monitoring, and FIG. 12 shows an example of the RTL monitoring start command.

  Hereinafter, the procedure for generating RTL monitoring data will be described in detail along the reference numerals attached to the respective steps in FIG. 11 with reference to the RTL monitoring start command in FIG. Note that the thick solid line in FIG. 11 indicates the flow of RTL monitoring data generation, and the thin broken line with an arrow indicates the data flow.

  S61. Waiting to receive email

  S62. Determine whether an email has been received. If it is determined that no e-mail has been received (No), the process returns to step S61 to continue receiving standby.

  S63. If it is determined in step S62 that an email has been received (Yes), the command mounted in the received email is analyzed.

  In the regular RTL monitoring start command mail, as shown in FIG. 12, the mail address of the delivery destination in the header part, “monitor on” as the RTL monitoring start command, the storage address of the RTL source, and the RTL source in the body part. The project name and large-scale integrated circuit name, which are names to be specified, are mounted.

  Note that the hierarchical name information such as the project name and the large-scale integrated circuit name is installed so that the large-scale integrated circuit with the same name can be correctly identified even if it is used in different projects. .

  S64. It is determined whether or not a regular RTL monitoring start command “monitor on” is installed.

  S65. As a result of command analysis in step S63, if it is determined that the regular RTL monitoring start command “monitor on” is not installed (No), an error mail indicating an error is transmitted to the design terminal, Returning to step S61, the e-mail reception standby is continued.

  Thereby, erroneous processing due to irrelevant electronic mail can be prevented.

  S66. If it is determined in step S64 that the regular RTL monitoring start command “monitor on” is installed (Yes), the storage address of the RTL source and the name information of the RTL source are extracted from the received mail.

  S67. The RTL monitoring data is searched using the RTL source storage address and RTL source name information extracted in step S66 as keys.

  S68. It is determined whether or not the RTL source is an RTL source that is already being monitored. If it is determined that the RTL source is an RTL source that is already being monitored (Yes), no processing is performed and the process returns to step S61 to enter standby for receiving an e-mail.

  As a result, even when a plurality of designers independently request RTL monitoring, it is possible to avoid duplication of the monitoring operation itself.

  S69. If it is determined in step S68 that the RTL source is not the monitored RTL source (No), the designated storage address is searched.

  S70. It is determined whether or not the specified storage address actually exists.

  S71. If it is determined that the storage address specified in step S70 does not actually exist (No), an error mail is transmitted, the process returns to step S61, and a standby for receiving an e-mail is entered.

  S72. If it is determined that the storage address specified in step S70 actually exists (Yes), a monitoring RTL source storage location in the monitoring server with a name having a hierarchy such as a project name and a large-scale integrated circuit name And RTL monitoring is executed by comparing RTL sources between designated storage addresses.

  S73. Store specified data in monitoring data.

  S74. The accepted data is transmitted to all design terminals, and the procedure for generating RTL monitoring data is completed.

  FIG. 13 shows an RTL source monitoring procedure based on the RTL monitoring data, and FIG. 14 shows an example of an RTL monitoring result reply mail.

  Hereinafter, the RTL monitoring procedure will be described along the reference numerals attached to the respective steps in FIG. 13 while referring to the RTL monitoring result reply mail in FIG. In FIG. 13, a solid line with a thick arrow indicates the flow of RTL monitoring, and a broken line with a thin arrow indicates the flow of data.

  S81. The project name, large-scale integrated circuit name, and storage address are extracted from the monitoring data shown in FIG.

  S82. It is determined whether the target data exists in the monitoring server.

  S83. If it is determined in step S82 that the data does not exist (No), the target RTL source is copied from the file server to the monitoring server from the storage address in the file server.

  S84. If it is determined in step S82 that the data exists (Yes), and after copying the RTL source in step S83, the RTL source file name list to be monitored is determined in order to determine whether the number of RTL source files is increased or decreased. Store in the array L, and store the RTL source file name list in the monitoring server in the array M.

  S85. The sizes of the array L and the array M are compared. If there is no difference between the sizes of the arrays L and M (denoted L = M for convenience), the process immediately proceeds to step S88 in the processing loop.

  S86. If there is a difference between the sizes of the array L and the array M, and the array L is larger than the array M (for convenience, L> M), it means that a new RTL source has been added. The new file name is stored in the array N1, and the process proceeds to step S88 in the processing loop.

  S87. If there is a difference between the sizes of the array L and the array M, and the array L is smaller than the array M (for convenience, L <M), the stored RTL source must be deleted. Therefore, the file name to be deleted is stored in the array N2, and the process proceeds to step S88 in the processing loop.

  S88. The difference between the contents of the RTL source with the matching file name is extracted.

  S89. It is determined whether there is a difference in the RTL source contents. If it is determined that there is no difference (No), the process of step S90 and subsequent steps S94 is skipped and looped. That is, the process returns to step S88.

  S90. If it is determined in step S89 that there is a difference in the RTL source contents (Yes), the version numbers are compared.

  S91. As a result of the version number comparison in step S90, it is determined whether or not the version numbers are the same.

  S92. If it is determined in step S91 that the version numbers are the same (Yes), there is a difference in the RTL source and the version numbers cannot be the same. Step S93 and step S94 are skipped and looped. That is, the process returns to step S88 substantially.

  As a result, the designer is informed that the version number has not been updated, and therefore it is possible to prevent omission of version number updates.

  S93. If it is determined in step S91 that the version numbers are not the same (No), the difference is stored in the difference file and the version number is recorded in the version number management table.

  S94. The file name having the difference is stored in the array N2.

  By executing Step S93 and Step S94, it is possible to automate version number management, and when necessary, it is possible to restore the required version number of the RTL source using the difference file. .

  If the above steps are executed for the RTL source at that time and the processing ends, the processing in the processing loop ends.

  S95. The file in the monitoring server is updated according to the processing in step S86, step S87, and step S94.

  That is, when a new RTL source is added, the new RTL source is copied from the storage address of the file server, and the storage address of the file server even if there is a difference in the RTL source even if no new RTL source is added. When a new RTL source is copied from the file server and the RTL source is deleted from the file server, the RTL source is deleted from the monitoring server, and the file in the monitoring server is updated.

  S96. The data in the arrays N1, N2, and N3 are transmitted to the design terminal by an RTL monitoring result reply mail, and the RTL source monitoring procedure ends.

  Note that the RTL monitoring result reply mail has a structure example shown in FIG. 14. The mail address of the delivery destination in the header part, the message indicating logic synthesis acceptance, and the large-scale integrated circuit of the file newly stored in the body part Name, RTL source file name, design terminal e-mail address, version number change information, large-scale integrated circuit name of updated file, RTL source file name, design terminal e-mail address, version number change information, large-scale integrated circuit of deleted file Name and RTL source file name.

  This concludes the description of RTL monitoring for logic synthesis, and the following shifts to the description of logic synthesis by mail order.

  FIG. 15 is a diagram for explaining the function of the logic synthesis mode.

  In FIG. 15, reference numeral 1 denotes a network for connecting components of the development tool, for example, Ethernet is applied. A monitoring server 2 is equipped with a program for constantly monitoring the RTL source. Design terminals 3a and 3b are operated and designed and verified by an RTL designer. A mail server 4 distributes various mails transferred through the development tool. A file server 5 stores a new RTL source or an updated RTL source. Reference numeral 6 denotes a synthesis server, which performs logic synthesis on a block for which RTL design has been completed.

  The outline of the function is as follows. That is, the monitoring server 2 constantly monitors the RTL source stored in the file server 5, and when the RTL source is added or updated, a mail is sent to the synthesis server 6 and the latest RTL source exists. Notify you. When receiving the mail from the monitoring server, the synthesizing server 6 extracts information necessary for synthesizing from the mail and executes logic synthesis, and transmits a synthesis result report to the design terminal after the circuit check.

  FIG. 16 shows a logic synthesis procedure, and FIG. 17 shows an example of a synthesis request mail.

  Hereinafter, the procedure of logic synthesis in FIG. 16 will be described with reference to the synthesis request mail in FIG.

  S101. The design terminal 3a or 3b performs RTL new design or RTL update design.

  S102. When the monitoring server 2 confirms the new RTL source or the updated RTL source, it sends a synthesis request mail to the synthesis server 6 and requests execution of logic synthesis.

  The composition request mail has a structure as shown in FIG. 17, the mail address of the delivery destination in the header part, the logic composition request command, the first keyword “Synth” in the body part and the name of the large scale integrated circuit accompanying it. The target block name, the mail address of the design terminal, the second keyword “RTL”, and the RTL source are installed.

  S103. The composition server 6 that has received the composition request mail analyzes the information installed in the mail, extracts the large-scale integrated circuit name, the target block name, and the design terminal mail address, and prepares a general-purpose script prepared in advance. Generates a predefined script and inserts a startup command.

  Note that the general-purpose script describes the synthesis constraint conditions common to all blocks, and the predefined script includes the synthesis constraint conditions specific to the specific block, the large-scale integrated circuit name, the target block name, and the email address of the design terminal Is formed.

  S104. Execute logic synthesis according to the defined script.

  S105. After the logic synthesis is completed, a synthesis result report including the RTL analysis result, circuit scale, timing information, and used cells is created.

  S106. The synthesis result report is transmitted to the design terminal.

  S107. The design terminal that has received the synthesis result report analyzes the synthesis result report.

  S108. If there is a problem with the synthesis result report, the process returns to the RTL logic design step to update the RTL source. When the monitoring server confirms that the RTL source has been updated, the process starts from step S102.

  If there is no problem in the synthesis result report, the logic synthesis is terminated.

  In this way, it is possible to determine the RTL source and the logic synthesis result for each block.

  Further, by sending an email from the design terminal with the RTL source attached to the second keyword, the synthesis server 6 cuts out the RTL source from the received email and stores it in the file server 5. When confirmed on the RTL source file server stored in this manner, the monitoring server 2 requests logic synthesis in step S102, and thus logic synthesis is executed according to the above procedure. Therefore, FIG. 8 shows a configuration in which a design terminal, a monitoring server, a synthesis server, and the like are connected to the same network. Also, RTL source transfer and logic synthesis are possible.

  FIG. 18 is a processing procedure of received mail.

  Hereinafter, the processing procedure of the received mail will be described along the reference numerals attached to the respective steps in FIG. In FIG. 18, a solid line with a thick arrow indicates the flow of received mail processing, and a broken line with a thin arrow indicates the flow of data.

  S111. The composition server 6 waits for the reception of mail from the monitoring server 2 or the design terminal 3a or 3b.

  S112. Determine whether an email has been received. If it is determined that no mail has been received (No), the process returns to step S111 and continues to wait for reception.

  S113. If it is determined that the mail has been received (Yes), the received mail is input to the text processing program and a keyword defined by matching with a regular expression is searched.

  S114. It is determined whether or not the first keyword has been extracted as a result of the search in step S113.

  S115. If it is determined in step S114 that the first keyword could not be extracted (No), an error mail is transmitted to the mail sender, and the process ends.

  S116. If it is determined in step S114 that the first keyword has been extracted (Yes), the large-scale integrated circuit name, block name, and e-mail address of the design terminal following the first keyword are extracted.

  S117. It is determined whether the second keyword has been extracted as a result of the search in step S113.

  S118. If it is determined in step S117 that the second keyword has been extracted (Yes), the RTL source mounted after the second keyword is cut out and stored in the RTL source file, and the process ends.

  S119. If it is determined in step S117 that the second keyword has not been extracted (No), step S116 is added to a predetermined portion of the general-purpose script that is prepared in advance and describes the synthesis constraint conditions common to all blocks. A predefined script is created by inserting the name of the large-scale integrated circuit and the block name extracted in step 1.

  S120. The logic synthesis is activated and executed with the file name of the defined script as an argument.

  S121. The circuit is checked after the logic synthesis is completed.

  S122. Then, a composition result report is created and transmitted to the originator of the composition request mail. At this time, the sender is identified with reference to the mail address extracted in step S116.

  This completes the received mail processing procedure, and thereafter, the apparatus enters a standby state for receiving a composite request mail based on the result of RTL monitoring.

  FIG. 19 shows a block layout procedure.

  A large-scale integrated circuit is divided into blocks for each function, logic design / verification and logic synthesis are performed, and layout of the completed blocks is performed in a building block system. At this time, blocks for which logic design / verification and logic synthesis have not been completed are treated as black boxes. However, even if the inside is a black box, since the ports are defined, wiring between the blocks is possible, and wiring between the blocks is determined, so that the load capacity of each port can be estimated. Therefore, it is possible to perform timing verification between blocks.

  Hereinafter, the block layout procedure will be described along the reference numerals attached to the respective steps in FIG. In FIG. 19, a solid line with a thick arrow indicates a block layout flow, and a thin broken line with an arrow indicates a data flow. Further, steps surrounded by a thick solid line are processing items in the block layout, and steps surrounded by a thin solid line are processing items performed before the block layout.

  S1. The circuit architecture is examined at the beginning of the development procedure, and as a result, a draft floor plan and a clock tree are obtained, and then an interblock netlist is obtained.

  The block layout starts from this state.

  S131. The clock skew between the blocks is adjusted in advance by using the floor plan, the clock tree and the inter-block netlist obtained as a result of the circuit circuit architecture study, and the clock skew is removed beforehand.

S132. It is determined whether or not the clock skew in step S131 is OK.
If it is determined that there is a problem (No), the process of returning to the circuit architecture study in step S1 and reconsidering the clock tree and the floor planning draft and adjusting the clock skew is determined to be OK. Do until it is done.

  S133. If it is determined in step S132 to be OK (Yes), the inter-block wiring is performed in consideration of the combined constraint condition of the load capacity and resistance of the inter-block wiring. At this time, in order to confirm the validity of the wiring connected to the block of the black box, a flip-flop is arranged at the input / output port of the block.

  S134. The validity of the timing between the blocks is confirmed, and if it is determined that the timing is not valid (No), the process returns to the circuit architecture examination in step S1, and the floor plan, the clock tree, and the inter-block netlist are again checked. Consideration is performed, and step S131 and step S133 are executed.

  S135. If it is determined in step S134 that the timing is appropriate (Yes), inter-block wiring is determined.

  S136. Extraction of synthesis constraints for fan-out and timing adjustment during intra-block synthesis.

  S137. From the block for which RTL design has been completed, logic synthesis is performed based on the synthesis constraint extracted in step S136, and replaced with a black box.

  S138. Place and wire inside the block replaced with the black box.

  S139. In step S138, timing verification is performed in the block that has been placed and wired. If it is determined that the timing is not appropriate (No), the process returns to step S137 to re-synthesize the logic in the block and execute steps S137, S138, and S139.

  S140. If it is determined in step S139 that the timing is appropriate (Yes), the wiring in the block is determined.

  S141. It is determined whether or not the design has been completed for all the blocks, and if it is determined that there are remaining blocks that have not been designed (No), step S136 and subsequent steps are repeated.

  On the other hand, if it is determined that the design has been completed for all the blocks (Yes), this processing procedure ends.

  In this way, by establishing the interblock netlist in advance, and placing and wiring in order from the block for which logic design / verification and logic synthesis has been completed, the design of the chip can be advanced in the building block method, Since the circuit architecture is not reverted from the chip design stage, the chip design efficiency and design quality can be improved.

The flow of the development process of the large-scale integrated circuit of the present invention. The principle procedure of large-scale integrated circuit development of this invention. Detailed procedure for development of a large scale integrated circuit of the present invention. Detailed procedure for circuit architecture study. The figure explaining allocation of the flip-flop to a clock port. Procedure for generating physical interface information. Diagram showing inter-block net generation conceptually Configuration of the development tool of the present invention. The figure explaining the function of RTL monitoring mode. General procedure for RTL monitoring. Procedure for generating RTL monitoring data. An example of an RTL monitoring start command. Procedure for RTL source monitoring. An example of an RTL monitoring result reply mail. The figure explaining the function of logic synthesis mode. Logic synthesis procedure. An example of a synthesis request email. Processing procedure for received mail. Block layout procedure. Flow of development process for conventional large-scale integrated circuits. Conventional large-scale integrated circuit development procedure.

Explanation of symbols

1 Network 2 Monitoring Server 3a Design Terminal 3b Design Terminal 4 Mail Server 5 File Server 6 Synthesis Server

Claims (5)

In development tools for large-scale integrated circuits that perform RTL design corresponding to blocks, which are units obtained by functionally dividing large-scale integrated circuits,
A file server for storing the result of the RTL design as an RTL source described in a function description language;
A monitoring server for checking a difference before and after the update of the RTL source stored in the file server;
A synthesis server that performs logic synthesis on the RTL source determined to have a difference before and after the update by the monitoring server;
Said file server, said monitoring server, and Bei example a network to pass data for performing the process cooperation between the synthesizing server,
The monitoring server includes a difference check unit that checks a difference between the updated RTL source and the RTL source before the update, a version number check unit that checks the version number of the RTL source, the difference check unit, and the version number. A development tool for a large-scale integrated circuit, comprising: means for checking a version number update omission based on a result of the checking means . The development tool for a large-scale integrated circuit according to claim 1,
The monitoring server includes means for requesting logic synthesis by sending a synthesis request command to the synthesis server when it is determined that there is a difference between before and after the update of the RTL source,
The synthesis server includes means for performing logic synthesis by receiving the synthesis request command from the monitoring server.
A large-scale integrated circuit development tool. The development tool for a large scale integrated circuit according to claim 2,
The synthesis request command includes a target block name to be subjected to logic synthesis,
The synthesis server includes a general-purpose script including synthesis constraint condition information common to all blocks, and means for generating a predefined script by adding synthesis condition information specific to the block indicated by the target block name to the general-purpose script; Means for performing logic synthesis based on the defined script.
A large-scale integrated circuit development tool. The development tool for a large scale integrated circuit according to claim 1,
One or more design terminals for inputting the RTL source stored in the file server, outputting the monitoring result of the monitoring server, and outputting the logic synthesis result of the synthesis server are provided.
A large-scale integrated circuit development tool. The development tool for a large-scale integrated circuit according to claim 4,
Data exchange for processing cooperation among the file server, the monitoring server, the synthesis server, and the one or more design terminals is performed by electronic mail via a mail server.
A large-scale integrated circuit development tool.

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