JP2000090142A - Development method and tool for large scale integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve both development efficiency and quality of an LSI by performing concurrently the study of a circuit architecture, the logical design/ verification, the logical synthesizing and the design of an implement respectively. SOLUTION: In a development process flow, the thick lines show the forward processes and the thin lines show the backward processes. The study of a circuit architecture and the floor planning, i.e., one of design processes of an implement are carried out in parallel to each other. Thus, the floor planning is decided when the study of the circuit architecture is over. The design conditions and design data which are generated in both study process of the circuit architecture and the floor planning process are used in common in the subsequent processes including the logical design/verification (RTL design and logical verification), logical synthesizing and layout to prevent the conflicts of design conditions and design data occurring among all processes. Thus, it's possible to improve both design efficiency and quality of an LSI circuit and also to contribute to development of the LSI circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a tool for developing a large-scale integrated circuit, and in particular, to concurrently perform floor planning as part of circuit architecture study and implementation design, and perform logical design / verification and logic design. A large-scale integrated circuit development method for concurrently performing layout and timing verification as part of synthesis and implementation design, and a large-scale integrated circuit development tool for developing a large-scale integrated circuit by the large-scale integrated circuit development method About.

There is a strong demand for higher performance, higher speed processing, and smaller size of communication devices and information processing devices, and in order to realize them, it is essential to realize circuits by large-scale integrated circuits.

In particular, in a communication device, an ASIC (Ap
Large-scale integrated circuits for realizing functions specific to communication devices called replication specific integrated circuits (ICs) are often applied, and the scale of ASICs is rapidly increasing. ing.

[0004] Of course, an increase in the scale of an integrated circuit complicates the design, and inevitably prolongs the design turn to ensure the design quality. However, on the other hand, there is an increasing demand for shorter delivery times of communication devices. Therefore, even if a communication device manufacturer develops and applies an ASIC,
Whether a specialized integrated circuit manufacturer develops and supplies an ASIC or a software vendor develops an integrated circuit, development with a short delivery time is essential to maintain market competitiveness.

In addition, the ASIC realizes a function unique to the communication device, and a standard circuit configuration cannot be applied in many cases. Therefore, it is necessary to design with a new configuration every time a new communication device is developed. Above, development work is A
Since the ratio of the SIC is increasing at a higher rate than that of the SIC, the number of personnel required for development is also increasing significantly. Even in such an ASIC development environment, the reliability of the developed product must be maintained.

[0006] As described above, the ASI is developed while satisfying the contradictory requirements of the development of a short delivery time and the maintenance of the reliability of the developed product.
The development of C is essential as a communication device maker, a manufacturer specializing in integrated circuits, and a software vendor, and only a manufacturer that solves this problem can survive severe competition.

[0007]

2. Description of the Related Art At present, large-scale integrated circuits such as ASICs are mainly developed by a method that combines a functional description language design using VHDL, Verilog and the like and logic synthesis. The whole process of circuit development can be roughly divided into the following processes.

That is, a. Circuit architecture study for studying circuit structure b. RTL (Register Transfer Le) using function description language
vel) Logic design / verification for design and verification c. Logic synthesis for logically synthesizing and optimizing circuits d. There are four stages of implementation design: floor planning, layout, and timing adjustment / verification.

FIG. 20 shows a flow of a conventional large-scale integrated circuit development. Here, the solid line with thick arrows in FIG. 20 indicates the flow of design in the forward direction, and the solid line with thin arrows indicates rework of design.

As clearly shown in FIG. 20, in the conventional large-scale integrated circuit development, the above-described circuit architecture study, logic design / verification, logic synthesis and implementation design are serialized in time series. If the previous process is not completed, the process does not move to the subsequent process. In this sense, the development process is simple if the development can be completed only by working forward in time.

FIG. 21 shows the procedure for developing a conventional large-scale integrated circuit in more detail. Here, the solid line with a thick arrow indicates the flow of development, and the broken line with a thin arrow indicates the flow of data.

The conventional procedure for developing a large-scale integrated circuit will now be described along the reference numerals assigned to the respective development stages in FIG. S151. Based on the required specifications and required examination items, the circuit structure is examined, the entire circuit is divided into functional blocks, and the required verification items are decomposed into blocks.

S152. The circuit is designed using the function description language for each block divided in the circuit architecture study in step S151, and RTL (Registor Transfer Level)
In addition to outputting the list, the function check items of the target block are subdivided according to the verification items divided in the circuit architecture study in step S151, and the function check items specific to the block are added to the verification items.

At this stage, a draft of an inter-block netlist, which is connection information between the terminals of the blocks and between the terminals of the blocks and the terminals of the chip of the large-scale integrated circuit, is generated. S153. Logic verification is performed in block units using the RTL list and the verification items.

S154. It is determined whether there is a problem in the result of the logic verification. If it is determined that there is a problem (Yes), the process returns to the RTL design in step S152 to update the circuit design, and the process proceeds to step S152 until it is determined that there is no problem.
152 and step S153 are repeated.

S155. If it is determined in step S154 that there is no problem (No), R
It is determined whether the TL design and the logic verification have been completed. If it is determined that the determination has not been completed for all the blocks (No), the process returns to the RTL design in step S152, and the process returns to step S152 until it is determined that all the blocks have been completed.
Step 152 and step S153 are performed.

S156. If the result of the determination in step S156 is that all blocks have ended (Yes), step S15
The logic synthesis is performed using the RTL list that is the result of Step 2, and the inter-block netlist for which the draft was created in the RTL design in step S152 is determined, and the result of logic synthesis is inserted into the inter-block netlist. , Generate an entire netlist.

S157. It is determined whether there is a problem in the logic synthesis. If there is a problem (Yes), the RTL design in step S152 or the
Returning to the examination of the circuit architecture of 151, the design is updated, and up to logic synthesis is repeated until it is determined that there is no problem.

S158. If there is no problem (No) in step S157, floor planning of the chip is performed based on the netlist output from the logic synthesis in step S156.

S159. It is determined whether there is a problem in the result of the floor planning. If there is a problem (Yes) as a result of this determination, logic synthesis in step S156 or RTL design in step S152 or step S15
Returning to the study of the circuit architecture of No. 1, the design is updated until the result of this determination is no problem.

S160. If the determination result in step S158 is no problem (No), layout is performed and SDF is performed.
(Standard Delay File). S161. The timing is verified based on the SDF output from step 160.

S162. It is determined whether there is a problem in the result of the timing verification. If the determination result is a problem (Yes), the process returns to the floor planning in step S158, the logic synthesis in step S156, or the examination of the circuit architecture in step S151, and the design is updated until the determination result shows no problem.

If the result of the above judgment is no problem (N
In the case of o), the design ends. It should be noted that lowercase alphabetic letters indicating the categories of the above-mentioned design steps are shown in FIG. That is, step S151 is the circuit architecture study a, and steps S152 to S155
The above is the above logic design / verification b, step S156
And step S157 corresponds to the logic synthesis c, and step S158 and subsequent steps correspond to the implementation design d.

In other words, in the development procedure of FIG. 21, as shown in the flow of the development process of FIG. 20, circuit architecture study, logic design / verification, logic synthesis, and implementation design are performed serially.

[0025]

However, in the development of a large-scale integrated circuit, it is rare that each design step is completed only once, resulting in specification changes, design errors, timing errors, and the like. For this reason, it often happens that the subsequent design process returns to the previous design process.

For example, if it is determined in step S154 of FIG. 21 that the result of the logic verification has a problem (Yes), the RTL design in step S152 is performed again. However, since this is a two-sided process of logic design and logic verification, it does not disrupt the design process.

The problem is the return from the subsequent process to the previous process. That is, if it is determined in step S157 that there is a problem in the logic synthesis (Yes) after the logic synthesis in step S156, the process returns to the RTL design in step S152 or the examination of the circuit architecture in step S151, and returns to the floor in step S158. If it is determined in step S159 after the planning that there is a problem in floor planning (Yes), step S15
6 and back to the RTL design in step S152 or the circuit architecture study in step S151,
Step S1 after the timing verification of step S161
If it is determined in step 62 that there is a problem in the timing verification (Yes), the process returns to the floor planning in step S157, the logic synthesis in step S155, or the examination of the circuit architecture in step S151. Then, such backward movement is repeated many times.

In FIG. 20, a solid line with an arrow is drawn at a place where the backward movement can occur. These retraces do not merely repeat the process that was supposed to be over, but also often have inconsistencies in the cause of each retrace, so reversing between specific processes and updating the design will also retrace between other processes. This has to be done, which can lead to difficulties in development work.

In such a case, the efficiency of large-scale integrated circuit development is significantly reduced, and the development process is extremely long. As a result, even if it is a communication device maker, a large-scale integrated circuit maker, or a software vendor, it will not be possible to avoid a decrease in competitiveness.

Up to now, the performance of the CAD machine has been improved, that is, the processing capability of the CAD machine itself such as a server has been increased. The speed of the CAD tool has been increased, that is, the processing speed of the software installed in the CAD tool has been increased. (For example, increasing the processing speed by changing the serial processing to parallel processing.) We have tried to prevent the reduction of development efficiency and the prolongation of the process due to the gradual reduction of mistakes due to repeated checking. CAD has become increasingly larger
It has become almost impossible to prevent a reduction in development efficiency and a prolonged process by merely increasing the performance of a machine, increasing the speed of a CAD tool, and gradually reducing errors due to repeated checks.

In view of the above problems, the present invention provides a method for developing a large-scale integrated circuit that concurrently performs circuit architecture examination, logic design / verification, logic synthesis, and implementation design, and a large-scale integrated circuit by the method for developing a large-scale integrated circuit. It is an object of the present invention to provide a large-scale integrated circuit development tool for developing circuits, to improve the efficiency of large-scale integrated circuit development, and to improve the quality of developed large-scale integrated circuits.

[0032]

FIG. 1 is a flow chart showing a development process of a large-scale integrated circuit according to the present invention. Here, a solid line with a thick arrow in FIG. 1 indicates a forward step, and a solid line with a thin arrow and a broken line with a thin arrow indicate a backward step.

As clearly shown in FIG. 1, the feature of the present invention is that the circuit architecture examination and the floor planning which is one step of the implementation design are performed in parallel, and when the circuit architecture examination is completed, the floor planning is also performed. It is confirmed that the design conditions and design data generated in the circuit architecture study process and the floor planning process can be used in subsequent logical design / verification (RT
(L design, logic verification), logic synthesis, and layout are used as common data to prevent inconsistency in design conditions and design data between all processes.

FIG. 2 shows the basic procedure for developing a large-scale integrated circuit according to the present invention, and shows the flow of the process of developing a large-scale integrated circuit according to the present invention in some detail. In FIG. 2, a solid line with a thick arrow indicates the flow of development, and a broken line with a thin arrow indicates the flow of data.

Hereinafter, the principle procedure of the development of a large-scale integrated circuit according to the present invention will be described along the reference numerals assigned to the respective development stages in FIG. S1. The circuit structure is examined by dividing the large-scale integrated circuit into functional blocks by inputting the required specifications and the required verification items, and estimating and setting the following items (a) to (h) for each block. .

(A) Number of flip-flops for judging whether or not a block can be accommodated (b) Input / output port information of a chip and input / output port information of a block (c) Realization scale (d) Clock drive capability judgment (E) Clock tree (f) Read-only memory (R) for estimating chip area
OM) and the number and scale of random access memory (RAM) (g) Operating speed (h) Functional verification items in block units As is clear from (a) to (h) above, draft floor planning at this stage Is being considered.

S2. The inter-block netlist is created by using the input / output port information of the chip and the input / output port information of each block, which are output as a result of the circuit architecture study in step S1, as inputs. Specifically, an operation of connecting ports having the same name is performed, and connection information is listed.

The inter-block netlist created here is a black box inside the block and contains only the wiring information between the blocks and between the block and the chip. As will be described later, This is common data for both logic design and implementation design.

S3. The estimation result or the setting result from (a) to (h) in the circuit architecture study in step S1 and the inter-block netlist created in step S2 are input as blocks on the chip while the inside of the block remains a black box. Then, the feasibility of the inter-block wiring is verified by estimating the area where the inter-block wiring is possible.

S4. It is determined whether there is a problem in the result of the floor planning in step S3, that is, whether there is any problem in the arrangement of all the blocks and the wiring between the blocks and between the blocks and chips.

If it is determined that there is a problem (Yes), the process returns to the examination of the circuit architecture in step S1, the block division is changed, and steps S2 and S3 are repeated. As described at the end of the description of step S1, the draft of the floor planning is considered in the study of the circuit architecture of step S1, and therefore, returning to step S1 here is substantially less.

As described above, by performing floor planning early and determining it, it is possible to avoid returning to the RTL design or the circuit architecture study due to a timing error conventionally known only in the timing verification performed after the layout.

Since the circuit architecture study, the generation of the inter-block netlist, and the floor planning are performed in parallel, they can be determined simultaneously. S5. If it is determined in step S4 that there is no problem (No), the inter-block net list generated in step S2 and the RTL source generated in step S6 described later are input, and A synthesis constraint condition for performing logic synthesis such as fan-out is extracted.

S6. On the other hand, an RTL source is generated by performing a circuit design (RTL design) using a functional description language for each block divided in step S1. By using this as data for logic synthesis at an early stage, it is possible to avoid inconsistency between logic design / verification and logic synthesis, and to ensure the quality and reliability of the RTL source at an early stage. Become.

After the RTL design, the function verification items of the target block are subdivided according to the verification items divided in step S1, and the operation check items unique to the target block are added to the verification items.

As a result, it is possible to prevent omission of verification regarding the required specifications and the functions and operations of the target block. S7. With the inter-block netlist generated in step S2, the synthesis constraint generated in step S5, and the RTL source generated in step S6 as inputs, logic synthesis is performed in block units, and the realization scale of the block is performed. Is calculated and confirmed, and the inter-block net list is filled with the design information of the block to generate a net list by a building block method.

S8. If it is determined that there is a problem in the implementation scale of the block calculated in step S7 (Yes), the process returns to the RTL design in step S6 to update the design, and the RTL design and logic verification are performed until it is determined that there is no problem. repeat.

S9. On the other hand, steps S1 and S6
A test having a function of generating an input signal for a block and a chip to be logically verified by using the verification item generated from the above and the block division result in step S1 as input, and a function of comparing an output signal with its expected value Generate a bench.

S10. Using the RTL source generated in step S6, the test bench generated in step S9, and the inter-block netlist generated in step S2 as input, the function and operation are confirmed in units of blocks and chips.

This statically verifies whether or not the RTL source is as expected without considering the delay time. As the validity of the RTL source with respect to the required specifications is confirmed in block units by this process, it becomes possible to confirm the function and operation of a combination of a plurality of confirmed blocks as necessary. That is, the function and operation of the large-scale integrated circuit can be confirmed by the building block method.

S11. It is determined whether there is a problem in the result of step S10. If it is determined that there is a problem (Yes), the RTL design in step S6 is updated, and the RTL design in step S6 and the logic verification in step S10 are repeated until it is determined that there is no problem.

S12. On the other hand, if it is determined in step S8 that there is no problem in the result of logic synthesis (No), the netlist generated in step S7 is used as an input, and the placement and wiring between the blocks and between the blocks according to the floor plan, ie, Perform layout.

After the layout, the SDF (Standard
Delay File). Specifically, for each cell used in the block, a delay between input and output, including a delay due to wiring, is calculated. This is used in the timing verification described later and, if necessary, the gate verification.

S13. No problem in step S11 (N
When it is determined as o), the operation check is performed using the inter-block netlist generated in step S2, the netlist generated in step S7, and the test bench generated in step S9 as inputs.

In this method, a netlist as a result of logic synthesis is used to perform static verification without considering delay. S14. It is determined whether there is a problem in the result of the gate verification in step S13. If it is determined that there is a problem (Yes), step S6, step S10,
Steps S11 and S13 are repeated.

Then, there is no problem in this step (No)
If it is determined that the logic has been matched between the logic design and the implementation design. Therefore, as long as there is no specification change or inconsistency with the result of logic synthesis, there is no return to the RTL design.

S15. If it is determined in step S14 that there is no problem in the gate verification result (No), the timing verification is performed by using the netlist generated in step S7, the test bench generated in step S9, and the SDF generated in step S12 as inputs. Perform

This is the SDF obtained after layout.
And dynamically verifying up to the delay time of the cell and wiring. S16. It is determined whether there is a problem in the timing verification in step S15, and the validity of the floor plan and the layout is confirmed.

If it is determined that there is a problem (Yes), the process returns to the logic synthesis in step S7, and steps S7, S8 and S12 are repeated. If it is determined in step S16 that there is no problem (No), the design of the large-scale integrated circuit ends.

In FIG. 2, reference numerals a to d attached to the large scale integrated circuit design process described in the prior art are described at the right shoulder of a rectangle indicating each design step.
The relationship between each design step in FIG. 2 and a rough design process of a large-scale integrated circuit is clearly shown.

That is, the examination of the circuit architecture of step S1 corresponds to the examination of the circuit architecture of step a, the RTL design of step S6, the logic verification of step S10, and the gate verification of step S13 correspond to the logic design and verification of step b. The logic synthesis corresponds to the logic synthesis of c, generation of a net list between blocks in step S2, floor planning in step S3, extraction of synthesis constraint conditions in step S5, and step S
The 12 layouts and the timing verification in step S15 correspond to the implementation design of d.

Since the generation of the netlist between blocks in step S2 and the floor planning in step S3 correspond to the floor planning referred to by d, the circuit architecture study and floor planning are performed in parallel as shown in FIG. During this time, if there is a problem in the design result, the process returns to the circuit architecture study and is reviewed again.

As described above, by performing the floor planning early and confirming it, it is possible to avoid a situation in which a timing error conventionally known for the first time in the timing verification performed after the layout causes a return to the RTL design or the circuit architecture study. it can. That is, the quality and reliability of circuit architecture study and floor planning can be improved.

Further, since the examination of the circuit architecture, the generation of the inter-block netlist, and the floor planning are performed in parallel, they can be simultaneously determined and used as common data in the subsequent design process. That is, since the examination of the circuit architecture and the floor planning can be determined at an early stage, inconsistencies in subsequent steps can be eliminated, and high quality and reliability of design can be secured in the subsequent steps.

The RTL design of step S6 corresponds to the logic design of b, and the logic verification of step S10 and the
Since the gate verification of 13 corresponds to the logic verification of b, these are performed in parallel as shown in FIG. 1 to generate an RTL source, and the RTL source is used as an input, and the logic synthesis of step S7 is performed in parallel. As a result, a high-quality RTL source and a netlist are determined in a building block manner.

Then, the layout in step S12 is performed according to the result of the logic synthesis in step S7, and the SDF
Is generated, and timing verification is performed using the netlist and the SDF as inputs. If there is a problem, the process returns to the logic synthesis in step S7 to update the design.
The quality and reliability of the netlist will be improved.

In addition, since the circuit architecture study and the floor plan have been determined, there is no need to go back to the circuit architecture study and floor planning, and the RTL design, logic verification, logic synthesis, layout and timing verification are performed. By being performed in parallel, logic design / verification, logic synthesis, layout, and timing verification can be quickly converged.

As described above, the time required for developing a large-scale integrated circuit can be shortened, and the quality and reliability of the design result can be improved.

[0069]

FIG. 3 shows a detailed procedure for developing a large-scale integrated circuit according to the present invention, and shows the basic procedure for developing a large-scale integrated circuit described in FIG. 2 in more detail. Each development stage in FIG. 3 is denoted by a reference numeral corresponding to the reference numeral assigned to each development stage in FIG. That is, the development stages having the same reference numerals are the development stages corresponding to each other.
Figure 2 shows the lowercase alphabet after the sign
Indicates that the development stage shown in a single stage is divided into multiple stages.

Hereinafter, the detailed procedure for developing a large-scale integrated circuit according to the present invention will be described along the reference numerals assigned to the respective development stages in FIG. In FIG. 3, a solid line with a thick arrow indicates a development flow, and a broken line with a thin arrow indicates a data flow.

S1a. With the required specifications as input, function division, block division, examination of the structure of the realized circuit, and estimation and setting of the following data or information required for implementation design are performed.

(A) Number of flip-flops for judging whether or not a block can be accommodated (b) Input / output port information of a chip and input / output port information of a block (c) Realization scale (d) Clock drive capability judgment (E) Clock tree (f) Read-only memory (R) for estimating chip area
OM) and the number and size of random access memory (RAM) used (g) Operating speed By the way, the average operating speed in a chip is a factor that determines the width of the power supply bus, and the operating speed of each block is determined by the location of floor layout. It gives a guide and becomes a constraint condition of the logic synthesis of the block.

(H) Functional Verification Items in Block Units As is clear from the above (A) to (H), drafts of floor planning are being considered at this stage.

S1b. The block design specification such as the function description and the circuit structure including the result of the review in step S1a is examined, and a document describing the design specification is created. S1c. With the request verification items as inputs, each item is subdivided into chip verification items based on the result of the block division examined in step S1a, and functions corresponding to the request verification items are clarified. Then, in this step, a verification item unique to the block, which is not included in the request verification item, is added.

S1d. With the chip verification item created in step S1c as an input, similar to step S1c,
It is subdivided into block verification items for each block. By layering the above three verification items, that is, the requirement verification item, the block verification item, and the chip verification item, since the requirement specification to the function of the realized circuit are organically connected, it is possible to prevent omission of function verification. become able to.

S2. The inter-block net list is created by using the input / output port information of the chip and the input / output port information of each block, that is, the pin data, which are output as a result of the examination of the circuit architecture in step S1. In particular,
Work to connect ports with the same name,
List connection information.

In the inter-block netlist created here, the inside of the block is a black box.
It contains only wiring information between blocks and between blocks and chips, and becomes common data for both logical design and implementation design, as described later.

S3. The estimation and setting results in the circuit architecture study in step S1 and the inter-block netlist created in step S2 are input,
The blocks are laid out on the chip while keeping the inside of the block as a black box, the area where inter-block wiring can be performed is estimated, and the feasibility of inter-block wiring is verified.

S4. It is determined whether there is a problem in the result of the floor planning in step S3. There is a problem (Y
If it is determined to be es), the process returns to the examination of the circuit architecture in step S1, the block division is changed, and steps S1 to S3 are repeated until it is determined that there is no problem.

However, since the draft of the floor plan is being considered in step S1a, the return to step S1a on the assumption that there is a problem in the floor planning in step S3 is substantially very few.

As described above, by performing the floor planning early and determining it, it is possible to avoid a situation in which the timing error conventionally known for the first time in the timing verification performed after the layout causes a return to the RTL design or the circuit architecture study. it can.

Since the circuit architecture study, the inter-block net list generation and the floor planning are performed in parallel, these can be determined simultaneously.
Moreover, inconsistencies between them can be avoided.

S5a. No problem in step S4 (No)
When it is determined that the timings in the blocks are input, the inter-block netlist generated in step S2 and the clock tree generated in step S1a are input.
The synthesis constraint conditions for logic synthesis, such as fanout and block area, are extracted.

S6. On the other hand, an RTL source is generated by performing circuit design (RTL design) using a functional description language for each block divided in step S1a. By using this as data for logic synthesis at an early stage, inconsistency between logic design / verification and logic synthesis can be avoided.
It is possible to ensure the quality and reliability of the TL source.

After the RTL design, the function verification items of the target block are subdivided according to the verification items divided in step S1, and operation check items specific to the target block are added to the verification items. As a result, it is possible to prevent the omission of verification regarding the required specification and the function and operation of the target block.

S7a. The inter-block netlist generated in step S2 and the RTL generated in step S6
Performs logic synthesis on a block basis using the source as input, calculates and confirms the realization scale of the block, and inserts the design information of the block into the inter-block netlist to generate a netlist in a building block manner I will do it.

More specifically, logic synthesis is performed using a development tool using electronic mail. This will be described later in detail. S7b. With the in-block constraint conditions extracted in step S5a as inputs, timing adjustment is performed on the block-by-block netlist generated by the logic synthesis in step S7a, and the block is optimized and synthesized.

S12c. Next, block layout is performed in order from the block on which the optimization synthesis has been completed. S12d. It is determined whether logic synthesis and optimization synthesis have been completed for all blocks. Logical synthesis and optimization synthesis have not been completed for all blocks (No)
If it is determined that this is the case, the flow returns to block automatic logic synthesis in step S7a, and the steps up to optimization synthesis are repeated until the processing is completed for all blocks.

S8. If it is determined that there is a problem in the realization scale of the block calculated up to step S7b (Yes), the process returns to the RTL design in step S6 to update the design, and the subsequent steps are repeated until it is determined that there is no problem. .

S5b. No problem in step S8 (No)
If it is determined that the timing condition is satisfied, a timing condition which is a logic synthesis constraint condition between blocks is extracted. S7c. The timing of the entire chip is optimized using the chip constraints extracted in step S5b.

The above steps S5a and S5b
Step S7c does not need to be performed every time the RTL design for each block is completed. Because step S
What to do in 5a does not change unless there is a significant increase or decrease in the block scale, and what to do in step S5b does not change unless there is an increase or decrease in the input / output ports of the block.
This is because there is no change unless the input / output port of the block increases or decreases or the number of flip-flops increases or decreases in step S7c.

S9a. On the other hand, a block verification item generated from step S1d and step S6,
1b, a block-based test bench having a function of generating an input signal for a block to be subjected to logic verification and a function of comparing an output signal with its expected value (in FIG. 3, referred to as a block TB). ing.)
Generate

S9b. Also, a chip test bench provided with a function of generating an input signal for the chip and a function of comparing an output signal with its expected value, using the chip verification items generated in step S1c and the block division result in step S1a as inputs. (In FIG. 3, this is indicated as chip TB).

S10a. RTL generated in step S6
Using the source, the test bench generated in steps S9a and S9b, and the inter-block netlist generated in step S2 as input, the function and operation are confirmed in block units.

This statically verifies whether or not the RTL source of the block is as expected without considering the delay time. By this process, the validity of the RTL source with respect to the required specification is confirmed in block units, so that it is possible to confirm the function and operation of a combination of a plurality of blocks that have been confirmed as necessary. That is, the function and operation of the large-scale integrated circuit can be confirmed by the building block method.

S11a. It is determined whether there is a problem in the result of step S10a. If there is a problem (Yes)
When it is determined that there is no problem, the process returns to the RTL design in step S6 to update the design, and the steps up to block logic verification in step S10a are repeated until it is determined that there is no problem.

S13. No problem in step S11a (N
When it is determined as o), the operation is confirmed by using the inter-block netlist generated in step S2, the netlist generated in step S7a, and the test bench generated in step S9 as inputs.

In this method, a netlist obtained as a result of logic synthesis of blocks is used to perform static verification without considering delay. S14. It is determined whether there is a problem in the result of the gate verification in step S13. If it is determined that there is a problem (Yes), the process returns to step S6 and returns to step S6.
6, Step S10, Step S11 and Step S1
The process of 3 is repeated until it is determined that there is no problem.

Then, there is no problem in this step (No)
If it is determined that the logic has been matched between the logic design and the implementation design. S10b. Using the test bench of the chip generated in step S9b and the RTL source generated in step S6 as inputs, logic verification of the chip is performed.

This is to verify whether or not the logic design including the wiring of the chip is as expected, and is a static verification without considering the delay time. S11b. It is determined whether there is a problem in the chip logic verification in step S10b. If it is determined that there is a problem (Yes), the process returns to step S6 and returns to step S6.
6, Step S10, Step S11, Step S13
And the process between step S10b is repeatedly performed until it is determined that there is no problem.

Then, there is no problem in this step (No)
If it is determined that the logic has been matched as a chip between the logic design and the implementation design. Therefore, as long as there is no change in the specification or inconsistency with the logic synthesis, there is no return to the RTL design in step S6.

S12a. On the other hand, the inter-block netlist which is the output of step S2 and the clock tree which is the clock connection information created in step S1a are input, and the clock tree is formed in consideration of the restriction of the driving capability of the clock driver and the reduction of the clock skew. Make the wiring. At this time, the clock skew can be reduced by making the clock wiring the same length.

The reason why the clock skew does not occur at this stage is that the inter-block netlist and the floor plan are determined first. As described above, since the clock skew can be prevented from occurring between the blocks, the design between the blocks and the design in the block can be made independent, and the layout in the block can be easily advanced.

S12b. A high-speed block that operates at high speed and whose timing is difficult to adjust is laid out, and layout data is generated. S12e. In step S12c, the low-speed operation blocks are laid out. In step S12b, the high-speed operation blocks are laid out and stored in the layout data. Therefore, the blocks are arranged and the wiring between the blocks is performed according to the floor plan. The result of the chip layout is stored in the layout data.

After layout, SDF (SDF;
Standard Delay File). This is the accumulation of the input / output delay time of the cell including the influence of the wiring.
This is used for timing verification described later, and is also used for gate verification in step S13 as needed.

The reason why the layout of the blocks operating at high speed and the layout of the blocks operating at low speed are performed in parallel in this way is to reduce the turnaround time of the layout design. As a result of this, this is possible.

That is, conventionally, it is difficult to automatically place and route blocks that operate at high speed, and therefore, prioritize manual placement and wiring by the designer.
For the blocks that operate at low speed, the placement and wiring were performed automatically after the placement and wiring of the blocks that operate at high speed were completed. In this case, the blocks that operate at low speed until the placement and wiring of the high-speed blocks were completed. Not be able to start placing and wiring.

However, according to the development method of the present invention, since the inter-block netlist and the floor plan have been determined at this stage, the low-speed operation can be performed without waiting for the result of the arrangement and wiring of the high-speed operation blocks. To start arranging and wiring blocks.

Again, in the conventional development method,
The inter-block netlist and floor plan cannot be determined before the layout stage, and the layout and timing verification results often need to change the inter-block netlist and floor plan, resulting in turnaround time for large-scale integrated circuit development. However, it can be easily understood that the above-described development method shortens the turnaround time of the layout and, consequently, the turnaround time of the development of a large-scale integrated circuit.

S15. In step S11b, it is determined that there is no problem (No) in the result of the chip logic verification, and step S1
When the chip layout of 2e is completed, the inter-block netlist generated in step S2 and the
7. The timing verification is performed using the netlist generated in step 7, the test bench of the chip generated in step S9b, and the SDF generated in step S12e as inputs.

This is the SDF obtained after layout.
And dynamically verifying up to the delay time of the cell and wiring. S16. It is determined whether there is a problem in the timing verification in step S15, and the validity of the floor plan and the layout is confirmed.

If it is determined that there is a problem (Yes), the process returns to step S7a, where the logic synthesis of steps S7a, S7b, and S7c and the layout of steps S12a, S12b, and S12c are performed. Repeat until there is no problem.

Then, in step S16, there is no problem (N
When it is determined as o), the design of the large-scale integrated circuit ends. As a whole, the output of the inter-block netlist generation and floorplanning, which is performed in parallel with the study of the circuit architecture, is used as the common data for logic design / verification, logic synthesis, and implementation design. We will proceed at the same time.

First, in the logical design, the RTL design and the logic verification are advanced in accordance with the inter-block netlist and the floor plan in consideration of the implementation design, while confirming the validity of the circuit architecture for the required specifications in block units.

In the logic synthesis, the RTL is used for each block.
Logic synthesis is performed using the designed RTL source as an input, the result is inserted into an inter-block net list to generate a net list, and further, an optimized synthesis of blocks and chips is performed.

On the other hand, in the implementation design, the layout of the block and the layout of the chip are sequentially advanced based on the floor plan and the inter-block netlist completed before the start of the RTL design. At this time, the layout design of the high-speed block and the low-speed block is performed in parallel,
It aims to shorten the turnaround time of layout design.

The feedback loop during the design process is shortened by this concurrent design work. In particular, since the result of the timing verification as the final step does not cause feedback to the circuit architecture study as the first step, confusion and congestion in the design work due to the feedback can be prevented.

Although the description has been made throughout the entire process of developing a large-scale integrated circuit, the main steps and the development tools applied to logic synthesis will be described individually.

FIG. 4 is a detailed procedure for examining the circuit architecture. In the examination of the circuit architecture, a plurality of constraints described in a block having a round shape on both sides, which are arranged on the left side in the flowchart of FIG. 4, are given and examined, and until all the constraints are satisfied. Repeat the examination.

Hereinafter, the detailed procedure for examining the circuit architecture will be described along the reference numerals assigned to the respective steps in FIG. In FIG. 4, a solid line with a thick arrow indicates a flow of development, a broken line with a thin arrow indicates a flow of data, and a solid line with a thin arrow indicates reference to a constraint condition.

S21. From the required specifications, clarify the position of the large-scale integrated circuit to be developed and extract the required functions without omission. S22. A function configuration (combination of functions) for satisfying the functions of the entire chip is examined, and the functions are largely divided for each function.

S23. With the operating speed, the function, and the number of nets between blocks as constraints, the result of the chip function division in step S22 is further subdivided to divide the chip into blocks.

At this time, with regard to the operation speed, the high-speed operation unit and the low-speed operation unit are divided, and the functions are divided into functions that can be shared and individual functions. Divide so that

S24. The size of a block is estimated using the gate size in the block as a constraint. The estimation of the gate size is performed for the feasibility of logic synthesis in block units, the reduction of turnaround time in layout design, and the flexibility of floor planning (movability of blocks).

S25. It is determined whether there is a problem in the result of the gate size estimation in step S24. If there is a problem (Yes), the process returns to block division in step S23, and the division is changed and steps S23 and S24 are repeated until it is determined that there is no problem.

S26. No problem in step S25 (N
If it is determined as o), for the blocks determined so far, the number of nets between blocks is set as a constraint for the possibility of wiring between the blocks, and the flip-flop calculated in step S24 for the driveability of the clock. Groups are grouped within a specified number to define the ports of the block including the clock port.

In particular, the definition of a clock port will be described with reference to FIG. 5, which is a diagram illustrating the assignment of flip-flops to clock ports. FIG. 5A shows the estimation result of the flip-flop group obtained in step S24. In this case, the result that 20 flip-flops are required is obtained, and it is shown that one kind of clock is supplied. I have.

Assuming that the driving capability of the flip-flop with one clock line is five, the group of twenty flip-flops is divided into four groups of five, and one group is divided into one group. A clock wiring may be connected.

FIG. 5B shows the result of this operation. S27. It is determined whether there is a problem in the result of step S26. If you determine that there is a problem (Yes),
Returning to the block division in step S23, step S2
3. Steps S24 and S26 are repeated.

S28. No problem in step S27 (N
If it is determined to be o), a clock tree is created based on the clock buffer constraint conditions for each technology related to the clock driving capability. The clock tree created here is clock connection information.

S29. It is determined whether there is a problem in the clock tree obtained in step S28. There is a problem (Ye
If determined to be s), the process returns to block division in step S23, and steps S23, S24, and S26 are repeated until it is determined that there is no problem, thereby completing the clock tree.

By completing the clock tree at this stage, the clock distribution to the blocks can be determined prior to the logic design, and the occurrence of clock inconsistency between the logic design and the implementation design can be prevented.

S30. No problem in step S29 (N
If determined to be o), the result of the block division in step S23, the result of the gate estimation in step S24, the definition of the block port in step S26, and the step S2
Floor planning is performed using the clock tree created in step 8 as an input.

At this stage, a draft of the floor plan examined on the desk is completed. S31. It is determined whether or not there is a problem with the consistency of the floor plan obtained in step S30, that is, whether or not the blocks can be laid on the chip in consideration of the inter-block wiring area. If it is determined that there is a problem with the consistency (Yes), the process returns to step S23, and the subsequent examination is repeated until it is determined that there is no problem.

S32. No problem in step S31 (N
When it is determined as o), the terminal arrangement of the large-scale integrated circuit is defined in consideration of the restriction on the number of simultaneous switching determined by the technology.

S33. It is determined whether there is a problem with the terminal arrangement defined in step S32. If there is a problem with the terminal arrangement (Yes), that is, if it is determined that there is a constraint violation regarding the number of simultaneous switching, step S
Returning to the floor planning of 30, the floor planning is repeatedly performed so that the terminal arrangement satisfying the restrictions of the technology can be performed.

If it is determined that there is no problem (No) in this step, the examination of the circuit architecture is completed.
FIG. 6 shows a procedure for generating physical interface information, that is, a procedure for generating a netlist between blocks.

Hereinafter, the procedure for generating the physical interface information will be described along the reference numerals assigned to the respective steps in FIG.
In FIG. 6, a solid line with a thick arrow indicates a flow of development, and a broken line with a thin arrow indicates a flow of data.

S41. This step is a step of examining the circuit architecture described with reference to FIGS. 2 and 3 and the like, and defines a port name, input / output information, and block port information of bit width.

S42. The block port information generated in step S41 is input to generate a port list for each block. The port list of this block unit is RT
Also used in L design.

S43. The port list having the same name is connected by using the port list of the block unit generated in step S42 and the terminal arrangement information of the large-scale integrated circuit as inputs, and a net list between blocks is generated.

FIG. 7 is a diagram conceptually showing generation of an inter-block net. In FIG. 7, a small circle indicates a port of a block (shown in FIG. 7A), and a small triangle indicates a port of a large-scale integrated circuit (chip) shown (shown in FIG. 7B). Then, by connecting the block ports and the block port and the chip port, an inter-block net (FIG. 7)
(C) is shown. ). A list of the connection information between the block ports and the connection information between the block ports and the chip ports is an inter-block netlist.

The inter-block netlist generated here is used as common data for logic verification, gate verification, and timing verification, that is, common data for logic design and implementation design.

Therefore, even if the logic design and the implementation design are performed in parallel, for example, the inconsistency of the interface between the blocks is eliminated, and the quality or reliability of the result of the logic design and the implementation design performed in parallel is improved. Can be.

Next, the logic synthesis will be described. Prior to that, the development tool used for the logic synthesis will be described, and then the logic synthesis using the development tool will be described.

FIG. 8 shows a configuration of a development tool for a large-scale integrated circuit according to the present invention. In FIG. 8, reference numeral 1 denotes a network for connecting the components of the development tool, and for example, Ethernet is applied as shown in FIG. Reference numeral 2 denotes a monitoring server on which a program for constantly monitoring the RTL source as a result of the RTL design is mounted. Design terminals 3a and 3b are operated by a designer who designs the RTL. A mail server 4 distributes various mails transferred in the development tool. Reference numeral 5 denotes a file server which stores an RTL source. Reference numeral 6 denotes a synthesis server which performs logic synthesis on the blocks for which the RTL design has been completed.

The operation mode of the development tool shown in FIG.
There are an L monitoring mode and a logic synthesis mode. The outline is as follows. First, in the case of the RTL monitoring mode, when an RTL monitoring command is e-mailed from the design terminals 3a and 3b to the monitoring server 2, the monitoring server 2 checks the command in the received mail, and if the command has a prescribed format, The monitoring program is started to start RTL monitoring, the presence or absence and the version number of a newly created or updated RTL source are confirmed, and if there is a corresponding RTL source, the design terminal and the synthesis server are notified by e-mail. The design terminal can confirm the RTL source to be subjected to logic synthesis and its version number by this mail, and can prevent the RTL source of the wrong version number from being logic-synthesized and omit omission of version number update.

Next, in the case of the logic synthesis mode, the operation is performed as follows. That is, when the RTL design is newly completed for each block or when the update of the RTL design is completed, the monitoring server 2 sends a synthesis request mail to the synthesis server 6.
Upon receiving the synthesis request mail, the synthesis server 6 confirms that the mail has the correct content, and executes logical synthesis.
After completion of the logic synthesis, the synthesis server 6 sends the result of the logic synthesis as a report to the design terminal. (Actually, instead of sending a report of the synthesis result directly to the design terminal, it is sent to the designer's own mailbox, and the designer goes to the mailbox, Here, the expression “transmit to the design terminal” is used consistently.) Thereby, the design terminal can confirm the validity of the logic synthesis. If the validity of the logic synthesis cannot be confirmed, the RTL design is redone and the logic synthesis is repeated until the validity of the logic synthesis is confirmed. or,
When the RTL source is mailed from the design terminal to the synthesis server, the RTL source is cut out from the received mail and stored in the file server. The stored RTL source is RTL
The file is recognized as a new file by the monitoring server 2 which constantly monitors the source, and can be logically synthesized by the above flow.

FIG. 9 is a diagram for explaining the function of the RTL monitoring mode. In FIG. 9, reference numeral 1 denotes a network for connecting the components of the development tool, for example, Ethernet as shown in FIG. 2 is a monitoring server, R
A program for constantly monitoring the RTL source as a result of the TL design is installed. Design terminals 3a and 3b are operated by a designer who designs the RTL. A mail server 4 controls transmission and reception of various mails transferred in the development tool. Reference numeral 5 denotes a file server which stores an RTL source of a design result.

When the new or updated RTL source is stored in the file server, the monitoring server notifies the design terminal via the mail server by e-mail, and also notifies the design terminal of the RTL source. It has a function of managing the version number of the RTL source in response to the update.

The design terminals 3a and 3b send an e-mail to the monitoring server 2 and activate a monitoring program mounted on the monitoring server 2. The mail managed by the mail server includes a mail for realizing a monitoring function of the monitoring server 2, a mail for transmitting a result monitored by the monitoring server 2 to the design terminal 3a or 3b,
a or a monitoring start command mail from 3b.

As described in detail with reference to FIG.
Design and logic verification are performed in block units in parallel. If there is a design error in the RTL source, it is updated and verified as needed, so it is necessary to check whether there is a new or updated RTL source and its version number. Otherwise, logic synthesis may be performed by an incorrect version of RTL source, or execution of logic synthesis may be omitted for a specific block, resulting in inconsistency between logic design and implementation design. There is fear.

Therefore, by arranging and monitoring a server for monitoring the RTL source, it is possible to avoid this inconsistency. The logic synthesis can be executed for the correct RTL source without being aware of this.

FIG. 10 shows a schematic procedure of RTL source monitoring. Hereinafter, the RTL monitoring procedure will be described along the reference numerals attached to the respective steps in FIG. It should be noted that the solid line with a thick arrow in FIG. 10 indicates the flow of RTL source monitoring in the monitoring server, the solid line with a thin arrow indicates the relationship between processing with other components, and the broken line with a thin arrow indicates the flow of data. ing.

First, an RTL monitoring start command mail is transmitted from the design terminal 3a or 3b. S51. The monitoring server is waiting for mail.

S52. If no mail is received (N
In the case of o), the flow returns to step S51 to continue waiting for the mail reception. S53. In step S52, if a mail has been received (Yes), the received command is checked.

S54. If it is determined that the command is not a command of a predetermined format (No), the process returns to step S51 to wait for mail reception. S55. If it is determined in step S54 that the command has a predetermined format (Yes), the monitoring program is started to generate RTL monitoring data including the storage address of the RTL source, the project name, and the name of the large-scale integrated circuit. .

S56. Check if there is a newly designed RTL source or an updated RTL source. S57. As a result of the check in step S56, when it is determined that there is no new or updated RTL source (No),
Returning to step S56, the check is continued.

S58. As a result of the check in step S56, if it is determined in step S57 that there is a new or updated RTL source (Yes), the RTL monitoring data is transmitted to the design terminals 3a and 3b and the synthesizing server 6 by e-mail. , End the RTL monitoring procedure.

As a result, on the design terminal side, the corresponding RT
It is possible to confirm that the L source exists and its version number. When a newly designed or updated RTL source, that is, the latest RTL source is present, the monitoring server requests the synthesizing server to perform the logic synthesis, so that the logic synthesis can be executed without fail for the latest RTL source.

FIG. 11 shows a procedure of RTL monitoring data generation performed by the monitoring server after receiving an RTL monitoring start command mail from the design terminal 3a or 3b in the general procedure of the RTL monitoring, and FIG. 12 shows an example of the RTL monitoring start command. It is.

Hereinafter, the generation procedure of the RTL monitoring data will be described in detail along the reference numerals assigned to the respective steps in FIG. 11 with reference to the RTL monitoring start command in FIG. Note that the thick solid line in FIG. 11 indicates the flow of RTL monitoring data generation, and the thin broken line with an arrow indicates the flow of data.

S61. Waiting to receive email. S62. It is determined whether an e-mail has been received. If it is determined that no e-mail has been received (No), the process returns to step S61 to continue waiting for reception.

S63. If it is determined in step S62 that the e-mail has been received (Yes), the command contained in the received e-mail is analyzed. As shown in FIG. 12, in the regular RTL monitoring start command mail, the mail address of the delivery destination, “monitoron” as the RTL monitoring start command are specified in the header part, and the storage address of the RTL source and the RTL source are specified in the body part. And a large-scale integrated circuit name.

It should be noted that the use of hierarchical name information such as a project name and a large-scale integrated circuit name allows a large-scale integrated circuit with the same name to be correctly specified even if it is used in different projects. That's why.

S64. It is determined whether or not a regular RTL monitoring start command “monitor on” is mounted. S65. As a result of the command analysis in step S63, when it is determined that the regular RTL monitoring start command “monitor on” is not mounted (No), an error mail indicating an error is transmitted to the design terminal,
Returning to step S61, the e-mail reception standby is continued.

As a result, erroneous processing due to irrelevant electronic mail can be prevented. S66. In step S64, a proper RTL monitoring start command "monitoron" is mounted (Yes).
If it is determined, the storage address of the RTL source and the name information of the RTL source are extracted from the received mail.

S67. RTL extracted in step S66
The RTL monitoring data is searched using the storage address of the source and the name information of the RTL source as keys. S68. It is determined whether the RTL source is an RTL source that is already being monitored. If it is determined that the RTL source is the RTL source that is already being monitored (Yes), the process returns to step S61 without performing any processing, and waits for reception of an e-mail.

Thus, a plurality of designers can independently execute RTL.
Even if monitoring is requested, duplication of the monitoring operation itself can be avoided. S69. If it is determined in step S68 that the RTL source is not the monitored RTL source (No), the specified storage address is searched.

S70. It is determined whether the specified storage address actually exists. S71. If it is determined in step S70 that the designated storage address does not exist (No), an error mail is transmitted, and the process returns to step S61 to wait for reception of an e-mail.

S72. If it is determined in step S70 that the storage address specified actually exists (Yes),
An RTL source storage location for monitoring is secured in the monitoring server with a hierarchical name such as a project name and a large-scale integrated circuit name, and RTL monitoring is performed by comparing RTL sources between designated storage addresses.

S73. Stores the specified data in the monitoring data. S74. The received data is transmitted to all the design terminals, and the procedure of generating the RTL monitoring data ends.

FIG. 13 shows an example of the R based on the RTL monitoring data.
FIG. 14 shows an example of the RTL monitoring result reply mail. Hereinafter, the RTL monitoring procedure will be described along the reference numerals attached to the respective steps in FIG. 13 with reference to the RTL monitoring result reply mail in FIG. In FIG. 13, a solid line with a thick arrow indicates a flow of RTL monitoring, and a broken line with a thin arrow indicates a flow of data.

S81. The project name, large-scale integrated circuit name, and storage address are extracted from the monitoring data shown in FIG. S82. It is determined whether the target data exists in the monitoring server.

S83. If it is determined in step S82 that the data does not exist (No), the target RTL source is copied from the file server to the monitoring server from the storage address in the file server.

S84. If it is determined in step S82 that the data exists (Yes), the process proceeds to step S83.
After the RTL source is copied in step (a), a list of RTL source file names to be monitored is stored in an array L in order to determine whether the number of RTL source files increases or decreases.
The TL source file name list is stored in the array M.

S85. The size of the array L and the size of the array M are compared. There is no difference between the sizes of the arrays L and M (for convenience, L
= M. ), The process immediately proceeds to step S88 in the processing loop.

S86. If there is a difference between the size of the array L and the size of the array M and the array L is larger than the array M (for convenience, L> M), it means that a new RTL source has been added. , The new file name is stored in the array N1, and the routine goes to Step S88 in the processing loop.

S87. When there is a difference between the size of the array L and the size of the array M and the array L is smaller than the array M (for convenience, L <M), the stored RTL source must be deleted. Therefore, the name of the file to be deleted is stored in the array N2, and step S8 in the processing loop is executed.
Move to 8.

S88. The difference between the contents of the RTL source having the same file name is extracted. S89. It is determined whether there is a difference in the contents of the RTL source. If it is determined that there is no difference (No), the process from step S90 to step S94 is skipped and looped. That is, the process returns to step S88.

S90. If it is determined in step S89 that there is a difference in the RTL source contents (Yes), the versions are compared. S91. As a result of the version number comparison in step S90, it is determined whether or not the version numbers are the same.

S92. If it is determined in step S91 that the version numbers are the same (Yes), it is impossible that the RTL source has a difference and the version numbers are the same, so that a warning mail is transmitted to the design terminal, and S93
And jump to step S94 to make a loop. That is,
Substantially, the process returns to step S88.

As a result, it is notified to the designer that the version number has not been updated, so that it is possible to prevent omission of version number update. S93. In step S91, the version numbers are not the same (No)
If it is determined that the difference is stored, the difference is stored in the difference file, and the version number is recorded in the version number management table.

S94. The file name with the difference is array N2
To be stored. Executing step S93 and step S94 makes it possible to automate the version number management and, if necessary, to restore the required version number of the RTL source using the difference file. .

If the above steps are executed for the RTL source at that time and the processing ends, the processing in the processing loop ends. S95. The file in the monitoring server is updated according to the processing in steps S86, S87, and S94.

That is, when a new RTL source is added, the new RTL source is copied from the storage address of the file server. Even when a new RTL source is not added, even if there is a difference in the RTL source, the file server is copied. When the new RTL source is copied from the storage address of the server, and the RTL source is deleted from the file server, the RTL source is deleted from the monitoring server and the file in the monitoring server is updated.

S96. The data of the arrays N1, N2, and N3 are transmitted to the design terminal by the RTL monitoring result reply mail, and the RTL source monitoring procedure is completed. It should be noted that the RTL monitoring result reply mail has a structure example as shown in FIG. 14, a mail address of a delivery destination in a header portion, a message indicating reception of logic synthesis, and a large-scale integrated circuit of a newly stored file in a body portion. Name, RTL source file name, design terminal mail address, version change information, large-scale integrated circuit name of updated file, RTL source file name, design terminal mail address, version number change information, large-scale integrated circuit of deleted file Name and RTL source file name.

[0188] This concludes the description of RTL monitoring for logic synthesis, and then shifts to the description of logic synthesis by mail order. FIG. 15 is a diagram for explaining the function of the logic synthesis mode.

In FIG. 15, reference numeral 1 denotes a network for connecting the components of the development tool, for example, Ethernet. Reference numeral 2 denotes a monitoring server on which a program for constantly monitoring the RTL source is mounted. Design terminals 3a and 3b are operated by a designer who designs the RTL to perform design and verification. A mail server 4 distributes various mails transferred in the development tool. A file server 5 stores a new RTL source or an updated RTL source.
Reference numeral 6 denotes a synthesis server which performs logic synthesis on the blocks for which the RTL design has been completed.

The outline of the function is as follows. That is, the monitoring server 2 constantly monitors the RTL source stored in the file server 5, and when an RTL source is added or updated, an e-mail is sent to the synthesizing server 6 so that the latest RTL source exists. Notify that you are. When the synthesizing server 6 receives the mail from the monitoring server,
Information necessary for synthesis is extracted from the e-mail, logic synthesis is performed, and after a circuit check, a synthesis result report is transmitted to the design terminal.

FIG. 16 shows an example of the procedure of the logic synthesis, and FIG. 17 shows an example of the synthesis request mail. Hereinafter, the procedure of the logic synthesis in FIG. 16 will be described with reference to the synthesis request mail in FIG.

S101. Design terminal 3a or 3b is RTL
New design or RTL update design. S102. If the monitoring server 2 has a new RTL source or updated R
When the TL source is confirmed, a synthesis request mail is transmitted to the synthesis server 6 to request execution of logic synthesis.

The combining request mail has a structure as shown in FIG. 17, and has a delivery destination mail address,
The logic synthesis request command includes a first keyword "Synth", a large-scale integrated circuit name, a target block name and a mail address of a design terminal, a second keyword "RTL", and an RTL source attached to the body portion.

S103. Upon receiving the synthesis request mail, the synthesis server 6 analyzes the information included in the mail,
The large-scale integrated circuit name, the target block name and the mail address of the design terminal are extracted and inserted into a prepared general-purpose script to generate a defined script,
Generate a start command.

In the general-purpose script, synthesis constraints common to all blocks are described, and the synthesis constraints unique to a specific block, the name of a large-scale integrated circuit, the name of a target block, and the mail address of a design terminal are inserted therein. A defined script is formed.

S104. Execute logic synthesis according to the defined script. S105. After the logic synthesis is completed, the RTL analysis result,
Create a synthesis result report consisting of circuit size, timing information, and cells used.

S106. The synthesis result report is transmitted to the design terminal. S107. The design terminal that has received the synthesis result report analyzes the synthesis result report.

S108. If there is a problem with the synthesis result report, return to the RTL logic design step and return to the RTL logic design step.
Have the source updated. Then, when the monitoring server confirms that the RTL source has been updated, step S1
02 starts the process.

If there is no problem in the synthesis result report, the logic synthesis ends. In this way, it is possible to determine the RTL source and the result of logic synthesis for each block.

[0200] By sending a mail from the design terminal with the RTL source attached to the second keyword, the synthesizing server 6 cuts out the RTL source from the received mail and stores it in the file server 5. When the monitoring server 2 confirms the stored RTL source file server, it requests the logic synthesis in step S102.
Logic synthesis is performed by the above procedure. Therefore, FIG.
Has shown the configuration where the design terminal, monitoring server, synthesis server, etc. are connected to the same network. However, if the networks of the development tools are connected to each other, even if the design terminal is installed in a remote place, the RTL source can be used. Transfer and logic synthesis are possible.

FIG. 18 shows the procedure for processing a received mail.
Hereinafter, the processing procedure of the received mail will be described along the reference numerals assigned to the respective steps in FIG. In FIG. 18, a solid line with a thick arrow indicates the flow of received mail processing, and a broken line with a thin arrow indicates the flow of data.

S111. The synthesizing server 6 is waiting for a mail from the monitoring server 2 or the design terminal 3a or 3b. S112. It is determined whether the mail has been received. If it is determined that the e-mail has not been received (No), the process returns to step S111 to continue waiting for reception.

S113. If it is determined that the mail has been received (Yes), the received mail is input to a text processing program to search for a keyword defined by matching with a regular expression.

S114. It is determined whether the first keyword has been extracted as a result of the search in step S113. S115. If it is determined in step S114 that the first keyword could not be extracted (No), an error mail is transmitted to the sender of the mail, and the process ends.

S116. If it is determined in step S114 that the first keyword has been extracted (Yes), the large-scale integrated circuit name, block name, and mail address of the design terminal following the first keyword are extracted.

S117. It is determined whether or not the second keyword has been extracted as a result of the search in step S113. S118. If it is determined in step S117 that the second keyword has been extracted (Yes), the RTL source mounted after the second keyword is cut out and the RTL is extracted.
Store it in the source file and end the process.

S119. If it is determined in step S117 that the second keyword has not been extracted (No), step S116 is performed in a predetermined location of a general-purpose script prepared in advance and describing a synthesis constraint condition common to all blocks. A defined script is created by filling in the large-scale integrated circuit name and block name extracted in step.

S120. Logic synthesis is started and executed using the file name of the defined script as an argument. S121. After completion of logic synthesis, check the circuit.

S122. Then, a synthesis result report is created and transmitted to the source of the synthesis request mail. On this occasion,
The source is specified with reference to the mail address extracted in step S116.

[0210] Thus, the processing procedure of the received mail is completed, and thereafter, the process waits for reception of the synthesis request mail based on the result of the RTL monitoring. FIG. 19 is a block layout procedure.

A large-scale integrated circuit is divided into blocks for each function, logic design / verification and logic synthesis are performed, and the layout of the completed blocks is performed. The chip layout is advanced in a building block system. At this time, blocks whose logic design / verification and logic synthesis have not been completed are treated as black boxes. However, even if the inside is a black box,
Since ports are defined, wiring between blocks is possible, and since wiring between blocks is determined, the load capacity of each port can be estimated. Therefore, it is possible to verify the timing between the blocks.

Hereinafter, the procedure of the block layout will be described along the reference numerals assigned to the respective steps in FIG.
In FIG. 19, a solid line with a thick arrow indicates a flow of a block layout, and a broken line with a thin arrow indicates a flow of data. Steps surrounded by thick solid lines are processing items in the block layout, and steps surrounded by thin solid lines are processing items performed before the block layout.

S1. At the beginning of the development procedure, the circuit architecture is examined, and as a result, a draft floor plan and a clock tree are obtained, and thereafter, an inter-block netlist is obtained.

The block layout starts from this state. S131. Circuit The clock skew between the blocks is adjusted by using the floor plan, the clock tree, and the inter-block netlist obtained as a result of the study of the circuit architecture, and the clock skew is removed in advance.

S132. It is determined whether or not the clock skew in step S131 is OK. There is a problem (No)
If it is determined, the process returns to step S1 for examining the circuit architecture, and the process of mainly reconsidering the draft of the clock tree and the floor planning and adjusting the clock skew is performed until it is determined to be OK.

S133. In step S132, OK (Ye
If it is determined to be s), the inter-block wiring is performed in consideration of the combined constraint condition of the load capacity and resistance of the inter-block wiring. At this time, flip-flops are arranged at the input / output ports of the block in order to confirm the validity of the timing of the wiring connected to the block of the black box.

S134. The validity of the timing between the blocks is confirmed, and if it is determined that the timing is not valid (No), the process returns to the examination of the circuit architect in step S1, and the floor plan, the clock tree, and the inter-block netlist are again checked. After examination, step S1
31. Step S133 is executed.

S135. If it is determined in step S134 that the timing is appropriate (Yes), the inter-block wiring is determined. S136. Extraction of synthesis constraint conditions for fan-out and timing adjustment when performing intra-block synthesis.

S137. From the block for which the RTL design has been completed, logic synthesis is performed based on the synthesis constraint conditions extracted in step S136, and the block is replaced with a black box. S138. Perform the placement and wiring inside the block replaced with the black box.

S139. In step S138, the timing in the block placed and wired is verified. If it is determined that the timing is not appropriate (No), the process returns to step S137, and the logic synthesis in the block is performed again, and steps S137, S138, and S138 are performed.
139 is executed.

S140. If it is determined in step S139 that the timing is appropriate (Yes), the wiring in the block is determined. S141. It is determined whether or not the design has been completed for all the blocks, and undesigned blocks remain (N
If it is determined as o), step S136 and subsequent steps are repeated.

On the other hand, if it is determined that the design has been completed for all the blocks (Yes), this processing procedure is terminated. In this way, the inter-block netlist is determined in advance, and the logic design / verification and logic synthesis are performed in order from the completed block, so that the chip design can be advanced in a building block manner. Since there is no return to the study of the circuit architecture from the chip design stage, the efficiency and design quality of the chip design can be improved.

[0223]

As described in detail above, the present invention provides a method for developing a large-scale integrated circuit that simultaneously performs circuit architecture study, logic design / verification, logic synthesis, and implementation design. Design efficiency and design quality can be improved.

Further, the development tool of the present invention makes it possible to concurrently conduct circuit architecture examination, logic design / verification, logic synthesis, and implementation design in the development of a large-scale integrated circuit.

As described above, the present invention can greatly contribute to the development of a large-scale integrated circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart of a development process of a large-scale integrated circuit according to the present invention.

FIG. 2 shows a principle procedure for developing a large-scale integrated circuit of the present invention.

FIG. 3 is a detailed procedure for developing a large-scale integrated circuit according to the present invention.

FIG. 4 is a detailed procedure for examining a circuit architecture.

FIG. 5 is a view for explaining assignment of flip-flops to clock ports.

FIG. 6 shows a procedure for generating physical interface information.

FIG. 7 is a diagram conceptually showing generation of a net between blocks;

FIG. 8 shows the configuration of a development tool according to the present invention.

FIG. 9 is a view for explaining the function of an RTL monitoring mode.

FIG. 10 is a schematic procedure of RTL monitoring.

FIG. 11 shows a procedure for generating RTL monitoring data.

FIG. 12 shows an example of an RTL monitoring start command.

FIG. 13 shows an RTL source monitoring procedure.

FIG. 14 is an example of an RTL monitoring result reply mail.

FIG. 15 is a diagram illustrating functions in a logic synthesis mode.

FIG. 16 shows a procedure of logic synthesis.

FIG. 17 shows an example of a logical synthesis request mail.

FIG. 18 is a processing procedure of a received mail.

FIG. 19 is a block layout procedure.

FIG. 20 shows a flow of a conventional large-scale integrated circuit development process.

FIG. 21 shows a conventional procedure for developing a large-scale integrated circuit.

[Explanation of symbols]

 Reference Signs List 1 network 2 monitoring server 3a design terminal 3b design terminal 4 mail server 5 file server 6 synthesis server

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideki Sakamoto 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka-shi, Fukuoka Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Masayuki Tsuda Hakata-ku, Fukuoka-shi, Fukuoka Fujita Kyushu Digital Technology Co., Ltd. (72) Inventor Akira Ohama 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inventor Noritoshi Yamakawa 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka, Fukuoka Prefecture F-term in Fujitsu Kyushu Digital Technology Co., Ltd. 5B046 AA08 BA01 BA03 BA04 CA03 DA05 KA01 KA10 5F064 DD03 DD25 EE54 HH06 HH10 HH12

Claims (8)

[Claims] 1. A circuit architecture study and a floor planning of a large-scale integrated circuit chip are concurrently advanced. In the circuit architecture study, port information of a block obtained by functionally dividing the chip and port information of the chip are used to connect information between ports. Generate the inter-block netlist as
A method for developing a large-scale integrated circuit, wherein the logic design / verification, the logic synthesis, the layout and the timing verification are performed concurrently as common data for verification, logic synthesis, layout and timing verification. 2. A large-scale integrated circuit according to claim 1, wherein, following the block division according to claim 1, a clock tree in the block is created and floor planning is performed, and clock skew is adjusted prior to logic design. Development method. 3. Using the result of block division according to claim 1 and an inter-block netlist, laying out blocks on a chip and laying out wiring between the blocks while leaving the blocks as black boxes; A method for developing a large-scale integrated circuit, comprising calculating the number of wirings between blocks, a fan-out, and a load caused by wirings, and using the calculated results as conditions for logic synthesis inside the blocks. 4. The logic tree according to claim 1, wherein logic synthesis is performed in order from a block for which logic design has been completed, using the clock tree described in claim 2 and the condition of logic synthesis described in claim 3. A method for developing a large-scale integrated circuit, wherein the method is inserted into a netlist between blocks. 5. A method for developing a large-scale integrated circuit, wherein a layout within a block is sequentially performed from a block on which logic synthesis is completed, and a chip layout is advanced in a building block system. 6. A design terminal which operates a designer to perform a logic design, a file server which stores an RTL source as a result of the logic design, a monitoring server which constantly monitors the RTL source, and via the network. A mail server that distributes various mails, a synthesis server that performs logic synthesis on the blocks for which the RTL design has been completed, and a network that houses the design terminal, the file server, the monitoring server, and the synthesis server. Development tools for large-scale integrated circuits. 7. The large-scale integrated circuit development tool according to claim 6, wherein the monitoring server is a monitoring server that starts monitoring according to a monitoring start request command from the design terminal. Development tools for integrated circuits. 8. The development tool for a large-scale integrated circuit according to claim 6, wherein the synthesis server is a synthesis server that starts logic synthesis according to a synthesis request command from the design terminal or the monitoring server. Development tools for large-scale integrated circuits.