JP3956382B2 - measuring device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a measurement apparatus, and more particularly to an improvement in capturing measurement data into a memory.
[0002]
[Prior art]
FIG. 3 is a block diagram showing an example of a system for fetching measurement data into a memory in a conventional digital oscilloscope.
The analog measurement signal is input to the A / D converter 001 and converted into a digital signal. The digital signal converted and output from the A / D converter 001 is written and stored in a memory 002 such as an SRAM. The conversion operation of the A / D converter 001 and the write operation of the memory 002 are performed in synchronism based on the clock input from the clock generator 004. The trigger generator 005 generates a trigger signal for determining a starting point for taking measurement data into the memory 002 and outputs the trigger signal to the memory address controller 003. The memory address controller 003 outputs an enable signal EN that permits writing of measurement data to the memory 002 based on the trigger signal input from the trigger generator 005.
[0003]
Thus, the measurement data is written from the A / D converter 001 to the memory 002 in synchronization with the clock input from the clock generator 004. Note that the memory address controller 003 also counts up the memory address in synchronization with the clock input from the clock generator 004.
[0004]
FIG. 4 is an explanatory diagram of memory address control by the conventional memory address controller 003. When a trigger signal is input from the trigger generator 005, an enable signal EN that permits writing of measurement data is output to the memory 002, and the memory 002 writes measurement data from address 0000 according to the memory address. When the memory address reaches the address xxxxx, a disenable signal is output from the memory address controller 003 to the memory 002, and the writing of the measurement data is completed.
[0005]
However, although this method is the simplest memory control method, there is a problem that only measurement data after the trigger signal is input can be captured.
In general, in a digital oscilloscope, a logic analyzer, or the like, it is desirable to be able to measure a state before a trigger signal is output, and it is also necessary to write measurement data before the trigger signal is output to the memory 2.
[0006]
FIG. 5 is an explanatory diagram of memory address control in which measurement data before a trigger signal is output can also be written into the memory 002. The measurement data is written to the memory 002 in FIG. 5 repeatedly from the address 0000 to the address xxx in accordance with the memory address before the trigger signal is output.
[0007]
When a trigger signal is output in this state, the memory address controller 003 outputs the enable signal EN to the memory 002 for a predetermined memory length, and counts up the memory address to increase the memory 002. Write measurement data to. When writing for a predetermined memory length is completed, a disenable signal is output from the memory address controller 003 to the memory 002, and writing of the measurement data is completed.
[0008]
That is, since the measurement data is written in the memory 002 before the trigger signal is generated, the memory length to be written after the trigger signal is generated is determined as the post-trigger memory area (B). Measurement data before the generation of the trigger signal is written as an area (A = T−B).
[0009]
Although FIG. 3 shows an example of a digital oscilloscope, since an input signal in the case of a logic analyzer is a digital signal, it may be replaced with a data latch circuit such as a flip-flop instead of the A / D converter 001.
[0010]
FIG. 3 illustrates an example in which an SRAM that does not require a refresh operation and can be written and read as needed is used as the memory 002. However, the SRAM is expensive and has a large mounting area, and has a large capacity for storing a large amount of data. Memory implementation is difficult.
Therefore, for example, a hard disk 103 is used as means for realizing a large-capacity memory at a low cost as shown in FIG.
[0011]
In FIG. 6, a digital signal converted and output from the A / D converter 101 is written in a FIFORAM (First In First Out RAM) 102. The operations of the A / D converter 101 and the FIFO RAM 102 are performed in synchronization with the clock input from the clock generator 104.
[0012]
On the other hand, data writing from the FIFO RAM 102 to the hard disk 103 differs depending on whether or not a seek or the like occurs depending on the data writing position to the hard disk 103, so the CPU 107 is executed at random asynchronous timing while monitoring and determining the status of the hard disk 103. To do. The FIFO controller 106 controls the read / write timing of the FIFO RAM 102 so that the FIFO RAM 102 absorbs such asynchronous deviation of timing.
[0013]
The FIFO controller 106 performs control to add 1 to the count value of the internal counter in synchronization with the clock input from the clock generator 104 and to subtract 1 according to the write signal input from the CPU 107. When the counter value is equal to or smaller than a predetermined value, permission is given to writing from the CPU 107.
This
When the relationship of clock cycle> write time from the CPU 107 is established, the counter value remains constant, and the FIFO RAM 102 functions normally as a buffer memory.
[0014]
The trigger generator 105 starts the FIFO by the FIFO controller 106 from the time when the trigger signal is generated, and starts to take in the measurement data. 6 differs from FIG. 3 in that an address control circuit is not required. This is based on the fact that the CPU 107 can freely determine an address for writing the measurement data because the CPU 107 is interposed in writing the measurement data to the hard disk 103.
[0015]
[Problems to be solved by the invention]
However, when the hard disk 103 is used as a large-capacity memory in this way, the measurement data must always be written to the hard disk 103 in order to capture the measurement data before the trigger signal is generated.
However, since the hard disk 103 is always in contact with the head during operation, there is a problem that the reliability is remarkably lowered if the hard disk 103 is used continuously for a long period of time.
[0016]
The present invention, which focuses on problems of a measuring device using such a conventional large-capacity memory, and an object, when capture also the measurement data before the trigger signal is generated, as a large capacity memory An object of the present invention is to provide a measuring apparatus that improves the reliability of a memory by reducing the number of accesses to a hard disk used .
[0017]
[Means for Solving the Problems]
Among the aspects of the present invention that achieves such an object, the invention according to claim 1 is a measurement apparatus that controls storage of measurement data based on a trigger signal.
It has a semiconductor memory in which measurement data before trigger signal generation is repeatedly stored, and a hard disk in which measurement data after trigger signal generation is stored,
In the pre-trigger area until the trigger signal is output , the measurement data is stored in the semiconductor memory repeatedly according to the memory address output from the memory address controller.
In the post-trigger area after the trigger signal is generated , the measurement data is stored in the hard disk by accessing intermittently only from the time when the trigger signal is generated until the measurement data for a predetermined length is written. It is characterized by.
[0018]
As a result, the number of accesses to the large-capacity memory is greatly reduced, and the reliability of the large-capacity memory is increased.
[0019]
According to a second aspect of the present invention, in the measuring apparatus according to the first aspect, the semiconductor memory is an SRAM.
[0020]
The SRAM does not require a refresh operation and can realize a high-speed operation.
[0021]
According to a third aspect of the present invention, in the measuring apparatus according to the first aspect, the semiconductor memory is a DRAM.
[0022]
Although DRAM requires a refresh operation, the capacity can be increased relatively inexpensively.
[0024]
According to a fourth aspect of the present invention, in the measuring apparatus according to the first aspect, a magneto-optical disk is used in place of the hard disk .
[0025]
A hard disk with a large capacity can be obtained at a relatively low cost, and a magneto-optical disk can be carried while the storage medium is replaced.
[0026]
According to a fifth aspect of the present invention, in the measuring apparatus according to the first aspect, a part of the measurement data stored in the semiconductor memory and the hard disk is overlapped after the trigger signal is generated.
[0027]
As a result, it is possible to prevent missing measurement data when switching the storage destination of measurement data from the semiconductor memory to the large-capacity memory when the trigger signal is generated.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
FIG. 1 is a block diagram showing an example of an embodiment of the present invention. In the figure, the digital signal converted and output from the A / D converter 201 is written in the FIFO RAM 202. The operations of the A / D converter 201 and the FIFO RAM 202 are performed in synchronization with the clock input from the clock generator 204.
[0029]
On the other hand, the writing of data from the FIFO RAM 202 to the hard disk 203 used as a large-capacity memory differs depending on whether or not a seek or the like is generated depending on the data writing position to the hard disk 203. Execute at asynchronous timing. The FIFO controller 206 controls the read / write timing of the FIFORAM 202 so that the FIFORAM 202 absorbs such asynchronous timing shift, but the read / write timing of the FIFORAM 202 differs before and after the trigger signal is generated.
[0030]
In the pre-trigger area until the trigger signal is generated, the conversion operation of the A / D converter 201 and the write operation to the FIFO RAM 202 are performed in synchronization with the clock input from the clock generator 204, and the CPU 207 stores the data in the memory 208. Writing of measurement data is always repeated between address 0000 and address xxx according to the memory address input from the memory address controller 209.
[0031]
In the post-trigger area after the trigger signal is generated, the writing of the measurement data to the memory 208 is completed, and the CPU 207 writes the measurement data to the hard disk 203 as in FIG. The memory length of the post-trigger area may be arbitrarily set by the user, and the CPU 207 finishes writing the measurement data when the measurement data having a predetermined length is written.
[0032]
FIG. 2 is an explanatory diagram of the memory address control of FIG. In the pre-trigger state until the trigger signal is output, the measurement data is written to the memory 208 repeatedly at addresses from 0000 to xxxxxx in accordance with the memory address input from the memory address controller 209. ing.
When the trigger signal is generated, measurement data writing is switched from the memory 208 to the hard disk 203. This switching may be performed by hardware using, for example, a switch unit or may be performed by software by the CPU 207.
[0033]
As a result, measurement data from before the trigger signal is generated is written to the memory 208, and measurement data after the trigger signal is generated is written to the hard disk 203 for a predetermined length set by the user.
That is, the hard disk 203 is intermittently accessed only from when the trigger signal is generated until measurement data of a predetermined length set by the user is written, and the hard disk 103 as shown in FIG. The number of accesses can be greatly reduced compared to the configuration of only the above, and high reliability can be realized.
[0034]
In addition, since it takes some time from the generation of the trigger signal to the switching of the measurement data writing from the memory 208 to the hard disk 203, the trigger signal is generated in order to prevent the measurement data from leaking during this time. For a while, the writing to the memory 208 is continued in parallel with the writing to the hard disk 203. The CPU 207 determines the joint of the measurement data between the memory 208 and the hard disk 203 by detecting the overlapping portion of the measurement data between the memory 208 and the hard disk 203.
[0035]
In the above embodiment, an example in which an SRAM is used as the semiconductor memory has been described. However, a DRAM may be used if the circuit configuration can be complicated.
[0036]
The large capacity memory may be a magneto-optical disk. Although the magneto-optical disk has a smaller storage capacity per storage medium than the hard disk, it has the convenience that the storage medium itself can be exchanged or carried.
[0037]
【The invention's effect】
As described above, according to the present invention, the number of accesses to the large-capacity memory can be reduced in the measurement apparatus that controls the storage of the measurement data based on the trigger signal. Can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an embodiment of the present invention.
2 is an explanatory diagram of memory address control in FIG. 1; FIG.
FIG. 3 is a block diagram showing an example of a conventional measuring apparatus.
4 is an explanatory diagram of memory address control of FIG. 3; FIG.
FIG. 5 is an explanatory diagram of memory address control of the pre-trigger in FIG. 3;
FIG. 6 is a block diagram showing another example of a conventional measuring apparatus.
[Explanation of symbols]
201 A / D converter 202 FIFORAM
203 Large-capacity memory (hard disk)
204 Clock generator 205 Trigger generator 206 FIFO controller 207 CPU
208 Semiconductor memory (SRAM)
209 Memory address controller

Claims (5)

In a measurement device that controls storage of measurement data based on a trigger signal,
It has a semiconductor memory in which measurement data before trigger signal generation is repeatedly stored, and a hard disk in which measurement data after trigger signal generation is stored,
In the pre-trigger area until the trigger signal is output , the measurement data is stored in the semiconductor memory repeatedly according to the memory address output from the memory address controller.
In the post-trigger area after the trigger signal is generated , the measurement data is stored in the hard disk by accessing intermittently only from the time when the trigger signal is generated until the measurement data for a predetermined length is written. Measuring device characterized by. The measuring apparatus according to claim 1,
A measuring apparatus, wherein the semiconductor memory is an SRAM. The measuring apparatus according to claim 1,
A measuring apparatus, wherein the semiconductor memory is a DRAM. The measuring apparatus according to claim 1,
A measuring apparatus using a magneto-optical disk instead of a hard disk. The measuring apparatus according to claim 1,
A measurement apparatus characterized by overlapping a part of measurement data stored in a semiconductor memory and a hard disk after generation of a trigger signal.

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