JP3953131B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having an FM detection circuit using an inverter.
[0002]
[Prior art]
In general, in a quadrature FM detection circuit using an inverter as a delay circuit, the FM detection circuit and an oscillation circuit composed of inverters having the same characteristics as the inverter are integrated on the same substrate, and the inverter is calculated from the oscillation frequency of the oscillation circuit. There is an integrated circuit that detects the characteristics of the delay circuit and adjusts the delay time of the delay circuit according to the characteristics of the inverter. Such an integrated circuit is shown in FIG.
[0003]
In FIG. 2, the control circuit 1 is connected to the external pins 2, 3 and 4 in the adjustment process of the manufacturing process. When the oscillation control signal f is applied to the external pin 2 and the oscillation circuit 5 is operated, the oscillation signal g of the oscillation circuit 5 is applied to the control circuit 1 via the external pin 3. The control circuit 1 detects the frequency of the oscillation signal g and detects the delay time of the inverter of the oscillation circuit 5 from the frequency. In accordance with the detected delay time, a selection control signal h is generated from the control circuit 1 and applied to the selection signal generation circuit 6 via the external pin 4. Further, the selection signal i is applied from the selection signal generation circuit 6 to the selection circuit 8 of the FM detection circuit 7. In response to the selection signal i, the selection circuit 8 selects one of the output signals of the delay circuits 9 to 11. After the selection, the control circuit 1 is removed and the adjustment process ends.
[0004]
By the way, since the oscillation circuit 5 and the delay circuits 9 to 11 are integrated on the same substrate so that the inverter characteristics are the same, the delay circuits 9 to 11 are detected by detecting the inverter characteristics of the oscillation circuit 5. The characteristics of 11 inverters can be known. Since the delay circuits 9 to 11 are configured by changing the number of inverters, the control circuit 1 calculates the delay times of the delay circuits 9 to 11 based on the delay time of the inverters. In the FM detection circuit 7, when the delay time of the delay circuit changes, the phase relationship between the two input signals of the multiplier 12 changes, so that the phase difference of the input signal of the multiplier 12 is calculated from the calculated delay time by 90 degrees. The delay time is selected. Then, a selection control signal h for selecting a delay circuit that can obtain this delay time is generated from the control circuit 1. In response to the selection control signal h, the selection signal generation circuit 6 holds a state in which the selection signal i for selecting the output signal of the delay circuit having the optimum delay time is generated. In this way, one of the output signals of the delay circuits 9 to 11 is selected.
[0005]
During normal radio reception operation, the RF signal is frequency-converted to an IF signal by the front end 14, and the IF signal is amplified by the IF amplifier circuit 15 and then delayed by the delay circuits 9 to 11. Then, one output signal of the delay circuits 9 to 11 is selected by the selection circuit 8 and applied to the multiplier 12. The multiplier 12 multiplies the IF signal and the output signal of the selection circuit 8 and then smoothes the output signal of the multiplier 12 to obtain an FM detection signal. Since the output signal of the delay circuit optimum for the FM detection characteristic is selected, the phase difference between the two input signals of the multiplier 12 is 90 degrees, and a good FM detection characteristic is obtained.
[0006]
[Problems to be solved by the invention]
However, in the circuit of FIG. 2, the external pins 2, 3, and 4 are necessary to adjust the detection characteristics of the FM detection circuit 7, which causes a problem that the number of external pins increases. In an IC, since the number of external pins is limited, the problem of an increase in external pins is serious.
[0007]
[Means for Solving the Problems]
The present invention relates to a plurality of delay circuits that respectively delay IF signals with different delay times, a selection circuit that selects one of the output signals of the plurality of delay circuits, and the IF signal multiplied by the output signal of the selection circuit In a semiconductor integrated circuit for a radio receiver, comprising: an FM detection circuit including a multiplying circuit that performs the same; and an oscillation circuit configured with the same delay element as the delay elements constituting the plurality of delay circuits. A reference signal generation circuit that generates a reference signal according to whether or not it is connected to a pin, and a first switch circuit that turns on the oscillation circuit according to the reference signal.
[0008]
The reference signal generation circuit includes a current mirror circuit, a transistor having a collector connected to the input side of the current mirror circuit, an emitter connected to the external resistor, and a reference voltage applied to a base, and the current mirror circuit And a resistor for converting the output current into a reference signal.
And an output circuit for deriving an output signal of the oscillation circuit to an external circuit, and a second switch circuit for detecting that the external resistor is not connected and turning on the output circuit. Features.
[0009]
Furthermore, an external pin for generating a detection output signal of the FM detection circuit and an external pin for generating an output signal of the output circuit are also used.
Still further, the reference signal is used in another utilization circuit in the semiconductor integrated circuit.
According to the present invention, the oscillation circuit can be oscillated unless an external resistor for generating a reference signal is connected, and the oscillation operation of the oscillation circuit can be stopped when an external resistor is connected. Therefore, the external pin for generating the reference signal can be used as the external pin for controlling the operation of the oscillation circuit.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing an embodiment of the present invention, in which 16 is an electric field strength detection circuit for detecting electric field strength in accordance with an output signal of the IF amplifier circuit 15, and 17 is for inverting the output signal of the electric field strength detection circuit 16. A current mirror circuit, 18 is a resistor for converting the output signal of the current mirror circuit 17 to generate a field strength instruction signal e, 19 is an external pin to which an external resistor R is connected, and 20 is a reference to the base A voltage Vref is applied, a transistor 21 that generates a reference current according to the external resistor R, a current mirror circuit 22 that inverts the reference current, and an output current of the current mirror circuit 22 is converted into a reference signal d. A reference signal generating circuit 24 comprising a resistor 23 for generating a signal, 24 is a station detecting circuit for comparing the electric field strength indicating signal e and the reference signal d and generating a station detecting signal, and 25 and 26 are respectively 1 and the second switch circuit, the transistor to which the reference signal d is applied, 27 is a current mirror circuit that is turned on or off in accordance with the output signal of the transistor 26, and 28 is the oscillation current generated by the output current of the current mirror circuit 27 An output circuit 29 for outputting the oscillation signal of the circuit 5 and an external pin 29 for generating the output signal of the FM detection circuit 7 and the output signal of the output circuit 28 are provided. In FIG. 1, the same circuits as those in FIG.
[0011]
First, in the adjustment process of the manufacturing process, the external pin 19 is opened, and the control circuit 1 is connected to the external pins 4 and 29. Since the external pin 19 is in an open state, the transistor 21 is turned off and the current mirror circuit 22 is also turned off. Since no output current is generated from the current mirror circuit 22, the voltage drop of the resistor 23 does not occur, and the base voltages of the transistors 25 and 26 become substantially equal to the ground level. Therefore, the transistors 25 and 26 are turned off. When the transistor 25 is turned off, the input on the transistor 25 side of the NAND gate G in the oscillation circuit 5 becomes “H”, and the NAND gate G becomes conductive. As a result, the oscillation circuit 15 is turned on and the oscillation signal a is generated. When the transistor 26 is turned off, the current mirror circuit 27 is turned on, and the output current of the current mirror circuit 27 flows to the output circuit 28 as an operating current. Therefore, the output circuit 28 is turned on, and the output circuit 28 supplies the oscillation signal a to the external pin 29. Therefore, by opening the external pin 19 connected to the reference signal generation circuit 20, the oscillation circuit 5 is oscillated and the output circuit 28 is operated to transmit the oscillation signal a to the subsequent circuit. .
[0012]
The oscillation signal a ′ from the output circuit 28 is applied to the control circuit 1 via the external pin 29. In the control circuit 1, the delay characteristic of the inverter in the IC is detected according to the oscillation frequency of the oscillation signal a ′, and the selection control signal b is generated according to the delay characteristic. The selection control signal b is applied to the selection signal generation circuit 6 through the external terminal 4. A selection signal c is generated from the selection signal generation circuit 6 in response to the selection control signal b, and an output signal of the delay circuit having the optimum delay time is selected from the delay circuits 9 to 11 based on the selection signal c. When the selection of the output signals of the delay circuits 9 to 11 is finished, the control circuit 1 is removed and the adjustment process is finished.
[0013]
Thereafter, when the circuit of FIG. 1 is used as a radio receiver, the external resistor R is connected to the external terminal 19. The connection of the external resistor R turns on the transistor 21, and a reference current set by the external resistor R is generated from the collector of the transistor 21. The reference current is inverted by the current mirror circuit 22 and then supplied to the resistor 23, and the reference signal d is generated by the voltage drop of the resistor 23. The reference signal d is applied to the bases of the transistors 25 and 26, and both the transistors 25 and 26 are turned on. When the transistor 25 is turned on, one input of the NAND gate G becomes “L”, so that the NAND gate G becomes non-conductive and the oscillation operation of the oscillation circuit 5 is prohibited. Further, when the transistor 26 is turned on, the base of the transistor constituting the current mirror circuit 7 is grounded and the current mirror circuit 27 is turned off, so that the supply of the operating current of the output circuit 28 is stopped. Turn off. The reference signal d is originally applied to the comparison circuit 24 and used as a reference level for station detection based on the received electric field strength. Therefore, by connecting the external resistor R, the oscillation operation of the oscillation circuit 5 can be stopped and the operation of the output circuit 28 can be stopped.
[0014]
In such a state, the reception RF signal is frequency-converted to an IF signal by the front end 14, and the IF signal is amplified by the IF amplifier circuit 15. The output signal of the IF amplifier circuit 15 is FM detected by the FM detection circuit 7. Since the output signal of the delay circuit having the optimum delay time among the delay circuits 9 to 11 is selected by the selection signal c in the FM detection circuit 7, a good detection characteristic can be obtained. The FM detection signal is transmitted to an external circuit via the external terminal 29. Since the output terminal of the output circuit 28 is in a high impedance state by being turned off, the output circuit 28 does not adversely affect the transmission of the detection signal.
[0015]
Further, the received field strength is detected by the field strength detection circuit 16 in accordance with the output signal of the IF amplifier circuit 15. The output current of the electric field strength detection circuit 16 is supplied to the resistor 18 via the current mirror circuit 17. Due to the voltage drop of the resistor 18, an electric field strength instruction signal e is generated and applied to the comparison circuit 24. In the comparison circuit 24, when the electric field strength instruction signal e is higher than the reference signal d, a station detection signal indicating that a station has been detected is generated from the comparison circuit 24. As described above, the on / off control of the operations of the oscillation circuit 5 and the output circuit 28 is performed using the external pin for generating the reference signal for station detection. There is no need to provide a dedicated pin for control.
[0016]
In FIG. 1, the reference signal generation circuit 20 is used for the comparison circuit 24 for performing the station detection. However, the reference signal generation circuit 20 oscillates by using the reference signal generation circuit for applying the reference signal to the other circuits of the station detection circuit. The operations of the circuit 5 and the output circuit 28 may be controlled.
[0017]
【The invention's effect】
According to the present invention, if an external resistor for generating a reference signal is connected, the oscillation circuit can be oscillated, and if no external resistor is connected, the oscillation operation of the oscillation circuit can be stopped. An external pin for generating a signal and an external pin for controlling the operation of the oscillation circuit can be used together, and an increase in the number of external pins can be prevented.
[0018]
Further, since the reference signal generation circuit is turned on or off depending on whether or not an external resistor is connected to the transistor, the operation of the oscillation circuit can be easily controlled only by connecting the external resistor.
Furthermore, if an external resistor for generating the reference signal is not connected, the oscillation signal is transmitted to an external circuit, and if an external resistor is connected, the oscillation signal output from the oscillation circuit is prohibited. Signal transmission is prevented, and adverse effects due to the oscillation signal can be prevented. For this reason, it is possible to use both an external pin for generating an oscillation signal and an external pin for the FM detection signal, thereby preventing an increase in the number of external pins.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Control circuit 4, 19, 29 External pin 5 Oscillation circuit 6 Selection signal generation circuit 7 FM detection circuit 8 Selection circuit 9, 10, 11 Delay circuit 12 Multiplication circuit 13 Smoothing circuit 14 Front end 15 IF amplification circuit 16 Electric field strength detection Circuits 17, 22, 27 Current mirror circuit 18, 23 Resistor 20 Reference signal generating circuit 21, 25, 26 Transistor 24 Station detection circuit 28 Output circuit

Claims (5)

A plurality of delay circuits that respectively delay the IF signal with different delay times; a selection circuit that selects one of the output signals of the plurality of delay circuits; and a multiplication circuit that multiplies the IF signal and the output signal of the selection circuit. In a semiconductor integrated circuit for a radio receiver comprising: an FM detection circuit including: an oscillation circuit configured by a delay element that is the same as a delay element that configures the plurality of delay circuits;
A reference signal generating circuit for generating a reference signal according to whether or not an external resistor is connected to an external pin; and
A first switch circuit for turning on the oscillation circuit in response to the reference signal;
A semiconductor integrated circuit comprising: The reference signal generation circuit includes:
A current mirror circuit; a collector connected to the input side of the current mirror circuit; an emitter connected to the external resistor; a reference voltage applied to a base; and an output current of the current mirror circuit converted into a reference signal 2. The semiconductor integrated circuit according to claim 1, comprising a resistor for the purpose. An output circuit for deriving an output signal of the oscillation circuit to an external circuit, and a second switch circuit that detects that the external resistor is not connected and turns on the output circuit. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 3, wherein an external pin that generates a detection output signal of the FM detection circuit is also used as an external pin that generates an output signal of the output circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the reference signal is used in another utilization circuit in the semiconductor integrated circuit.

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