JP3951760B2 - controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a controller.
[0002]
[Prior art]
As one of the control methods of output devices in PLC (programmable controller) and other controllers, it outputs a pulse based on the pulse output function built in the CPU unit of the PLC, and the output device follows the pulse (ON / OFF signal) There is a working system.
[0003]
As an example, as shown in FIG. 1, for example, there is a system that controls the operation of the drive motor of the belt conveyor apparatus 1. That is, the PLC 2 includes a power supply unit 2a and a CPU unit 2b, and a rotary encoder 4 rotates a main motor (a motor that drives a device different from the belt conveyor device 1) 3 to an I / O terminal 2b 'of the CPU unit 2b. And a pulse corresponding to the rotation speed is given as input information. The CPU unit 2b performs calculation based on the received input information (frequency of the input pulse), and determines operating conditions such as the rotational speed of the drive motor (motor that drives the belt conveyor device 1). In this calculation process, for example, the ratio of the output frequency to the input frequency is given as a “ratio setting value” in advance, and when the frequency of the input pulse is acquired, the frequency of the pulse output (output frequency) is obtained based on the ratio setting value, A pulse is output so that the output frequency is obtained.
[0004]
The operation of the motor driver is controlled according to this pulse output. That is, this output pulse is given to the motor driver 5 for the drive motor. Then, the motor driver 5 drives the drive motor by one step with the input of one pulse. Accordingly, the higher the frequency of the output pulse, the higher the rotation speed of the drive motor and thus the conveying speed in the belt conveyor apparatus 1.
[0005]
As a result, when the rotation speed of the main motor 3 is changed, the frequency of the input pulse is changed. Accordingly, the frequency of the output pulse is also changed at a constant ratio, and the rotation of the drive motor of the belt conveyor device 1 is followed accordingly. The number changes. Therefore, synchronous control can be performed in which the rotation speed of the main motor 3 and the rotation speed of the drive motor rotate while maintaining a constant ratio.
[0006]
For example, as shown in FIG. 2, the MPU counts the input pulses (counter input) as a process (1) as shown in FIG. 2, and from the number of pulses input within a predetermined time, Find the frequency of the input pulse. Next, as processing (2), an output frequency with respect to the input frequency obtained in processing (1) is obtained. Specifically, it is obtained by multiplying the input frequency by a preset ratio setting value.
[0007]
Next, as a process (3), a pulse output is set at the output frequency obtained in the process (2). Thereby, after this setting, a pulse is continuously output so that it may become the set output frequency.
[0008]
Furthermore, when the setting of the output frequency is completed as described above, another process is executed as process (4). Then, the processes (1) to (4) described above are executed at intervals of about 10 msec, for example.
[0009]
[Problems to be solved by the invention]
In the conventional control system, once the output frequency is set, the frequency is fixed for a period of about 10 ms of the control cycle, so that an error occurs between the ideal and actual output frequency. Furthermore, since the frequency is calculated from the number of pulses within a certain time, the accuracy is lowered.
[0010]
Furthermore, the conventional control obtains the input frequency based on the input pulse, calculates the output frequency using the ratio setting value therefrom, and actually sets the output frequency based on it. There is a time lag (time to execute steps (1) to (3) in FIG. 2) from when the input frequency actually changes to when the output frequency actually changes. I can't.
[0011]
An object of the present invention is to provide a controller that can quickly reflect a change in an input frequency in an output frequency.
[0012]
[Means for Solving the Problems]
In the controller according to the present invention, an input frequency detection unit that obtains frequency information of an input pulse, a storage unit that stores the frequency information obtained by the input frequency detection unit, and the frequency information stored in the storage unit On the other hand, calculation means for calculating an output frequency setting value of pulse output by performing arithmetic processing based on a predetermined ratio setting value, and a pulse for performing pulse output based on the output frequency setting value output from the calculation means Output means, and the pulse output means has a function of outputting a request signal instructing the calculation means to execute the arithmetic processing based on a state of pulse output, the calculation means from the pulse output means When the request signal is received, the arithmetic processing is executed . The request issuance timing can be performed, for example, every time one pulse is output.
[0013]
Here, the frequency information of the pulse may be the frequency itself or a count value (time) as in the embodiment. In short, it may be anything corresponding to the frequency. The input frequency detection unit corresponds to the frequency counter unit 22 in the embodiment. The storage means corresponds to the latch unit 23 in the embodiment. The calculating means corresponds to the ratio dividing unit 24 in the embodiment. In the embodiment, the storage unit corresponds to the latch unit 23 which is a form of the temporary storage unit.
[0014]
The function of the pulse output means, “to output a request signal instructing the calculation means to execute the arithmetic processing based on the state of pulse output” is a request when the pulse output is in a predetermined state. The predetermined state can be, for example, the end of one cycle of pulse output (before a predetermined period with reference to the end). As described above, when a request is issued at the end of one cycle, it is possible to determine the frequency of the pulse output in accordance with the current frequency state of the input pulse. Of course, in the present invention, calculating the input frequency using the pulse output side as a trigger and calculating the frequency of the pulse output is one of the features, and therefore, a request is issued based on the end of one cycle of the pulse output. For example, a request may be issued based on an arbitrary point (reference) in addition to issuing a request at an intermediate point of pulse output (a switching point between ON and OFF within one cycle). it can.
[0015]
Further, the controller of the present invention corresponds to the CPU unit 2b in the embodiment, but the entire PLC main body may of course be used. That is, it includes a controller (control device) for FA that inputs a pulse having a predetermined frequency and outputs a pulse having an arbitrary frequency according to the frequency.
[0016]
According to the present invention, the storage means always stores and holds the latest frequency information of the input pulse. Then, the calculation means is operated according to the request signal issued based on the state of the pulse output, and the output frequency setting value of the pulse output is based on the frequency information of the previous input pulse stored when the request signal is received. Therefore, quick and accurate synchronous control can be performed.
[0017]
Further, when the rising or falling edge of the input pulse is used as a reference change point, the input frequency detecting means is based on a period from detection of the reference change point to detection of the next reference change point. The frequency information is obtained, and it is preferable to provide a function of stopping the pulse output when the period is equal to or greater than a certain value.
[0018]
That is, if the frequency information is obtained based on the period from the rising edge of the pulse to the rising edge of the next pulse, or from the falling edge to the next falling edge, for example, the frequency becomes extremely low, noise or other It may take time for the next pulse reference change point to occur due to the factor. In this case, the latest frequency information is based on the previous input pulse, and the deviation from the actual one becomes large. On the other hand, according to the present invention, since the pulse output is stopped when the input pulse is stopped or the frequency becomes extremely low, more accurate control can be performed.
[0019]
In addition, storage means for storing the output frequency lower limit setting value is provided, and the calculation means is configured such that the output frequency setting value of the pulse output obtained by the arithmetic processing is greater than the output frequency lower limit setting value stored in the storage means. When the frequency becomes low, the output frequency lower limit set value can be output as the output frequency set value. Since the frequency is low, for example, when the frequency information is a count value (time), a large (long) value is obtained.
[0020]
In this way, when the frequency of the output frequency set value obtained by the calculating means is low, the output is performed based on the output frequency lower limit set value, so there is no possibility that an output frequency lower than a certain level is output.
[0021]
Furthermore, a ratio set value storage means for storing the ratio set value may be provided, and a means for changing the ratio set value stored in the ratio set value storage means during operation of the controller may be provided. In this way, since the condition can be changed in the middle, more accurate control can be performed.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 is an example of an internal structure showing a preferred embodiment of the CPU unit 2b which is an aspect of the controller according to the present invention. As shown in FIG. 3, a counter block 20 that executes a predetermined calculation process on a counter input given via the I / O terminal 11 and an actual pulse according to the output frequency of the output pulse obtained by the counter block 20 It has a pulse block 30 for outputting. The output of the pulse block 30 is connected to the I / O terminal 11 and is given to a motor driver (not shown) through the I / O terminal 11. The counter block 20 and the pulse block 30 are both configured by hardware.
[0023]
There are a plurality of types of signals as pulse signals input from an encoder (see FIG. 1) of the main motor (not shown). There are various combinations, but in this embodiment, there are a signal A for obtaining the frequency and a signal B for obtaining the rotation direction. These two signals A and B are given to the input pulse converter 21 of the counter block 20, where a Feed signal and a Dir signal are output through a predetermined conversion process. In other words, in the example shown in FIG. 1, one pulse is output each time the encoder rotates by a reference angle, but the Feed signal is output from the encoder and is turned ON / OFF in synchronization with the pulse input to the CPU unit. It becomes a pulse signal. Further, the Dir signal is a signal that becomes High / Low in accordance with the rotation direction (forward / reverse rotation) of the main motor in the example shown in FIG. 1, for example.
[0024]
The Feed signal and the Dir signal are given to the frequency counter unit 22. The frequency counter unit 22 has a counter function of counting up according to the CPU clock and other reference clocks, and counts one period of the Feed signal (input pulse), that is, from the rising edge of a certain pulse to the next rising edge. When the next rising edge is detected, the count value is set to 0 and restarted.
[0025]
The output of the frequency counter unit 22 is given to the latch unit 23. The latch unit 23 latches a value (count value) based on the frequency of the latest input pulse. Specifically, for the input frequency (count value), the latch unit 23 monitors the value and calculates the previous count value. Temporarily stored, and when the count value reaches 0, the previous count value (count value corresponding to the frequency of the current input pulse) is latched.
[0026]
Further, when the count value is restarted on the frequency counter unit 22 side (when the rising edge of the next pulse is detected), if the count value at that time is given to the latch unit 23 at the next stage, the latch unit 23 side It is only necessary to wait for the count value to be transferred from the frequency counter unit 22 and hold the transferred count value.
[0027]
Further, a direction signal (Dir signal) specifying the current direction output from the frequency counter unit 22 is also input to the latch unit 23. The direction signal acquisition timing may be obtained by, for example, acquiring and latching a direction signal when the input frequency count value is latched by the latch unit 23, or the frequency counter unit 22 may be sequentially latched in the through state. 23 may be input.
[0028]
Thus, the latch unit 23 holds the acquired count value and direction until the frequency counter unit 22 is restarted next time. Therefore, as described above, the latch unit 23 always stores a value (count value) based on the latest frequency of the input pulse.
[0029]
Of the information held in the latch unit 23, the count value is given to the ratio divider 24 at a predetermined timing (actually, the ratio divider 24 reads), and the Dir signal is the pulse of the pulse block 30. It is given to the output unit 31. The ratio dividing unit 24 calculates the current (latest) input pulse frequency (count value) acquired from the latch unit 23 using the ratio setting value (n) stored in the ratio setting register 26, and outputs the output frequency. Obtain the set value (count value).
[0030]
That is, a predetermined value from n = (1/256) to 256 is set in the ratio setting register 26. Therefore, if the current input frequency count value is 4096 and the ratio set value is 1/16, the output frequency count value is 256 as shown in FIG.
[0031]
The arithmetic processing in the ratio divider 24 is executed using a request signal output from the pulse output unit 31 to the ratio divider 24 as a trigger. This request signal is issued when one cycle of the current pulse output from the pulse output unit 31 ends (actually, several clocks before considering the processing time).
[0032]
The ratio divider 24 that has received this request signal executes a predetermined calculation process as described above. When the calculation process ends, the ratio divider 24 issues a permission signal to the pulse output unit 31 and obtains it. Send the output pulse frequency setting value (count value). Therefore, the pulse output unit 31 sets the frequency (count value) of the next pulse output according to the output pulse frequency setting value received after receiving the permission signal, and outputs the pulse. A direction signal is also output together with this pulse output. These pulse output and direction signal are given to an output device (motor driver or the like) via the I / O terminal 11.
[0033]
The above-described configuration is a basic configuration, which operates as shown in the timing chart of FIG. That is, on the counter block 20 side, the frequency is measured by the frequency counter unit 22 for each pulse of the counter input (1), and the current latest input pulse frequency (count value) is stored in the latch unit 23 ( 2). The processes (1) and (2) are repeatedly executed every time a pulse is input regardless of other processes (see FIG. 6). The numbers in parentheses described above indicate each processing step in the flowchart shown in FIG. 6 and the timing position in the timing chart shown in FIG. 5 when the processing step is executed. This also applies to the relationship between FIGS. 5 and 7 shown below.
[0034]
On the other hand, as shown in FIG. 5 and FIG. 7, when the pulse output is started as the synchronous control in the pulse block 30 (3), the pulse block 30 (pulse output unit) is output before the pulse output is output for one cycle (several clocks). A request signal is output from (31) (4).
[0035]
Then, the ratio divider 24 of the counter block 20 that has received this request signal obtains the current latest input frequency latched in the latch part 23 (5), and with respect to the input frequency obtained from the ratio setting register 26. The output frequency is calculated using the ratio of output frequencies (ratio setting value) (6).
[0036]
When the calculation is completed, a permission signal is returned from the counter block 20 (ratio divider 24) to the pulse block 30 (pulse output unit 31), and the next output frequency is output (7). When one pulse is output, the pulse is continuously output at the output frequency of the calculation result (8).
[0037]
In addition to the basic configuration described above, the present embodiment further adds the following functions to execute more accurate and stable control. First, the latch unit 23 is given the input frequency lower limit setting value set in the input frequency lower limit setting register 25. When the frequency of the input pulse is equal to or lower than the set frequency, the latch unit 23 determines that the input frequency is 0, It has a function to make the value of.
[0038]
That is, in this embodiment, since the rising edge of the input pulse is counted from the rising edge to the next rising edge, when the next rising edge cannot be detected, the count value continues to increase and is reset to 0. If not started, a new input frequency count value is not set in the latch unit 23, and the previous input frequency count value remains latched. Accordingly, when the frequency of the input pulse is lowered, naturally, it takes time until the next pulse rises, and the frequency counter unit 22 continues to increase the count value.
[0039]
Then, for example, even when the frequency of the input pulse suddenly fluctuates and decreases or stops, the count value based on the previous input pulse frequency is latched in the latch unit 23, so that Then, the pulse output continues to be output at an output frequency based on the latched count value. That is, although the frequency of the actual input pulse is a low value and is stopped, it is determined that the frequency is a predetermined frequency and a pulse is output, and accurate synchronization control cannot be performed.
[0040]
Therefore, as described above, when the frequency of the input pulse is equal to or lower than the set frequency, the input frequency is determined to be 0, and the latch unit 23 determines a predetermined value (for example, “0”) as the input frequency count value. ) Is set and held. As a result, even when the frequency of the input pulse is lowered or the input pulse remains OFF for a certain period, when an appropriate time (one pulse time corresponding to the input frequency lower limit setting value) elapses, the latch unit 23 The value is updated to a value based on the input frequency lower limit setting value.
[0041]
An output frequency count value is obtained based on the input frequency count value latched in the latch unit 23. When the frequency is equal to or lower than the input frequency lower limit set value, the value is held in the latch unit 23 at a predetermined value. Control is performed so that the output is stopped instead of performing the arithmetic processing at the ratio. When the value held in the latch unit 23 is set to “0” as described above, the calculation result is “0” even if the calculation process using the ratio setting value (n) in the ratio frequency dividing unit 24 is performed. Is preferable.
[0042]
In the present embodiment, since the processing is performed with the count value corresponding to the frequency, the count value increases as the frequency decreases. Therefore, in practice, whether the input frequency of the input pulse currently being counted is a frequency equal to or lower than the input frequency lower limit set value is determined by storing the count value of the frequency counter unit 22 in the input frequency lower limit set value register. Judgment is made based on whether or not the set value is exceeded.
[0043]
Specifically, for example, when the latch unit 23 employs a method of constantly monitoring the count value of the frequency counter unit 22, the count value is compared with the set value, and whether or not the set value is exceeded. It can be judged. In addition, when it is transferred from the frequency counter unit 22 at the time of restart, since the count value is unknown until it is transferred, a separate counter or the like is provided to count the elapsed time since the previous transfer was received. This can also be dealt with by comparing it with the set value. Further, in the example shown in FIG. 3, the output of the input frequency lower limit setting register 25 is given to the latch unit 23. However, the output is given to the frequency counter unit 22, and the count value is set on the frequency counter unit 22 side. If it exceeds, a predetermined value may be output.
[0044]
The actual operation of this input lower limit frequency setting function is, for example, as shown in FIG. That is, if the input pulse is as shown in FIG. 8 (a), the end of one cycle of the first pulse output (1) as shown in FIG. 8 (b) (rising edge of the second pulse output). ) (Actually several clocks before), since the frequency count value (t) of the leading input pulse is latched in the latch unit, the output frequency based on the frequency count value is obtained and the obtained output is obtained. A second pulse output {circle around (2)} is generated according to the frequency.
[0045]
By the way, if the input continues for a certain period after the second input pulse is input, the frequency counter unit 22 continues to count up, so the latch unit 23 at the end of the second pulse output (2). The value latched in (1) is a value (t) based on the first input pulse. Therefore, the third pulse output (3) is also output at the same frequency as the second pulse output (2). The same applies to the fourth pulse output (4).
[0046]
Here, if the lower limit of the input frequency is 100 Hz, the input frequency lower limit setting value is a count value corresponding to 10 msec. Accordingly, at the end of one cycle of the fourth pulse output (4), the count value in the frequency counter unit 22 exceeds the value corresponding to 10 msec, so that the latch unit 23 has a predetermined value ( For example, “0”) is set. Therefore, the output pulse frequency setting value output from the ratio divider 24 is “0”, and the pulse output is OFF.
[0047]
In the case of the present embodiment, since the frequency of the next pulse output is calculated and set by using the pulse output operation (end of one cycle) as a trigger, when the pulse output continues in the OFF state in this way. The request signal is not output, and the frequency of the next pulse output cannot be calculated. Therefore, when the output becomes 0 based on the input frequency lower limit setting value in this way, the latch unit 23 knows the current state (output OFF), so the frequency counter unit 22 sets the frequency of the input pulse. When the counter counts and returns to a normal value that is equal to or higher than the input frequency lower limit set value, the input frequency count value is given from the input side (latch unit 23) to the ratio divider 24, and the ratio divider 24 based on the count value. The output frequency count value is calculated. When this calculation is finished, the count value obtained together with the permission signal is given to the pulse output unit 31 to return to normal operation (pulse output (5) is output).
[0048]
Further, an output frequency lower limit set value set in the output frequency lower limit setting register 27 is given to the ratio divider 24, and the output frequency obtained by calculation according to the ratio set value of the ratio setting register 26 is related. The output frequency lower limit set value is compared, and if the calculation result is larger, the output frequency lower limit set value is determined as the output pulse frequency set value, and the value is output. Thereby, it can suppress that the frequency of a pulse output becomes extremely low.
[0049]
For example, as shown in FIG. 8, when the output frequency lower limit set value is “256” and the ratio set value is “6”, the output frequency of the calculation result is obtained when the input frequency count value is “32”. Although the count value is output as it is, since the calculation result is “384” when the input frequency count value becomes “64”, the output frequency lower limit set value “256” is determined as the output frequency set value and output.
[0050]
Furthermore, since the ratio dividing unit 24 reads the ratio setting value stored in the ratio setting register 26 every time it calculates, for example, means for writing the ratio setting value to the ratio setting register 26 during operation of the CPU unit. By providing it, the ratio setting value can be rewritten during pulse output, so that the correlation (ratio) between the input frequency and output frequency can be changed, and the accuracy can be adjusted in response to changes in the situation. Control is possible.
[0051]
As described above, in the present embodiment, the frequency to be output next is calculated and output for each pulse of the pulse output, so that the accuracy of the control cycle is greatly improved.
[0052]
Furthermore, using the operation on the pulse output side as a trigger, when one cycle of one pulse output ends (rising of the next pulse output), the frequency of the input pulse immediately before is obtained, and a predetermined ratio setting value is obtained based on that Accordingly, the frequency of the pulse output is obtained according to the above, so that the fluctuation of the output frequency accompanying the fluctuation of the input frequency can be performed in real time, and more accurate synchronization control can be performed. Since the latest frequency count value of the input pulse has already been obtained, the ratio frequency dividing unit 24 reads the input frequency from the latch unit 23 and performs arithmetic processing based on the ratio set value after the trigger is generated. Therefore, the calculation process can be sufficiently completed and sent to the pulse output unit 31 in the time until the next rise of the pulse output.
[0053]
【The invention's effect】
As described above, according to the present invention, the change in the input frequency can be quickly reflected in the output frequency.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a control system using output pulses output from a CPU unit of a PLC.
FIG. 2 is a time chart illustrating a conventional operation.
FIG. 3 is a diagram showing an embodiment of the present invention.
FIG. 4 is a diagram for explaining the operation of a ratio divider.
FIG. 5 is a timing chart illustrating the operation of the present embodiment.
FIG. 6 is a part of a flowchart for explaining the operation of the present embodiment;
FIG. 7 is a part of a flowchart for explaining the operation of the present embodiment;
FIG. 8 is a diagram for explaining an input frequency lower limit setting function;
FIG. 9 is a diagram for explaining an output frequency lower limit setting function;
[Explanation of symbols]
10 CPU unit 11 I / O terminal 20 Counter block 21 Input pulse conversion unit 22 Frequency counter unit 23 Latch unit 24 Ratio division unit 25 Input frequency lower limit setting register 26 Ratio setting register 27 Output frequency lower limit setting register 30 Pulse block 31 Pulse output Part

Claims (5)

An input frequency detector for obtaining frequency information of the input pulse;
Storage means for storing the frequency information obtained by the input frequency detector;
Calculation means for calculating the output frequency setting value of the pulse output by performing arithmetic processing based on a predetermined ratio setting value for the frequency information stored in the storage means;
Based on the output frequency setting value output from the calculation means, comprises pulse output means for performing pulse output,
The pulse output means has a function of outputting a request signal instructing the calculation means to execute the arithmetic processing based on a state of pulse output,
The controller, wherein the calculation means executes the arithmetic processing when receiving a request signal from the pulse output means. The controller according to claim 1, wherein the request signal is issued every time the pulse output is output by one pulse. When the rising or falling edge of the input pulse is used as a reference change point, the input frequency detecting means detects the reference change point and detects the next reference change point based on a period from the detection of the reference change point. To find frequency information,
The controller according to claim 1, further comprising a function of stopping pulse output when the period is equal to or greater than a certain period. Storage means for storing the output frequency lower limit set value;
The calculation means outputs the output frequency lower limit setting value when the output frequency setting value of the pulse output obtained by the arithmetic processing is lower than the output frequency lower limit setting value stored in the storage means. The controller according to any one of claims 1 to 3, wherein the controller outputs the frequency setting value. Providing ratio setting value storage means for storing the ratio setting value,
The controller according to any one of claims 1 to 4, further comprising means for changing the ratio setting value stored in the ratio setting value storage means during operation of the controller.

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