JP3948547B2 - Multi-value non-volatile memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-level nonvolatile memory, and more particularly to a technology that is particularly effective when used as a defect relieving technology, with a memory array in which 8-level memory cells are arranged in a lattice as a basic component.
[0002]
[Prior art]
There is a two-layer gate structure type memory cell having a control gate and a floating gate. In addition, there is a quaternary memory cell comprising the two-layer gate structure type memory cell and capable of holding stored data of 2 bits, for example, by switching its threshold voltage in four stages. There is a multi-value flash memory whose basic component is a memory array in which cells are arranged in a grid.
[0003]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application studied storing eight values in the multi-level flash memory as described above and storing three bits in one memory cell. In this case, if the same Y address is assigned to one memory cell as in the prior art, three memory cells can be selected and 9-bit storage data can be stored, but in general, in units of 8 bits (1 byte) Since data is input / output, 1/9 of the storage capacity is wasted.
[0004]
In view of this, multi-valued Y addresses have been studied in which different Y addresses are assigned so that the memory cell memory information can be used effectively. However, if Y addresses are assigned consecutively, the relief unit becomes a 3Y address unit, and the coincidence / mismatch between the Y address and the relief address in the relief circuit becomes complicated and the Y gate signal generation circuit becomes complicated. Problems arise.
[0005]
That is, out of the 3 bits stored in one memory cell, if even one bit is defective, it is necessary to make the memory cell defective and replace it with a redundant memory cell. When the 3Y address is assigned, it is necessary to compare all the bits and detect a plurality of addresses of the defective bit and the memory cell to which it belongs. For example, as shown in FIG. 6, since the defective address Yfuz for three addresses corresponding to the memory cell is stored in the relief address fuse (address fuze), it is converted into Yred = Yfuz + 0 to Yfuz2 by the address conversion circuit. However, it is necessary to supply to the repair comparison circuit that receives the address signal Yadd formed by the Y address counter. In the repair comparison circuit, when all the bits of the address signal Yadd and the repair address Yred match, the repair address is determined.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-value non-volatile memory that realizes 3-bit / 1-cell and defect relief with a simple circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, 3-bit storage information is stored in one memory cell, and different Y addresses are assigned to the respective bits. The first address signal designating each bit of one memory cell is formed by a ternary counter. The second address is a 2-bit address signal, a second address signal for selecting one memory cell is a multi-bit address signal formed by a binary counter that receives the carry signal of the ternary counter, and the second address Corresponding to the signal, a repair comparison circuit and a repair address storage circuit, and a corresponding redundant circuit are provided.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a multi-value flash memory (semiconductor memory device) to which the present invention is applied. First, the outline of the configuration and operation of the multilevel flash memory of this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). It is formed on the surface of a single semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique.
[0009]
In FIG. 1, the multi-value flash memory of this embodiment is not particularly limited, but a pair of memory arrays ARYL (first memory array) and ARYR (second memory array) in which one of them is selectively activated. Memory array) and a latch part LT arranged to be sandwiched between these memory arrays. Among these, the memory arrays ARYL and ARYR are, as will be described later, a predetermined number of word lines arranged in parallel with the vertical direction of the figure and a predetermined number of global data lines arranged in parallel with the horizontal direction of the figure. And each. Two-layer gate structure type memory cells having floating gates and control gates are arranged in the vicinity of the intersections of the word lines and global data lines constituting each memory array.
[0010]
In this embodiment, the memory arrays ARYL and ARYR have a hierarchical data line system, and the memory cells are grouped into cell blocks in units of m + 1. The drains of the m + 1 memory cells constituting each cell block are commonly coupled to corresponding local data lines, and the sources thereof are commonly coupled to corresponding source lines. Further, the local data line of each cell block is coupled to the corresponding global data line via an N-channel type switch MOSFET that receives a predetermined block selection signal at its gate, and the source line of each cell block is connected to its gate. It is coupled to the common source line via an N-channel type switch MOSFET that receives another predetermined block selection signal.
[0011]
On the other hand, the memory cells constituting the memory arrays ARYL and ARYR are 8-level memory cells, and their threshold voltages are switched in 8 steps according to the logical value of the 3-bit stored data to be held. The specific configuration of the memory arrays ARYL and ARYR and the operation characteristics of the memory cells will be described later in detail.
[0012]
The word lines constituting the memory arrays ARYL and ARYR are coupled to the X address decoder XDL or XDR below and selectively set to a predetermined selection or non-selection level. The X address decoders XDL and XDR are commonly supplied with an internal X address signal of a predetermined bit from the X address buffer XB and are commonly supplied with an internal control signal XG from the memory control circuit CTL. The X address buffer XB is supplied with X address signals from the data input / output terminals IO0 to IO7 via the data input / output circuit IO and the multiplexer MX, and is supplied with internal control signals XL1 and XL2 from the memory control circuit CTL. .
[0013]
Here, the X address signal has a number of bits exceeding 8, and is supplied in a time division manner from the data input / output terminals IO0 to IO7 in two cycles. Of these, the lower bits of the X address signal input in the first cycle are taken into the lower bits of the X address buffer XB according to the internal control signal XL1, and the upper bits input in the second cycle are the internal control signal It is taken into the upper bits of the X address buffer XB according to XL2. The X address buffer XB forms internal X address signals composed of non-inverted and inverted signals based on these X address signals, and supplies them to the X address decoders XDL and XDR.
[0014]
The X address decoders XDL and XDR are selectively activated in response to the high level of the internal control signal XG, decode the internal X address signal supplied from the X address buffer XB, and correspond to the memory array ARYL or ARYR. The word line and block selection signal are set to a predetermined selection or non-selection level.
[0015]
Next, the global data lines constituting the memory arrays ARYL and ARYR are coupled to the corresponding unit circuits of the latch unit LT inside. As will be described later, the latch unit LT includes a predetermined number of unit circuits provided corresponding to the adjacent data lines of the memory arrays ARYL and ARYR, that is, the adjacent global data lines. First to fourth latches, and a precharge circuit and a Y gate circuit provided in correspondence with each other are included. A corresponding column selection signal is supplied from the Y address decoder YD to the Y gate circuit of each unit circuit. The Y address decoder YD is supplied with an internal Y address signal of a predetermined bit from the Y address counter YC and with an internal control signal YG from the memory control circuit CTL.
[0016]
The first to fourth latches of each unit circuit of the latch unit LT are selectively connected to the upper, middle, and data latch write data or read data according to which of the memory arrays ARYL or ARYR is activated. It consists of 3 holding lower bits in a predetermined combination and one sense latch used for verify operation. The precharge circuit of each unit circuit is used for the precharge operation of the corresponding data line of the memory array ARYL or ARYR, and the Y gate circuit is not shown as a corresponding latch according to the column selection signal supplied from the Y address decoder YD. A connection is made selectively to the common IO line.
[0017]
The Y address counter YC performs a stepping operation according to an internal clock signal (not shown), forms an internal Y address signal of a predetermined bit, and supplies it to the Y address decoder YD. In this embodiment, it is constituted by a combination of two counters as will be described later. That is, the lower Y-bit first Y address signal is formed by a ternary counter, and the carry signal of the ternary counter is supplied to a binary counter that forms a second Y address signal composed of upper bits. The Y address decoder YD selectively operates in response to the high level of the internal control signal YG, decodes the first and second Y address signals supplied from the Y address counter YC, and supplies them to the Y gate circuit. The corresponding bits of the column selection signal are sequentially set to the high level.
[0018]
The multiplexer MX includes a first input / output terminal provided on the left side thereof, and a second output terminal, a third input / output terminal, and a fourth output terminal provided on the right side thereof. Among these, the first input / output terminal is coupled to the input / output terminal on the right side of the data input / output circuit IO, and the third input / output terminal is coupled to the latch unit LT via eight sets of common IO lines (not shown). Is done. The second output terminal is coupled to the input terminal of the command register CR, and the fourth output terminal is coupled to the input terminal of the X address buffer XB. The left input / output terminal of data input / output circuit IO is coupled to data input / output terminals IO0-IO7.
[0019]
The multiplexer MX receives an X address signal, write data, and command data input from an external access device via the data input / output terminals IO0 to IO7 and the data input / output circuit IO, and the corresponding X address buffer XB, latch portion LT or In addition to transmitting to the command register CR, a total of 8-bit output data output from the eight designated latches of the latch unit LT is transmitted to the data input / output circuit IO. The data input / output circuit IO transmits an X address signal, write data, and command data input from an external access device via the data input / output terminals IO0 to IO7 to the multiplexer MX and from the latch portion LT to the multiplexer MX. The output data output via is output to the access device via the data input / output terminals IO0 to IO7.
[0020]
On the other hand, the command register CR fetches and holds command data of a predetermined bit input from the data input / output terminals IO0 to IO7 via the data input / output circuit IO and the multiplexer MX according to the internal control signal CL, and also stores the memory control circuit CTL. To communicate. The internal voltage generation circuit VG generates various internal voltages based on the power supply voltage VCC supplied through the external terminal VCC and the ground potential VSS supplied through the external terminal VSS, and supplies the internal voltages to each unit. To do.
[0021]
The memory control circuit CTL is supplied with a chip enable signal CEB supplied as an activation control signal from an external access device (here, a so-called inversion signal or the like that is selectively set to a low level when it is enabled has its name) Based on the write enable signal WEB, output enable signal OEB, reset signal RESB, command enable signal CDEB, clock signal SC, and command data supplied from the command register CR In addition, the various internal control signals and the like are selectively formed and supplied to each part of the multilevel flash memory. In addition, the ready / busy signal R / BB is selectively set to the low level to notify the external access device of the use state of the multi-level flash memory.
[0022]
FIG. 2 shows a partial circuit diagram of an embodiment of the memory array ARYL of the multilevel flash memory of FIG. 1, and FIG. 3 shows a two-layer gate structure type memory cell constituting the memory arrays ARYL and ARYR. A distribution characteristic diagram of one embodiment of the threshold voltage is shown. Based on these drawings, the specific configuration and operation of the memory arrays ARYL and ARYR of the multilevel flash memory of this embodiment and the threshold voltage distribution characteristics of the two-layer gate structure type memory cells will be described.
[0023]
FIG. 2 illustrates cell blocks CBL00 to CBL0n arranged at the left end of the memory array ARYL and cell blocks CBLk0 to CBLkn arranged at the right end thereof. Hereinafter, a specific description of the memory array ARYL will be given by taking the part shown in the figure as an example. Since the memory array ARYR has a symmetrical configuration, it should be analogized. In the following circuit diagrams, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0024]
In FIG. 2, the memory array ARYL has a so-called AND type array structure, and a total of (k + 1) × (m + 1) word lines WL00 to WL0m to WLk0 to WLkm arranged in parallel in the vertical direction of the figure. And n + 1 global data lines DLL0 to DLLn arranged in parallel in the horizontal direction of the figure. Near the intersection of these word lines and global data lines, a total of (k + 1) × (m + 1) × (n + 1) two-layer gate structure type memory cells MC each having a control gate and a floating gate are arranged in a lattice pattern. The
[0025]
In this embodiment, the multi-level flash memory employs a hierarchical data line system, and the memory cells MC constituting the memory array ARYL have a total of (k + 1) × (n + 1) memory cells in units of m + 1 arranged in the same column. Cell blocks CBL00 to CBL0n to CBLk0 to CBLkn.
[0026]
The drains of m + 1 memory cells MC constituting each cell block of the memory array ARYL are commonly coupled to corresponding local data lines LDL00 to LDL0n to LDLk0 to LDLkn, and their sources are connected to corresponding source lines SLL00 to SLL0n to Commonly coupled to SLLk0 to SLLkn. Local data lines LDL00 to LDL0n to LDLk0 to LDLkn are coupled to corresponding global data lines DLL0 to DLLn via N channel type selection MOSFETs NM1, respectively, and source lines SLL00 to SLL0n to SLLk0 to SLLkn are N channel type selections. Coupled to corresponding common source lines SSL0 to SSLk through MOSFET NM2.
[0027]
Corresponding block selection signals MDL0 to MDLk are respectively supplied from the X address decoder XDL to the gates of the selection MOSFETs NM1 of the n + 1 cell blocks CBL00 to CBL0n to CBLk0 to CBLkn arranged in the same row of the memory array ARYL. Corresponding block selection signals MSL0 to MSLk are commonly supplied to the gates of the n + 1 selection MOSFETs NM2. Control gates of n + 1 memory cells MC arranged in the same row of memory array ARYL are commonly coupled to corresponding word lines WL00 to WL0m to WLk0 to WLkm, respectively.
[0028]
Here, the two-layer gate structure type memory cell MC constituting the memory arrays ARYL and ARYR is an 8-level memory cell as illustrated in FIG. 3, and the threshold voltage thereof corresponds to the erased state. The threshold voltage and the threshold voltage corresponding to the write state are distributed in eight stages so as to be the target values. For this reason, each memory cell MC holds 3 bits of stored data, and the logical values of the stored data in each distribution area are “111”, “110”, “101”, “ 100 ”,“ 011 ”,“ 010 ”,“ 001 ”,“ 000 ”.
[0029]
In the 3-bit storage information “XXX” stored in the one memory cell, Y addresses of Y = 3n + 2 (n = 0 to) are assigned to the upper bits, and Y = 3n + 1 (n = 0 to 0) are assigned to the middle bits. ) Y address is assigned, and Y = 3n (n = 0 to) Y address is assigned to the lower bits to be multi-valued. As a result, information bits can be stored in the memory cells without waste even for the storage information in units of 8 bits.
[0030]
In FIG. 2, at the time of verify operation in the read mode or write mode, the memory cells MC constituting the memory arrays ARYL and ARYR have their control gates, that is, the corresponding word lines WL00 to WL0m to WLk0 to WLkm selected by the read word line voltage. Each of the global data lines DLL0 to DLLn is selectively pulled out, and a read signal corresponding to the logical value of the stored data is applied to each global data line. Output.
[0031]
FIG. 4 is a block diagram showing an embodiment of a relief circuit for a multi-value nonvolatile memory according to the present invention. The Y address counter is composed of a lower 2-bit Y address signal Yadd1 and an upper Y address signal Yadd2. The lower 2-bit Y address signal Yadd1 is a signal formed by a ternary counter. Of the 2-bit signal, the lower-order bit of the 3-bit stored information stored in one memory cell is stored as 00. 01 designates the middle bit, 10 designates the upper bit, and 11 is not used.
[0032]
The carry signal of the ternary counter is supplied to the binary counter to form the upper Y address signal Yadd2. Therefore, the upper Y address signal Yadd2 is a binary signal. The address signal Yadd2 is a signal corresponding to one memory cell that stores the 3-bit storage information. Therefore, only the address signal Yadd2 is supplied to the repair comparison circuit. The relief address fuse (address fuze) stores a relief address Yfuz corresponding to the Y address Yadd2 assigned to each of the memory cells.
[0033]
The lower 2-bit Y address signal Yadd1 formed by the Y address counter (Y address counter), the upper Y address signal Yadd2, and the output signal of the repair comparison circuit are supplied to the Y decoder. If the output signals of the repair comparison circuit do not match, the address signals Yadd1 and Yadd2 are decoded to form a Y selection signal. If the output signals of the repair comparison circuit match, the decode output of the address signals Yadd1 and Yad2 is invalidated and switched to the selection of redundant memory cells.
[0034]
In this embodiment, the internal Y address signal formed by the Y address counter is divided into two, the lower bits are formed by a ternary counter corresponding to the storage information of one memory cell, and the remaining higher address By forming the signal with a binary counter corresponding to the memory cell, the relief comparison circuit ignores the lower bit and compares the higher address signal with the relief address formed by the relief address fuse circuit. Just do it. The address conversion circuit as shown in FIG. 6 is also unnecessary.
[0035]
FIG. 5 is a schematic circuit diagram showing one embodiment of the Y gate circuit of the multi-value nonvolatile memory according to the present invention. The sense latch is composed of a CMOS latch circuit in which the inputs and outputs of two CMOS inverter circuits are cross-connected, and the sense latch has three address units (Y = n, n + 3) for one IO line. , N + 6), and other IO lines are also configured in three address units (Y = n + 1, n + 4, n + 7). Correspondingly, the Y gate signal generation circuit is also composed of three address units. This reduces the circuit area of the Y gate circuit. Of the four sense latches, one performs a verify operation, and the other three are used as data latches that hold 3-bit data.
[0036]
The effects obtained from the above embodiments are as follows. That is, 3-bit storage information is stored in one memory cell, and different Y addresses are assigned to the respective bits. The first address signal designating each bit of one memory cell is formed by a ternary counter. The second address is a 2-bit address signal, a second address signal for selecting one memory cell is a multi-bit address signal formed by a binary counter that receives the carry signal of the ternary counter, and the second address By providing a repair comparison circuit and a repair address memory circuit corresponding to the signal and a redundant circuit corresponding to the circuit, it is possible to realize an efficient storage of information bits and defect repair with a simple circuit.
[0037]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, in the multilevel flash memory, the data input / output terminals IO0 to IO7 may be dedicated as data input terminals or data output terminals, respectively. Memory arrays ARYL and ARYR and their peripheral parts can be divided into an arbitrary number of memory mats. The block configuration of the multi-level flash memory, the names and combinations of the start control signal, the internal control signal, and the like, and their effective levels can take various embodiments.
[0038]
In FIG. 2, the memory arrays ARYL and ARYR can include an arbitrary number of redundant elements, and the related parts thereof are also the same. Further, the memory arrays ARYL and ARYR do not have to have an AND type array structure or a hierarchical data line system, but can also have a hierarchical word line system. The present invention can also be applied to a single chip microcomputer including such a multi-level flash memory. The present invention can be widely applied to a semiconductor memory device including a memory array in which 8-level memory cells are arranged in a grid, a data latch and a sense latch, and a device or system including the same.
[0039]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, 3-bit storage information is stored in one memory cell, and different Y addresses are assigned to the respective bits. The first address signal designating each bit of one memory cell is formed by a ternary counter. The second address is a 2-bit address signal, a second address signal for selecting one memory cell is a multi-bit address signal formed by a binary counter that receives the carry signal of the ternary counter, and the second address By providing a repair comparison circuit and a repair address storage circuit corresponding to the signal and a redundant circuit corresponding to the circuit, efficient storage of information bits and defect repair can be realized with a simple circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a multi-value flash memory to which the present invention is applied.
FIG. 2 is a partial circuit diagram showing an embodiment of a memory array of the multi-level flash memory of FIG. 1;
FIG. 3 is a distribution characteristic diagram showing an example of threshold voltages of a two-layer gate structure type memory cell constituting the memory array of FIG. 2;
FIG. 4 is a block diagram showing an embodiment of a relief circuit for a multi-value nonvolatile memory according to the present invention.
FIG. 5 is a schematic circuit diagram showing one embodiment of a Y gate circuit of the multi-value nonvolatile memory according to the present invention.
FIG. 6 is a block diagram showing an example of a relief circuit for a multi-level nonvolatile memory studied prior to the present invention.
[Explanation of symbols]
ARYL, ARYR: Memory array, XDL, XDR: X address decoder, XB: X address buffer, LT: Latch unit, YD: Y address decoder, YC: Y address counter, MX: Multiplexer, IO ... I / O buffer, CR ... Command register, VG ... Internal voltage generation circuit, CTL ... Memory control circuit, SC ... Serial clock signal or its input terminal, CEB ... Chip enable signal or its input terminal, WEB ...... Write enable signal or its input terminal, OEB ... Output enable signal or its input terminal, RESB ... Reset signal or its input terminal, CDEB ... Command enable signal or its input terminal, R / BB ... Ready / busy Signal or its output terminal, IO0 to IO7 ... Input or output data Data or input and output terminals thereof, VCC ...... supply voltage or the input terminal, VSS ...... ground potential or the input terminal.
CBL00 to CBL0n to CBLk0 to CBLkn ... cell block, LDL00 to LDL0n to LDLk0 to LDLkn ... local data line, SLL00 to SLL0n to SLLk0 to SLLkn ... source line, WL00 to WL0m to WLk0 to WLkm ... word line, DLL0 ... DLLn, DLR0 to DLRn... Global data line, MDL0 to MDLk, MSL0 to MSLk... Block selection signal, SLL0 to SLLk.

Claims (1)

A multi-value nonvolatile memory in which 3 bits of storage information is stored in one memory cell, and different Y addresses are assigned to each bit,
The first address signal designating each bit is a 2-bit address signal formed by a ternary counter,
A second address signal for selecting one memory cell is a multi-bit address signal formed by a binary counter that receives the carry signal of the ternary counter;
A multi-value nonvolatile memory comprising a relief comparison circuit and a relief address storage circuit corresponding to the second address signal, and a redundancy circuit corresponding thereto.

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