JP3941093B2 - Network quality evaluation equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information, and more particularly to a network quality evaluation apparatus that can reduce the circuit scale.
[0002]
[Prior art]
Conventional network quality evaluation devices measure communication packets propagating on a communication network at each point of the communication network, evaluate the communication quality of the communication network line based on the measured communication packet, monitor traffic, etc. Is what you do.
[0003]
For example, as such a network quality evaluation apparatus, there are “Japanese Patent Application No. 11-274273” and “Japanese Patent Application No. 11-304215” related to the application of the present applicant.
[0004]
FIG. 5 is a configuration block diagram showing an example of such a conventional network quality evaluation apparatus. In FIG. 5, 1 is a physical layer circuit, 2 is a packet filter circuit, 3 is a data filter circuit, and 4 is a memory circuit.
[0005]
In FIG. 5, 100 is a communication network, 101 is a packet signal captured by the physical layer circuit 1, 102 is a packet signal selected by the packet filter circuit 2, 103 is a data signal selected by the data filter circuit 3, and 104 Is a discarded packet signal, and 105 is a discarded data signal.
[0006]
The communication network 100 is connected to the physical layer circuit 1, and the packet signal 101 that is the output of the physical layer circuit 1 is connected to the packet filter circuit 2. The packet signal 102 that is the output of the packet filter circuit 2 is connected to the data filter circuit 3, and the data signal 103 that is the output of the data filter circuit 3 is connected to the storage circuit 4.
[0007]
Here, the operation of the conventional example shown in FIG. 5 will be briefly described. A communication packet signal propagating through the communication network 100 is received by the physical layer circuit 1 and processed in the packet filter circuit 2 based on the filter condition. In other words, the packet signal satisfying the filter condition is selected as the selected packet signal 102 in the data filter circuit 3. To be supplied.
[0008]
In the data filter circuit 3, the data of the designated portion of the packet signal 102 selected by the packet filter circuit 2 is extracted and stored in the storage circuit 4 as the data signal 103.
[0009]
On the other hand, a packet signal that does not satisfy the filter condition in the packet filter circuit 2 is discarded as the packet signal 104, and similarly, data other than the designated portion is discarded as the data signal 105 in the data filter circuit 3.
[0010]
In practice, however, a buffer circuit for temporarily storing the selected packet signal 102 is required between the packet filter circuit 2 and the data filter circuit 3. FIG. 6 is a block diagram showing the configuration of an example of such a conventional network quality evaluation apparatus.
[0011]
In FIG. 6, 1, 2, 3, 4, 100, 101, 102, 103 and 105 are assigned the same reference numerals as in FIG. 5, 5 is a buffer circuit, and 106 is a packet signal which is an output of the buffer circuit 5. .
[0012]
The communication network 100 is connected to the physical layer circuit 1, and the packet signal 101 that is the output of the physical layer circuit 1 is connected to the packet filter circuit 2. The packet signal 102 that is the output of the packet filter circuit 2 is connected to the buffer circuit 5, and the packet signal 106 that is the output of the buffer circuit 5 is connected to the data filter circuit 3. Further, the data signal 103 that is the output of the data filter circuit 3 is connected to the memory circuit 4.
[0013]
6 will be described in detail with reference to FIGS. 7, 8, 9 and 10. FIG. FIG. 7 is a flowchart for explaining the overall operation of the conventional example, FIG. 8 is a diagram for explaining specific examples of packet data and the operations of the packet filter circuit 2 and the data filter circuit 3, and FIG. FIG. 10 is an explanatory diagram for explaining the operation of the packet filter circuit 2. FIG. 10 is a diagram for explaining a specific example of packet data and the operation of the data filter circuit 3. However, the description overlapping with the conventional example shown in FIG. 5 is omitted.
[0014]
In “S001” to “S004” in FIG. 7, the packet filter circuit 2 processes the packet signal 101 taken in by the physical layer circuit 1 based on the filter condition.
[0015]
That is, in “S001” in FIG. 7, the packet filter circuit 2 determines whether or not the packet filter processing for all packets has been completed. If the packet filter processing has not been completed, the packet filter circuit 2 in “S002” in FIG. The filter circuit 2 determines whether or not the fetched processing unit data matches the filter condition.
[0016]
If the data matches the filter condition in “S002” in FIG. 7, the packet filter circuit 2 stores the matching portion in the buffer circuit 5 in “S003” in FIG. 7 and completes the packet filter processing for all packets. Until then, the loop of “S001” to “S003” in FIG. 7 is repeated.
[0017]
On the other hand, if the data does not match the filter condition in “S002” in FIG. 7, the packet filter circuit 2 discards the packet signal stored in the buffer circuit 5 until that time in “S004” in FIG. The process ends.
[0018]
In FIG. 7, when the packet filtering process for all packets is completed in “S001”, in other words, when all the packet data 101 captured by the physical layer circuit 1 matches the filter condition, “S005” to “S008” in FIG. The data filter circuit 3 extracts the packet signal 106 subjected to the packet filter processing from the buffer circuit 5 and extracts the data of the designated portion.
[0019]
That is, in “S005” in FIG. 7, the data filter circuit 3 determines whether or not the data corresponding to the processing unit of the packet signal read from the buffer circuit 5 corresponds to the designated portion. In FIG. 7, “S006”, the data filter circuit 3 stores the data of the designated portion in the storage circuit 4.
[0020]
On the other hand, if the data corresponding to the processing unit of the packet signal read from the buffer circuit 5 in “S005” in FIG. 7 does not correspond to the designated portion, the data filter circuit 3 displays the data in “S007” in FIG. Discard.
[0021]
Finally, in “S008” in FIG. 7, it is determined whether or not the data filter processing has been performed on all the packet signals 106. If the data filter processing has not been completed, “S005” to “” in FIG. The process of S007 "is repeated.
[0022]
For example, consider the case where a packet signal as shown in FIG. Here, it is assumed that the packet signal is checked for packet matching in units of 32 bits and data is stored in the storage circuit 4 in units of 32 bits.
[0023]
In FIG. 8, “O” in the “packet filter column” checks whether the data in the portion matches the filter condition, and “O” in the “data filter column” stores the data in that portion. Each of them is stored in the circuit 4.
[0024]
For example, in the part indicated by “LN01” in FIG. 8, the data of this part is checked for coincidence / non-coincidence with the filter condition and the data of this part is stored in the storage circuit 4. The data in this part is simply checked for coincidence / non-coincidence with the filter condition, and no processing is performed in the part indicated by “LN03” in FIG.
[0025]
However, the processing in the data filter circuit 3 is performed after the packet filter processing is completed for all parts of the packet signal. That is, the series of processing shown in FIG. 10 is performed after the series of processing shown in FIG.
[0026]
For example, in the portion indicated by “LN11” in FIG. 9, the data is unconditionally stored in the buffer circuit 5, and in the portion indicated by “LN12” in FIG. 9, when the filter condition matches the data of the portion, the data is stored in the buffer circuit 5. Store the data.
[0027]
Further, for example, data is discarded at a portion indicated by “LN21” in FIG. 10, and data is stored in the storage circuit 4 at a portion indicated by “LN22” in FIG.
[0028]
However, if the data in the portion indicated by “LN12” in FIG. 9 does not match the filter condition, all the data in the buffer circuit 5 is discarded as described above, so the processing as shown in FIG. Not done.
[0029]
As a result, the buffer circuit 5 is provided between the packet filter circuit 2 and the data filter circuit 3, and the data satisfying the filter condition is temporarily stored in the buffer circuit 5, and then the contents of the buffer circuit 5 are read and the data By performing the filtering process, it is possible to extract a specific portion of data from a specific packet signal.
[0030]
[Problems to be solved by the invention]
However, in the conventional example shown in FIG. 6, it cannot be determined whether the packet signal currently flowing on the communication network satisfies the filter condition specified by the packet filter circuit 2 until the end of the packet signal is checked. For example, it is not possible to determine whether or not the data filter processing can be performed on the packet signal until the check of the portion indicated by “LN04” in FIG.
[0031]
For this reason, as a storage capacity necessary for the buffer circuit 5 provided in the subsequent stage of the packet filter circuit 2, a storage capacity sufficient to temporarily store the maximum packet signal is required.
[0032]
For example, in the Ethernet standard stipulated in “IEEE802.3”, the longest packet length is “1518 Bytes”. In this case, a storage capacity capable of temporarily storing “1518 Bytes” which is the longest packet length is required. become.
[0033]
That is, the conventional example shown in FIG. 6 has a problem that the circuit scale of the buffer circuit is increased.
Therefore, the problem to be solved by the present invention is to realize a network quality evaluation apparatus capable of reducing the circuit scale of the buffer circuit.
[0034]
[Means for Solving the Problems]
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information , performs a data filter process on the acquired communication packet and performs a packet filter process in parallel. A packet capture unit that selects or discards data of a specified portion extracted and accumulated by the data filter process based on a processing result of the packet filter process; and a storage circuit that stores the data selected by the packet capture unit. As a result, the circuit scale of the buffer circuit can be reduced.
[0035]
The invention according to claim 2
In the network quality evaluation apparatus according to claim 1,
The packet capture means is
A physical layer circuit that captures the communication packet propagating on the communication network; a buffer circuit; a data filter circuit that extracts data of a designated portion of an output of the physical layer circuit and sequentially stores the data in the buffer circuit; and the data filter The circuit scale of the buffer circuit is configured by a packet filter circuit that operates in parallel with the circuit and stores the stored data of the buffer circuit in the storage circuit when the output of the physical layer circuit satisfies a filter condition. Can be reduced.
[0036]
The invention described in claim 3
In the network quality evaluation device according to claim 2,
The data filter circuit is
The processing unit sequentially fetches data for processing units from the output of the physical layer circuit, determines whether the data is a designated part, and if it is a designated part, stores the data of the designated part in the buffer circuit, By discarding data other than the designated portion and processing all packet signals taken in by the physical layer circuit, the processing is terminated, whereby the circuit scale of the buffer circuit can be reduced.
[0037]
The invention according to claim 4
In the network quality evaluation device according to claim 2,
The packet filter circuit is
When processing unit data is sequentially fetched from the output of the physical layer circuit to determine whether the data satisfies a filter condition, and when all the packet signals fetched by the physical layer circuit are processed It is determined whether or not the packet signal satisfies all the filter conditions. If the filter condition is satisfied, the data signal stored in the buffer circuit is selected and stored in the storage circuit. In this case, the circuit scale of the buffer circuit can be reduced by discarding the data signal stored in the buffer circuit.
[0038]
The invention according to claim 5
In the network quality evaluation apparatus according to claim 1,
The packet capture means;
By using the FPGA, a small chip can be used, so that the cost can be reduced.
[0039]
The invention described in claim 6
In the network quality evaluation apparatus according to claim 1,
The packet capture means;
By configuring with the ASIC, a small chip can be used, so that the cost can be reduced.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a network quality evaluation apparatus according to the present invention.
[0041]
1, 1, 4, 100 and 101 are denoted by the same reference numerals as in FIG. 6, 6 is a packet file circuit, 7 is a data filter circuit, 8 is a buffer circuit, and 107 is data selected by the data filter circuit 7. A signal 108 is a data signal which is an output of the buffer circuit 8, and a control signal 109 is an output of the packet filter circuit 6. 1, 6, 7 and 8 constitute a packet capture means 50.
[0042]
The communication network 100 is connected to the physical layer circuit 1, and the packet signal 101 that is the output of the physical layer circuit 1 is connected to the packet filter circuit 6 and the data filter circuit 7, respectively.
[0043]
The data signal 107 that is the output of the data filter circuit 7 is connected to the buffer circuit 8, and the data signal 108 that is the output of the buffer circuit 8 is connected to the storage circuit 4. A control signal 109 from the packet filter circuit 6 is connected to the control input terminal of the buffer circuit 8.
[0044]
Here, the operation of the embodiment shown in FIG. 1 will be described. In the embodiment shown in FIG. 1, the packet filter circuit 6 and the data filter circuit 7 operate in parallel, and the data filter circuit 7 sequentially extracts the designated portion of data from the packet signal fetched by the physical layer circuit 1 and buffers it. Accumulate in circuit 8.
[0045]
On the other hand, the packet filter circuit 6 checks the packet signal based on the filter condition, finally determines whether the filter condition is satisfied, and discards the data stored in the buffer circuit 8 or sends it to the storage circuit 4. Is instructed to store.
[0046]
Here, the operation of the embodiment shown in FIG. 1 will be described in detail with reference to FIGS. FIG. 2 is a flowchart for explaining the operation of the data filter circuit 7. FIG. 3 is a diagram for explaining a specific example of packet data and the operations of the packet filter circuit 6 and the data filter circuit 7. FIG. FIG.
[0047]
In “S101” in FIG. 2, the data filter circuit 7 determines whether or not the input packet signal is a designated part. If it is a designated part, the data filter circuit 7 designates the designated in “S102” in FIG. The portion of data is stored in the buffer circuit 8, and if it is not a designated portion, the data is discarded in "S103" in FIG.
[0048]
In FIG. 2, it is determined whether or not all packet signals have been processed in “S104”. If the processing has not been completed, the processing of “S101” to “S103” in FIG. 2 is repeated.
[0049]
For example, the data filter circuit 7 extracts the data indicated by “LN31”, “LN32”, “LN33”, “LN34” and “LN35” in FIG. 3 regardless of the judgment result of the packet filter circuit 6 and the like. The data is sequentially stored in the buffer circuit 8.
[0050]
In the example shown in FIG. 3, the processing unit is “32 bits”, so that data of “32 bits × 5 = 160 bits” is finally stored in the buffer circuit 8.
[0051]
On the other hand, in “S201” in FIG. 4, the packet filter circuit 6 performs the packet filtering process as described above, and determines whether or not the packet filtering process has been performed on all the packet signals in “S202” in FIG.
[0052]
When packet filter processing is performed on all packet signals, the packet filter circuit 6 determines whether or not the packet signal satisfies all filter conditions in “S203” in FIG.
[0053]
If the filter condition is satisfied, the packet filter circuit 6 sends an instruction to the buffer circuit 8 using the control signal 109 in “S204” in FIG. Select and store in the memory circuit 4.
[0054]
On the other hand, if the filter condition is not satisfied, the packet filter circuit 6 sends an instruction to the buffer circuit 8 using the control signal 109 in “S205” in FIG. Discard the signal.
[0055]
For example, the packet filter circuit 6 sequentially checks the match / mismatch of the data and the filter conditions of “LN31”, “LN36”, “LN37”... In FIG. 3 and shows “LN35” in FIG. When the check of the portion is completed, it is determined whether or not the packet signal satisfies all the filter conditions, and the buffer circuit 8 is controlled by the control signal 109.
[0056]
That is, the buffer circuit 8 only needs a storage capacity that can store the number of data extraction portions that can be set by the data filter circuit 7 at the maximum, and does not need a storage capacity for the maximum packet length as in the conventional example.
[0057]
For example, in the case shown in FIG. 3, if the maximum number of data extraction parts that can be set by the data filter circuit 7 is “16”, the processing unit is “32 bits”, and therefore only “32 bits × 16 = 64 bytes”. Therefore, the buffer circuit 8 has a storage capacity of about 1/23 as compared with the conventional “1518 bytes”.
[0058]
As a result, the packet filter circuit 6 and the data filter circuit 7 are operated in parallel, and the data stored in the buffer circuit 8 by the data filter circuit 7 is selected or discarded based on the processing result of the packet filter circuit 6, whereby the buffer circuit 8 circuit scale can be reduced.
[0059]
In addition, the processing speed that can omit the process of reading all the packet data once written in the buffer circuit as in the conventional example can be increased.
[0060]
In the embodiment shown in FIG. 1, since the circuit scale of the buffer circuit 8 is reduced, the packet capture means 50 is realized by a small chip such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). It is possible to reduce the cost of the network quality evaluation apparatus.
[0061]
In the description of the embodiment shown in FIG. 1, “32 bit” is exemplified as a processing unit. However, the processing unit is of course not limited to this value, and an arbitrary processing unit such as “16 bit” or “64 bit” can be used. You may use.
[0062]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first to fourth aspects of the present invention, the packet filter circuit and the data filter circuit are operated in parallel, and the data accumulated in the buffer circuit by the data filter circuit is selected or discarded based on the processing result of the packet filter circuit. As a result, the circuit scale of the buffer circuit can be reduced. In addition, the processing speed that can omit the process of reading all the packet data once written in the buffer circuit as in the conventional example can be increased.
[0063]
In addition, according to the inventions of claims 5 and 6, by configuring the packet capture means by FPGA or ASIC, a small chip can be used, so that the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus according to the present invention.
FIG. 2 is a flowchart for explaining the operation of the data filter circuit;
FIG. 3 is an explanatory diagram for explaining a specific example of packet data, a packet filter circuit, and an operation of the data filter circuit;
FIG. 4 is a flowchart for explaining the operation of the packet filter circuit.
FIG. 5 is a configuration block diagram showing an example of a conventional network quality evaluation apparatus.
FIG. 6 is a configuration block diagram showing an example of a conventional network quality evaluation apparatus.
FIG. 7 is a flowchart illustrating the overall operation of a conventional example.
FIG. 8 is an explanatory diagram for explaining a specific example of packet data and the operation of the packet filter circuit and the data filter circuit;
FIG. 9 is an explanatory diagram illustrating a specific example of packet data and the operation of the packet filter circuit.
FIG. 10 is an explanatory diagram illustrating a specific example of packet data and the operation of the data filter circuit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Physical layer circuit 2, 6 Packet filter circuit 3, 7 Data filter circuit 4 Memory circuit 5, 8 Buffer circuit 50 Packet capture means 100 Communication network 101,102,104,106 Packet signal 103,105,107,108 Data signal 109 Control signal

Claims (6)

In a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information,
Packet capture that performs data filter processing on the captured communication packet and performs packet filter processing in parallel, and selects or discards data of a specified portion extracted and accumulated by the data filter processing based on the processing result of the packet filter processing Means,
A network quality evaluation apparatus comprising: a storage circuit for storing the data selected by the packet capture means. The packet capture means is
A physical layer circuit that captures the communication packet propagating on the communication network;
A buffer circuit;
A data filter circuit for extracting the data of the designated portion of the output of the physical layer circuit and sequentially storing it in the buffer circuit;
The data filter circuit includes a packet filter circuit that operates in parallel and stores data stored in the buffer circuit in the storage circuit when the output of the physical layer circuit satisfies a filter condition. The network quality evaluation apparatus according to claim 1. The data filter circuit is
Sequentially fetching data for processing units from the output of the physical layer circuit to determine whether the data is a designated part;
If it is a designated part, the data of the designated part is stored in the buffer circuit, the data other than the designated part is discarded,
3. The network quality evaluation apparatus according to claim 2, wherein the processing is terminated when processing is performed on all packet signals taken in by the physical layer circuit. The packet filter circuit is
Sequentially fetching data for processing units from the output of the physical layer circuit to determine whether the data satisfies a filter condition;
Determining whether or not the packet signal satisfies all filter conditions when processing is performed on all packet signals captured by the physical layer circuit;
If the filter condition is satisfied, the data signal stored in the buffer circuit is selected and stored in the storage circuit; otherwise, the data signal stored in the buffer circuit is discarded. The network quality evaluation apparatus according to claim 2. The packet capture means;
The network quality evaluation apparatus according to claim 1, comprising an FPGA. The packet capture means;
2. The network quality evaluation apparatus according to claim 1, wherein the network quality evaluation apparatus is configured by an ASIC.

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